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96d55b88 PBG |
1 | # Put here option for CPU selection and depending optimization |
2 | if !X86_ELAN | |
3 | ||
4 | choice | |
5 | prompt "Processor family" | |
1032c0ba SR |
6 | default M686 if X86_32 |
7 | default GENERIC_CPU if X86_64 | |
96d55b88 PBG |
8 | |
9 | config M386 | |
10 | bool "386" | |
1032c0ba | 11 | depends on X86_32 && !UML |
96d55b88 PBG |
12 | ---help--- |
13 | This is the processor type of your CPU. This information is used for | |
14 | optimizing purposes. In order to compile a kernel that can run on | |
15 | all x86 CPU types (albeit not optimally fast), you can specify | |
16 | "386" here. | |
17 | ||
18 | The kernel will not necessarily run on earlier architectures than | |
19 | the one you have chosen, e.g. a Pentium optimized kernel will run on | |
20 | a PPro, but not necessarily on a i486. | |
21 | ||
22 | Here are the settings recommended for greatest speed: | |
23 | - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI | |
f7f17a67 DV |
24 | 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386 |
25 | class machine. | |
96d55b88 PBG |
26 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
27 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. | |
28 | - "586" for generic Pentium CPUs lacking the TSC | |
29 | (time stamp counter) register. | |
30 | - "Pentium-Classic" for the Intel Pentium. | |
31 | - "Pentium-MMX" for the Intel Pentium MMX. | |
32 | - "Pentium-Pro" for the Intel Pentium Pro. | |
33 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. | |
34 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. | |
35 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. | |
36 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). | |
37 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). | |
38 | - "Crusoe" for the Transmeta Crusoe series. | |
39 | - "Efficeon" for the Transmeta Efficeon series. | |
40 | - "Winchip-C6" for original IDT Winchip. | |
69d45dd1 | 41 | - "Winchip-2" for IDT Winchips with 3dNow! capabilities. |
96d55b88 | 42 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
f90b8116 | 43 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
96d55b88 | 44 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
48a1204c | 45 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
0949be35 | 46 | - "VIA C7" for VIA C7. |
96d55b88 PBG |
47 | |
48 | If you don't know what to do, choose "386". | |
49 | ||
50 | config M486 | |
51 | bool "486" | |
1032c0ba | 52 | depends on X86_32 |
8f9ca475 | 53 | ---help--- |
96d55b88 PBG |
54 | Select this for a 486 series processor, either Intel or one of the |
55 | compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX, | |
56 | DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or | |
57 | U5S. | |
58 | ||
59 | config M586 | |
60 | bool "586/K5/5x86/6x86/6x86MX" | |
1032c0ba | 61 | depends on X86_32 |
8f9ca475 | 62 | ---help--- |
96d55b88 PBG |
63 | Select this for an 586 or 686 series processor such as the AMD K5, |
64 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not | |
65 | assume the RDTSC (Read Time Stamp Counter) instruction. | |
66 | ||
67 | config M586TSC | |
68 | bool "Pentium-Classic" | |
1032c0ba | 69 | depends on X86_32 |
8f9ca475 | 70 | ---help--- |
96d55b88 PBG |
71 | Select this for a Pentium Classic processor with the RDTSC (Read |
72 | Time Stamp Counter) instruction for benchmarking. | |
73 | ||
74 | config M586MMX | |
75 | bool "Pentium-MMX" | |
1032c0ba | 76 | depends on X86_32 |
8f9ca475 | 77 | ---help--- |
96d55b88 PBG |
78 | Select this for a Pentium with the MMX graphics/multimedia |
79 | extended instructions. | |
80 | ||
81 | config M686 | |
82 | bool "Pentium-Pro" | |
1032c0ba | 83 | depends on X86_32 |
8f9ca475 | 84 | ---help--- |
96d55b88 PBG |
85 | Select this for Intel Pentium Pro chips. This enables the use of |
86 | Pentium Pro extended instructions, and disables the init-time guard | |
87 | against the f00f bug found in earlier Pentiums. | |
88 | ||
89 | config MPENTIUMII | |
90 | bool "Pentium-II/Celeron(pre-Coppermine)" | |
1032c0ba | 91 | depends on X86_32 |
8f9ca475 | 92 | ---help--- |
96d55b88 PBG |
93 | Select this for Intel chips based on the Pentium-II and |
94 | pre-Coppermine Celeron core. This option enables an unaligned | |
95 | copy optimization, compiles the kernel with optimization flags | |
96 | tailored for the chip, and applies any applicable Pentium Pro | |
97 | optimizations. | |
98 | ||
99 | config MPENTIUMIII | |
100 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" | |
1032c0ba | 101 | depends on X86_32 |
8f9ca475 | 102 | ---help--- |
96d55b88 PBG |
103 | Select this for Intel chips based on the Pentium-III and |
104 | Celeron-Coppermine core. This option enables use of some | |
105 | extended prefetch instructions in addition to the Pentium II | |
106 | extensions. | |
107 | ||
108 | config MPENTIUMM | |
109 | bool "Pentium M" | |
1032c0ba | 110 | depends on X86_32 |
8f9ca475 | 111 | ---help--- |
96d55b88 PBG |
112 | Select this for Intel Pentium M (not Pentium-4 M) |
113 | notebook chips. | |
114 | ||
115 | config MPENTIUM4 | |
c55d92d1 | 116 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
1032c0ba | 117 | depends on X86_32 |
8f9ca475 | 118 | ---help--- |
96d55b88 | 119 | Select this for Intel Pentium 4 chips. This includes the |
75e3808b OP |
120 | Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
121 | Pentium-4 M (not Pentium M) chips. This option enables compile | |
122 | flags optimized for the chip, uses the correct cache line size, and | |
123 | applies any applicable optimizations. | |
124 | ||
125 | CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) | |
126 | ||
127 | Select this for: | |
128 | Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: | |
129 | -Willamette | |
130 | -Northwood | |
131 | -Mobile Pentium 4 | |
132 | -Mobile Pentium 4 M | |
133 | -Extreme Edition (Gallatin) | |
134 | -Prescott | |
135 | -Prescott 2M | |
136 | -Cedar Mill | |
137 | -Presler | |
138 | -Smithfiled | |
139 | Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: | |
140 | -Foster | |
141 | -Prestonia | |
142 | -Gallatin | |
143 | -Nocona | |
144 | -Irwindale | |
145 | -Cranford | |
146 | -Potomac | |
147 | -Paxville | |
148 | -Dempsey | |
149 | ||
96d55b88 PBG |
150 | |
151 | config MK6 | |
152 | bool "K6/K6-II/K6-III" | |
1032c0ba | 153 | depends on X86_32 |
8f9ca475 | 154 | ---help--- |
96d55b88 PBG |
155 | Select this for an AMD K6-family processor. Enables use of |
156 | some extended instructions, and passes appropriate optimization | |
157 | flags to GCC. | |
158 | ||
159 | config MK7 | |
160 | bool "Athlon/Duron/K7" | |
1032c0ba | 161 | depends on X86_32 |
8f9ca475 | 162 | ---help--- |
96d55b88 PBG |
163 | Select this for an AMD Athlon K7-family processor. Enables use of |
164 | some extended instructions, and passes appropriate optimization | |
165 | flags to GCC. | |
166 | ||
167 | config MK8 | |
168 | bool "Opteron/Athlon64/Hammer/K8" | |
8f9ca475 | 169 | ---help--- |
36723bfe BP |
170 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
171 | Enables use of some extended instructions, and passes appropriate | |
172 | optimization flags to GCC. | |
96d55b88 PBG |
173 | |
174 | config MCRUSOE | |
175 | bool "Crusoe" | |
1032c0ba | 176 | depends on X86_32 |
8f9ca475 | 177 | ---help--- |
96d55b88 PBG |
178 | Select this for a Transmeta Crusoe processor. Treats the processor |
179 | like a 586 with TSC, and sets some GCC optimization flags (like a | |
180 | Pentium Pro with no alignment requirements). | |
181 | ||
182 | config MEFFICEON | |
183 | bool "Efficeon" | |
1032c0ba | 184 | depends on X86_32 |
8f9ca475 | 185 | ---help--- |
96d55b88 PBG |
186 | Select this for a Transmeta Efficeon processor. |
187 | ||
188 | config MWINCHIPC6 | |
189 | bool "Winchip-C6" | |
1032c0ba | 190 | depends on X86_32 |
8f9ca475 | 191 | ---help--- |
96d55b88 PBG |
192 | Select this for an IDT Winchip C6 chip. Linux and GCC |
193 | treat this chip as a 586TSC with some extended instructions | |
194 | and alignment requirements. | |
195 | ||
96d55b88 | 196 | config MWINCHIP3D |
69d45dd1 | 197 | bool "Winchip-2/Winchip-2A/Winchip-3" |
1032c0ba | 198 | depends on X86_32 |
8f9ca475 | 199 | ---help--- |
69d45dd1 | 200 | Select this for an IDT Winchip-2, 2A or 3. Linux and GCC |
96d55b88 | 201 | treat this chip as a 586TSC with some extended instructions |
3dde6ad8 | 202 | and alignment requirements. Also enable out of order memory |
96d55b88 PBG |
203 | stores for this CPU, which can increase performance of some |
204 | operations. | |
205 | ||
206 | config MGEODEGX1 | |
207 | bool "GeodeGX1" | |
1032c0ba | 208 | depends on X86_32 |
8f9ca475 | 209 | ---help--- |
96d55b88 PBG |
210 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
211 | ||
f90b8116 | 212 | config MGEODE_LX |
96daa8cd | 213 | bool "Geode GX/LX" |
1032c0ba | 214 | depends on X86_32 |
8f9ca475 | 215 | ---help--- |
96daa8cd | 216 | Select this for AMD Geode GX and LX processors. |
f90b8116 | 217 | |
96d55b88 PBG |
218 | config MCYRIXIII |
219 | bool "CyrixIII/VIA-C3" | |
1032c0ba | 220 | depends on X86_32 |
8f9ca475 | 221 | ---help--- |
96d55b88 PBG |
222 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
223 | treat this chip as a generic 586. Whilst the CPU is 686 class, | |
224 | it lacks the cmov extension which gcc assumes is present when | |
225 | generating 686 code. | |
226 | Note that Nehemiah (Model 9) and above will not boot with this | |
227 | kernel due to them lacking the 3DNow! instructions used in earlier | |
228 | incarnations of the CPU. | |
229 | ||
230 | config MVIAC3_2 | |
231 | bool "VIA C3-2 (Nehemiah)" | |
1032c0ba | 232 | depends on X86_32 |
8f9ca475 | 233 | ---help--- |
96d55b88 PBG |
234 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
235 | of SSE and tells gcc to treat the CPU as a 686. | |
236 | Note, this kernel will not boot on older (pre model 9) C3s. | |
237 | ||
0949be35 SA |
238 | config MVIAC7 |
239 | bool "VIA C7" | |
1032c0ba | 240 | depends on X86_32 |
8f9ca475 | 241 | ---help--- |
0949be35 SA |
242 | Select this for a VIA C7. Selecting this uses the correct cache |
243 | shift and tells gcc to treat the CPU as a 686. | |
244 | ||
1032c0ba SR |
245 | config MPSC |
246 | bool "Intel P4 / older Netburst based Xeon" | |
247 | depends on X86_64 | |
8f9ca475 | 248 | ---help--- |
1032c0ba SR |
249 | Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
250 | Xeon CPUs with Intel 64bit which is compatible with x86-64. | |
251 | Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the | |
96daa8cd | 252 | Netburst core and shouldn't use this option. You can distinguish them |
1032c0ba SR |
253 | using the cpu family field |
254 | in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. | |
255 | ||
256 | config MCORE2 | |
257 | bool "Core 2/newer Xeon" | |
8f9ca475 | 258 | ---help--- |
36723bfe BP |
259 | |
260 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and | |
261 | 53xx) CPUs. You can distinguish newer from older Xeons by the CPU | |
262 | family in /proc/cpuinfo. Newer ones have 6 and older ones 15 | |
263 | (not a typo) | |
1032c0ba | 264 | |
366d19e1 TD |
265 | config MATOM |
266 | bool "Intel Atom" | |
267 | ---help--- | |
268 | ||
269 | Select this for the Intel Atom platform. Intel Atom CPUs have an | |
270 | in-order pipelining architecture and thus can benefit from | |
271 | accordingly optimized code. Use a recent GCC with specific Atom | |
272 | support in order to fully benefit from selecting this option. | |
273 | ||
1032c0ba SR |
274 | config GENERIC_CPU |
275 | bool "Generic-x86-64" | |
276 | depends on X86_64 | |
8f9ca475 | 277 | ---help--- |
1032c0ba SR |
278 | Generic x86-64 CPU. |
279 | Run equally well on all x86-64 CPUs. | |
280 | ||
96d55b88 PBG |
281 | endchoice |
282 | ||
283 | config X86_GENERIC | |
1032c0ba SR |
284 | bool "Generic x86 support" |
285 | depends on X86_32 | |
8f9ca475 | 286 | ---help--- |
96d55b88 PBG |
287 | Instead of just including optimizations for the selected |
288 | x86 variant (e.g. PII, Crusoe or Athlon), include some more | |
289 | generic optimizations as well. This will make the kernel | |
290 | perform better on x86 CPUs other than that selected. | |
291 | ||
292 | This is really intended for distributors who need more | |
293 | generic optimizations. | |
294 | ||
295 | endif | |
296 | ||
acbaa93e IM |
297 | config X86_CPU |
298 | def_bool y | |
299 | select GENERIC_FIND_FIRST_BIT | |
300 | select GENERIC_FIND_NEXT_BIT | |
301 | ||
96d55b88 PBG |
302 | # |
303 | # Define implied options from the CPU selection here | |
350f8f56 | 304 | config X86_INTERNODE_CACHE_SHIFT |
1032c0ba | 305 | int |
350f8f56 JB |
306 | default "12" if X86_VSMP |
307 | default "7" if NUMA | |
308 | default X86_L1_CACHE_SHIFT | |
1032c0ba | 309 | |
96d55b88 | 310 | config X86_CMPXCHG |
1032c0ba | 311 | def_bool X86_64 || (X86_32 && !M386) |
96d55b88 | 312 | |
96d55b88 PBG |
313 | config X86_L1_CACHE_SHIFT |
314 | int | |
0a2a18b7 | 315 | default "7" if MPENTIUM4 || MPSC |
350f8f56 | 316 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
f90b8116 | 317 | default "4" if X86_ELAN || M486 || M386 || MGEODEGX1 |
69d45dd1 | 318 | default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
96d55b88 | 319 | |
c7f81c94 | 320 | config X86_XADD |
96daa8cd | 321 | def_bool y |
1032c0ba | 322 | depends on X86_32 && !M386 |
96d55b88 PBG |
323 | |
324 | config X86_PPRO_FENCE | |
fb0328e2 | 325 | bool "PentiumPro memory ordering errata workaround" |
96d55b88 | 326 | depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 |
8f9ca475 | 327 | ---help--- |
36723bfe BP |
328 | Old PentiumPro multiprocessor systems had errata that could cause |
329 | memory operations to violate the x86 ordering standard in rare cases. | |
330 | Enabling this option will attempt to work around some (but not all) | |
331 | occurances of this problem, at the cost of much heavier spinlock and | |
332 | memory barrier operations. | |
333 | ||
334 | If unsure, say n here. Even distro kernels should think twice before | |
335 | enabling this: there are few systems, and an unlikely bug. | |
96d55b88 PBG |
336 | |
337 | config X86_F00F_BUG | |
96daa8cd | 338 | def_bool y |
96d55b88 | 339 | depends on M586MMX || M586TSC || M586 || M486 || M386 |
96d55b88 PBG |
340 | |
341 | config X86_WP_WORKS_OK | |
96daa8cd | 342 | def_bool y |
293e6a25 | 343 | depends on !M386 |
96d55b88 PBG |
344 | |
345 | config X86_INVLPG | |
96daa8cd | 346 | def_bool y |
1032c0ba | 347 | depends on X86_32 && !M386 |
96d55b88 PBG |
348 | |
349 | config X86_BSWAP | |
96daa8cd | 350 | def_bool y |
1032c0ba | 351 | depends on X86_32 && !M386 |
96d55b88 PBG |
352 | |
353 | config X86_POPAD_OK | |
96daa8cd | 354 | def_bool y |
1032c0ba | 355 | depends on X86_32 && !M386 |
96d55b88 | 356 | |
96d55b88 | 357 | config X86_ALIGNMENT_16 |
96daa8cd | 358 | def_bool y |
69d45dd1 | 359 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1 |
96d55b88 | 360 | |
96d55b88 | 361 | config X86_INTEL_USERCOPY |
96daa8cd | 362 | def_bool y |
c55d92d1 | 363 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
96d55b88 PBG |
364 | |
365 | config X86_USE_PPRO_CHECKSUM | |
96daa8cd | 366 | def_bool y |
366d19e1 | 367 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
96d55b88 PBG |
368 | |
369 | config X86_USE_3DNOW | |
96daa8cd | 370 | def_bool y |
1b4ad242 | 371 | depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML |
96d55b88 PBG |
372 | |
373 | config X86_OOSTORE | |
96daa8cd | 374 | def_bool y |
69d45dd1 | 375 | depends on (MWINCHIP3D || MWINCHIPC6) && MTRR |
96d55b88 | 376 | |
959b3be6 PA |
377 | # |
378 | # P6_NOPs are a relatively minor optimization that require a family >= | |
379 | # 6 processor, except that it is broken on certain VIA chips. | |
380 | # Furthermore, AMD chips prefer a totally different sequence of NOPs | |
14469a8d LT |
381 | # (which work on all CPUs). In addition, it looks like Virtual PC |
382 | # does not understand them. | |
383 | # | |
384 | # As a result, disallow these if we're not compiling for X86_64 (these | |
385 | # NOPs do work on all x86-64 capable chips); the list of processors in | |
386 | # the right-hand clause are the cores that benefit from this optimization. | |
959b3be6 | 387 | # |
7343b3b3 PA |
388 | config X86_P6_NOP |
389 | def_bool y | |
14469a8d LT |
390 | depends on X86_64 |
391 | depends on (MCORE2 || MPENTIUM4 || MPSC) | |
7343b3b3 | 392 | |
96d55b88 | 393 | config X86_TSC |
96daa8cd | 394 | def_bool y |
366d19e1 | 395 | depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64 |
c7f81c94 | 396 | |
f8096f92 JB |
397 | config X86_CMPXCHG64 |
398 | def_bool y | |
db677ffa | 399 | depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM |
f8096f92 | 400 | |
c7f81c94 AK |
401 | # this should be set for all -march=.. options where the compiler |
402 | # generates cmov. | |
403 | config X86_CMOV | |
96daa8cd | 404 | def_bool y |
98059e34 | 405 | depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
c7f81c94 | 406 | |
de32e041 | 407 | config X86_MINIMUM_CPU_FAMILY |
c7f81c94 | 408 | int |
1032c0ba | 409 | default "64" if X86_64 |
7343b3b3 | 410 | default "6" if X86_32 && X86_P6_NOP |
982d007a | 411 | default "5" if X86_32 && X86_CMPXCHG64 |
1032c0ba | 412 | default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK) |
de32e041 | 413 | default "3" |
c7f81c94 | 414 | |
0a049bb0 | 415 | config X86_DEBUGCTLMSR |
96daa8cd | 416 | def_bool y |
5641f1fd | 417 | depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML |
8d02c211 TP |
418 | |
419 | menuconfig PROCESSOR_SELECT | |
8d02c211 | 420 | bool "Supported processor vendors" if EMBEDDED |
8f9ca475 | 421 | ---help--- |
8d02c211 TP |
422 | This lets you choose what x86 vendor support code your kernel |
423 | will include. | |
424 | ||
879d792b | 425 | config CPU_SUP_INTEL |
8d02c211 TP |
426 | default y |
427 | bool "Support Intel processors" if PROCESSOR_SELECT | |
8f9ca475 | 428 | ---help--- |
b7b3a425 IM |
429 | This enables detection, tunings and quirks for Intel processors |
430 | ||
431 | You need this enabled if you want your kernel to run on an | |
432 | Intel CPU. Disabling this option on other types of CPUs | |
433 | makes the kernel a tiny bit smaller. Disabling it on an Intel | |
434 | CPU might render the kernel unbootable. | |
435 | ||
436 | If unsure, say N. | |
8d02c211 TP |
437 | |
438 | config CPU_SUP_CYRIX_32 | |
439 | default y | |
440 | bool "Support Cyrix processors" if PROCESSOR_SELECT | |
441 | depends on !64BIT | |
8f9ca475 | 442 | ---help--- |
b7b3a425 IM |
443 | This enables detection, tunings and quirks for Cyrix processors |
444 | ||
445 | You need this enabled if you want your kernel to run on a | |
446 | Cyrix CPU. Disabling this option on other types of CPUs | |
447 | makes the kernel a tiny bit smaller. Disabling it on a Cyrix | |
448 | CPU might render the kernel unbootable. | |
449 | ||
450 | If unsure, say N. | |
8d02c211 | 451 | |
ff73152c | 452 | config CPU_SUP_AMD |
8d02c211 TP |
453 | default y |
454 | bool "Support AMD processors" if PROCESSOR_SELECT | |
8f9ca475 | 455 | ---help--- |
b7b3a425 IM |
456 | This enables detection, tunings and quirks for AMD processors |
457 | ||
458 | You need this enabled if you want your kernel to run on an | |
459 | AMD CPU. Disabling this option on other types of CPUs | |
460 | makes the kernel a tiny bit smaller. Disabling it on an AMD | |
461 | CPU might render the kernel unbootable. | |
462 | ||
463 | If unsure, say N. | |
8d02c211 | 464 | |
48f4c485 | 465 | config CPU_SUP_CENTAUR |
8d02c211 TP |
466 | default y |
467 | bool "Support Centaur processors" if PROCESSOR_SELECT | |
8f9ca475 | 468 | ---help--- |
b7b3a425 IM |
469 | This enables detection, tunings and quirks for Centaur processors |
470 | ||
471 | You need this enabled if you want your kernel to run on a | |
472 | Centaur CPU. Disabling this option on other types of CPUs | |
473 | makes the kernel a tiny bit smaller. Disabling it on a Centaur | |
474 | CPU might render the kernel unbootable. | |
475 | ||
476 | If unsure, say N. | |
8d02c211 TP |
477 | |
478 | config CPU_SUP_TRANSMETA_32 | |
479 | default y | |
480 | bool "Support Transmeta processors" if PROCESSOR_SELECT | |
481 | depends on !64BIT | |
8f9ca475 | 482 | ---help--- |
b7b3a425 IM |
483 | This enables detection, tunings and quirks for Transmeta processors |
484 | ||
485 | You need this enabled if you want your kernel to run on a | |
486 | Transmeta CPU. Disabling this option on other types of CPUs | |
487 | makes the kernel a tiny bit smaller. Disabling it on a Transmeta | |
488 | CPU might render the kernel unbootable. | |
489 | ||
490 | If unsure, say N. | |
8d02c211 TP |
491 | |
492 | config CPU_SUP_UMC_32 | |
493 | default y | |
494 | bool "Support UMC processors" if PROCESSOR_SELECT | |
495 | depends on !64BIT | |
8f9ca475 | 496 | ---help--- |
b7b3a425 IM |
497 | This enables detection, tunings and quirks for UMC processors |
498 | ||
499 | You need this enabled if you want your kernel to run on a | |
500 | UMC CPU. Disabling this option on other types of CPUs | |
501 | makes the kernel a tiny bit smaller. Disabling it on a UMC | |
502 | CPU might render the kernel unbootable. | |
503 | ||
504 | If unsure, say N. | |
81faaae4 | 505 | |
93fa7636 | 506 | config X86_DS |
531f6ed7 MM |
507 | def_bool X86_PTRACE_BTS |
508 | depends on X86_DEBUGCTLMSR | |
1e9b51c2 | 509 | select HAVE_HW_BRANCH_TRACER |
93fa7636 MM |
510 | |
511 | config X86_PTRACE_BTS | |
531f6ed7 | 512 | bool "Branch Trace Store" |
93fa7636 | 513 | default y |
531f6ed7 | 514 | depends on X86_DEBUGCTLMSR |
d45b41ae | 515 | depends on BROKEN |
8f9ca475 | 516 | ---help--- |
531f6ed7 MM |
517 | This adds a ptrace interface to the hardware's branch trace store. |
518 | ||
519 | Debuggers may use it to collect an execution trace of the debugged | |
520 | application in order to answer the question 'how did I get here?'. | |
521 | Debuggers may trace user mode as well as kernel mode. | |
522 | ||
523 | Say Y unless there is no application development on this machine | |
524 | and you want to save a small amount of code size. |