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[linux.git] / drivers / iommu / amd_iommu_init.c
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f6e2e6b6 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <[email protected]>
f6e2e6b6
JR		 4 * Leo Duran <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
f6e2e6b6 22#include <linux/list.h>
5c87f62d 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
f3c6ea1b 25#include <linux/syscore_ops.h>
a80dc3e0
JR		 26#include <linux/interrupt.h>
27#include <linux/msi.h>
403f81d8 28#include <linux/amd-iommu.h>
400a28a0 29#include <linux/export.h>
066f2e98 30#include <linux/iommu.h>
ebcfa284 31#include <linux/kmemleak.h>
54bd6357 32#include <linux/crash_dump.h>
f6e2e6b6 33#include <asm/pci-direct.h>
46a7fa27 34#include <asm/iommu.h>
1d9b16d1 35#include <asm/gart.h>
ea1b0d39 36#include <asm/x86_init.h>
22e6daf4 37#include <asm/iommu_table.h>
eb1eb7ae 38#include <asm/io_apic.h>
6b474b82 39#include <asm/irq_remapping.h>
403f81d8
JR		 40
41#include "amd_iommu_proto.h"
42#include "amd_iommu_types.h"
05152a04 43#include "irq_remapping.h"
403f81d8 44
f6e2e6b6
JR		 45/*
46 * definitions for the ACPI scanning code
47 */
f6e2e6b6 48#define IVRS_HEADER_LENGTH 48
f6e2e6b6 49
8c7142f5 50#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
f6e2e6b6
JR		 51#define ACPI_IVMD_TYPE_ALL 0x20
52#define ACPI_IVMD_TYPE 0x21
53#define ACPI_IVMD_TYPE_RANGE 0x22
54
55#define IVHD_DEV_ALL 0x01
56#define IVHD_DEV_SELECT 0x02
57#define IVHD_DEV_SELECT_RANGE_START 0x03
58#define IVHD_DEV_RANGE_END 0x04
59#define IVHD_DEV_ALIAS 0x42
60#define IVHD_DEV_ALIAS_RANGE 0x43
61#define IVHD_DEV_EXT_SELECT 0x46
62#define IVHD_DEV_EXT_SELECT_RANGE 0x47
6efed63b 63#define IVHD_DEV_SPECIAL 0x48
8c7142f5 64#define IVHD_DEV_ACPI_HID 0xf0
6efed63b 65
2a0cb4e2
WZ		 66#define UID_NOT_PRESENT 0
67#define UID_IS_INTEGER 1
68#define UID_IS_CHARACTER 2
69
6efed63b
JR		 70#define IVHD_SPECIAL_IOAPIC 1
71#define IVHD_SPECIAL_HPET 2
f6e2e6b6 72
6da7342f
JR		 73#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
74#define IVHD_FLAG_PASSPW_EN_MASK 0x02
75#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
76#define IVHD_FLAG_ISOC_EN_MASK 0x08
f6e2e6b6
JR		 77
78#define IVMD_FLAG_EXCL_RANGE 0x08
79#define IVMD_FLAG_UNITY_MAP 0x01
80
81#define ACPI_DEVFLAG_INITPASS 0x01
82#define ACPI_DEVFLAG_EXTINT 0x02
83#define ACPI_DEVFLAG_NMI 0x04
84#define ACPI_DEVFLAG_SYSMGT1 0x10
85#define ACPI_DEVFLAG_SYSMGT2 0x20
86#define ACPI_DEVFLAG_LINT0 0x40
87#define ACPI_DEVFLAG_LINT1 0x80
88#define ACPI_DEVFLAG_ATSDIS 0x10000000
89
8bda0cfb 90#define LOOP_TIMEOUT 100000
b65233a9
JR		 91/*
92 * ACPI table definitions
93 *
94 * These data structures are laid over the table to parse the important values
95 * out of it.
96 */
97
b0119e87
JR		 98extern const struct iommu_ops amd_iommu_ops;
99
b65233a9
JR		 100/*
101 * structure describing one IOMMU in the ACPI table. Typically followed by one
102 * or more ivhd_entrys.
103 */
f6e2e6b6
JR		 104struct ivhd_header {
105 u8 type;
106 u8 flags;
107 u16 length;
108 u16 devid;
109 u16 cap_ptr;
110 u64 mmio_phys;
111 u16 pci_seg;
112 u16 info;
7d7d38af
SS		 113 u32 efr_attr;
114
115 /* Following only valid on IVHD type 11h and 40h */
116 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
117 u64 res;
f6e2e6b6
JR		 118} __attribute__((packed));
119
b65233a9
JR		 120/*
121 * A device entry describing which devices a specific IOMMU translates and
122 * which requestor ids they use.
123 */
f6e2e6b6
JR		 124struct ivhd_entry {
125 u8 type;
126 u16 devid;
127 u8 flags;
128 u32 ext;
2a0cb4e2
WZ		 129 u32 hidh;
130 u64 cid;
131 u8 uidf;
132 u8 uidl;
133 u8 uid;
f6e2e6b6
JR		 134} __attribute__((packed));
135
b65233a9
JR		 136/*
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
138 * ranges for devices and regions that should be unity mapped.
139 */
f6e2e6b6
JR		 140struct ivmd_header {
141 u8 type;
142 u8 flags;
143 u16 length;
144 u16 devid;
145 u16 aux;
146 u64 resv;
147 u64 range_start;
148 u64 range_length;
149} __attribute__((packed));
150
fefda117 151bool amd_iommu_dump;
05152a04 152bool amd_iommu_irq_remap __read_mostly;
fefda117 153
d98de49a 154int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
3928aa3f 155
02f3b3f5 156static bool amd_iommu_detected;
a5235725 157static bool __initdata amd_iommu_disabled;
8c7142f5 158static int amd_iommu_target_ivhd_type;
c1cbebee 159
b65233a9
JR		 160u16 amd_iommu_last_bdf; /* largest PCI device id we have
161 to handle */
2e22847f 162LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
b65233a9 163 we find in ACPI */
621a5f7a 164bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
928abd25 165
2e22847f 166LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
b65233a9 167 system */
928abd25 168
bb52777e
JR		 169/* Array to assign indices to IOMMUs*/
170struct amd_iommu *amd_iommus[MAX_IOMMUS];
6b9376e3
SS		 171
172/* Number of IOMMUs present in the system */
173static int amd_iommus_present;
bb52777e 174
318afd41
JR		 175/* IOMMUs have a non-present cache? */
176bool amd_iommu_np_cache __read_mostly;
60f723b4 177bool amd_iommu_iotlb_sup __read_mostly = true;
318afd41 178
a919a018 179u32 amd_iommu_max_pasid __read_mostly = ~0;
62f71abb 180
400a28a0 181bool amd_iommu_v2_present __read_mostly;
4160cd9e 182static bool amd_iommu_pc_present __read_mostly;
400a28a0 183
5abcdba4
JR		 184bool amd_iommu_force_isolation __read_mostly;
185
aeb26f55
JR		 186/*
187 * List of protection domains - used during resume
188 */
189LIST_HEAD(amd_iommu_pd_list);
190spinlock_t amd_iommu_pd_lock;
191
b65233a9
JR		 192/*
193 * Pointer to the device table which is shared by all AMD IOMMUs
194 * it is indexed by the PCI device id or the HT unit id and contains
195 * information about the domain the device belongs to as well as the
196 * page table root pointer.
197 */
928abd25 198struct dev_table_entry *amd_iommu_dev_table;
b65233a9
JR		 199
200/*
201 * The alias table is a driver specific data structure which contains the
202 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
203 * More than one device can share the same requestor id.
204 */
928abd25 205u16 *amd_iommu_alias_table;
b65233a9
JR		 206
207/*
208 * The rlookup table is used to find the IOMMU which is responsible
209 * for a specific device. It is also indexed by the PCI device id.
210 */
928abd25 211struct amd_iommu **amd_iommu_rlookup_table;
b65233a9 212
b65233a9 213/*
0ea2c422
JR		 214 * This table is used to find the irq remapping table for a given device id
215 * quickly.
216 */
217struct irq_remap_table **irq_lookup_table;
218
b65233a9 219/*
df805abb 220 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
b65233a9
JR		 221 * to know which ones are already in use.
222 */
928abd25
JR		 223unsigned long *amd_iommu_pd_alloc_bitmap;
224
b65233a9
JR		 225static u32 dev_table_size; /* size of the device table */
226static u32 alias_table_size; /* size of the alias table */
227static u32 rlookup_table_size; /* size if the rlookup table */
3e8064ba 228
2c0ae172
JR		 229enum iommu_init_state {
230 IOMMU_START_STATE,
231 IOMMU_IVRS_DETECTED,
232 IOMMU_ACPI_FINISHED,
233 IOMMU_ENABLED,
234 IOMMU_PCI_INIT,
235 IOMMU_INTERRUPTS_EN,
236 IOMMU_DMA_OPS,
237 IOMMU_INITIALIZED,
238 IOMMU_NOT_FOUND,
239 IOMMU_INIT_ERROR,
1b1e942e 240 IOMMU_CMDLINE_DISABLED,
2c0ae172
JR		 241};
242
235dacbc
JR		 243/* Early ioapic and hpet maps from kernel command line */
244#define EARLY_MAP_SIZE 4
245static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
246static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
2a0cb4e2
WZ		 247static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
248
235dacbc
JR		 249static int __initdata early_ioapic_map_size;
250static int __initdata early_hpet_map_size;
2a0cb4e2
WZ		 251static int __initdata early_acpihid_map_size;
252
dfbb6d47 253static bool __initdata cmdline_maps;
235dacbc 254
2c0ae172
JR		 255static enum iommu_init_state init_state = IOMMU_START_STATE;
256
ae295142 257static int amd_iommu_enable_interrupts(void);
2c0ae172 258static int __init iommu_go_to_state(enum iommu_init_state state);
aafd8ba0 259static void init_device_table_dma(void);
3d9761e7 260
208ec8c9
JR		 261static inline void update_last_devid(u16 devid)
262{
263 if (devid > amd_iommu_last_bdf)
264 amd_iommu_last_bdf = devid;
265}
266
c571484e
JR		 267static inline unsigned long tbl_size(int entry_size)
268{
269 unsigned shift = PAGE_SHIFT +
421f909c 270 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
c571484e
JR		 271
272 return 1UL << shift;
273}
274
6b9376e3
SS		 275int amd_iommu_get_num_iommus(void)
276{
277 return amd_iommus_present;
278}
279
5bcd757f
MG		 280/* Access to l1 and l2 indexed register spaces */
281
282static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
283{
284 u32 val;
285
286 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
287 pci_read_config_dword(iommu->dev, 0xfc, &val);
288 return val;
289}
290
291static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
292{
293 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
294 pci_write_config_dword(iommu->dev, 0xfc, val);
295 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
296}
297
298static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
299{
300 u32 val;
301
302 pci_write_config_dword(iommu->dev, 0xf0, address);
303 pci_read_config_dword(iommu->dev, 0xf4, &val);
304 return val;
305}
306
307static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
308{
309 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
310 pci_write_config_dword(iommu->dev, 0xf4, val);
311}
312
b65233a9
JR		 313/****************************************************************************
314 *
315 * AMD IOMMU MMIO register space handling functions
316 *
317 * These functions are used to program the IOMMU device registers in
318 * MMIO space required for that driver.
319 *
320 ****************************************************************************/
3e8064ba 321
b65233a9
JR		 322/*
323 * This function set the exclusion range in the IOMMU. DMA accesses to the
324 * exclusion range are passed through untranslated
325 */
05f92db9 326static void iommu_set_exclusion_range(struct amd_iommu *iommu)
b2026aa2
JR		 327{
328 u64 start = iommu->exclusion_start & PAGE_MASK;
329 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
330 u64 entry;
331
332 if (!iommu->exclusion_start)
333 return;
334
335 entry = start | MMIO_EXCL_ENABLE_MASK;
336 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
337 &entry, sizeof(entry));
338
339 entry = limit;
340 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
341 &entry, sizeof(entry));
342}
343
b65233a9 344/* Programs the physical address of the device table into the IOMMU hardware */
6b7f000e 345static void iommu_set_device_table(struct amd_iommu *iommu)
b2026aa2 346{
f609891f 347 u64 entry;
b2026aa2
JR		 348
349 BUG_ON(iommu->mmio_base == NULL);
350
351 entry = virt_to_phys(amd_iommu_dev_table);
352 entry |= (dev_table_size >> 12) - 1;
353 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
354 &entry, sizeof(entry));
355}
356
b65233a9 357/* Generic functions to enable/disable certain features of the IOMMU. */
05f92db9 358static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 359{
360 u32 ctrl;
361
362 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
363 ctrl |= (1 << bit);
364 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
365}
366
ca020711 367static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 368{
369 u32 ctrl;
370
199d0d50 371 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
b2026aa2
JR		 372 ctrl &= ~(1 << bit);
373 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
374}
375
1456e9d2
JR		 376static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
377{
378 u32 ctrl;
379
380 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
381 ctrl &= ~CTRL_INV_TO_MASK;
382 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
383 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
384}
385
b65233a9 386/* Function to enable the hardware */
05f92db9 387static void iommu_enable(struct amd_iommu *iommu)
b2026aa2 388{
b2026aa2 389 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
b2026aa2
JR		 390}
391
92ac4320 392static void iommu_disable(struct amd_iommu *iommu)
126c52be 393{
a8c485bb
CW		 394 /* Disable command buffer */
395 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
396
397 /* Disable event logging and event interrupts */
398 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
399 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
400
8bda0cfb
SS		 401 /* Disable IOMMU GA_LOG */
402 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
403 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
404
a8c485bb 405 /* Disable IOMMU hardware itself */
92ac4320 406 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
126c52be
JR		 407}
408
b65233a9
JR		 409/*
410 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
411 * the system has one.
412 */
30861ddc 413static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
6c56747b 414{
30861ddc
SK		 415 if (!request_mem_region(address, end, "amd_iommu")) {
416 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
417 address, end);
e82752d8 418 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
6c56747b 419 return NULL;
e82752d8 420 }
6c56747b 421
30861ddc 422 return (u8 __iomem *)ioremap_nocache(address, end);
6c56747b
JR		 423}
424
425static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
426{
427 if (iommu->mmio_base)
428 iounmap(iommu->mmio_base);
30861ddc 429 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
6c56747b
JR		 430}
431
ac7ccf67
SS		 432static inline u32 get_ivhd_header_size(struct ivhd_header *h)
433{
434 u32 size = 0;
435
436 switch (h->type) {
437 case 0x10:
438 size = 24;
439 break;
440 case 0x11:
441 case 0x40:
442 size = 40;
443 break;
444 }
445 return size;
446}
447
b65233a9
JR		 448/****************************************************************************
449 *
450 * The functions below belong to the first pass of AMD IOMMU ACPI table
451 * parsing. In this pass we try to find out the highest device id this
452 * code has to handle. Upon this information the size of the shared data
453 * structures is determined later.
454 *
455 ****************************************************************************/
456
b514e555
JR		 457/*
458 * This function calculates the length of a given IVHD entry
459 */
460static inline int ivhd_entry_length(u8 *ivhd)
461{
8c7142f5
SS		 462 u32 type = ((struct ivhd_entry *)ivhd)->type;
463
464 if (type < 0x80) {
465 return 0x04 << (*ivhd >> 6);
466 } else if (type == IVHD_DEV_ACPI_HID) {
467 /* For ACPI_HID, offset 21 is uid len */
468 return *((u8 *)ivhd + 21) + 22;
469 }
470 return 0;
b514e555
JR		 471}
472
b65233a9
JR		 473/*
474 * After reading the highest device id from the IOMMU PCI capability header
475 * this function looks if there is a higher device id defined in the ACPI table
476 */
3e8064ba
JR		 477static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
478{
479 u8 *p = (void *)h, *end = (void *)h;
480 struct ivhd_entry *dev;
481
ac7ccf67
SS		 482 u32 ivhd_size = get_ivhd_header_size(h);
483
484 if (!ivhd_size) {
485 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
486 return -EINVAL;
487 }
488
489 p += ivhd_size;
3e8064ba
JR		 490 end += h->length;
491
3e8064ba
JR		 492 while (p < end) {
493 dev = (struct ivhd_entry *)p;
494 switch (dev->type) {
d1259416
JR		 495 case IVHD_DEV_ALL:
496 /* Use maximum BDF value for DEV_ALL */
497 update_last_devid(0xffff);
498 break;
3e8064ba
JR		 499 case IVHD_DEV_SELECT:
500 case IVHD_DEV_RANGE_END:
501 case IVHD_DEV_ALIAS:
502 case IVHD_DEV_EXT_SELECT:
b65233a9 503 /* all the above subfield types refer to device ids */
208ec8c9 504 update_last_devid(dev->devid);
3e8064ba
JR		 505 break;
506 default:
507 break;
508 }
b514e555 509 p += ivhd_entry_length(p);
3e8064ba
JR		 510 }
511
512 WARN_ON(p != end);
513
514 return 0;
515}
516
8c7142f5
SS		 517static int __init check_ivrs_checksum(struct acpi_table_header *table)
518{
519 int i;
520 u8 checksum = 0, *p = (u8 *)table;
521
522 for (i = 0; i < table->length; ++i)
523 checksum += p[i];
524 if (checksum != 0) {
525 /* ACPI table corrupt */
526 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
527 return -ENODEV;
528 }
529
530 return 0;
531}
532
b65233a9
JR		 533/*
534 * Iterate over all IVHD entries in the ACPI table and find the highest device
535 * id which we need to handle. This is the first of three functions which parse
536 * the ACPI table. So we check the checksum here.
537 */
3e8064ba
JR		 538static int __init find_last_devid_acpi(struct acpi_table_header *table)
539{
8c7142f5 540 u8 *p = (u8 *)table, *end = (u8 *)table;
3e8064ba
JR		 541 struct ivhd_header *h;
542
3e8064ba
JR		 543 p += IVRS_HEADER_LENGTH;
544
545 end += table->length;
546 while (p < end) {
547 h = (struct ivhd_header *)p;
8c7142f5
SS		 548 if (h->type == amd_iommu_target_ivhd_type) {
549 int ret = find_last_devid_from_ivhd(h);
550
551 if (ret)
552 return ret;
3e8064ba
JR		 553 }
554 p += h->length;
555 }
556 WARN_ON(p != end);
557
558 return 0;
559}
560
b65233a9
JR		 561/****************************************************************************
562 *
df805abb 563 * The following functions belong to the code path which parses the ACPI table
b65233a9
JR		 564 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
565 * data structures, initialize the device/alias/rlookup table and also
566 * basically initialize the hardware.
567 *
568 ****************************************************************************/
569
570/*
571 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
572 * write commands to that buffer later and the IOMMU will execute them
573 * asynchronously
574 */
f2c2db53 575static int __init alloc_command_buffer(struct amd_iommu *iommu)
b36ca91e 576{
f2c2db53
JR		 577 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
578 get_order(CMD_BUFFER_SIZE));
b36ca91e 579
f2c2db53 580 return iommu->cmd_buf ? 0 : -ENOMEM;
58492e12
JR		 581}
582
93f1cc67
JR		 583/*
584 * This function resets the command buffer if the IOMMU stopped fetching
585 * commands from it.
586 */
587void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
588{
589 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
590
591 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
592 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
d334a563
TL		 593 iommu->cmd_buf_head = 0;
594 iommu->cmd_buf_tail = 0;
93f1cc67
JR		 595
596 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
597}
598
58492e12
JR		 599/*
600 * This function writes the command buffer address to the hardware and
601 * enables it.
602 */
603static void iommu_enable_command_buffer(struct amd_iommu *iommu)
604{
605 u64 entry;
606
607 BUG_ON(iommu->cmd_buf == NULL);
608
609 entry = (u64)virt_to_phys(iommu->cmd_buf);
b36ca91e 610 entry |= MMIO_CMD_SIZE_512;
58492e12 611
b36ca91e 612 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
58492e12 613 &entry, sizeof(entry));
b36ca91e 614
93f1cc67 615 amd_iommu_reset_cmd_buffer(iommu);
b36ca91e
JR		 616}
617
618static void __init free_command_buffer(struct amd_iommu *iommu)
619{
deba4bce 620 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
b36ca91e
JR		 621}
622
335503e5 623/* allocates the memory where the IOMMU will log its events to */
f2c2db53 624static int __init alloc_event_buffer(struct amd_iommu *iommu)
335503e5 625{
f2c2db53
JR		 626 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
627 get_order(EVT_BUFFER_SIZE));
335503e5 628
f2c2db53 629 return iommu->evt_buf ? 0 : -ENOMEM;
58492e12
JR		 630}
631
632static void iommu_enable_event_buffer(struct amd_iommu *iommu)
633{
634 u64 entry;
635
636 BUG_ON(iommu->evt_buf == NULL);
637
335503e5 638 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
58492e12 639
335503e5
JR		 640 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
641 &entry, sizeof(entry));
642
09067207
JR		 643 /* set head and tail to zero manually */
644 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
645 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
646
58492e12 647 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
335503e5
JR		 648}
649
650static void __init free_event_buffer(struct amd_iommu *iommu)
651{
652 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
653}
654
1a29ac01 655/* allocates the memory where the IOMMU will log its events to */
f2c2db53 656static int __init alloc_ppr_log(struct amd_iommu *iommu)
1a29ac01 657{
f2c2db53
JR		 658 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
659 get_order(PPR_LOG_SIZE));
1a29ac01 660
f2c2db53 661 return iommu->ppr_log ? 0 : -ENOMEM;
1a29ac01
JR		 662}
663
664static void iommu_enable_ppr_log(struct amd_iommu *iommu)
665{
666 u64 entry;
667
668 if (iommu->ppr_log == NULL)
669 return;
670
671 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
672
673 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
674 &entry, sizeof(entry));
675
676 /* set head and tail to zero manually */
677 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
679
680 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
681 iommu_feature_enable(iommu, CONTROL_PPR_EN);
682}
683
684static void __init free_ppr_log(struct amd_iommu *iommu)
685{
686 if (iommu->ppr_log == NULL)
687 return;
688
689 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
690}
691
8bda0cfb
SS		 692static void free_ga_log(struct amd_iommu *iommu)
693{
694#ifdef CONFIG_IRQ_REMAP
695 if (iommu->ga_log)
696 free_pages((unsigned long)iommu->ga_log,
697 get_order(GA_LOG_SIZE));
698 if (iommu->ga_log_tail)
699 free_pages((unsigned long)iommu->ga_log_tail,
700 get_order(8));
701#endif
702}
703
704static int iommu_ga_log_enable(struct amd_iommu *iommu)
705{
706#ifdef CONFIG_IRQ_REMAP
707 u32 status, i;
708
709 if (!iommu->ga_log)
710 return -EINVAL;
711
712 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
713
714 /* Check if already running */
715 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
716 return 0;
717
718 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
719 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
720
721 for (i = 0; i < LOOP_TIMEOUT; ++i) {
722 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
723 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
724 break;
725 }
726
727 if (i >= LOOP_TIMEOUT)
728 return -EINVAL;
729#endif /* CONFIG_IRQ_REMAP */
730 return 0;
731}
732
733#ifdef CONFIG_IRQ_REMAP
734static int iommu_init_ga_log(struct amd_iommu *iommu)
735{
736 u64 entry;
737
738 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
739 return 0;
740
741 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
742 get_order(GA_LOG_SIZE));
743 if (!iommu->ga_log)
744 goto err_out;
745
746 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
747 get_order(8));
748 if (!iommu->ga_log_tail)
749 goto err_out;
750
751 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
752 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
753 &entry, sizeof(entry));
754 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
755 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
756 &entry, sizeof(entry));
757 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
758 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
759
760 return 0;
761err_out:
762 free_ga_log(iommu);
763 return -EINVAL;
764}
765#endif /* CONFIG_IRQ_REMAP */
766
767static int iommu_init_ga(struct amd_iommu *iommu)
768{
769 int ret = 0;
770
771#ifdef CONFIG_IRQ_REMAP
772 /* Note: We have already checked GASup from IVRS table.
773 * Now, we need to make sure that GAMSup is set.
774 */
775 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
776 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
777 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
778
779 ret = iommu_init_ga_log(iommu);
780#endif /* CONFIG_IRQ_REMAP */
781
782 return ret;
783}
784
cbc33a90
JR		 785static void iommu_enable_gt(struct amd_iommu *iommu)
786{
787 if (!iommu_feature(iommu, FEATURE_GT))
788 return;
789
790 iommu_feature_enable(iommu, CONTROL_GT_EN);
791}
792
b65233a9 793/* sets a specific bit in the device table entry. */
3566b778
JR		 794static void set_dev_entry_bit(u16 devid, u8 bit)
795{
ee6c2868
JR		 796 int i = (bit >> 6) & 0x03;
797 int _bit = bit & 0x3f;
3566b778 798
ee6c2868 799 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
3566b778
JR		 800}
801
c5cca146
JR		 802static int get_dev_entry_bit(u16 devid, u8 bit)
803{
ee6c2868
JR		 804 int i = (bit >> 6) & 0x03;
805 int _bit = bit & 0x3f;
c5cca146 806
ee6c2868 807 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
c5cca146
JR		 808}
809
810
811void amd_iommu_apply_erratum_63(u16 devid)
812{
813 int sysmgt;
814
815 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
816 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
817
818 if (sysmgt == 0x01)
819 set_dev_entry_bit(devid, DEV_ENTRY_IW);
820}
821
5ff4789d
JR		 822/* Writes the specific IOMMU for a device into the rlookup table */
823static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
824{
825 amd_iommu_rlookup_table[devid] = iommu;
826}
827
b65233a9
JR		 828/*
829 * This function takes the device specific flags read from the ACPI
830 * table and sets up the device table entry with that information
831 */
5ff4789d
JR		 832static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
833 u16 devid, u32 flags, u32 ext_flags)
3566b778
JR		 834{
835 if (flags & ACPI_DEVFLAG_INITPASS)
836 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
837 if (flags & ACPI_DEVFLAG_EXTINT)
838 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
839 if (flags & ACPI_DEVFLAG_NMI)
840 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
841 if (flags & ACPI_DEVFLAG_SYSMGT1)
842 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
843 if (flags & ACPI_DEVFLAG_SYSMGT2)
844 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
845 if (flags & ACPI_DEVFLAG_LINT0)
846 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
847 if (flags & ACPI_DEVFLAG_LINT1)
848 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
3566b778 849
c5cca146
JR		 850 amd_iommu_apply_erratum_63(devid);
851
5ff4789d 852 set_iommu_for_device(iommu, devid);
3566b778
JR		 853}
854
c50e3247 855static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
6efed63b
JR		 856{
857 struct devid_map *entry;
858 struct list_head *list;
859
31cff67f
JR		 860 if (type == IVHD_SPECIAL_IOAPIC)
861 list = &ioapic_map;
862 else if (type == IVHD_SPECIAL_HPET)
863 list = &hpet_map;
864 else
6efed63b
JR		 865 return -EINVAL;
866
31cff67f
JR		 867 list_for_each_entry(entry, list, list) {
868 if (!(entry->id == id && entry->cmd_line))
869 continue;
870
871 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
872 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
873
c50e3247
JR		 874 *devid = entry->devid;
875
31cff67f
JR		 876 return 0;
877 }
878
6efed63b
JR		 879 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
880 if (!entry)
881 return -ENOMEM;
882
31cff67f 883 entry->id = id;
c50e3247 884 entry->devid = *devid;
31cff67f 885 entry->cmd_line = cmd_line;
6efed63b
JR		 886
887 list_add_tail(&entry->list, list);
888
889 return 0;
890}
891
2a0cb4e2
WZ		 892static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
893 bool cmd_line)
894{
895 struct acpihid_map_entry *entry;
896 struct list_head *list = &acpihid_map;
897
898 list_for_each_entry(entry, list, list) {
899 if (strcmp(entry->hid, hid) ||
900 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
901 !entry->cmd_line)
902 continue;
903
904 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
905 hid, uid);
906 *devid = entry->devid;
907 return 0;
908 }
909
910 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
911 if (!entry)
912 return -ENOMEM;
913
914 memcpy(entry->uid, uid, strlen(uid));
915 memcpy(entry->hid, hid, strlen(hid));
916 entry->devid = *devid;
917 entry->cmd_line = cmd_line;
918 entry->root_devid = (entry->devid & (~0x7));
919
920 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
921 entry->cmd_line ? "cmd" : "ivrs",
922 entry->hid, entry->uid, entry->root_devid);
923
924 list_add_tail(&entry->list, list);
925 return 0;
926}
927
235dacbc
JR		 928static int __init add_early_maps(void)
929{
930 int i, ret;
931
932 for (i = 0; i < early_ioapic_map_size; ++i) {
933 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
934 early_ioapic_map[i].id,
c50e3247 935 &early_ioapic_map[i].devid,
235dacbc
JR		 936 early_ioapic_map[i].cmd_line);
937 if (ret)
938 return ret;
939 }
940
941 for (i = 0; i < early_hpet_map_size; ++i) {
942 ret = add_special_device(IVHD_SPECIAL_HPET,
943 early_hpet_map[i].id,
c50e3247 944 &early_hpet_map[i].devid,
235dacbc
JR		 945 early_hpet_map[i].cmd_line);
946 if (ret)
947 return ret;
948 }
949
2a0cb4e2
WZ		 950 for (i = 0; i < early_acpihid_map_size; ++i) {
951 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
952 early_acpihid_map[i].uid,
953 &early_acpihid_map[i].devid,
954 early_acpihid_map[i].cmd_line);
955 if (ret)
956 return ret;
957 }
958
235dacbc
JR		 959 return 0;
960}
961
b65233a9 962/*
df805abb 963 * Reads the device exclusion range from ACPI and initializes the IOMMU with
b65233a9
JR		 964 * it
965 */
3566b778
JR		 966static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
967{
968 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
969
970 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
971 return;
972
973 if (iommu) {
b65233a9
JR		 974 /*
975 * We only can configure exclusion ranges per IOMMU, not
976 * per device. But we can enable the exclusion range per
977 * device. This is done here
978 */
2c16c9fd 979 set_dev_entry_bit(devid, DEV_ENTRY_EX);
3566b778
JR		 980 iommu->exclusion_start = m->range_start;
981 iommu->exclusion_length = m->range_length;
982 }
983}
984
b65233a9
JR		 985/*
986 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
987 * initializes the hardware and our data structures with it.
988 */
6efed63b 989static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
5d0c8e49
JR		 990 struct ivhd_header *h)
991{
992 u8 *p = (u8 *)h;
993 u8 *end = p, flags = 0;
0de66d5b
JR		 994 u16 devid = 0, devid_start = 0, devid_to = 0;
995 u32 dev_i, ext_flags = 0;
58a3bee5 996 bool alias = false;
5d0c8e49 997 struct ivhd_entry *e;
ac7ccf67 998 u32 ivhd_size;
235dacbc
JR		 999 int ret;
1000
1001
1002 ret = add_early_maps();
1003 if (ret)
1004 return ret;
5d0c8e49
JR		 1005
1006 /*
e9bf5197 1007 * First save the recommended feature enable bits from ACPI
5d0c8e49 1008 */
e9bf5197 1009 iommu->acpi_flags = h->flags;
5d0c8e49
JR		 1010
1011 /*
1012 * Done. Now parse the device entries
1013 */
ac7ccf67
SS		 1014 ivhd_size = get_ivhd_header_size(h);
1015 if (!ivhd_size) {
1016 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1017 return -EINVAL;
1018 }
1019
1020 p += ivhd_size;
1021
5d0c8e49
JR		 1022 end += h->length;
1023
42a698f4 1024
5d0c8e49
JR		 1025 while (p < end) {
1026 e = (struct ivhd_entry *)p;
1027 switch (e->type) {
1028 case IVHD_DEV_ALL:
42a698f4 1029
226e889b 1030 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
42a698f4 1031
226e889b
JR		 1032 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1033 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
5d0c8e49
JR		 1034 break;
1035 case IVHD_DEV_SELECT:
42a698f4
JR		 1036
1037 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1038 "flags: %02x\n",
c5081cd7 1039 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1040 PCI_SLOT(e->devid),
1041 PCI_FUNC(e->devid),
1042 e->flags);
1043
5d0c8e49 1044 devid = e->devid;
5ff4789d 1045 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
5d0c8e49
JR		 1046 break;
1047 case IVHD_DEV_SELECT_RANGE_START:
42a698f4
JR		 1048
1049 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1050 "devid: %02x:%02x.%x flags: %02x\n",
c5081cd7 1051 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1052 PCI_SLOT(e->devid),
1053 PCI_FUNC(e->devid),
1054 e->flags);
1055
5d0c8e49
JR		 1056 devid_start = e->devid;
1057 flags = e->flags;
1058 ext_flags = 0;
58a3bee5 1059 alias = false;
5d0c8e49
JR		 1060 break;
1061 case IVHD_DEV_ALIAS:
42a698f4
JR		 1062
1063 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1064 "flags: %02x devid_to: %02x:%02x.%x\n",
c5081cd7 1065 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1066 PCI_SLOT(e->devid),
1067 PCI_FUNC(e->devid),
1068 e->flags,
c5081cd7 1069 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1070 PCI_SLOT(e->ext >> 8),
1071 PCI_FUNC(e->ext >> 8));
1072
5d0c8e49
JR		 1073 devid = e->devid;
1074 devid_to = e->ext >> 8;
7a6a3a08 1075 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
7455aab1 1076 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
5d0c8e49
JR		 1077 amd_iommu_alias_table[devid] = devid_to;
1078 break;
1079 case IVHD_DEV_ALIAS_RANGE:
42a698f4
JR		 1080
1081 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1082 "devid: %02x:%02x.%x flags: %02x "
1083 "devid_to: %02x:%02x.%x\n",
c5081cd7 1084 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1085 PCI_SLOT(e->devid),
1086 PCI_FUNC(e->devid),
1087 e->flags,
c5081cd7 1088 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1089 PCI_SLOT(e->ext >> 8),
1090 PCI_FUNC(e->ext >> 8));
1091
5d0c8e49
JR		 1092 devid_start = e->devid;
1093 flags = e->flags;
1094 devid_to = e->ext >> 8;
1095 ext_flags = 0;
58a3bee5 1096 alias = true;
5d0c8e49
JR		 1097 break;
1098 case IVHD_DEV_EXT_SELECT:
42a698f4
JR		 1099
1100 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1101 "flags: %02x ext: %08x\n",
c5081cd7 1102 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1103 PCI_SLOT(e->devid),
1104 PCI_FUNC(e->devid),
1105 e->flags, e->ext);
1106
5d0c8e49 1107 devid = e->devid;
5ff4789d
JR		 1108 set_dev_entry_from_acpi(iommu, devid, e->flags,
1109 e->ext);
5d0c8e49
JR		 1110 break;
1111 case IVHD_DEV_EXT_SELECT_RANGE:
42a698f4
JR		 1112
1113 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1114 "%02x:%02x.%x flags: %02x ext: %08x\n",
c5081cd7 1115 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1116 PCI_SLOT(e->devid),
1117 PCI_FUNC(e->devid),
1118 e->flags, e->ext);
1119
5d0c8e49
JR		 1120 devid_start = e->devid;
1121 flags = e->flags;
1122 ext_flags = e->ext;
58a3bee5 1123 alias = false;
5d0c8e49
JR		 1124 break;
1125 case IVHD_DEV_RANGE_END:
42a698f4
JR		 1126
1127 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
c5081cd7 1128 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1129 PCI_SLOT(e->devid),
1130 PCI_FUNC(e->devid));
1131
5d0c8e49
JR		 1132 devid = e->devid;
1133 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
7a6a3a08 1134 if (alias) {
5d0c8e49 1135 amd_iommu_alias_table[dev_i] = devid_to;
7a6a3a08
JR		 1136 set_dev_entry_from_acpi(iommu,
1137 devid_to, flags, ext_flags);
1138 }
1139 set_dev_entry_from_acpi(iommu, dev_i,
1140 flags, ext_flags);
5d0c8e49
JR		 1141 }
1142 break;
6efed63b
JR		 1143 case IVHD_DEV_SPECIAL: {
1144 u8 handle, type;
1145 const char *var;
1146 u16 devid;
1147 int ret;
1148
1149 handle = e->ext & 0xff;
1150 devid = (e->ext >> 8) & 0xffff;
1151 type = (e->ext >> 24) & 0xff;
1152
1153 if (type == IVHD_SPECIAL_IOAPIC)
1154 var = "IOAPIC";
1155 else if (type == IVHD_SPECIAL_HPET)
1156 var = "HPET";
1157 else
1158 var = "UNKNOWN";
1159
1160 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1161 var, (int)handle,
c5081cd7 1162 PCI_BUS_NUM(devid),
6efed63b
JR		 1163 PCI_SLOT(devid),
1164 PCI_FUNC(devid));
1165
c50e3247 1166 ret = add_special_device(type, handle, &devid, false);
6efed63b
JR		 1167 if (ret)
1168 return ret;
c50e3247
JR		 1169
1170 /*
1171 * add_special_device might update the devid in case a
1172 * command-line override is present. So call
1173 * set_dev_entry_from_acpi after add_special_device.
1174 */
1175 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1176
6efed63b
JR		 1177 break;
1178 }
2a0cb4e2
WZ		 1179 case IVHD_DEV_ACPI_HID: {
1180 u16 devid;
1181 u8 hid[ACPIHID_HID_LEN] = {0};
1182 u8 uid[ACPIHID_UID_LEN] = {0};
1183 int ret;
1184
1185 if (h->type != 0x40) {
1186 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1187 e->type);
1188 break;
1189 }
1190
1191 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1192 hid[ACPIHID_HID_LEN - 1] = '\0';
1193
1194 if (!(*hid)) {
1195 pr_err(FW_BUG "Invalid HID.\n");
1196 break;
1197 }
1198
1199 switch (e->uidf) {
1200 case UID_NOT_PRESENT:
1201
1202 if (e->uidl != 0)
1203 pr_warn(FW_BUG "Invalid UID length.\n");
1204
1205 break;
1206 case UID_IS_INTEGER:
1207
1208 sprintf(uid, "%d", e->uid);
1209
1210 break;
1211 case UID_IS_CHARACTER:
1212
1213 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1214 uid[ACPIHID_UID_LEN - 1] = '\0';
1215
1216 break;
1217 default:
1218 break;
1219 }
1220
6082ee72 1221 devid = e->devid;
2a0cb4e2
WZ		 1222 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1223 hid, uid,
1224 PCI_BUS_NUM(devid),
1225 PCI_SLOT(devid),
1226 PCI_FUNC(devid));
1227
2a0cb4e2
WZ		 1228 flags = e->flags;
1229
1230 ret = add_acpi_hid_device(hid, uid, &devid, false);
1231 if (ret)
1232 return ret;
1233
1234 /*
1235 * add_special_device might update the devid in case a
1236 * command-line override is present. So call
1237 * set_dev_entry_from_acpi after add_special_device.
1238 */
1239 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1240
1241 break;
1242 }
5d0c8e49
JR		 1243 default:
1244 break;
1245 }
1246
b514e555 1247 p += ivhd_entry_length(p);
5d0c8e49 1248 }
6efed63b
JR		 1249
1250 return 0;
5d0c8e49
JR		 1251}
1252
e47d402d
JR		 1253static void __init free_iommu_one(struct amd_iommu *iommu)
1254{
1255 free_command_buffer(iommu);
335503e5 1256 free_event_buffer(iommu);
1a29ac01 1257 free_ppr_log(iommu);
8bda0cfb 1258 free_ga_log(iommu);
e47d402d
JR		 1259 iommu_unmap_mmio_space(iommu);
1260}
1261
1262static void __init free_iommu_all(void)
1263{
1264 struct amd_iommu *iommu, *next;
1265
3bd22172 1266 for_each_iommu_safe(iommu, next) {
e47d402d
JR		 1267 list_del(&iommu->list);
1268 free_iommu_one(iommu);
1269 kfree(iommu);
1270 }
1271}
1272
318fe782
SS		 1273/*
1274 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1275 * Workaround:
1276 * BIOS should disable L2B micellaneous clock gating by setting
1277 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1278 */
e2f1a3bd 1279static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
318fe782
SS		 1280{
1281 u32 value;
1282
1283 if ((boot_cpu_data.x86 != 0x15) ||
1284 (boot_cpu_data.x86_model < 0x10) ||
1285 (boot_cpu_data.x86_model > 0x1f))
1286 return;
1287
1288 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1289 pci_read_config_dword(iommu->dev, 0xf4, &value);
1290
1291 if (value & BIT(2))
1292 return;
1293
1294 /* Select NB indirect register 0x90 and enable writing */
1295 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1296
1297 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1298 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1299 dev_name(&iommu->dev->dev));
1300
1301 /* Clear the enable writing bit */
1302 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1303}
1304
358875fd
JC		 1305/*
1306 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1307 * Workaround:
1308 * BIOS should enable ATS write permission check by setting
1309 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1310 */
1311static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1312{
1313 u32 value;
1314
1315 if ((boot_cpu_data.x86 != 0x15) ||
1316 (boot_cpu_data.x86_model < 0x30) ||
1317 (boot_cpu_data.x86_model > 0x3f))
1318 return;
1319
1320 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1321 value = iommu_read_l2(iommu, 0x47);
1322
1323 if (value & BIT(0))
1324 return;
1325
1326 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1327 iommu_write_l2(iommu, 0x47, value | BIT(0));
1328
1329 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1330 dev_name(&iommu->dev->dev));
1331}
1332
b65233a9
JR		 1333/*
1334 * This function clues the initialization function for one IOMMU
1335 * together and also allocates the command buffer and programs the
1336 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1337 */
e47d402d
JR		 1338static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1339{
6efed63b
JR		 1340 int ret;
1341
e47d402d 1342 spin_lock_init(&iommu->lock);
bb52777e
JR		 1343
1344 /* Add IOMMU to internal data structures */
e47d402d 1345 list_add_tail(&iommu->list, &amd_iommu_list);
6b9376e3 1346 iommu->index = amd_iommus_present++;
bb52777e
JR		 1347
1348 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1349 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1350 return -ENOSYS;
1351 }
1352
1353 /* Index is fine - add IOMMU to the array */
1354 amd_iommus[iommu->index] = iommu;
e47d402d
JR		 1355
1356 /*
1357 * Copy data from ACPI table entry to the iommu struct
1358 */
23c742db 1359 iommu->devid = h->devid;
e47d402d 1360 iommu->cap_ptr = h->cap_ptr;
ee893c24 1361 iommu->pci_seg = h->pci_seg;
e47d402d 1362 iommu->mmio_phys = h->mmio_phys;
30861ddc 1363
7d7d38af
SS		 1364 switch (h->type) {
1365 case 0x10:
1366 /* Check if IVHD EFR contains proper max banks/counters */
1367 if ((h->efr_attr != 0) &&
1368 ((h->efr_attr & (0xF << 13)) != 0) &&
1369 ((h->efr_attr & (0x3F << 17)) != 0))
1370 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1371 else
1372 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1373 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1374 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1375 break;
1376 case 0x11:
1377 case 0x40:
1378 if (h->efr_reg & (1 << 9))
1379 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1380 else
1381 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1382 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1383 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1384 break;
1385 default:
1386 return -EINVAL;
30861ddc
SK		 1387 }
1388
1389 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1390 iommu->mmio_phys_end);
e47d402d
JR		 1391 if (!iommu->mmio_base)
1392 return -ENOMEM;
1393
f2c2db53 1394 if (alloc_command_buffer(iommu))
e47d402d
JR		 1395 return -ENOMEM;
1396
f2c2db53 1397 if (alloc_event_buffer(iommu))
335503e5
JR		 1398 return -ENOMEM;
1399
a80dc3e0
JR		 1400 iommu->int_enabled = false;
1401
6efed63b
JR		 1402 ret = init_iommu_from_acpi(iommu, h);
1403 if (ret)
1404 return ret;
f6fec00a 1405
7c71d306
JL		 1406 ret = amd_iommu_create_irq_domain(iommu);
1407 if (ret)
1408 return ret;
1409
f6fec00a
JR		 1410 /*
1411 * Make sure IOMMU is not considered to translate itself. The IVRS
1412 * table tells us so, but this is a lie!
1413 */
1414 amd_iommu_rlookup_table[iommu->devid] = NULL;
1415
23c742db 1416 return 0;
e47d402d
JR		 1417}
1418
8c7142f5
SS		 1419/**
1420 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1421 * @ivrs Pointer to the IVRS header
1422 *
1423 * This function search through all IVDB of the maximum supported IVHD
1424 */
1425static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1426{
1427 u8 *base = (u8 *)ivrs;
1428 struct ivhd_header *ivhd = (struct ivhd_header *)
1429 (base + IVRS_HEADER_LENGTH);
1430 u8 last_type = ivhd->type;
1431 u16 devid = ivhd->devid;
1432
1433 while (((u8 *)ivhd - base < ivrs->length) &&
1434 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1435 u8 *p = (u8 *) ivhd;
1436
1437 if (ivhd->devid == devid)
1438 last_type = ivhd->type;
1439 ivhd = (struct ivhd_header *)(p + ivhd->length);
1440 }
1441
1442 return last_type;
1443}
1444
b65233a9
JR		 1445/*
1446 * Iterates over all IOMMU entries in the ACPI table, allocates the
1447 * IOMMU structure and initializes it with init_iommu_one()
1448 */
e47d402d
JR		 1449static int __init init_iommu_all(struct acpi_table_header *table)
1450{
1451 u8 *p = (u8 *)table, *end = (u8 *)table;
1452 struct ivhd_header *h;
1453 struct amd_iommu *iommu;
1454 int ret;
1455
e47d402d
JR		 1456 end += table->length;
1457 p += IVRS_HEADER_LENGTH;
1458
1459 while (p < end) {
1460 h = (struct ivhd_header *)p;
8c7142f5 1461 if (*p == amd_iommu_target_ivhd_type) {
9c72041f 1462
ae908c22 1463 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
9c72041f 1464 "seg: %d flags: %01x info %04x\n",
c5081cd7 1465 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
9c72041f
JR		 1466 PCI_FUNC(h->devid), h->cap_ptr,
1467 h->pci_seg, h->flags, h->info);
1468 DUMP_printk(" mmio-addr: %016llx\n",
1469 h->mmio_phys);
1470
e47d402d 1471 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
02f3b3f5
JR		 1472 if (iommu == NULL)
1473 return -ENOMEM;
3551a708 1474
e47d402d 1475 ret = init_iommu_one(iommu, h);
02f3b3f5
JR		 1476 if (ret)
1477 return ret;
e47d402d
JR		 1478 }
1479 p += h->length;
1480
1481 }
1482 WARN_ON(p != end);
1483
1484 return 0;
1485}
1486
1650dfd1
SS		 1487static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1488 u8 fxn, u64 *value, bool is_write);
30861ddc
SK		 1489
1490static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1491{
1492 u64 val = 0xabcd, val2 = 0;
1493
1494 if (!iommu_feature(iommu, FEATURE_PC))
1495 return;
1496
1497 amd_iommu_pc_present = true;
1498
1499 /* Check if the performance counters can be written to */
1650dfd1
SS		 1500 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1501 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
30861ddc
SK		 1502 (val != val2)) {
1503 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1504 amd_iommu_pc_present = false;
1505 return;
1506 }
1507
1508 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1509
1510 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1511 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1512 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1513}
1514
066f2e98
AW		 1515static ssize_t amd_iommu_show_cap(struct device *dev,
1516 struct device_attribute *attr,
1517 char *buf)
1518{
b7a42b9d 1519 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
066f2e98
AW		 1520 return sprintf(buf, "%x\n", iommu->cap);
1521}
1522static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1523
1524static ssize_t amd_iommu_show_features(struct device *dev,
1525 struct device_attribute *attr,
1526 char *buf)
1527{
b7a42b9d 1528 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
066f2e98
AW		 1529 return sprintf(buf, "%llx\n", iommu->features);
1530}
1531static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1532
1533static struct attribute *amd_iommu_attrs[] = {
1534 &dev_attr_cap.attr,
1535 &dev_attr_features.attr,
1536 NULL,
1537};
1538
1539static struct attribute_group amd_iommu_group = {
1540 .name = "amd-iommu",
1541 .attrs = amd_iommu_attrs,
1542};
1543
1544static const struct attribute_group *amd_iommu_groups[] = {
1545 &amd_iommu_group,
1546 NULL,
1547};
30861ddc 1548
23c742db
JR		 1549static int iommu_init_pci(struct amd_iommu *iommu)
1550{
1551 int cap_ptr = iommu->cap_ptr;
1552 u32 range, misc, low, high;
8bda0cfb 1553 int ret;
23c742db 1554
c5081cd7 1555 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
23c742db
JR		 1556 iommu->devid & 0xff);
1557 if (!iommu->dev)
1558 return -ENODEV;
1559
cbbc00be
JL		 1560 /* Prevent binding other PCI device drivers to IOMMU devices */
1561 iommu->dev->match_driver = false;
1562
23c742db
JR		 1563 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1564 &iommu->cap);
1565 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1566 &range);
1567 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1568 &misc);
1569
23c742db
JR		 1570 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1571 amd_iommu_iotlb_sup = false;
1572
1573 /* read extended feature bits */
1574 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1575 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1576
1577 iommu->features = ((u64)high << 32) | low;
1578
1579 if (iommu_feature(iommu, FEATURE_GT)) {
1580 int glxval;
a919a018
SS		 1581 u32 max_pasid;
1582 u64 pasmax;
23c742db 1583
a919a018
SS		 1584 pasmax = iommu->features & FEATURE_PASID_MASK;
1585 pasmax >>= FEATURE_PASID_SHIFT;
1586 max_pasid = (1 << (pasmax + 1)) - 1;
23c742db 1587
a919a018
SS		 1588 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1589
1590 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
23c742db
JR		 1591
1592 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1593 glxval >>= FEATURE_GLXVAL_SHIFT;
1594
1595 if (amd_iommu_max_glx_val == -1)
1596 amd_iommu_max_glx_val = glxval;
1597 else
1598 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1599 }
1600
1601 if (iommu_feature(iommu, FEATURE_GT) &&
1602 iommu_feature(iommu, FEATURE_PPR)) {
1603 iommu->is_iommu_v2 = true;
1604 amd_iommu_v2_present = true;
1605 }
1606
f2c2db53
JR		 1607 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1608 return -ENOMEM;
23c742db 1609
8bda0cfb
SS		 1610 ret = iommu_init_ga(iommu);
1611 if (ret)
1612 return ret;
3928aa3f 1613
23c742db
JR		 1614 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1615 amd_iommu_np_cache = true;
1616
30861ddc
SK		 1617 init_iommu_perf_ctr(iommu);
1618
23c742db
JR		 1619 if (is_rd890_iommu(iommu->dev)) {
1620 int i, j;
1621
1622 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1623 PCI_DEVFN(0, 0));
1624
1625 /*
1626 * Some rd890 systems may not be fully reconfigured by the
1627 * BIOS, so it's necessary for us to store this information so
1628 * it can be reprogrammed on resume
1629 */
1630 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1631 &iommu->stored_addr_lo);
1632 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1633 &iommu->stored_addr_hi);
1634
1635 /* Low bit locks writes to configuration space */
1636 iommu->stored_addr_lo &= ~1;
1637
1638 for (i = 0; i < 6; i++)
1639 for (j = 0; j < 0x12; j++)
1640 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1641
1642 for (i = 0; i < 0x83; i++)
1643 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1644 }
1645
318fe782 1646 amd_iommu_erratum_746_workaround(iommu);
358875fd 1647 amd_iommu_ats_write_check_workaround(iommu);
318fe782 1648
39ab9555
JR		 1649 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1650 amd_iommu_groups, "ivhd%d", iommu->index);
b0119e87
JR		 1651 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1652 iommu_device_register(&iommu->iommu);
066f2e98 1653
23c742db
JR		 1654 return pci_enable_device(iommu->dev);
1655}
1656
4d121c32
JR		 1657static void print_iommu_info(void)
1658{
1659 static const char * const feat_str[] = {
1660 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1661 "IA", "GA", "HE", "PC"
1662 };
1663 struct amd_iommu *iommu;
1664
1665 for_each_iommu(iommu) {
1666 int i;
1667
1668 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1669 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1670
1671 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
3928aa3f
SS		 1672 pr_info("AMD-Vi: Extended features (%#llx):\n",
1673 iommu->features);
2bd5ed00 1674 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
4d121c32
JR		 1675 if (iommu_feature(iommu, (1ULL << i)))
1676 pr_cont(" %s", feat_str[i]);
1677 }
3928aa3f
SS		 1678
1679 if (iommu->features & FEATURE_GAM_VAPIC)
1680 pr_cont(" GA_vAPIC");
1681
30861ddc 1682 pr_cont("\n");
500c25ed 1683 }
4d121c32 1684 }
3928aa3f 1685 if (irq_remapping_enabled) {
ebe60bbf 1686 pr_info("AMD-Vi: Interrupt remapping enabled\n");
3928aa3f
SS		 1687 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1688 pr_info("AMD-Vi: virtual APIC enabled\n");
1689 }
4d121c32
JR		 1690}
1691
2c0ae172 1692static int __init amd_iommu_init_pci(void)
23c742db
JR		 1693{
1694 struct amd_iommu *iommu;
1695 int ret = 0;
1696
1697 for_each_iommu(iommu) {
1698 ret = iommu_init_pci(iommu);
1699 if (ret)
1700 break;
1701 }
1702
522e5cb7
JR		 1703 /*
1704 * Order is important here to make sure any unity map requirements are
1705 * fulfilled. The unity mappings are created and written to the device
1706 * table during the amd_iommu_init_api() call.
1707 *
1708 * After that we call init_device_table_dma() to make sure any
1709 * uninitialized DTE will block DMA, and in the end we flush the caches
1710 * of all IOMMUs to make sure the changes to the device table are
1711 * active.
1712 */
1713 ret = amd_iommu_init_api();
1714
aafd8ba0
JR		 1715 init_device_table_dma();
1716
1717 for_each_iommu(iommu)
1718 iommu_flush_all_caches(iommu);
1719
3a18404c
JR		 1720 if (!ret)
1721 print_iommu_info();
4d121c32 1722
23c742db
JR		 1723 return ret;
1724}
1725
a80dc3e0
JR		 1726/****************************************************************************
1727 *
1728 * The following functions initialize the MSI interrupts for all IOMMUs
df805abb 1729 * in the system. It's a bit challenging because there could be multiple
a80dc3e0
JR		 1730 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1731 * pci_dev.
1732 *
1733 ****************************************************************************/
1734
9f800de3 1735static int iommu_setup_msi(struct amd_iommu *iommu)
a80dc3e0
JR		 1736{
1737 int r;
a80dc3e0 1738
9ddd592a
JR		 1739 r = pci_enable_msi(iommu->dev);
1740 if (r)
1741 return r;
a80dc3e0 1742
72fe00f0
JR		 1743 r = request_threaded_irq(iommu->dev->irq,
1744 amd_iommu_int_handler,
1745 amd_iommu_int_thread,
1746 0, "AMD-Vi",
3f398bc7 1747 iommu);
a80dc3e0
JR		 1748
1749 if (r) {
1750 pci_disable_msi(iommu->dev);
9ddd592a 1751 return r;
a80dc3e0
JR		 1752 }
1753
fab6afa3 1754 iommu->int_enabled = true;
1a29ac01 1755
a80dc3e0
JR		 1756 return 0;
1757}
1758
05f92db9 1759static int iommu_init_msi(struct amd_iommu *iommu)
a80dc3e0 1760{
9ddd592a
JR		 1761 int ret;
1762
a80dc3e0 1763 if (iommu->int_enabled)
9ddd592a 1764 goto enable_faults;
a80dc3e0 1765
82fcfc67 1766 if (iommu->dev->msi_cap)
9ddd592a
JR		 1767 ret = iommu_setup_msi(iommu);
1768 else
1769 ret = -ENODEV;
1770
1771 if (ret)
1772 return ret;
a80dc3e0 1773
9ddd592a
JR		 1774enable_faults:
1775 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
a80dc3e0 1776
9ddd592a
JR		 1777 if (iommu->ppr_log != NULL)
1778 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1779
8bda0cfb
SS		 1780 iommu_ga_log_enable(iommu);
1781
9ddd592a 1782 return 0;
a80dc3e0
JR		 1783}
1784
b65233a9
JR		 1785/****************************************************************************
1786 *
1787 * The next functions belong to the third pass of parsing the ACPI
1788 * table. In this last pass the memory mapping requirements are
df805abb 1789 * gathered (like exclusion and unity mapping ranges).
b65233a9
JR		 1790 *
1791 ****************************************************************************/
1792
be2a022c
JR		 1793static void __init free_unity_maps(void)
1794{
1795 struct unity_map_entry *entry, *next;
1796
1797 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1798 list_del(&entry->list);
1799 kfree(entry);
1800 }
1801}
1802
b65233a9 1803/* called when we find an exclusion range definition in ACPI */
be2a022c
JR		 1804static int __init init_exclusion_range(struct ivmd_header *m)
1805{
1806 int i;
1807
1808 switch (m->type) {
1809 case ACPI_IVMD_TYPE:
1810 set_device_exclusion_range(m->devid, m);
1811 break;
1812 case ACPI_IVMD_TYPE_ALL:
3a61ec38 1813 for (i = 0; i <= amd_iommu_last_bdf; ++i)
be2a022c
JR		 1814 set_device_exclusion_range(i, m);
1815 break;
1816 case ACPI_IVMD_TYPE_RANGE:
1817 for (i = m->devid; i <= m->aux; ++i)
1818 set_device_exclusion_range(i, m);
1819 break;
1820 default:
1821 break;
1822 }
1823
1824 return 0;
1825}
1826
b65233a9 1827/* called for unity map ACPI definition */
be2a022c
JR		 1828static int __init init_unity_map_range(struct ivmd_header *m)
1829{
98f1ad25 1830 struct unity_map_entry *e = NULL;
02acc43a 1831 char *s;
be2a022c
JR		 1832
1833 e = kzalloc(sizeof(*e), GFP_KERNEL);
1834 if (e == NULL)
1835 return -ENOMEM;
1836
1837 switch (m->type) {
1838 default:
0bc252f4
JR		 1839 kfree(e);
1840 return 0;
be2a022c 1841 case ACPI_IVMD_TYPE:
02acc43a 1842 s = "IVMD_TYPEi\t\t\t";
be2a022c
JR		 1843 e->devid_start = e->devid_end = m->devid;
1844 break;
1845 case ACPI_IVMD_TYPE_ALL:
02acc43a 1846 s = "IVMD_TYPE_ALL\t\t";
be2a022c
JR		 1847 e->devid_start = 0;
1848 e->devid_end = amd_iommu_last_bdf;
1849 break;
1850 case ACPI_IVMD_TYPE_RANGE:
02acc43a 1851 s = "IVMD_TYPE_RANGE\t\t";
be2a022c
JR		 1852 e->devid_start = m->devid;
1853 e->devid_end = m->aux;
1854 break;
1855 }
1856 e->address_start = PAGE_ALIGN(m->range_start);
1857 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1858 e->prot = m->flags >> 1;
1859
02acc43a
JR		 1860 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1861 " range_start: %016llx range_end: %016llx flags: %x\n", s,
c5081cd7
SK		 1862 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1863 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
02acc43a
JR		 1864 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1865 e->address_start, e->address_end, m->flags);
1866
be2a022c
JR		 1867 list_add_tail(&e->list, &amd_iommu_unity_map);
1868
1869 return 0;
1870}
1871
b65233a9 1872/* iterates over all memory definitions we find in the ACPI table */
be2a022c
JR		 1873static int __init init_memory_definitions(struct acpi_table_header *table)
1874{
1875 u8 *p = (u8 *)table, *end = (u8 *)table;
1876 struct ivmd_header *m;
1877
be2a022c
JR		 1878 end += table->length;
1879 p += IVRS_HEADER_LENGTH;
1880
1881 while (p < end) {
1882 m = (struct ivmd_header *)p;
1883 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1884 init_exclusion_range(m);
1885 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1886 init_unity_map_range(m);
1887
1888 p += m->length;
1889 }
1890
1891 return 0;
1892}
1893
9f5f5fb3
JR		 1894/*
1895 * Init the device table to not allow DMA access for devices and
1896 * suppress all page faults
1897 */
33f28c59 1898static void init_device_table_dma(void)
9f5f5fb3 1899{
0de66d5b 1900 u32 devid;
9f5f5fb3
JR		 1901
1902 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1903 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1904 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
54bd6357
JR		 1905 /*
1906 * In kdump kernels in-flight DMA from the old kernel might
1907 * cause IO_PAGE_FAULTs. There are no reports that a kdump
1908 * actually failed because of that, so just disable fault
1909 * reporting in the hardware to get rid of the messages
1910 */
1911 if (is_kdump_kernel())
1912 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
9f5f5fb3
JR		 1913 }
1914}
1915
d04e0ba3
JR		 1916static void __init uninit_device_table_dma(void)
1917{
1918 u32 devid;
1919
1920 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1921 amd_iommu_dev_table[devid].data[0] = 0ULL;
1922 amd_iommu_dev_table[devid].data[1] = 0ULL;
1923 }
1924}
1925
33f28c59
JR		 1926static void init_device_table(void)
1927{
1928 u32 devid;
1929
1930 if (!amd_iommu_irq_remap)
1931 return;
1932
1933 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1934 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1935}
1936
e9bf5197
JR		 1937static void iommu_init_flags(struct amd_iommu *iommu)
1938{
1939 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1940 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1941 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1942
1943 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1944 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1945 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1946
1947 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1948 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1949 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1950
1951 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1952 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1953 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1954
1955 /*
1956 * make IOMMU memory accesses cache coherent
1957 */
1958 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1456e9d2
JR		 1959
1960 /* Set IOTLB invalidation timeout to 1s */
1961 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
e9bf5197
JR		 1962}
1963
5bcd757f 1964static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
4c894f47 1965{
5bcd757f
MG		 1966 int i, j;
1967 u32 ioc_feature_control;
c1bf94ec 1968 struct pci_dev *pdev = iommu->root_pdev;
5bcd757f
MG		 1969
1970 /* RD890 BIOSes may not have completely reconfigured the iommu */
c1bf94ec 1971 if (!is_rd890_iommu(iommu->dev) || !pdev)
5bcd757f
MG		 1972 return;
1973
1974 /*
1975 * First, we need to ensure that the iommu is enabled. This is
1976 * controlled by a register in the northbridge
1977 */
5bcd757f
MG		 1978
1979 /* Select Northbridge indirect register 0x75 and enable writing */
1980 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1981 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1982
1983 /* Enable the iommu */
1984 if (!(ioc_feature_control & 0x1))
1985 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1986
5bcd757f
MG		 1987 /* Restore the iommu BAR */
1988 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1989 iommu->stored_addr_lo);
1990 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1991 iommu->stored_addr_hi);
1992
1993 /* Restore the l1 indirect regs for each of the 6 l1s */
1994 for (i = 0; i < 6; i++)
1995 for (j = 0; j < 0x12; j++)
1996 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1997
1998 /* Restore the l2 indirect regs */
1999 for (i = 0; i < 0x83; i++)
2000 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2001
2002 /* Lock PCI setup registers */
2003 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2004 iommu->stored_addr_lo | 1);
4c894f47
JR		 2005}
2006
3928aa3f
SS		 2007static void iommu_enable_ga(struct amd_iommu *iommu)
2008{
2009#ifdef CONFIG_IRQ_REMAP
2010 switch (amd_iommu_guest_ir) {
2011 case AMD_IOMMU_GUEST_IR_VAPIC:
2012 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2013 /* Fall through */
2014 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2015 iommu_feature_enable(iommu, CONTROL_GA_EN);
77bdab46 2016 iommu->irte_ops = &irte_128_ops;
3928aa3f
SS		 2017 break;
2018 default:
77bdab46 2019 iommu->irte_ops = &irte_32_ops;
3928aa3f
SS		 2020 break;
2021 }
2022#endif
2023}
2024
b65233a9
JR		 2025/*
2026 * This function finally enables all IOMMUs found in the system after
2027 * they have been initialized
2028 */
11ee5ac4 2029static void early_enable_iommus(void)
8736197b
JR		 2030{
2031 struct amd_iommu *iommu;
2032
3bd22172 2033 for_each_iommu(iommu) {
a8c485bb 2034 iommu_disable(iommu);
e9bf5197 2035 iommu_init_flags(iommu);
58492e12
JR		 2036 iommu_set_device_table(iommu);
2037 iommu_enable_command_buffer(iommu);
2038 iommu_enable_event_buffer(iommu);
8736197b 2039 iommu_set_exclusion_range(iommu);
3928aa3f 2040 iommu_enable_ga(iommu);
8736197b 2041 iommu_enable(iommu);
7d0c5cc5 2042 iommu_flush_all_caches(iommu);
8736197b 2043 }
d98de49a
SS		 2044
2045#ifdef CONFIG_IRQ_REMAP
2046 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2047 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2048#endif
8736197b
JR		 2049}
2050
11ee5ac4
JR		 2051static void enable_iommus_v2(void)
2052{
2053 struct amd_iommu *iommu;
2054
2055 for_each_iommu(iommu) {
2056 iommu_enable_ppr_log(iommu);
2057 iommu_enable_gt(iommu);
2058 }
2059}
2060
2061static void enable_iommus(void)
2062{
2063 early_enable_iommus();
2064
2065 enable_iommus_v2();
2066}
2067
92ac4320
JR		 2068static void disable_iommus(void)
2069{
2070 struct amd_iommu *iommu;
2071
2072 for_each_iommu(iommu)
2073 iommu_disable(iommu);
d98de49a
SS		 2074
2075#ifdef CONFIG_IRQ_REMAP
2076 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2077 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2078#endif
92ac4320
JR		 2079}
2080
7441e9cb
JR		 2081/*
2082 * Suspend/Resume support
2083 * disable suspend until real resume implemented
2084 */
2085
f3c6ea1b 2086static void amd_iommu_resume(void)
7441e9cb 2087{
5bcd757f
MG		 2088 struct amd_iommu *iommu;
2089
2090 for_each_iommu(iommu)
2091 iommu_apply_resume_quirks(iommu);
2092
736501ee
JR		 2093 /* re-load the hardware */
2094 enable_iommus();
3d9761e7
JR		 2095
2096 amd_iommu_enable_interrupts();
7441e9cb
JR		 2097}
2098
f3c6ea1b 2099static int amd_iommu_suspend(void)
7441e9cb 2100{
736501ee
JR		 2101 /* disable IOMMUs to go out of the way for BIOS */
2102 disable_iommus();
2103
2104 return 0;
7441e9cb
JR		 2105}
2106
f3c6ea1b 2107static struct syscore_ops amd_iommu_syscore_ops = {
7441e9cb
JR		 2108 .suspend = amd_iommu_suspend,
2109 .resume = amd_iommu_resume,
2110};
2111
90b3eb03 2112static void __init free_iommu_resources(void)
8704a1ba 2113{
ebcfa284 2114 kmemleak_free(irq_lookup_table);
0ea2c422
JR		 2115 free_pages((unsigned long)irq_lookup_table,
2116 get_order(rlookup_table_size));
f6019271 2117 irq_lookup_table = NULL;
8704a1ba 2118
a591989a
JL		 2119 kmem_cache_destroy(amd_iommu_irq_cache);
2120 amd_iommu_irq_cache = NULL;
8704a1ba
JR		 2121
2122 free_pages((unsigned long)amd_iommu_rlookup_table,
2123 get_order(rlookup_table_size));
f6019271 2124 amd_iommu_rlookup_table = NULL;
8704a1ba
JR		 2125
2126 free_pages((unsigned long)amd_iommu_alias_table,
2127 get_order(alias_table_size));
f6019271 2128 amd_iommu_alias_table = NULL;
8704a1ba
JR		 2129
2130 free_pages((unsigned long)amd_iommu_dev_table,
2131 get_order(dev_table_size));
f6019271 2132 amd_iommu_dev_table = NULL;
8704a1ba
JR		 2133
2134 free_iommu_all();
2135
8704a1ba
JR		 2136#ifdef CONFIG_GART_IOMMU
2137 /*
2138 * We failed to initialize the AMD IOMMU - try fallback to GART
2139 * if possible.
2140 */
2141 gart_iommu_init();
2142
2143#endif
2144}
2145
c2ff5cf5
JR		 2146/* SB IOAPIC is always on this device in AMD systems */
2147#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2148
eb1eb7ae
JR		 2149static bool __init check_ioapic_information(void)
2150{
dfbb6d47 2151 const char *fw_bug = FW_BUG;
c2ff5cf5 2152 bool ret, has_sb_ioapic;
eb1eb7ae
JR		 2153 int idx;
2154
c2ff5cf5
JR		 2155 has_sb_ioapic = false;
2156 ret = false;
eb1eb7ae 2157
dfbb6d47
JR		 2158 /*
2159 * If we have map overrides on the kernel command line the
2160 * messages in this function might not describe firmware bugs
2161 * anymore - so be careful
2162 */
2163 if (cmdline_maps)
2164 fw_bug = "";
2165
c2ff5cf5
JR		 2166 for (idx = 0; idx < nr_ioapics; idx++) {
2167 int devid, id = mpc_ioapic_id(idx);
2168
2169 devid = get_ioapic_devid(id);
2170 if (devid < 0) {
dfbb6d47
JR		 2171 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2172 fw_bug, id);
c2ff5cf5
JR		 2173 ret = false;
2174 } else if (devid == IOAPIC_SB_DEVID) {
2175 has_sb_ioapic = true;
2176 ret = true;
eb1eb7ae
JR		 2177 }
2178 }
2179
c2ff5cf5
JR		 2180 if (!has_sb_ioapic) {
2181 /*
2182 * We expect the SB IOAPIC to be listed in the IVRS
2183 * table. The system timer is connected to the SB IOAPIC
2184 * and if we don't have it in the list the system will
2185 * panic at boot time. This situation usually happens
2186 * when the BIOS is buggy and provides us the wrong
2187 * device id for the IOAPIC in the system.
2188 */
dfbb6d47 2189 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
c2ff5cf5
JR		 2190 }
2191
2192 if (!ret)
dfbb6d47 2193 pr_err("AMD-Vi: Disabling interrupt remapping\n");
c2ff5cf5
JR		 2194
2195 return ret;
eb1eb7ae
JR		 2196}
2197
d04e0ba3
JR		 2198static void __init free_dma_resources(void)
2199{
d04e0ba3
JR		 2200 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2201 get_order(MAX_DOMAIN_ID/8));
f6019271 2202 amd_iommu_pd_alloc_bitmap = NULL;
d04e0ba3
JR		 2203
2204 free_unity_maps();
2205}
2206
b65233a9 2207/*
8704a1ba
JR		 2208 * This is the hardware init function for AMD IOMMU in the system.
2209 * This function is called either from amd_iommu_init or from the interrupt
2210 * remapping setup code.
b65233a9
JR		 2211 *
2212 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
8c7142f5 2213 * four times:
b65233a9 2214 *
8c7142f5
SS		 2215 * 1 pass) Discover the most comprehensive IVHD type to use.
2216 *
2217 * 2 pass) Find the highest PCI device id the driver has to handle.
b65233a9
JR		 2218 * Upon this information the size of the data structures is
2219 * determined that needs to be allocated.
2220 *
8c7142f5 2221 * 3 pass) Initialize the data structures just allocated with the
b65233a9
JR		 2222 * information in the ACPI table about available AMD IOMMUs
2223 * in the system. It also maps the PCI devices in the
2224 * system to specific IOMMUs
2225 *
8c7142f5 2226 * 4 pass) After the basic data structures are allocated and
b65233a9
JR		 2227 * initialized we update them with information about memory
2228 * remapping requirements parsed out of the ACPI table in
2229 * this last pass.
2230 *
8704a1ba
JR		 2231 * After everything is set up the IOMMUs are enabled and the necessary
2232 * hotplug and suspend notifiers are registered.
b65233a9 2233 */
643511b3 2234static int __init early_amd_iommu_init(void)
fe74c9cf 2235{
02f3b3f5 2236 struct acpi_table_header *ivrs_base;
02f3b3f5 2237 acpi_status status;
3928aa3f 2238 int i, remap_cache_sz, ret = 0;
fe74c9cf 2239
643511b3 2240 if (!amd_iommu_detected)
8704a1ba
JR		 2241 return -ENODEV;
2242
6b11d1d6 2243 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2244 if (status == AE_NOT_FOUND)
2245 return -ENODEV;
2246 else if (ACPI_FAILURE(status)) {
2247 const char *err = acpi_format_exception(status);
2248 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2249 return -EINVAL;
2250 }
2251
8c7142f5
SS		 2252 /*
2253 * Validate checksum here so we don't need to do it when
2254 * we actually parse the table
2255 */
2256 ret = check_ivrs_checksum(ivrs_base);
2257 if (ret)
99e8ccd3 2258 goto out;
8c7142f5
SS		 2259
2260 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2261 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2262
fe74c9cf
JR		 2263 /*
2264 * First parse ACPI tables to find the largest Bus/Dev/Func
2265 * we need to handle. Upon this information the shared data
2266 * structures for the IOMMUs in the system will be allocated
2267 */
2c0ae172
JR		 2268 ret = find_last_devid_acpi(ivrs_base);
2269 if (ret)
3551a708
JR		 2270 goto out;
2271
c571484e
JR		 2272 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2273 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2274 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
fe74c9cf 2275
fe74c9cf 2276 /* Device table - directly used by all IOMMUs */
8704a1ba 2277 ret = -ENOMEM;
5dc8bff0 2278 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2279 get_order(dev_table_size));
2280 if (amd_iommu_dev_table == NULL)
2281 goto out;
2282
2283 /*
2284 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2285 * IOMMU see for that device
2286 */
2287 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2288 get_order(alias_table_size));
2289 if (amd_iommu_alias_table == NULL)
2c0ae172 2290 goto out;
fe74c9cf
JR		 2291
2292 /* IOMMU rlookup table - find the IOMMU for a specific device */
83fd5cc6
JR		 2293 amd_iommu_rlookup_table = (void *)__get_free_pages(
2294 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2295 get_order(rlookup_table_size));
2296 if (amd_iommu_rlookup_table == NULL)
2c0ae172 2297 goto out;
fe74c9cf 2298
5dc8bff0
JR		 2299 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2300 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2301 get_order(MAX_DOMAIN_ID/8));
2302 if (amd_iommu_pd_alloc_bitmap == NULL)
2c0ae172 2303 goto out;
fe74c9cf
JR		 2304
2305 /*
5dc8bff0 2306 * let all alias entries point to itself
fe74c9cf 2307 */
3a61ec38 2308 for (i = 0; i <= amd_iommu_last_bdf; ++i)
fe74c9cf
JR		 2309 amd_iommu_alias_table[i] = i;
2310
fe74c9cf
JR		 2311 /*
2312 * never allocate domain 0 because its used as the non-allocated and
2313 * error value placeholder
2314 */
5c87f62d 2315 __set_bit(0, amd_iommu_pd_alloc_bitmap);
fe74c9cf 2316
aeb26f55
JR		 2317 spin_lock_init(&amd_iommu_pd_lock);
2318
fe74c9cf
JR		 2319 /*
2320 * now the data structures are allocated and basically initialized
2321 * start the real acpi table scan
2322 */
02f3b3f5
JR		 2323 ret = init_iommu_all(ivrs_base);
2324 if (ret)
2c0ae172 2325 goto out;
fe74c9cf 2326
11123741
JR		 2327 /* Disable any previously enabled IOMMUs */
2328 disable_iommus();
2329
eb1eb7ae
JR		 2330 if (amd_iommu_irq_remap)
2331 amd_iommu_irq_remap = check_ioapic_information();
2332
05152a04
JR		 2333 if (amd_iommu_irq_remap) {
2334 /*
2335 * Interrupt remapping enabled, create kmem_cache for the
2336 * remapping tables.
2337 */
83ed9c13 2338 ret = -ENOMEM;
3928aa3f
SS		 2339 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2340 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2341 else
2342 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
05152a04 2343 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
3928aa3f
SS		 2344 remap_cache_sz,
2345 IRQ_TABLE_ALIGNMENT,
2346 0, NULL);
05152a04
JR		 2347 if (!amd_iommu_irq_cache)
2348 goto out;
0ea2c422
JR		 2349
2350 irq_lookup_table = (void *)__get_free_pages(
2351 GFP_KERNEL | __GFP_ZERO,
2352 get_order(rlookup_table_size));
ebcfa284
LS		 2353 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2354 1, GFP_KERNEL);
0ea2c422
JR		 2355 if (!irq_lookup_table)
2356 goto out;
05152a04
JR		 2357 }
2358
02f3b3f5
JR		 2359 ret = init_memory_definitions(ivrs_base);
2360 if (ret)
2c0ae172 2361 goto out;
3551a708 2362
eb1eb7ae
JR		 2363 /* init the device table */
2364 init_device_table();
2365
8704a1ba 2366out:
02f3b3f5 2367 /* Don't leak any ACPI memory */
6b11d1d6 2368 acpi_put_table(ivrs_base);
02f3b3f5
JR		 2369 ivrs_base = NULL;
2370
643511b3
JR		 2371 return ret;
2372}
2373
ae295142 2374static int amd_iommu_enable_interrupts(void)
3d9761e7
JR		 2375{
2376 struct amd_iommu *iommu;
2377 int ret = 0;
2378
2379 for_each_iommu(iommu) {
2380 ret = iommu_init_msi(iommu);
2381 if (ret)
2382 goto out;
2383 }
2384
2385out:
2386 return ret;
2387}
2388
02f3b3f5
JR		 2389static bool detect_ivrs(void)
2390{
2391 struct acpi_table_header *ivrs_base;
02f3b3f5
JR		 2392 acpi_status status;
2393
6b11d1d6 2394 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2395 if (status == AE_NOT_FOUND)
2396 return false;
2397 else if (ACPI_FAILURE(status)) {
2398 const char *err = acpi_format_exception(status);
2399 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2400 return false;
2401 }
2402
6b11d1d6 2403 acpi_put_table(ivrs_base);
02f3b3f5 2404
1adb7d31
JR		 2405 /* Make sure ACS will be enabled during PCI probe */
2406 pci_request_acs();
2407
02f3b3f5
JR		 2408 return true;
2409}
2410
2c0ae172 2411/****************************************************************************
8704a1ba 2412 *
2c0ae172
JR		 2413 * AMD IOMMU Initialization State Machine
2414 *
2415 ****************************************************************************/
2416
2417static int __init state_next(void)
8704a1ba
JR		 2418{
2419 int ret = 0;
2420
2c0ae172
JR		 2421 switch (init_state) {
2422 case IOMMU_START_STATE:
2423 if (!detect_ivrs()) {
2424 init_state = IOMMU_NOT_FOUND;
2425 ret = -ENODEV;
2426 } else {
2427 init_state = IOMMU_IVRS_DETECTED;
2428 }
2429 break;
2430 case IOMMU_IVRS_DETECTED:
2431 ret = early_amd_iommu_init();
2432 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
7ad820e4
JR		 2433 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2434 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2435 free_dma_resources();
2436 free_iommu_resources();
2437 init_state = IOMMU_CMDLINE_DISABLED;
2438 ret = -EINVAL;
2439 }
2c0ae172
JR		 2440 break;
2441 case IOMMU_ACPI_FINISHED:
2442 early_enable_iommus();
2c0ae172
JR		 2443 x86_platform.iommu_shutdown = disable_iommus;
2444 init_state = IOMMU_ENABLED;
2445 break;
2446 case IOMMU_ENABLED:
74ddda71 2447 register_syscore_ops(&amd_iommu_syscore_ops);
2c0ae172
JR		 2448 ret = amd_iommu_init_pci();
2449 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2450 enable_iommus_v2();
2451 break;
2452 case IOMMU_PCI_INIT:
2453 ret = amd_iommu_enable_interrupts();
2454 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2455 break;
2456 case IOMMU_INTERRUPTS_EN:
1e6a7b04 2457 ret = amd_iommu_init_dma_ops();
2c0ae172
JR		 2458 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2459 break;
2460 case IOMMU_DMA_OPS:
2461 init_state = IOMMU_INITIALIZED;
2462 break;
2463 case IOMMU_INITIALIZED:
2464 /* Nothing to do */
2465 break;
2466 case IOMMU_NOT_FOUND:
2467 case IOMMU_INIT_ERROR:
1b1e942e 2468 case IOMMU_CMDLINE_DISABLED:
2c0ae172
JR		 2469 /* Error states => do nothing */
2470 ret = -EINVAL;
2471 break;
2472 default:
2473 /* Unknown state */
2474 BUG();
2475 }
3d9761e7 2476
2c0ae172
JR		 2477 return ret;
2478}
7441e9cb 2479
2c0ae172
JR		 2480static int __init iommu_go_to_state(enum iommu_init_state state)
2481{
151b0903 2482 int ret = -EINVAL;
f5325094 2483
2c0ae172 2484 while (init_state != state) {
1b1e942e
JR		 2485 if (init_state == IOMMU_NOT_FOUND ||
2486 init_state == IOMMU_INIT_ERROR ||
2487 init_state == IOMMU_CMDLINE_DISABLED)
2c0ae172 2488 break;
151b0903 2489 ret = state_next();
2c0ae172 2490 }
f2f12b6f 2491
fe74c9cf 2492 return ret;
2c0ae172 2493}
fe74c9cf 2494
6b474b82
JR		 2495#ifdef CONFIG_IRQ_REMAP
2496int __init amd_iommu_prepare(void)
2497{
3f4cb7c0
TG		 2498 int ret;
2499
7fa1c842 2500 amd_iommu_irq_remap = true;
84d07793 2501
3f4cb7c0
TG		 2502 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2503 if (ret)
2504 return ret;
2505 return amd_iommu_irq_remap ? 0 : -ENODEV;
6b474b82 2506}
d7f07769 2507
6b474b82
JR		 2508int __init amd_iommu_enable(void)
2509{
2510 int ret;
2511
2512 ret = iommu_go_to_state(IOMMU_ENABLED);
2513 if (ret)
2514 return ret;
d7f07769 2515
6b474b82 2516 irq_remapping_enabled = 1;
d7f07769 2517
6b474b82
JR		 2518 return 0;
2519}
2520
2521void amd_iommu_disable(void)
2522{
2523 amd_iommu_suspend();
2524}
2525
2526int amd_iommu_reenable(int mode)
2527{
2528 amd_iommu_resume();
2529
2530 return 0;
2531}
d7f07769 2532
6b474b82
JR		 2533int __init amd_iommu_enable_faulting(void)
2534{
2535 /* We enable MSI later when PCI is initialized */
2536 return 0;
2537}
2538#endif
d7f07769 2539
2c0ae172
JR		 2540/*
2541 * This is the core init function for AMD IOMMU hardware in the system.
2542 * This function is called from the generic x86 DMA layer initialization
2543 * code.
2544 */
2545static int __init amd_iommu_init(void)
2546{
2547 int ret;
2548
2549 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2550 if (ret) {
d04e0ba3
JR		 2551 free_dma_resources();
2552 if (!irq_remapping_enabled) {
2553 disable_iommus();
90b3eb03 2554 free_iommu_resources();
d04e0ba3
JR		 2555 } else {
2556 struct amd_iommu *iommu;
2557
2558 uninit_device_table_dma();
2559 for_each_iommu(iommu)
2560 iommu_flush_all_caches(iommu);
2561 }
2c0ae172
JR		 2562 }
2563
2564 return ret;
fe74c9cf
JR		 2565}
2566
b65233a9
JR		 2567/****************************************************************************
2568 *
2569 * Early detect code. This code runs at IOMMU detection time in the DMA
2570 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2571 * IOMMUs
2572 *
2573 ****************************************************************************/
480125ba 2574int __init amd_iommu_detect(void)
ae7877de 2575{
2c0ae172 2576 int ret;
02f3b3f5 2577
75f1cdf1 2578 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
480125ba 2579 return -ENODEV;
ae7877de 2580
2c0ae172
JR		 2581 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2582 if (ret)
2583 return ret;
11bd04f6 2584
02f3b3f5
JR		 2585 amd_iommu_detected = true;
2586 iommu_detected = 1;
2587 x86_init.iommu.iommu_init = amd_iommu_init;
2588
4781bc42 2589 return 1;
ae7877de
JR		 2590}
2591
b65233a9
JR		 2592/****************************************************************************
2593 *
2594 * Parsing functions for the AMD IOMMU specific kernel command line
2595 * options.
2596 *
2597 ****************************************************************************/
2598
fefda117
JR		 2599static int __init parse_amd_iommu_dump(char *str)
2600{
2601 amd_iommu_dump = true;
2602
2603 return 1;
2604}
2605
3928aa3f
SS		 2606static int __init parse_amd_iommu_intr(char *str)
2607{
2608 for (; *str; ++str) {
2609 if (strncmp(str, "legacy", 6) == 0) {
2610 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2611 break;
2612 }
2613 if (strncmp(str, "vapic", 5) == 0) {
2614 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2615 break;
2616 }
2617 }
2618 return 1;
2619}
2620
918ad6c5
JR		 2621static int __init parse_amd_iommu_options(char *str)
2622{
2623 for (; *str; ++str) {
695b5676 2624 if (strncmp(str, "fullflush", 9) == 0)
afa9fdc2 2625 amd_iommu_unmap_flush = true;
a5235725
JR		 2626 if (strncmp(str, "off", 3) == 0)
2627 amd_iommu_disabled = true;
5abcdba4
JR		 2628 if (strncmp(str, "force_isolation", 15) == 0)
2629 amd_iommu_force_isolation = true;
918ad6c5
JR		 2630 }
2631
2632 return 1;
2633}
2634
440e8998
JR		 2635static int __init parse_ivrs_ioapic(char *str)
2636{
2637 unsigned int bus, dev, fn;
2638 int ret, id, i;
2639 u16 devid;
2640
2641 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2642
2643 if (ret != 4) {
2644 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2645 return 1;
2646 }
2647
2648 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2649 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2650 str);
2651 return 1;
2652 }
2653
2654 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2655
dfbb6d47 2656 cmdline_maps = true;
440e8998
JR		 2657 i = early_ioapic_map_size++;
2658 early_ioapic_map[i].id = id;
2659 early_ioapic_map[i].devid = devid;
2660 early_ioapic_map[i].cmd_line = true;
2661
2662 return 1;
2663}
2664
2665static int __init parse_ivrs_hpet(char *str)
2666{
2667 unsigned int bus, dev, fn;
2668 int ret, id, i;
2669 u16 devid;
2670
2671 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2672
2673 if (ret != 4) {
2674 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2675 return 1;
2676 }
2677
2678 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2679 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2680 str);
2681 return 1;
2682 }
2683
2684 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2685
dfbb6d47 2686 cmdline_maps = true;
440e8998
JR		 2687 i = early_hpet_map_size++;
2688 early_hpet_map[i].id = id;
2689 early_hpet_map[i].devid = devid;
2690 early_hpet_map[i].cmd_line = true;
2691
2692 return 1;
2693}
2694
ca3bf5d4
SS		 2695static int __init parse_ivrs_acpihid(char *str)
2696{
2697 u32 bus, dev, fn;
2698 char *hid, *uid, *p;
2699 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2700 int ret, i;
2701
2702 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2703 if (ret != 4) {
2704 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2705 return 1;
2706 }
2707
2708 p = acpiid;
2709 hid = strsep(&p, ":");
2710 uid = p;
2711
2712 if (!hid || !(*hid) || !uid) {
2713 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2714 return 1;
2715 }
2716
2717 i = early_acpihid_map_size++;
2718 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2719 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2720 early_acpihid_map[i].devid =
2721 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2722 early_acpihid_map[i].cmd_line = true;
2723
2724 return 1;
2725}
2726
440e8998
JR		 2727__setup("amd_iommu_dump", parse_amd_iommu_dump);
2728__setup("amd_iommu=", parse_amd_iommu_options);
3928aa3f 2729__setup("amd_iommu_intr=", parse_amd_iommu_intr);
440e8998
JR		 2730__setup("ivrs_ioapic", parse_ivrs_ioapic);
2731__setup("ivrs_hpet", parse_ivrs_hpet);
ca3bf5d4 2732__setup("ivrs_acpihid", parse_ivrs_acpihid);
22e6daf4
KRW		 2733
2734IOMMU_INIT_FINISH(amd_iommu_detect,
2735 gart_iommu_hole_init,
98f1ad25
JR		 2736 NULL,
2737 NULL);
400a28a0
JR		 2738
2739bool amd_iommu_v2_supported(void)
2740{
2741 return amd_iommu_v2_present;
2742}
2743EXPORT_SYMBOL(amd_iommu_v2_supported);
30861ddc 2744
f5863a00
SS		 2745struct amd_iommu *get_amd_iommu(unsigned int idx)
2746{
2747 unsigned int i = 0;
2748 struct amd_iommu *iommu;
2749
2750 for_each_iommu(iommu)
2751 if (i++ == idx)
2752 return iommu;
2753 return NULL;
2754}
2755EXPORT_SYMBOL(get_amd_iommu);
2756
30861ddc
SK		 2757/****************************************************************************
2758 *
2759 * IOMMU EFR Performance Counter support functionality. This code allows
2760 * access to the IOMMU PC functionality.
2761 *
2762 ****************************************************************************/
2763
f5863a00 2764u8 amd_iommu_pc_get_max_banks(unsigned int idx)
30861ddc 2765{
f5863a00 2766 struct amd_iommu *iommu = get_amd_iommu(idx);
30861ddc 2767
30861ddc 2768 if (iommu)
f5863a00 2769 return iommu->max_banks;
30861ddc 2770
f5863a00 2771 return 0;
30861ddc
SK		 2772}
2773EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2774
2775bool amd_iommu_pc_supported(void)
2776{
2777 return amd_iommu_pc_present;
2778}
2779EXPORT_SYMBOL(amd_iommu_pc_supported);
2780
f5863a00 2781u8 amd_iommu_pc_get_max_counters(unsigned int idx)
30861ddc 2782{
f5863a00 2783 struct amd_iommu *iommu = get_amd_iommu(idx);
30861ddc 2784
30861ddc 2785 if (iommu)
f5863a00 2786 return iommu->max_counters;
30861ddc 2787
f5863a00 2788 return 0;
30861ddc
SK		 2789}
2790EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2791
1650dfd1
SS		 2792static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2793 u8 fxn, u64 *value, bool is_write)
30861ddc 2794{
30861ddc
SK		 2795 u32 offset;
2796 u32 max_offset_lim;
2797
1650dfd1
SS		 2798 /* Make sure the IOMMU PC resource is available */
2799 if (!amd_iommu_pc_present)
2800 return -ENODEV;
2801
30861ddc 2802 /* Check for valid iommu and pc register indexing */
1650dfd1 2803 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
30861ddc
SK		 2804 return -ENODEV;
2805
0a6d80c7 2806 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
30861ddc
SK		 2807
2808 /* Limit the offset to the hw defined mmio region aperture */
0a6d80c7 2809 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
30861ddc
SK		 2810 (iommu->max_counters << 8) | 0x28);
2811 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2812 (offset > max_offset_lim))
2813 return -EINVAL;
2814
2815 if (is_write) {
0a6d80c7
SS		 2816 u64 val = *value & GENMASK_ULL(47, 0);
2817
2818 writel((u32)val, iommu->mmio_base + offset);
2819 writel((val >> 32), iommu->mmio_base + offset + 4);
30861ddc
SK		 2820 } else {
2821 *value = readl(iommu->mmio_base + offset + 4);
2822 *value <<= 32;
0a6d80c7
SS		 2823 *value |= readl(iommu->mmio_base + offset);
2824 *value &= GENMASK_ULL(47, 0);
30861ddc
SK		 2825 }
2826
2827 return 0;
2828}
38e45d02 2829
1650dfd1 2830int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
38e45d02 2831{
1650dfd1
SS		 2832 if (!iommu)
2833 return -EINVAL;
38e45d02 2834
1650dfd1
SS		 2835 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
2836}
2837EXPORT_SYMBOL(amd_iommu_pc_get_reg);
2838
2839int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2840{
2841 if (!iommu)
2842 return -EINVAL;
38e45d02 2843
1650dfd1 2844 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
38e45d02 2845}
1650dfd1 2846EXPORT_SYMBOL(amd_iommu_pc_set_reg);
Empty description
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