[linux.git] / drivers / net / dsa / mv88e6131.c

/*
 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

/*
 * Switch product IDs
 */
#define ID_6085		0x04a0
#define ID_6095		0x0950
#define ID_6131		0x1060

static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	if (ret >= 0) {
		ret &= 0xfff0;
		if (ret == ID_6085)
			return "Marvell 88E6085";
		if (ret == ID_6095)
			return "Marvell 88E6095/88E6095F";
		if (ret == ID_6131)
			return "Marvell 88E6131";
	}

	return NULL;
}

static int mv88e6131_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/*
	 * Set all ports to the disabled state.
	 */
	for (i = 0; i < 11; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/*
	 * Wait for transmit queues to drain.
	 */
	msleep(2);

	/*
	 * Reset the switch.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);

	/*
	 * Wait up to one second for reset to complete.
	 */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0xc800) == 0xc800)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6131_setup_global(struct dsa_switch *ds)
{
	int ret;
	int i;

	/*
	 * Enable the PHY polling unit, don't discard packets with
	 * excessive collisions, use a weighted fair queueing scheme
	 * to arbitrate between packet queues, set the maximum frame
	 * size to 1632, and mask all interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);

	/*
	 * Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);

	/*
	 * Configure the priority mapping registers.
	 */
	ret = mv88e6xxx_config_prio(ds);
	if (ret < 0)
		return ret;

	/*
	 * Set the VLAN ethertype to 0x8100.
	 */
	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);

	/*
	 * Disable ARP mirroring, and configure the upstream port as
	 * the port to which ingress and egress monitor frames are to
	 * be sent.
	 */
	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);

	/*
	 * Disable cascade port functionality unless this device
	 * is used in a cascade configuration, and set the switch's
	 * DSA device number.
	 */
	if (ds->dst->pd->nr_chips > 1)
		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
	else
		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));

	/*
	 * Send all frames with destination addresses matching
	 * 01:80:c2:00:00:0x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);

	/*
	 * Ignore removed tag data on doubly tagged packets, disable
	 * flow control messages, force flow control priority to the
	 * highest, and send all special multicast frames to the CPU
	 * port at the highest priority.
	 */
	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);

	/*
	 * Program the DSA routing table.
	 */
	for (i = 0; i < 32; i++) {
		int nexthop;

		nexthop = 0x1f;
		if (i != ds->index && i < ds->dst->pd->nr_chips)
			nexthop = ds->pd->rtable[i] & 0x1f;

		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
	}

	/*
	 * Clear all trunk masks.
	 */
	for (i = 0; i < 8; i++)
		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);

	/*
	 * Clear all trunk mappings.
	 */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

	/*
	 * Force the priority of IGMP/MLD snoop frames and ARP frames
	 * to the highest setting.
	 */
	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);

	return 0;
}

static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int addr = REG_PORT(p);
	u16 val;

	/*
	 * MAC Forcing register: don't force link, speed, duplex
	 * or flow control state to any particular values on physical
	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
	 * (100 Mb/s on 6085) full duplex.
	 */
	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
		if (ps->id == ID_6085)
			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
		else
			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
	else
		REG_WRITE(addr, 0x01, 0x0003);

	/*
	 * Port Control: disable Core Tag, disable Drop-on-Lock,
	 * transmit frames unmodified, disable Header mode,
	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and
	 * IP priority fields (IP prio has precedence), and set STP
	 * state to Forwarding.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts, and enable DSA tagging
	 * mode.
	 *
	 * If this is the link to another switch, use DSA tagging
	 * mode, but do not enable forwarding of unknown unicasts.
	 */
	val = 0x0433;
	if (p == dsa_upstream_port(ds)) {
		val |= 0x0104;
		/*
		 * On 6085, unknown multicast forward is controlled
		 * here rather than in Port Control 2 register.
		 */
		if (ps->id == ID_6085)
			val |= 0x0008;
	}
	if (ds->dsa_port_mask & (1 << p))
		val |= 0x0100;
	REG_WRITE(addr, 0x04, val);

	/*
	 * Port Control 1: disable trunking.  Also, if this is the
	 * CPU port, enable learn messages to be sent to this port.
	 */
	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);

	/*
	 * Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	val = (p & 0xf) << 12;
	if (dsa_is_cpu_port(ds, p))
		val |= ds->phys_port_mask;
	else
		val |= 1 << dsa_upstream_port(ds);
	REG_WRITE(addr, 0x06, val);

	/*
	 * Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	REG_WRITE(addr, 0x07, 0x0000);

	/*
	 * Port Control 2: don't force a good FCS, don't use
	 * VLAN-based, source address-based or destination
	 * address-based priority overrides, don't let the switch
	 * add or strip 802.1q tags, don't discard tagged or
	 * untagged frames on this port, do a destination address
	 * lookup on received packets as usual, don't send a copy
	 * of all transmitted/received frames on this port to the
	 * CPU, and configure the upstream port number.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown multicast addresses.
	 */
	if (ps->id == ID_6085)
		/*
		 * on 6085, bits 3:0 are reserved, bit 6 control ARP
		 * mirroring, and multicast forward is handled in
		 * Port Control register.
		 */
		REG_WRITE(addr, 0x08, 0x0080);
	else {
		val = 0x0080 | dsa_upstream_port(ds);
		if (p == dsa_upstream_port(ds))
			val |= 0x0040;
		REG_WRITE(addr, 0x08, val);
	}

	/*
	 * Rate Control: disable ingress rate limiting.
	 */
	REG_WRITE(addr, 0x09, 0x0000);

	/*
	 * Rate Control 2: disable egress rate limiting.
	 */
	REG_WRITE(addr, 0x0a, 0x0000);

	/*
	 * Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	/*
	 * Tag Remap: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x18, 0x3210);

	/*
	 * Tag Remap 2: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x19, 0x7654);

	return 0;
}

static int mv88e6131_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int i;
	int ret;

	mutex_init(&ps->smi_mutex);
	mv88e6xxx_ppu_state_init(ds);
	mutex_init(&ps->stats_mutex);

	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;

	ret = mv88e6131_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise vtu and atu */

	ret = mv88e6131_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 11; i++) {
		ret = mv88e6131_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6131_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 11)
		return port;
	return -1;
}

static int
mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
}

static int
mv88e6131_phy_write(struct dsa_switch *ds,
			      int port, int regnum, u16 val)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
}

static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	{ "in_good_octets", 8, 0x00, },
	{ "in_bad_octets", 4, 0x02, },
	{ "in_unicast", 4, 0x04, },
	{ "in_broadcasts", 4, 0x06, },
	{ "in_multicasts", 4, 0x07, },
	{ "in_pause", 4, 0x16, },
	{ "in_undersize", 4, 0x18, },
	{ "in_fragments", 4, 0x19, },
	{ "in_oversize", 4, 0x1a, },
	{ "in_jabber", 4, 0x1b, },
	{ "in_rx_error", 4, 0x1c, },
	{ "in_fcs_error", 4, 0x1d, },
	{ "out_octets", 8, 0x0e, },
	{ "out_unicast", 4, 0x10, },
	{ "out_broadcasts", 4, 0x13, },
	{ "out_multicasts", 4, 0x12, },
	{ "out_pause", 4, 0x15, },
	{ "excessive", 4, 0x11, },
	{ "collisions", 4, 0x1e, },
	{ "deferred", 4, 0x05, },
	{ "single", 4, 0x14, },
	{ "multiple", 4, 0x17, },
	{ "out_fcs_error", 4, 0x03, },
	{ "late", 4, 0x1f, },
	{ "hist_64bytes", 4, 0x08, },
	{ "hist_65_127bytes", 4, 0x09, },
	{ "hist_128_255bytes", 4, 0x0a, },
	{ "hist_256_511bytes", 4, 0x0b, },
	{ "hist_512_1023bytes", 4, 0x0c, },
	{ "hist_1024_max_bytes", 4, 0x0d, },
};

static void
mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
{
	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
			      mv88e6131_hw_stats, port, data);
}

static void
mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
				  int port, uint64_t *data)
{
	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
				    mv88e6131_hw_stats, port, data);
}

static int mv88e6131_get_sset_count(struct dsa_switch *ds)
{
	return ARRAY_SIZE(mv88e6131_hw_stats);
}

struct dsa_switch_driver mv88e6131_switch_driver = {
	.tag_protocol		= cpu_to_be16(ETH_P_DSA),
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6131_probe,
	.setup			= mv88e6131_setup,
	.set_addr		= mv88e6xxx_set_addr_direct,
	.phy_read		= mv88e6131_phy_read,
	.phy_write		= mv88e6131_phy_write,
	.poll_link		= mv88e6xxx_poll_link,
	.get_strings		= mv88e6131_get_strings,
	.get_ethtool_stats	= mv88e6131_get_ethtool_stats,
	.get_sset_count		= mv88e6131_get_sset_count,
};

MODULE_ALIAS("platform:mv88e6085");
MODULE_ALIAS("platform:mv88e6095");
MODULE_ALIAS("platform:mv88e6095f");
MODULE_ALIAS("platform:mv88e6131");
Commit	Line	Data
2e5f0320	1	/*
076d3e10 LB	2	* net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
076d3e10 LB	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e5f0320 LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
2bbba277	12	#include <linux/module.h>
2e5f0320 LB	13	#include <linux/netdevice.h>
2e5f0320 LB	14	#include <linux/phy.h>
c8f0b869	15	#include <net/dsa.h>
2e5f0320 LB	16	#include "mv88e6xxx.h"
2e5f0320 LB	17
ec80bfcb PK	18	/*
	19	* Switch product IDs
	20	*/
	21	#define ID_6085 0x04a0
	22	#define ID_6095 0x0950
	23	#define ID_6131 0x1060
	24
2e5f0320 LB	25	static char mv88e6131_probe(struct mii_bus bus, int sw_addr)
	26	{
	27	int ret;
	28
	29	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	30	if (ret >= 0) {
	31	ret &= 0xfff0;
ec80bfcb PK	32	if (ret == ID_6085)
	33	return "Marvell 88E6085";
	34	if (ret == ID_6095)
076d3e10	35	return "Marvell 88E6095/88E6095F";
ec80bfcb	36	if (ret == ID_6131)
2e5f0320 LB	37	return "Marvell 88E6131";
	38	}
	39
	40	return NULL;
	41	}
	42
	43	static int mv88e6131_switch_reset(struct dsa_switch *ds)
	44	{
	45	int i;
	46	int ret;
	47
	48	/*
	49	* Set all ports to the disabled state.
	50	*/
076d3e10	51	for (i = 0; i < 11; i++) {
2e5f0320 LB	52	ret = REG_READ(REG_PORT(i), 0x04);
	53	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	54	}
	55
	56	/*
	57	* Wait for transmit queues to drain.
	58	*/
	59	msleep(2);
	60
	61	/*
	62	* Reset the switch.
	63	*/
	64	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
	65
	66	/*
	67	* Wait up to one second for reset to complete.
	68	*/
	69	for (i = 0; i < 1000; i++) {
	70	ret = REG_READ(REG_GLOBAL, 0x00);
	71	if ((ret & 0xc800) == 0xc800)
	72	break;
	73
	74	msleep(1);
	75	}
	76	if (i == 1000)
	77	return -ETIMEDOUT;
	78
	79	return 0;
	80	}
	81
	82	static int mv88e6131_setup_global(struct dsa_switch *ds)
	83	{
	84	int ret;
	85	int i;
	86
	87	/*
	88	* Enable the PHY polling unit, don't discard packets with
	89	* excessive collisions, use a weighted fair queueing scheme
	90	* to arbitrate between packet queues, set the maximum frame
	91	* size to 1632, and mask all interrupt sources.
	92	*/
	93	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
	94
	95	/*
	96	* Set the default address aging time to 5 minutes, and
	97	* enable address learn messages to be sent to all message
	98	* ports.
	99	*/
	100	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
	101
	102	/*
	103	* Configure the priority mapping registers.
	104	*/
	105	ret = mv88e6xxx_config_prio(ds);
	106	if (ret < 0)
	107	return ret;
	108
	109	/*
	110	* Set the VLAN ethertype to 0x8100.
	111	*/
	112	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
	113
	114	/*
e84665c9 LB	115	* Disable ARP mirroring, and configure the upstream port as
	116	* the port to which ingress and egress monitor frames are to
	117	* be sent.
2e5f0320	118	*/
e84665c9	119	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) \| 0x00f0);
2e5f0320 LB	120
2e5f0320 LB	121	/*
81399ec6 BG	122	* Disable cascade port functionality unless this device
81399ec6 BG	123	* is used in a cascade configuration, and set the switch's
e84665c9	124	* DSA device number.
2e5f0320	125	*/
81399ec6 BG	126	if (ds->dst->pd->nr_chips > 1)
	127	REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 \| (ds->index & 0x1f));
	128	else
	129	REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 \| (ds->index & 0x1f));
2e5f0320 LB	130
	131	/*
	132	* Send all frames with destination addresses matching
	133	* 01:80:c2:00:00:0x to the CPU port.
	134	*/
	135	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
	136
	137	/*
	138	* Ignore removed tag data on doubly tagged packets, disable
	139	* flow control messages, force flow control priority to the
	140	* highest, and send all special multicast frames to the CPU
25985edc	141	* port at the highest priority.
2e5f0320 LB	142	*/
	143	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
	144
	145	/*
e84665c9	146	* Program the DSA routing table.
2e5f0320	147	*/
e84665c9 LB	148	for (i = 0; i < 32; i++) {
	149	int nexthop;
	150
	151	nexthop = 0x1f;
	152	if (i != ds->index && i < ds->dst->pd->nr_chips)
	153	nexthop = ds->pd->rtable[i] & 0x1f;
	154
	155	REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 \| (i << 8) \| nexthop);
	156	}
2e5f0320 LB	157
	158	/*
	159	* Clear all trunk masks.
	160	*/
	161	for (i = 0; i < 8; i++)
076d3e10	162	REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 \| (i << 12) \| 0x7ff);
2e5f0320 LB	163
	164	/*
	165	* Clear all trunk mappings.
	166	*/
	167	for (i = 0; i < 16; i++)
	168	REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 \| (i << 11));
	169
	170	/*
	171	* Force the priority of IGMP/MLD snoop frames and ARP frames
	172	* to the highest setting.
	173	*/
	174	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
	175
	176	return 0;
	177	}
	178
	179	static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
	180	{
ec80bfcb	181	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
2e5f0320	182	int addr = REG_PORT(p);
e84665c9	183	u16 val;
2e5f0320 LB	184
	185	/*
	186	* MAC Forcing register: don't force link, speed, duplex
076d3e10	187	* or flow control state to any particular values on physical
e84665c9	188	* ports, but force the CPU port and all DSA ports to 1000 Mb/s
ec80bfcb	189	* (100 Mb/s on 6085) full duplex.
2e5f0320	190	*/
e84665c9	191	if (dsa_is_cpu_port(ds, p) \|\| ds->dsa_port_mask & (1 << p))
ec80bfcb PK	192	if (ps->id == ID_6085)
	193	REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
	194	else
	195	REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
076d3e10 LB	196	else
076d3e10 LB	197	REG_WRITE(addr, 0x01, 0x0003);
2e5f0320 LB	198
	199	/*
	200	* Port Control: disable Core Tag, disable Drop-on-Lock,
	201	* transmit frames unmodified, disable Header mode,
	202	* enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	203	* tunneling, determine priority by looking at 802.1p and
	204	* IP priority fields (IP prio has precedence), and set STP
e84665c9 LB	205	* state to Forwarding.
	206	*
	207	* If this is the upstream port for this switch, enable
	208	* forwarding of unknown unicasts, and enable DSA tagging
	209	* mode.
	210	*
	211	* If this is the link to another switch, use DSA tagging
	212	* mode, but do not enable forwarding of unknown unicasts.
2e5f0320	213	*/
e84665c9	214	val = 0x0433;
b3b27005	215	if (p == dsa_upstream_port(ds)) {
e84665c9	216	val \|= 0x0104;
b3b27005 PK	217	/*
	218	* On 6085, unknown multicast forward is controlled
	219	* here rather than in Port Control 2 register.
	220	*/
	221	if (ps->id == ID_6085)
	222	val \|= 0x0008;
	223	}
e84665c9 LB	224	if (ds->dsa_port_mask & (1 << p))
	225	val \|= 0x0100;
	226	REG_WRITE(addr, 0x04, val);
2e5f0320 LB	227
	228	/*
	229	* Port Control 1: disable trunking. Also, if this is the
	230	* CPU port, enable learn messages to be sent to this port.
	231	*/
e84665c9	232	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
2e5f0320 LB	233
	234	/*
	235	* Port based VLAN map: give each port its own address
	236	* database, allow the CPU port to talk to each of the 'real'
	237	* ports, and allow each of the 'real' ports to only talk to
e84665c9	238	* the upstream port.
2e5f0320	239	*/
e84665c9 LB	240	val = (p & 0xf) << 12;
	241	if (dsa_is_cpu_port(ds, p))
	242	val \|= ds->phys_port_mask;
	243	else
	244	val \|= 1 << dsa_upstream_port(ds);
	245	REG_WRITE(addr, 0x06, val);
2e5f0320 LB	246
	247	/*
	248	* Default VLAN ID and priority: don't set a default VLAN
	249	* ID, and set the default packet priority to zero.
	250	*/
	251	REG_WRITE(addr, 0x07, 0x0000);
	252
	253	/*
	254	* Port Control 2: don't force a good FCS, don't use
	255	* VLAN-based, source address-based or destination
	256	* address-based priority overrides, don't let the switch
	257	* add or strip 802.1q tags, don't discard tagged or
	258	* untagged frames on this port, do a destination address
	259	* lookup on received packets as usual, don't send a copy
	260	* of all transmitted/received frames on this port to the
e84665c9 LB	261	* CPU, and configure the upstream port number.
	262	*
	263	* If this is the upstream port for this switch, enable
	264	* forwarding of unknown multicast addresses.
2e5f0320	265	*/
b3b27005 PK	266	if (ps->id == ID_6085)
	267	/*
	268	* on 6085, bits 3:0 are reserved, bit 6 control ARP
	269	* mirroring, and multicast forward is handled in
	270	* Port Control register.
	271	*/
	272	REG_WRITE(addr, 0x08, 0x0080);
	273	else {
	274	val = 0x0080 \| dsa_upstream_port(ds);
	275	if (p == dsa_upstream_port(ds))
	276	val \|= 0x0040;
	277	REG_WRITE(addr, 0x08, val);
	278	}
2e5f0320 LB	279
	280	/*
	281	* Rate Control: disable ingress rate limiting.
	282	*/
	283	REG_WRITE(addr, 0x09, 0x0000);
	284
	285	/*
	286	* Rate Control 2: disable egress rate limiting.
	287	*/
	288	REG_WRITE(addr, 0x0a, 0x0000);
	289
	290	/*
	291	* Port Association Vector: when learning source addresses
	292	* of packets, add the address to the address database using
	293	* a port bitmap that has only the bit for this port set and
	294	* the other bits clear.
	295	*/
	296	REG_WRITE(addr, 0x0b, 1 << p);
	297
	298	/*
	299	* Tag Remap: use an identity 802.1p prio -> switch prio
	300	* mapping.
	301	*/
	302	REG_WRITE(addr, 0x18, 0x3210);
	303
	304	/*
	305	* Tag Remap 2: use an identity 802.1p prio -> switch prio
	306	* mapping.
	307	*/
	308	REG_WRITE(addr, 0x19, 0x7654);
	309
	310	return 0;
	311	}
	312
	313	static int mv88e6131_setup(struct dsa_switch *ds)
	314	{
	315	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
	316	int i;
	317	int ret;
	318
	319	mutex_init(&ps->smi_mutex);
	320	mv88e6xxx_ppu_state_init(ds);
	321	mutex_init(&ps->stats_mutex);
	322
ec80bfcb PK	323	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
ec80bfcb PK	324
2e5f0320 LB	325	ret = mv88e6131_switch_reset(ds);
	326	if (ret < 0)
	327	return ret;
	328
	329	/* @@@ initialise vtu and atu */
	330
	331	ret = mv88e6131_setup_global(ds);
	332	if (ret < 0)
	333	return ret;
	334
076d3e10	335	for (i = 0; i < 11; i++) {
2e5f0320 LB	336	ret = mv88e6131_setup_port(ds, i);
	337	if (ret < 0)
	338	return ret;
	339	}
	340
	341	return 0;
	342	}
	343
	344	static int mv88e6131_port_to_phy_addr(int port)
	345	{
076d3e10	346	if (port >= 0 && port <= 11)
2e5f0320 LB	347	return port;
	348	return -1;
	349	}
	350
	351	static int
	352	mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
	353	{
	354	int addr = mv88e6131_port_to_phy_addr(port);
	355	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
	356	}
	357
	358	static int
	359	mv88e6131_phy_write(struct dsa_switch *ds,
	360	int port, int regnum, u16 val)
	361	{
	362	int addr = mv88e6131_port_to_phy_addr(port);
	363	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
	364	}
	365
	366	static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	367	{ "in_good_octets", 8, 0x00, },
	368	{ "in_bad_octets", 4, 0x02, },
	369	{ "in_unicast", 4, 0x04, },
	370	{ "in_broadcasts", 4, 0x06, },
	371	{ "in_multicasts", 4, 0x07, },
	372	{ "in_pause", 4, 0x16, },
	373	{ "in_undersize", 4, 0x18, },
	374	{ "in_fragments", 4, 0x19, },
	375	{ "in_oversize", 4, 0x1a, },
	376	{ "in_jabber", 4, 0x1b, },
	377	{ "in_rx_error", 4, 0x1c, },
	378	{ "in_fcs_error", 4, 0x1d, },
	379	{ "out_octets", 8, 0x0e, },
	380	{ "out_unicast", 4, 0x10, },
	381	{ "out_broadcasts", 4, 0x13, },
	382	{ "out_multicasts", 4, 0x12, },
	383	{ "out_pause", 4, 0x15, },
	384	{ "excessive", 4, 0x11, },
	385	{ "collisions", 4, 0x1e, },
	386	{ "deferred", 4, 0x05, },
	387	{ "single", 4, 0x14, },
	388	{ "multiple", 4, 0x17, },
	389	{ "out_fcs_error", 4, 0x03, },
	390	{ "late", 4, 0x1f, },
	391	{ "hist_64bytes", 4, 0x08, },
	392	{ "hist_65_127bytes", 4, 0x09, },
	393	{ "hist_128_255bytes", 4, 0x0a, },
	394	{ "hist_256_511bytes", 4, 0x0b, },
	395	{ "hist_512_1023bytes", 4, 0x0c, },
	396	{ "hist_1024_max_bytes", 4, 0x0d, },
	397	};
	398
	399	static void
	400	mv88e6131_get_strings(struct dsa_switch ds, int port, uint8_t data)
	401	{
	402	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
	403	mv88e6131_hw_stats, port, data);
	404	}
	405
	406	static void
	407	mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
	408	int port, uint64_t *data)
	409	{
	410	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
411	mv88e6131_hw_stats, port, data);
412	}
413
414	static int mv88e6131_get_sset_count(struct dsa_switch *ds)
415	{
416	return ARRAY_SIZE(mv88e6131_hw_stats);
417	}
418
98e67308	419	struct dsa_switch_driver mv88e6131_switch_driver = {
09640e63	420	.tag_protocol = cpu_to_be16(ETH_P_DSA),
2e5f0320 LB	421	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	422	.probe = mv88e6131_probe,
	423	.setup = mv88e6131_setup,
	424	.set_addr = mv88e6xxx_set_addr_direct,
	425	.phy_read = mv88e6131_phy_read,
	426	.phy_write = mv88e6131_phy_write,
	427	.poll_link = mv88e6xxx_poll_link,
	428	.get_strings = mv88e6131_get_strings,
	429	.get_ethtool_stats = mv88e6131_get_ethtool_stats,
	430	.get_sset_count = mv88e6131_get_sset_count,
	431	};
3d825ede BH	432
	433	MODULE_ALIAS("platform:mv88e6085");
	434	MODULE_ALIAS("platform:mv88e6095");
	435	MODULE_ALIAS("platform:mv88e6095f");
	436	MODULE_ALIAS("platform:mv88e6131");