[linux.git] / drivers / rtc / rtc-au1xxx.c

/*
 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
 *
 * Copyright (C) 2008 Manuel Lauss <[email protected]>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
 * crystal. Counter 0, which keeps counting during sleep/powerdown, is
 * used to count seconds since the beginning of the unix epoch.
 *
 * The counters must be configured and enabled by bootloader/board code;
 * no checks as to whether they really get a proper 32.768kHz clock are
 * made as this would take far too long.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <asm/mach-au1x00/au1000.h>

/* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)

static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long t;

	t = au_readl(SYS_TOYREAD);

	rtc_time_to_tm(t, tm);

	return rtc_valid_tm(tm);
}

static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long t;

	rtc_tm_to_time(tm, &t);

	au_writel(t, SYS_TOYWRITE);
	au_sync();

	/* wait for the pending register write to succeed.  This can
	 * take up to 6 seconds...
	 */
	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
		msleep(1);

	return 0;
}

static struct rtc_class_ops au1xtoy_rtc_ops = {
	.read_time	= au1xtoy_rtc_read_time,
	.set_time	= au1xtoy_rtc_set_time,
};

static int au1xtoy_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtcdev;
	unsigned long t;
	int ret;

	t = au_readl(SYS_COUNTER_CNTRL);
	if (!(t & CNTR_OK)) {
		dev_err(&pdev->dev, "counters not working; aborting.\n");
		ret = -ENODEV;
		goto out_err;
	}

	ret = -ETIMEDOUT;

	/* set counter0 tickrate to 1Hz if necessary */
	if (au_readl(SYS_TOYTRIM) != 32767) {
		/* wait until hardware gives access to TRIM register */
		t = 0x00100000;
		while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && --t)
			msleep(1);

		if (!t) {
			/* timed out waiting for register access; assume
			 * counters are unusable.
			 */
			dev_err(&pdev->dev, "timeout waiting for access\n");
			goto out_err;
		}

		/* set 1Hz TOY tick rate */
		au_writel(32767, SYS_TOYTRIM);
		au_sync();
	}

	/* wait until the hardware allows writes to the counter reg */
	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
		msleep(1);

	rtcdev = devm_rtc_device_register(&pdev->dev, "rtc-au1xxx",
				     &au1xtoy_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtcdev)) {
		ret = PTR_ERR(rtcdev);
		goto out_err;
	}

	platform_set_drvdata(pdev, rtcdev);

	return 0;

out_err:
	return ret;
}

static int au1xtoy_rtc_remove(struct platform_device *pdev)
{
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver au1xrtc_driver = {
	.driver		= {
		.name	= "rtc-au1xxx",
		.owner	= THIS_MODULE,
	},
	.remove		= au1xtoy_rtc_remove,
};

module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);

MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
MODULE_AUTHOR("Manuel Lauss <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:rtc-au1xxx");
Commit	Line	Data
45fd8a0c ML	1	/*
	2	* Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
	3	*
	4	* Copyright (C) 2008 Manuel Lauss <[email protected]>
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
	12	* crystal. Counter 0, which keeps counting during sleep/powerdown, is
	13	* used to count seconds since the beginning of the unix epoch.
	14	*
	15	* The counters must be configured and enabled by bootloader/board code;
	16	* no checks as to whether they really get a proper 32.768kHz clock are
	17	* made as this would take far too long.
	18	*/
	19
	20	#include <linux/module.h>
	21	#include <linux/kernel.h>
	22	#include <linux/rtc.h>
	23	#include <linux/init.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/io.h>
	26	#include <asm/mach-au1x00/au1000.h>
	27
	28	/* 32kHz clock enabled and detected */
	29	#define CNTR_OK (SYS_CNTRL_E0 \| SYS_CNTRL_32S)
	30
	31	static int au1xtoy_rtc_read_time(struct device dev, struct rtc_time tm)
	32	{
	33	unsigned long t;
	34
	35	t = au_readl(SYS_TOYREAD);
	36
	37	rtc_time_to_tm(t, tm);
	38
	39	return rtc_valid_tm(tm);
	40	}
	41
	42	static int au1xtoy_rtc_set_time(struct device dev, struct rtc_time tm)
	43	{
	44	unsigned long t;
	45
	46	rtc_tm_to_time(tm, &t);
	47
	48	au_writel(t, SYS_TOYWRITE);
	49	au_sync();
	50
	51	/* wait for the pending register write to succeed. This can
	52	* take up to 6 seconds...
	53	*/
	54	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
	55	msleep(1);
	56
	57	return 0;
	58	}
	59
	60	static struct rtc_class_ops au1xtoy_rtc_ops = {
	61	.read_time = au1xtoy_rtc_read_time,
	62	.set_time = au1xtoy_rtc_set_time,
	63	};
	64
5a167f45	65	static int au1xtoy_rtc_probe(struct platform_device *pdev)
45fd8a0c ML	66	{
	67	struct rtc_device *rtcdev;
	68	unsigned long t;
	69	int ret;
	70
	71	t = au_readl(SYS_COUNTER_CNTRL);
	72	if (!(t & CNTR_OK)) {
	73	dev_err(&pdev->dev, "counters not working; aborting.\n");
	74	ret = -ENODEV;
	75	goto out_err;
	76	}
	77
	78	ret = -ETIMEDOUT;
	79
	80	/* set counter0 tickrate to 1Hz if necessary */
	81	if (au_readl(SYS_TOYTRIM) != 32767) {
	82	/* wait until hardware gives access to TRIM register */
	83	t = 0x00100000;
c318c7ac	84	while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && --t)
45fd8a0c ML	85	msleep(1);
	86
	87	if (!t) {
	88	/* timed out waiting for register access; assume
	89	* counters are unusable.
	90	*/
	91	dev_err(&pdev->dev, "timeout waiting for access\n");
	92	goto out_err;
	93	}
	94
	95	/* set 1Hz TOY tick rate */
	96	au_writel(32767, SYS_TOYTRIM);
	97	au_sync();
	98	}
	99
	100	/* wait until the hardware allows writes to the counter reg */
	101	while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
	102	msleep(1);
	103
6c068605	104	rtcdev = devm_rtc_device_register(&pdev->dev, "rtc-au1xxx",
45fd8a0c ML	105	&au1xtoy_rtc_ops, THIS_MODULE);
	106	if (IS_ERR(rtcdev)) {
	107	ret = PTR_ERR(rtcdev);
	108	goto out_err;
	109	}
	110
	111	platform_set_drvdata(pdev, rtcdev);
	112
	113	return 0;
	114
	115	out_err:
	116	return ret;
	117	}
	118
5a167f45	119	static int au1xtoy_rtc_remove(struct platform_device *pdev)
45fd8a0c	120	{
45fd8a0c ML	121	platform_set_drvdata(pdev, NULL);
	122
	123	return 0;
	124	}
	125
	126	static struct platform_driver au1xrtc_driver = {
	127	.driver = {
	128	.name = "rtc-au1xxx",
	129	.owner = THIS_MODULE,
	130	},
5a167f45	131	.remove = au1xtoy_rtc_remove,
45fd8a0c ML	132	};
45fd8a0c ML	133
aaa83458	134	module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
45fd8a0c ML	135
	136	MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
	137	MODULE_AUTHOR("Manuel Lauss <[email protected]>");
	138	MODULE_LICENSE("GPL");
	139	MODULE_ALIAS("platform:rtc-au1xxx");