[linux.git] / drivers / mfd / sec-irq.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
//              http://www.samsung.com

#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/regmap.h>

#include <linux/mfd/samsung/core.h>
#include <linux/mfd/samsung/irq.h>
#include <linux/mfd/samsung/s2mps11.h>
#include <linux/mfd/samsung/s2mps14.h>
#include <linux/mfd/samsung/s2mpu02.h>
#include <linux/mfd/samsung/s5m8763.h>
#include <linux/mfd/samsung/s5m8767.h>

static const struct regmap_irq s2mps11_irqs[] = {
	[S2MPS11_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONF_MASK,
	},
	[S2MPS11_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONR_MASK,
	},
	[S2MPS11_IRQ_JIGONBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBF_MASK,
	},
	[S2MPS11_IRQ_JIGONBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBR_MASK,
	},
	[S2MPS11_IRQ_ACOKBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBF_MASK,
	},
	[S2MPS11_IRQ_ACOKBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBR_MASK,
	},
	[S2MPS11_IRQ_PWRON1S] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRON1S_MASK,
	},
	[S2MPS11_IRQ_MRB] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_MRB_MASK,
	},
	[S2MPS11_IRQ_RTC60S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC60S_MASK,
	},
	[S2MPS11_IRQ_RTCA1] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA1_MASK,
	},
	[S2MPS11_IRQ_RTCA0] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA0_MASK,
	},
	[S2MPS11_IRQ_SMPL] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_SMPL_MASK,
	},
	[S2MPS11_IRQ_RTC1S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC1S_MASK,
	},
	[S2MPS11_IRQ_WTSR] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_WTSR_MASK,
	},
	[S2MPS11_IRQ_INT120C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT120C_MASK,
	},
	[S2MPS11_IRQ_INT140C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT140C_MASK,
	},
};

static const struct regmap_irq s2mps14_irqs[] = {
	[S2MPS14_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONF_MASK,
	},
	[S2MPS14_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONR_MASK,
	},
	[S2MPS14_IRQ_JIGONBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBF_MASK,
	},
	[S2MPS14_IRQ_JIGONBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBR_MASK,
	},
	[S2MPS14_IRQ_ACOKBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBF_MASK,
	},
	[S2MPS14_IRQ_ACOKBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBR_MASK,
	},
	[S2MPS14_IRQ_PWRON1S] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRON1S_MASK,
	},
	[S2MPS14_IRQ_MRB] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_MRB_MASK,
	},
	[S2MPS14_IRQ_RTC60S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC60S_MASK,
	},
	[S2MPS14_IRQ_RTCA1] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA1_MASK,
	},
	[S2MPS14_IRQ_RTCA0] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA0_MASK,
	},
	[S2MPS14_IRQ_SMPL] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_SMPL_MASK,
	},
	[S2MPS14_IRQ_RTC1S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC1S_MASK,
	},
	[S2MPS14_IRQ_WTSR] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_WTSR_MASK,
	},
	[S2MPS14_IRQ_INT120C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT120C_MASK,
	},
	[S2MPS14_IRQ_INT140C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT140C_MASK,
	},
	[S2MPS14_IRQ_TSD] = {
		.reg_offset = 2,
		.mask = S2MPS14_IRQ_TSD_MASK,
	},
};

static const struct regmap_irq s2mpu02_irqs[] = {
	[S2MPU02_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONF_MASK,
	},
	[S2MPU02_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONR_MASK,
	},
	[S2MPU02_IRQ_JIGONBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBF_MASK,
	},
	[S2MPU02_IRQ_JIGONBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBR_MASK,
	},
	[S2MPU02_IRQ_ACOKBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBF_MASK,
	},
	[S2MPU02_IRQ_ACOKBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBR_MASK,
	},
	[S2MPU02_IRQ_PWRON1S] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRON1S_MASK,
	},
	[S2MPU02_IRQ_MRB] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_MRB_MASK,
	},
	[S2MPU02_IRQ_RTC60S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC60S_MASK,
	},
	[S2MPU02_IRQ_RTCA1] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA1_MASK,
	},
	[S2MPU02_IRQ_RTCA0] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA0_MASK,
	},
	[S2MPU02_IRQ_SMPL] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_SMPL_MASK,
	},
	[S2MPU02_IRQ_RTC1S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC1S_MASK,
	},
	[S2MPU02_IRQ_WTSR] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_WTSR_MASK,
	},
	[S2MPU02_IRQ_INT120C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT120C_MASK,
	},
	[S2MPU02_IRQ_INT140C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT140C_MASK,
	},
	[S2MPU02_IRQ_TSD] = {
		.reg_offset = 2,
		.mask = S2MPS14_IRQ_TSD_MASK,
	},
};

static const struct regmap_irq s5m8767_irqs[] = {
	[S5M8767_IRQ_PWRR] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWRR_MASK,
	},
	[S5M8767_IRQ_PWRF] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWRF_MASK,
	},
	[S5M8767_IRQ_PWR1S] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWR1S_MASK,
	},
	[S5M8767_IRQ_JIGR] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_JIGR_MASK,
	},
	[S5M8767_IRQ_JIGF] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_JIGF_MASK,
	},
	[S5M8767_IRQ_LOWBAT2] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_LOWBAT2_MASK,
	},
	[S5M8767_IRQ_LOWBAT1] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_LOWBAT1_MASK,
	},
	[S5M8767_IRQ_MRB] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_MRB_MASK,
	},
	[S5M8767_IRQ_DVSOK2] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK2_MASK,
	},
	[S5M8767_IRQ_DVSOK3] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK3_MASK,
	},
	[S5M8767_IRQ_DVSOK4] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK4_MASK,
	},
	[S5M8767_IRQ_RTC60S] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTC60S_MASK,
	},
	[S5M8767_IRQ_RTCA1] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTCA1_MASK,
	},
	[S5M8767_IRQ_RTCA2] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTCA2_MASK,
	},
	[S5M8767_IRQ_SMPL] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_SMPL_MASK,
	},
	[S5M8767_IRQ_RTC1S] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTC1S_MASK,
	},
	[S5M8767_IRQ_WTSR] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_WTSR_MASK,
	},
};

static const struct regmap_irq s5m8763_irqs[] = {
	[S5M8763_IRQ_DCINF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_DCINF_MASK,
	},
	[S5M8763_IRQ_DCINR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_DCINR_MASK,
	},
	[S5M8763_IRQ_JIGF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_JIGF_MASK,
	},
	[S5M8763_IRQ_JIGR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_JIGR_MASK,
	},
	[S5M8763_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_PWRONF_MASK,
	},
	[S5M8763_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_PWRONR_MASK,
	},
	[S5M8763_IRQ_WTSREVNT] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_WTSREVNT_MASK,
	},
	[S5M8763_IRQ_SMPLEVNT] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_SMPLEVNT_MASK,
	},
	[S5M8763_IRQ_ALARM1] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_ALARM1_MASK,
	},
	[S5M8763_IRQ_ALARM0] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_ALARM0_MASK,
	},
	[S5M8763_IRQ_ONKEY1S] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_ONKEY1S_MASK,
	},
	[S5M8763_IRQ_TOPOFFR] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_TOPOFFR_MASK,
	},
	[S5M8763_IRQ_DCINOVPR] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_DCINOVPR_MASK,
	},
	[S5M8763_IRQ_CHGRSTF] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_CHGRSTF_MASK,
	},
	[S5M8763_IRQ_DONER] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_DONER_MASK,
	},
	[S5M8763_IRQ_CHGFAULT] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_CHGFAULT_MASK,
	},
	[S5M8763_IRQ_LOBAT1] = {
		.reg_offset = 3,
		.mask = S5M8763_IRQ_LOBAT1_MASK,
	},
	[S5M8763_IRQ_LOBAT2] = {
		.reg_offset = 3,
		.mask = S5M8763_IRQ_LOBAT2_MASK,
	},
};

static const struct regmap_irq_chip s2mps11_irq_chip = {
	.name = "s2mps11",
	.irqs = s2mps11_irqs,
	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
	.num_regs = 3,
	.status_base = S2MPS11_REG_INT1,
	.mask_base = S2MPS11_REG_INT1M,
	.ack_base = S2MPS11_REG_INT1,
};

#define S2MPS1X_IRQ_CHIP_COMMON_DATA		\
	.irqs = s2mps14_irqs,			\
	.num_irqs = ARRAY_SIZE(s2mps14_irqs),	\
	.num_regs = 3,				\
	.status_base = S2MPS14_REG_INT1,	\
	.mask_base = S2MPS14_REG_INT1M,		\
	.ack_base = S2MPS14_REG_INT1		\

static const struct regmap_irq_chip s2mps13_irq_chip = {
	.name = "s2mps13",
	S2MPS1X_IRQ_CHIP_COMMON_DATA,
};

static const struct regmap_irq_chip s2mps14_irq_chip = {
	.name = "s2mps14",
	S2MPS1X_IRQ_CHIP_COMMON_DATA,
};

static const struct regmap_irq_chip s2mps15_irq_chip = {
	.name = "s2mps15",
	S2MPS1X_IRQ_CHIP_COMMON_DATA,
};

static const struct regmap_irq_chip s2mpu02_irq_chip = {
	.name = "s2mpu02",
	.irqs = s2mpu02_irqs,
	.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
	.num_regs = 3,
	.status_base = S2MPU02_REG_INT1,
	.mask_base = S2MPU02_REG_INT1M,
	.ack_base = S2MPU02_REG_INT1,
};

static const struct regmap_irq_chip s5m8767_irq_chip = {
	.name = "s5m8767",
	.irqs = s5m8767_irqs,
	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
	.num_regs = 3,
	.status_base = S5M8767_REG_INT1,
	.mask_base = S5M8767_REG_INT1M,
	.ack_base = S5M8767_REG_INT1,
};

static const struct regmap_irq_chip s5m8763_irq_chip = {
	.name = "s5m8763",
	.irqs = s5m8763_irqs,
	.num_irqs = ARRAY_SIZE(s5m8763_irqs),
	.num_regs = 4,
	.status_base = S5M8763_REG_IRQ1,
	.mask_base = S5M8763_REG_IRQM1,
	.ack_base = S5M8763_REG_IRQ1,
};

int sec_irq_init(struct sec_pmic_dev *sec_pmic)
{
	int ret = 0;
	int type = sec_pmic->device_type;
	const struct regmap_irq_chip *sec_irq_chip;

	if (!sec_pmic->irq) {
		dev_warn(sec_pmic->dev,
			 "No interrupt specified, no interrupts\n");
		sec_pmic->irq_base = 0;
		return 0;
	}

	switch (type) {
	case S5M8763X:
		sec_irq_chip = &s5m8763_irq_chip;
		break;
	case S5M8767X:
		sec_irq_chip = &s5m8767_irq_chip;
		break;
	case S2MPS11X:
		sec_irq_chip = &s2mps11_irq_chip;
		break;
	case S2MPS13X:
		sec_irq_chip = &s2mps13_irq_chip;
		break;
	case S2MPS14X:
		sec_irq_chip = &s2mps14_irq_chip;
		break;
	case S2MPS15X:
		sec_irq_chip = &s2mps15_irq_chip;
		break;
	case S2MPU02:
		sec_irq_chip = &s2mpu02_irq_chip;
		break;
	default:
		dev_err(sec_pmic->dev, "Unknown device type %lu\n",
			sec_pmic->device_type);
		return -EINVAL;
	}

	ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
				       sec_pmic->irq,
				       IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				       sec_pmic->irq_base, sec_irq_chip,
				       &sec_pmic->irq_data);
	if (ret != 0) {
		dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
		return ret;
	}

	/*
	 * The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
	 * so the interrupt number must be consistent.
	 */
	BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);

	return 0;
}
EXPORT_SYMBOL_GPL(sec_irq_init);

MODULE_AUTHOR("Sangbeom Kim <[email protected]>");
MODULE_AUTHOR("Chanwoo Choi <[email protected]>");
MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>");
MODULE_DESCRIPTION("Interrupt support for the S5M MFD");
MODULE_LICENSE("GPL");
Commit	Line	Data
39b27ad9 KK	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
	4	// http://www.samsung.com
5ac2ffa7 SK	5
	6	#include <linux/device.h>
	7	#include <linux/interrupt.h>
	8	#include <linux/irq.h>
eef0594a	9	#include <linux/module.h>
6445b84a SK	10	#include <linux/regmap.h>
6445b84a SK	11
54227bcf SK	12	#include <linux/mfd/samsung/core.h>
54227bcf SK	13	#include <linux/mfd/samsung/irq.h>
6445b84a	14	#include <linux/mfd/samsung/s2mps11.h>
dc691966	15	#include <linux/mfd/samsung/s2mps14.h>
54e8827d	16	#include <linux/mfd/samsung/s2mpu02.h>
54227bcf SK	17	#include <linux/mfd/samsung/s5m8763.h>
54227bcf SK	18	#include <linux/mfd/samsung/s5m8767.h>
5ac2ffa7	19
a30fffb0	20	static const struct regmap_irq s2mps11_irqs[] = {
6445b84a	21	[S2MPS11_IRQ_PWRONF] = {
5e393a22	22	.reg_offset = 0,
6445b84a SK	23	.mask = S2MPS11_IRQ_PWRONF_MASK,
	24	},
	25	[S2MPS11_IRQ_PWRONR] = {
5e393a22	26	.reg_offset = 0,
6445b84a SK	27	.mask = S2MPS11_IRQ_PWRONR_MASK,
	28	},
	29	[S2MPS11_IRQ_JIGONBF] = {
5e393a22	30	.reg_offset = 0,
6445b84a SK	31	.mask = S2MPS11_IRQ_JIGONBF_MASK,
	32	},
	33	[S2MPS11_IRQ_JIGONBR] = {
5e393a22	34	.reg_offset = 0,
6445b84a SK	35	.mask = S2MPS11_IRQ_JIGONBR_MASK,
	36	},
	37	[S2MPS11_IRQ_ACOKBF] = {
5e393a22	38	.reg_offset = 0,
6445b84a SK	39	.mask = S2MPS11_IRQ_ACOKBF_MASK,
	40	},
	41	[S2MPS11_IRQ_ACOKBR] = {
5e393a22	42	.reg_offset = 0,
6445b84a SK	43	.mask = S2MPS11_IRQ_ACOKBR_MASK,
	44	},
	45	[S2MPS11_IRQ_PWRON1S] = {
5e393a22	46	.reg_offset = 0,
6445b84a SK	47	.mask = S2MPS11_IRQ_PWRON1S_MASK,
	48	},
	49	[S2MPS11_IRQ_MRB] = {
5e393a22	50	.reg_offset = 0,
6445b84a SK	51	.mask = S2MPS11_IRQ_MRB_MASK,
	52	},
	53	[S2MPS11_IRQ_RTC60S] = {
5e393a22	54	.reg_offset = 1,
6445b84a SK	55	.mask = S2MPS11_IRQ_RTC60S_MASK,
6445b84a SK	56	},
67762095	57	[S2MPS11_IRQ_RTCA1] = {
5e393a22	58	.reg_offset = 1,
67762095	59	.mask = S2MPS11_IRQ_RTCA1_MASK,
6445b84a	60	},
e554a99e KK	61	[S2MPS11_IRQ_RTCA0] = {
	62	.reg_offset = 1,
	63	.mask = S2MPS11_IRQ_RTCA0_MASK,
	64	},
6445b84a	65	[S2MPS11_IRQ_SMPL] = {
5e393a22	66	.reg_offset = 1,
6445b84a SK	67	.mask = S2MPS11_IRQ_SMPL_MASK,
	68	},
	69	[S2MPS11_IRQ_RTC1S] = {
5e393a22	70	.reg_offset = 1,
6445b84a SK	71	.mask = S2MPS11_IRQ_RTC1S_MASK,
	72	},
	73	[S2MPS11_IRQ_WTSR] = {
5e393a22	74	.reg_offset = 1,
6445b84a SK	75	.mask = S2MPS11_IRQ_WTSR_MASK,
	76	},
	77	[S2MPS11_IRQ_INT120C] = {
5e393a22	78	.reg_offset = 2,
6445b84a SK	79	.mask = S2MPS11_IRQ_INT120C_MASK,
	80	},
	81	[S2MPS11_IRQ_INT140C] = {
5e393a22	82	.reg_offset = 2,
6445b84a SK	83	.mask = S2MPS11_IRQ_INT140C_MASK,
6445b84a SK	84	},
5ac2ffa7 SK	85	};
5ac2ffa7 SK	86
dc691966 KK	87	static const struct regmap_irq s2mps14_irqs[] = {
	88	[S2MPS14_IRQ_PWRONF] = {
	89	.reg_offset = 0,
	90	.mask = S2MPS11_IRQ_PWRONF_MASK,
	91	},
	92	[S2MPS14_IRQ_PWRONR] = {
	93	.reg_offset = 0,
	94	.mask = S2MPS11_IRQ_PWRONR_MASK,
	95	},
	96	[S2MPS14_IRQ_JIGONBF] = {
	97	.reg_offset = 0,
	98	.mask = S2MPS11_IRQ_JIGONBF_MASK,
	99	},
	100	[S2MPS14_IRQ_JIGONBR] = {
	101	.reg_offset = 0,
	102	.mask = S2MPS11_IRQ_JIGONBR_MASK,
	103	},
	104	[S2MPS14_IRQ_ACOKBF] = {
	105	.reg_offset = 0,
	106	.mask = S2MPS11_IRQ_ACOKBF_MASK,
	107	},
	108	[S2MPS14_IRQ_ACOKBR] = {
	109	.reg_offset = 0,
	110	.mask = S2MPS11_IRQ_ACOKBR_MASK,
	111	},
	112	[S2MPS14_IRQ_PWRON1S] = {
	113	.reg_offset = 0,
	114	.mask = S2MPS11_IRQ_PWRON1S_MASK,
	115	},
	116	[S2MPS14_IRQ_MRB] = {
	117	.reg_offset = 0,
	118	.mask = S2MPS11_IRQ_MRB_MASK,
	119	},
	120	[S2MPS14_IRQ_RTC60S] = {
	121	.reg_offset = 1,
	122	.mask = S2MPS11_IRQ_RTC60S_MASK,
	123	},
	124	[S2MPS14_IRQ_RTCA1] = {
	125	.reg_offset = 1,
	126	.mask = S2MPS11_IRQ_RTCA1_MASK,
	127	},
	128	[S2MPS14_IRQ_RTCA0] = {
	129	.reg_offset = 1,
	130	.mask = S2MPS11_IRQ_RTCA0_MASK,
	131	},
	132	[S2MPS14_IRQ_SMPL] = {
	133	.reg_offset = 1,
	134	.mask = S2MPS11_IRQ_SMPL_MASK,
	135	},
	136	[S2MPS14_IRQ_RTC1S] = {
	137	.reg_offset = 1,
	138	.mask = S2MPS11_IRQ_RTC1S_MASK,
	139	},
	140	[S2MPS14_IRQ_WTSR] = {
	141	.reg_offset = 1,
	142	.mask = S2MPS11_IRQ_WTSR_MASK,
	143	},
	144	[S2MPS14_IRQ_INT120C] = {
	145	.reg_offset = 2,
	146	.mask = S2MPS11_IRQ_INT120C_MASK,
	147	},
	148	[S2MPS14_IRQ_INT140C] = {
	149	.reg_offset = 2,
	150	.mask = S2MPS11_IRQ_INT140C_MASK,
151	},
152	[S2MPS14_IRQ_TSD] = {
153	.reg_offset = 2,
154	.mask = S2MPS14_IRQ_TSD_MASK,
155	},
156	};
6445b84a	157
54e8827d CC	158	static const struct regmap_irq s2mpu02_irqs[] = {
	159	[S2MPU02_IRQ_PWRONF] = {
	160	.reg_offset = 0,
	161	.mask = S2MPS11_IRQ_PWRONF_MASK,
	162	},
	163	[S2MPU02_IRQ_PWRONR] = {
	164	.reg_offset = 0,
	165	.mask = S2MPS11_IRQ_PWRONR_MASK,
	166	},
	167	[S2MPU02_IRQ_JIGONBF] = {
	168	.reg_offset = 0,
	169	.mask = S2MPS11_IRQ_JIGONBF_MASK,
	170	},
	171	[S2MPU02_IRQ_JIGONBR] = {
	172	.reg_offset = 0,
	173	.mask = S2MPS11_IRQ_JIGONBR_MASK,
	174	},
	175	[S2MPU02_IRQ_ACOKBF] = {
	176	.reg_offset = 0,
	177	.mask = S2MPS11_IRQ_ACOKBF_MASK,
	178	},
	179	[S2MPU02_IRQ_ACOKBR] = {
	180	.reg_offset = 0,
	181	.mask = S2MPS11_IRQ_ACOKBR_MASK,
	182	},
	183	[S2MPU02_IRQ_PWRON1S] = {
	184	.reg_offset = 0,
	185	.mask = S2MPS11_IRQ_PWRON1S_MASK,
	186	},
	187	[S2MPU02_IRQ_MRB] = {
	188	.reg_offset = 0,
	189	.mask = S2MPS11_IRQ_MRB_MASK,
	190	},
	191	[S2MPU02_IRQ_RTC60S] = {
	192	.reg_offset = 1,
	193	.mask = S2MPS11_IRQ_RTC60S_MASK,
	194	},
	195	[S2MPU02_IRQ_RTCA1] = {
	196	.reg_offset = 1,
	197	.mask = S2MPS11_IRQ_RTCA1_MASK,
	198	},
	199	[S2MPU02_IRQ_RTCA0] = {
	200	.reg_offset = 1,
	201	.mask = S2MPS11_IRQ_RTCA0_MASK,
	202	},
	203	[S2MPU02_IRQ_SMPL] = {
	204	.reg_offset = 1,
	205	.mask = S2MPS11_IRQ_SMPL_MASK,
	206	},
	207	[S2MPU02_IRQ_RTC1S] = {
	208	.reg_offset = 1,
	209	.mask = S2MPS11_IRQ_RTC1S_MASK,
	210	},
	211	[S2MPU02_IRQ_WTSR] = {
	212	.reg_offset = 1,
	213	.mask = S2MPS11_IRQ_WTSR_MASK,
	214	},
	215	[S2MPU02_IRQ_INT120C] = {
	216	.reg_offset = 2,
	217	.mask = S2MPS11_IRQ_INT120C_MASK,
	218	},
	219	[S2MPU02_IRQ_INT140C] = {
	220	.reg_offset = 2,
	221	.mask = S2MPS11_IRQ_INT140C_MASK,
222	},
223	[S2MPU02_IRQ_TSD] = {
224	.reg_offset = 2,
225	.mask = S2MPS14_IRQ_TSD_MASK,
226	},
227	};
228
a30fffb0	229	static const struct regmap_irq s5m8767_irqs[] = {
5ac2ffa7	230	[S5M8767_IRQ_PWRR] = {
5e393a22	231	.reg_offset = 0,
5ac2ffa7 SK	232	.mask = S5M8767_IRQ_PWRR_MASK,
	233	},
	234	[S5M8767_IRQ_PWRF] = {
5e393a22	235	.reg_offset = 0,
5ac2ffa7 SK	236	.mask = S5M8767_IRQ_PWRF_MASK,
	237	},
	238	[S5M8767_IRQ_PWR1S] = {
5e393a22	239	.reg_offset = 0,
5ac2ffa7 SK	240	.mask = S5M8767_IRQ_PWR1S_MASK,
	241	},
	242	[S5M8767_IRQ_JIGR] = {
5e393a22	243	.reg_offset = 0,
5ac2ffa7 SK	244	.mask = S5M8767_IRQ_JIGR_MASK,
	245	},
	246	[S5M8767_IRQ_JIGF] = {
5e393a22	247	.reg_offset = 0,
5ac2ffa7 SK	248	.mask = S5M8767_IRQ_JIGF_MASK,
	249	},
	250	[S5M8767_IRQ_LOWBAT2] = {
5e393a22	251	.reg_offset = 0,
5ac2ffa7 SK	252	.mask = S5M8767_IRQ_LOWBAT2_MASK,
	253	},
	254	[S5M8767_IRQ_LOWBAT1] = {
5e393a22	255	.reg_offset = 0,
5ac2ffa7 SK	256	.mask = S5M8767_IRQ_LOWBAT1_MASK,
	257	},
	258	[S5M8767_IRQ_MRB] = {
5e393a22	259	.reg_offset = 1,
5ac2ffa7 SK	260	.mask = S5M8767_IRQ_MRB_MASK,
	261	},
	262	[S5M8767_IRQ_DVSOK2] = {
5e393a22	263	.reg_offset = 1,
5ac2ffa7 SK	264	.mask = S5M8767_IRQ_DVSOK2_MASK,
	265	},
	266	[S5M8767_IRQ_DVSOK3] = {
5e393a22	267	.reg_offset = 1,
5ac2ffa7 SK	268	.mask = S5M8767_IRQ_DVSOK3_MASK,
	269	},
	270	[S5M8767_IRQ_DVSOK4] = {
5e393a22	271	.reg_offset = 1,
5ac2ffa7 SK	272	.mask = S5M8767_IRQ_DVSOK4_MASK,
	273	},
	274	[S5M8767_IRQ_RTC60S] = {
5e393a22	275	.reg_offset = 2,
5ac2ffa7 SK	276	.mask = S5M8767_IRQ_RTC60S_MASK,
	277	},
	278	[S5M8767_IRQ_RTCA1] = {
5e393a22	279	.reg_offset = 2,
5ac2ffa7 SK	280	.mask = S5M8767_IRQ_RTCA1_MASK,
	281	},
	282	[S5M8767_IRQ_RTCA2] = {
5e393a22	283	.reg_offset = 2,
5ac2ffa7 SK	284	.mask = S5M8767_IRQ_RTCA2_MASK,
	285	},
	286	[S5M8767_IRQ_SMPL] = {
5e393a22	287	.reg_offset = 2,
5ac2ffa7 SK	288	.mask = S5M8767_IRQ_SMPL_MASK,
	289	},
	290	[S5M8767_IRQ_RTC1S] = {
5e393a22	291	.reg_offset = 2,
5ac2ffa7 SK	292	.mask = S5M8767_IRQ_RTC1S_MASK,
	293	},
	294	[S5M8767_IRQ_WTSR] = {
5e393a22	295	.reg_offset = 2,
5ac2ffa7 SK	296	.mask = S5M8767_IRQ_WTSR_MASK,
	297	},
	298	};
	299
a30fffb0	300	static const struct regmap_irq s5m8763_irqs[] = {
5ac2ffa7	301	[S5M8763_IRQ_DCINF] = {
5e393a22	302	.reg_offset = 0,
5ac2ffa7 SK	303	.mask = S5M8763_IRQ_DCINF_MASK,
	304	},
	305	[S5M8763_IRQ_DCINR] = {
5e393a22	306	.reg_offset = 0,
5ac2ffa7 SK	307	.mask = S5M8763_IRQ_DCINR_MASK,
	308	},
	309	[S5M8763_IRQ_JIGF] = {
5e393a22	310	.reg_offset = 0,
5ac2ffa7 SK	311	.mask = S5M8763_IRQ_JIGF_MASK,
	312	},
	313	[S5M8763_IRQ_JIGR] = {
5e393a22	314	.reg_offset = 0,
5ac2ffa7 SK	315	.mask = S5M8763_IRQ_JIGR_MASK,
	316	},
	317	[S5M8763_IRQ_PWRONF] = {
5e393a22	318	.reg_offset = 0,
5ac2ffa7 SK	319	.mask = S5M8763_IRQ_PWRONF_MASK,
	320	},
	321	[S5M8763_IRQ_PWRONR] = {
5e393a22	322	.reg_offset = 0,
5ac2ffa7 SK	323	.mask = S5M8763_IRQ_PWRONR_MASK,
	324	},
	325	[S5M8763_IRQ_WTSREVNT] = {
5e393a22	326	.reg_offset = 1,
5ac2ffa7 SK	327	.mask = S5M8763_IRQ_WTSREVNT_MASK,
	328	},
	329	[S5M8763_IRQ_SMPLEVNT] = {
5e393a22	330	.reg_offset = 1,
5ac2ffa7 SK	331	.mask = S5M8763_IRQ_SMPLEVNT_MASK,
	332	},
	333	[S5M8763_IRQ_ALARM1] = {
5e393a22	334	.reg_offset = 1,
5ac2ffa7 SK	335	.mask = S5M8763_IRQ_ALARM1_MASK,
	336	},
	337	[S5M8763_IRQ_ALARM0] = {
5e393a22	338	.reg_offset = 1,
5ac2ffa7 SK	339	.mask = S5M8763_IRQ_ALARM0_MASK,
	340	},
	341	[S5M8763_IRQ_ONKEY1S] = {
5e393a22	342	.reg_offset = 2,
5ac2ffa7 SK	343	.mask = S5M8763_IRQ_ONKEY1S_MASK,
	344	},
	345	[S5M8763_IRQ_TOPOFFR] = {
5e393a22	346	.reg_offset = 2,
5ac2ffa7 SK	347	.mask = S5M8763_IRQ_TOPOFFR_MASK,
	348	},
	349	[S5M8763_IRQ_DCINOVPR] = {
5e393a22	350	.reg_offset = 2,
5ac2ffa7 SK	351	.mask = S5M8763_IRQ_DCINOVPR_MASK,
	352	},
	353	[S5M8763_IRQ_CHGRSTF] = {
5e393a22	354	.reg_offset = 2,
5ac2ffa7 SK	355	.mask = S5M8763_IRQ_CHGRSTF_MASK,
	356	},
	357	[S5M8763_IRQ_DONER] = {
5e393a22	358	.reg_offset = 2,
5ac2ffa7 SK	359	.mask = S5M8763_IRQ_DONER_MASK,
	360	},
	361	[S5M8763_IRQ_CHGFAULT] = {
5e393a22	362	.reg_offset = 2,
5ac2ffa7 SK	363	.mask = S5M8763_IRQ_CHGFAULT_MASK,
	364	},
	365	[S5M8763_IRQ_LOBAT1] = {
5e393a22	366	.reg_offset = 3,
5ac2ffa7 SK	367	.mask = S5M8763_IRQ_LOBAT1_MASK,
	368	},
	369	[S5M8763_IRQ_LOBAT2] = {
5e393a22	370	.reg_offset = 3,
5ac2ffa7 SK	371	.mask = S5M8763_IRQ_LOBAT2_MASK,
	372	},
	373	};
	374
a30fffb0	375	static const struct regmap_irq_chip s2mps11_irq_chip = {
6445b84a SK	376	.name = "s2mps11",
	377	.irqs = s2mps11_irqs,
	378	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
	379	.num_regs = 3,
	380	.status_base = S2MPS11_REG_INT1,
	381	.mask_base = S2MPS11_REG_INT1M,
	382	.ack_base = S2MPS11_REG_INT1,
	383	};
5ac2ffa7	384
3bc2ee91 CC	385	#define S2MPS1X_IRQ_CHIP_COMMON_DATA \
	386	.irqs = s2mps14_irqs, \
	387	.num_irqs = ARRAY_SIZE(s2mps14_irqs), \
	388	.num_regs = 3, \
	389	.status_base = S2MPS14_REG_INT1, \
	390	.mask_base = S2MPS14_REG_INT1M, \
	391	.ack_base = S2MPS14_REG_INT1 \
	392
	393	static const struct regmap_irq_chip s2mps13_irq_chip = {
	394	.name = "s2mps13",
	395	S2MPS1X_IRQ_CHIP_COMMON_DATA,
	396	};
	397
dc691966 KK	398	static const struct regmap_irq_chip s2mps14_irq_chip = {
dc691966 KK	399	.name = "s2mps14",
3bc2ee91	400	S2MPS1X_IRQ_CHIP_COMMON_DATA,
dc691966 KK	401	};
dc691966 KK	402
9e4808d2 TA	403	static const struct regmap_irq_chip s2mps15_irq_chip = {
	404	.name = "s2mps15",
	405	S2MPS1X_IRQ_CHIP_COMMON_DATA,
	406	};
	407
54e8827d CC	408	static const struct regmap_irq_chip s2mpu02_irq_chip = {
	409	.name = "s2mpu02",
	410	.irqs = s2mpu02_irqs,
	411	.num_irqs = ARRAY_SIZE(s2mpu02_irqs),
	412	.num_regs = 3,
	413	.status_base = S2MPU02_REG_INT1,
	414	.mask_base = S2MPU02_REG_INT1M,
	415	.ack_base = S2MPU02_REG_INT1,
	416	};
	417
a30fffb0	418	static const struct regmap_irq_chip s5m8767_irq_chip = {
5ac2ffa7	419	.name = "s5m8767",
6445b84a SK	420	.irqs = s5m8767_irqs,
	421	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
	422	.num_regs = 3,
	423	.status_base = S5M8767_REG_INT1,
	424	.mask_base = S5M8767_REG_INT1M,
	425	.ack_base = S5M8767_REG_INT1,
5ac2ffa7 SK	426	};
5ac2ffa7 SK	427
a30fffb0	428	static const struct regmap_irq_chip s5m8763_irq_chip = {
5ac2ffa7	429	.name = "s5m8763",
6445b84a SK	430	.irqs = s5m8763_irqs,
	431	.num_irqs = ARRAY_SIZE(s5m8763_irqs),
	432	.num_regs = 4,
	433	.status_base = S5M8763_REG_IRQ1,
	434	.mask_base = S5M8763_REG_IRQM1,
	435	.ack_base = S5M8763_REG_IRQ1,
5ac2ffa7 SK	436	};
5ac2ffa7 SK	437
63063bfb	438	int sec_irq_init(struct sec_pmic_dev *sec_pmic)
5ac2ffa7	439	{
5ac2ffa7	440	int ret = 0;
63063bfb	441	int type = sec_pmic->device_type;
54e8827d	442	const struct regmap_irq_chip *sec_irq_chip;
5ac2ffa7	443
63063bfb SK	444	if (!sec_pmic->irq) {
63063bfb SK	445	dev_warn(sec_pmic->dev,
5ac2ffa7	446	"No interrupt specified, no interrupts\n");
63063bfb	447	sec_pmic->irq_base = 0;
5ac2ffa7 SK	448	return 0;
	449	}
	450
5ac2ffa7 SK	451	switch (type) {
5ac2ffa7 SK	452	case S5M8763X:
54e8827d	453	sec_irq_chip = &s5m8763_irq_chip;
5ac2ffa7 SK	454	break;
5ac2ffa7 SK	455	case S5M8767X:
54e8827d	456	sec_irq_chip = &s5m8767_irq_chip;
5ac2ffa7	457	break;
6445b84a	458	case S2MPS11X:
54e8827d	459	sec_irq_chip = &s2mps11_irq_chip;
5ac2ffa7	460	break;
3bc2ee91 CC	461	case S2MPS13X:
	462	sec_irq_chip = &s2mps13_irq_chip;
	463	break;
dc691966	464	case S2MPS14X:
54e8827d CC	465	sec_irq_chip = &s2mps14_irq_chip;
54e8827d CC	466	break;
9e4808d2 TA	467	case S2MPS15X:
	468	sec_irq_chip = &s2mps15_irq_chip;
	469	break;
54e8827d CC	470	case S2MPU02:
54e8827d CC	471	sec_irq_chip = &s2mpu02_irq_chip;
dc691966	472	break;
5ac2ffa7	473	default:
9549b5ff	474	dev_err(sec_pmic->dev, "Unknown device type %lu\n",
6445b84a SK	475	sec_pmic->device_type);
6445b84a SK	476	return -EINVAL;
5ac2ffa7 SK	477	}
5ac2ffa7 SK	478
3dc6f4aa LD	479	ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic,
	480	sec_pmic->irq,
	481	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	482	sec_pmic->irq_base, sec_irq_chip,
	483	&sec_pmic->irq_data);
6445b84a SK	484	if (ret != 0) {
6445b84a SK	485	dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
c7a1fcf3 JC	486	return ret;
c7a1fcf3 JC	487	}
5ac2ffa7	488
e554a99e KK	489	/*
	490	* The rtc-s5m driver requests S2MPS14_IRQ_RTCA0 also for S2MPS11
	491	* so the interrupt number must be consistent.
	492	*/
	493	BUILD_BUG_ON(((enum s2mps14_irq)S2MPS11_IRQ_RTCA0) != S2MPS14_IRQ_RTCA0);
	494
5ac2ffa7 SK	495	return 0;
5ac2ffa7 SK	496	}
eef0594a KK	497	EXPORT_SYMBOL_GPL(sec_irq_init);
	498
	499	MODULE_AUTHOR("Sangbeom Kim <[email protected]>");
	500	MODULE_AUTHOR("Chanwoo Choi <[email protected]>");
	501	MODULE_AUTHOR("Krzysztof Kozlowski <[email protected]>");
	502	MODULE_DESCRIPTION("Interrupt support for the S5M MFD");
	503	MODULE_LICENSE("GPL");