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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7cb6dcff AD |
2 | /* |
3 | * INA3221 Triple Current/Voltage Monitor | |
4 | * | |
ad736c1a | 5 | * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ |
7cb6dcff | 6 | * Andrew F. Davis <[email protected]> |
7cb6dcff AD |
7 | */ |
8 | ||
9 | #include <linux/hwmon.h> | |
10 | #include <linux/hwmon-sysfs.h> | |
11 | #include <linux/i2c.h> | |
12 | #include <linux/module.h> | |
87625b24 | 13 | #include <linux/mutex.h> |
7cb6dcff | 14 | #include <linux/of.h> |
323aeb0e | 15 | #include <linux/pm_runtime.h> |
7cb6dcff | 16 | #include <linux/regmap.h> |
5c090abf | 17 | #include <linux/util_macros.h> |
7cb6dcff AD |
18 | |
19 | #define INA3221_DRIVER_NAME "ina3221" | |
20 | ||
21 | #define INA3221_CONFIG 0x00 | |
22 | #define INA3221_SHUNT1 0x01 | |
23 | #define INA3221_BUS1 0x02 | |
24 | #define INA3221_SHUNT2 0x03 | |
25 | #define INA3221_BUS2 0x04 | |
26 | #define INA3221_SHUNT3 0x05 | |
27 | #define INA3221_BUS3 0x06 | |
28 | #define INA3221_CRIT1 0x07 | |
29 | #define INA3221_WARN1 0x08 | |
30 | #define INA3221_CRIT2 0x09 | |
31 | #define INA3221_WARN2 0x0a | |
32 | #define INA3221_CRIT3 0x0b | |
33 | #define INA3221_WARN3 0x0c | |
2057bdfb NC |
34 | #define INA3221_SHUNT_SUM 0x0d |
35 | #define INA3221_CRIT_SUM 0x0e | |
7cb6dcff AD |
36 | #define INA3221_MASK_ENABLE 0x0f |
37 | ||
59d608e1 NC |
38 | #define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) |
39 | #define INA3221_CONFIG_MODE_POWERDOWN 0 | |
791ebc9d NC |
40 | #define INA3221_CONFIG_MODE_SHUNT BIT(0) |
41 | #define INA3221_CONFIG_MODE_BUS BIT(1) | |
42 | #define INA3221_CONFIG_MODE_CONTINUOUS BIT(2) | |
4c0415a3 NC |
43 | #define INA3221_CONFIG_VSH_CT_SHIFT 3 |
44 | #define INA3221_CONFIG_VSH_CT_MASK GENMASK(5, 3) | |
45 | #define INA3221_CONFIG_VSH_CT(x) (((x) & GENMASK(5, 3)) >> 3) | |
46 | #define INA3221_CONFIG_VBUS_CT_SHIFT 6 | |
47 | #define INA3221_CONFIG_VBUS_CT_MASK GENMASK(8, 6) | |
48 | #define INA3221_CONFIG_VBUS_CT(x) (((x) & GENMASK(8, 6)) >> 6) | |
5c090abf NC |
49 | #define INA3221_CONFIG_AVG_SHIFT 9 |
50 | #define INA3221_CONFIG_AVG_MASK GENMASK(11, 9) | |
51 | #define INA3221_CONFIG_AVG(x) (((x) & GENMASK(11, 9)) >> 9) | |
4c0415a3 | 52 | #define INA3221_CONFIG_CHs_EN_MASK GENMASK(14, 12) |
a9e9dd9c | 53 | #define INA3221_CONFIG_CHx_EN(x) BIT(14 - (x)) |
7cb6dcff | 54 | |
2057bdfb NC |
55 | #define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) |
56 | ||
323aeb0e | 57 | #define INA3221_CONFIG_DEFAULT 0x7127 |
7cb6dcff AD |
58 | #define INA3221_RSHUNT_DEFAULT 10000 |
59 | ||
60 | enum ina3221_fields { | |
61 | /* Configuration */ | |
62 | F_RST, | |
63 | ||
4c0415a3 NC |
64 | /* Status Flags */ |
65 | F_CVRF, | |
66 | ||
2057bdfb | 67 | /* Warning Flags */ |
7cb6dcff | 68 | F_WF3, F_WF2, F_WF1, |
2057bdfb NC |
69 | |
70 | /* Alert Flags: SF is the summation-alert flag */ | |
71 | F_SF, F_CF3, F_CF2, F_CF1, | |
7cb6dcff AD |
72 | |
73 | /* sentinel */ | |
74 | F_MAX_FIELDS | |
75 | }; | |
76 | ||
77 | static const struct reg_field ina3221_reg_fields[] = { | |
78 | [F_RST] = REG_FIELD(INA3221_CONFIG, 15, 15), | |
79 | ||
4c0415a3 | 80 | [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0), |
7cb6dcff AD |
81 | [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3), |
82 | [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4), | |
83 | [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5), | |
2057bdfb | 84 | [F_SF] = REG_FIELD(INA3221_MASK_ENABLE, 6, 6), |
7cb6dcff AD |
85 | [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7), |
86 | [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8), | |
87 | [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9), | |
88 | }; | |
89 | ||
90 | enum ina3221_channels { | |
91 | INA3221_CHANNEL1, | |
92 | INA3221_CHANNEL2, | |
93 | INA3221_CHANNEL3, | |
94 | INA3221_NUM_CHANNELS | |
95 | }; | |
96 | ||
a9e9dd9c NC |
97 | /** |
98 | * struct ina3221_input - channel input source specific information | |
99 | * @label: label of channel input source | |
100 | * @shunt_resistor: shunt resistor value of channel input source | |
101 | * @disconnected: connection status of channel input source | |
102 | */ | |
103 | struct ina3221_input { | |
104 | const char *label; | |
105 | int shunt_resistor; | |
106 | bool disconnected; | |
107 | }; | |
108 | ||
7cb6dcff AD |
109 | /** |
110 | * struct ina3221_data - device specific information | |
323aeb0e | 111 | * @pm_dev: Device pointer for pm runtime |
7cb6dcff AD |
112 | * @regmap: Register map of the device |
113 | * @fields: Register fields of the device | |
a9e9dd9c | 114 | * @inputs: Array of channel input source specific structures |
87625b24 | 115 | * @lock: mutex lock to serialize sysfs attribute accesses |
59d608e1 | 116 | * @reg_config: Register value of INA3221_CONFIG |
2057bdfb | 117 | * @summation_shunt_resistor: equivalent shunt resistor value for summation |
43dece16 | 118 | * @single_shot: running in single-shot operating mode |
7cb6dcff AD |
119 | */ |
120 | struct ina3221_data { | |
323aeb0e | 121 | struct device *pm_dev; |
7cb6dcff AD |
122 | struct regmap *regmap; |
123 | struct regmap_field *fields[F_MAX_FIELDS]; | |
a9e9dd9c | 124 | struct ina3221_input inputs[INA3221_NUM_CHANNELS]; |
87625b24 | 125 | struct mutex lock; |
59d608e1 | 126 | u32 reg_config; |
2057bdfb | 127 | int summation_shunt_resistor; |
43dece16 NC |
128 | |
129 | bool single_shot; | |
7cb6dcff AD |
130 | }; |
131 | ||
a9e9dd9c NC |
132 | static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channel) |
133 | { | |
2057bdfb NC |
134 | /* Summation channel checks shunt resistor values */ |
135 | if (channel > INA3221_CHANNEL3) | |
136 | return ina->summation_shunt_resistor != 0; | |
137 | ||
323aeb0e NC |
138 | return pm_runtime_active(ina->pm_dev) && |
139 | (ina->reg_config & INA3221_CONFIG_CHx_EN(channel)); | |
a9e9dd9c NC |
140 | } |
141 | ||
f9279cda | 142 | /* |
2057bdfb NC |
143 | * Helper function to return the resistor value for current summation. |
144 | * | |
145 | * There is a condition to calculate current summation -- all the shunt | |
146 | * resistor values should be the same, so as to simply fit the formula: | |
147 | * current summation = shunt voltage summation / shunt resistor | |
148 | * | |
149 | * Returns the equivalent shunt resistor value on success or 0 on failure | |
150 | */ | |
151 | static inline int ina3221_summation_shunt_resistor(struct ina3221_data *ina) | |
152 | { | |
153 | struct ina3221_input *input = ina->inputs; | |
154 | int i, shunt_resistor = 0; | |
155 | ||
156 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) { | |
157 | if (input[i].disconnected || !input[i].shunt_resistor) | |
158 | continue; | |
159 | if (!shunt_resistor) { | |
160 | /* Found the reference shunt resistor value */ | |
161 | shunt_resistor = input[i].shunt_resistor; | |
162 | } else { | |
163 | /* No summation if resistor values are different */ | |
164 | if (shunt_resistor != input[i].shunt_resistor) | |
165 | return 0; | |
166 | } | |
167 | } | |
168 | ||
169 | return shunt_resistor; | |
170 | } | |
171 | ||
4c0415a3 NC |
172 | /* Lookup table for Bus and Shunt conversion times in usec */ |
173 | static const u16 ina3221_conv_time[] = { | |
174 | 140, 204, 332, 588, 1100, 2116, 4156, 8244, | |
175 | }; | |
176 | ||
5c090abf NC |
177 | /* Lookup table for number of samples using in averaging mode */ |
178 | static const int ina3221_avg_samples[] = { | |
179 | 1, 4, 16, 64, 128, 256, 512, 1024, | |
180 | }; | |
181 | ||
023912db NC |
182 | /* Converting update_interval in msec to conversion time in usec */ |
183 | static inline u32 ina3221_interval_ms_to_conv_time(u16 config, int interval) | |
184 | { | |
185 | u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); | |
186 | u32 samples_idx = INA3221_CONFIG_AVG(config); | |
187 | u32 samples = ina3221_avg_samples[samples_idx]; | |
188 | ||
189 | /* Bisect the result to Bus and Shunt conversion times */ | |
190 | return DIV_ROUND_CLOSEST(interval * 1000 / 2, channels * samples); | |
191 | } | |
192 | ||
193 | /* Converting CONFIG register value to update_interval in usec */ | |
194 | static inline u32 ina3221_reg_to_interval_us(u16 config) | |
4c0415a3 | 195 | { |
023912db NC |
196 | u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); |
197 | u32 vbus_ct_idx = INA3221_CONFIG_VBUS_CT(config); | |
198 | u32 vsh_ct_idx = INA3221_CONFIG_VSH_CT(config); | |
4c0415a3 NC |
199 | u32 vbus_ct = ina3221_conv_time[vbus_ct_idx]; |
200 | u32 vsh_ct = ina3221_conv_time[vsh_ct_idx]; | |
4c0415a3 NC |
201 | |
202 | /* Calculate total conversion time */ | |
6b6af854 | 203 | return channels * (vbus_ct + vsh_ct); |
023912db NC |
204 | } |
205 | ||
206 | static inline int ina3221_wait_for_data(struct ina3221_data *ina) | |
207 | { | |
208 | u32 wait, cvrf; | |
209 | ||
210 | wait = ina3221_reg_to_interval_us(ina->reg_config); | |
4c0415a3 NC |
211 | |
212 | /* Polling the CVRF bit to make sure read data is ready */ | |
213 | return regmap_field_read_poll_timeout(ina->fields[F_CVRF], | |
2ccb4f16 | 214 | cvrf, cvrf, wait, wait * 2); |
4c0415a3 NC |
215 | } |
216 | ||
d4b0166d NC |
217 | static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, |
218 | int *val) | |
219 | { | |
220 | unsigned int regval; | |
221 | int ret; | |
222 | ||
223 | ret = regmap_read(ina->regmap, reg, ®val); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
2057bdfb NC |
227 | /* |
228 | * Shunt Voltage Sum register has 14-bit value with 1-bit shift | |
229 | * Other Shunt Voltage registers have 12 bits with 3-bit shift | |
230 | */ | |
231 | if (reg == INA3221_SHUNT_SUM) | |
232 | *val = sign_extend32(regval >> 1, 14); | |
233 | else | |
234 | *val = sign_extend32(regval >> 3, 12); | |
d4b0166d NC |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static const u8 ina3221_in_reg[] = { | |
240 | INA3221_BUS1, | |
241 | INA3221_BUS2, | |
242 | INA3221_BUS3, | |
243 | INA3221_SHUNT1, | |
244 | INA3221_SHUNT2, | |
245 | INA3221_SHUNT3, | |
2057bdfb | 246 | INA3221_SHUNT_SUM, |
d4b0166d NC |
247 | }; |
248 | ||
5c090abf NC |
249 | static int ina3221_read_chip(struct device *dev, u32 attr, long *val) |
250 | { | |
251 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
252 | int regval; | |
253 | ||
254 | switch (attr) { | |
255 | case hwmon_chip_samples: | |
256 | regval = INA3221_CONFIG_AVG(ina->reg_config); | |
257 | *val = ina3221_avg_samples[regval]; | |
258 | return 0; | |
023912db NC |
259 | case hwmon_chip_update_interval: |
260 | /* Return in msec */ | |
261 | *val = ina3221_reg_to_interval_us(ina->reg_config); | |
262 | *val = DIV_ROUND_CLOSEST(*val, 1000); | |
263 | return 0; | |
5c090abf NC |
264 | default: |
265 | return -EOPNOTSUPP; | |
266 | } | |
267 | } | |
268 | ||
d4b0166d NC |
269 | static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val) |
270 | { | |
271 | const bool is_shunt = channel > INA3221_CHANNEL3; | |
272 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
273 | u8 reg = ina3221_in_reg[channel]; | |
274 | int regval, ret; | |
275 | ||
2057bdfb NC |
276 | /* |
277 | * Translate shunt channel index to sensor channel index except | |
278 | * the 7th channel (6 since being 0-aligned) is for summation. | |
279 | */ | |
280 | if (channel != 6) | |
281 | channel %= INA3221_NUM_CHANNELS; | |
d4b0166d NC |
282 | |
283 | switch (attr) { | |
284 | case hwmon_in_input: | |
285 | if (!ina3221_is_enabled(ina, channel)) | |
286 | return -ENODATA; | |
287 | ||
43dece16 | 288 | /* Write CONFIG register to trigger a single-shot measurement */ |
6b6af854 | 289 | if (ina->single_shot) { |
43dece16 NC |
290 | regmap_write(ina->regmap, INA3221_CONFIG, |
291 | ina->reg_config); | |
292 | ||
6b6af854 NM |
293 | ret = ina3221_wait_for_data(ina); |
294 | if (ret) | |
295 | return ret; | |
296 | } | |
4c0415a3 | 297 | |
d4b0166d NC |
298 | ret = ina3221_read_value(ina, reg, ®val); |
299 | if (ret) | |
300 | return ret; | |
301 | ||
302 | /* | |
303 | * Scale of shunt voltage (uV): LSB is 40uV | |
304 | * Scale of bus voltage (mV): LSB is 8mV | |
305 | */ | |
306 | *val = regval * (is_shunt ? 40 : 8); | |
307 | return 0; | |
308 | case hwmon_in_enable: | |
309 | *val = ina3221_is_enabled(ina, channel); | |
310 | return 0; | |
311 | default: | |
312 | return -EOPNOTSUPP; | |
313 | } | |
314 | } | |
315 | ||
2057bdfb NC |
316 | static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNELS + 1] = { |
317 | [hwmon_curr_input] = { INA3221_SHUNT1, INA3221_SHUNT2, | |
318 | INA3221_SHUNT3, INA3221_SHUNT_SUM }, | |
319 | [hwmon_curr_max] = { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3, 0 }, | |
320 | [hwmon_curr_crit] = { INA3221_CRIT1, INA3221_CRIT2, | |
321 | INA3221_CRIT3, INA3221_CRIT_SUM }, | |
322 | [hwmon_curr_max_alarm] = { F_WF1, F_WF2, F_WF3, 0 }, | |
323 | [hwmon_curr_crit_alarm] = { F_CF1, F_CF2, F_CF3, F_SF }, | |
d4b0166d NC |
324 | }; |
325 | ||
326 | static int ina3221_read_curr(struct device *dev, u32 attr, | |
327 | int channel, long *val) | |
a9e9dd9c | 328 | { |
a9e9dd9c | 329 | struct ina3221_data *ina = dev_get_drvdata(dev); |
2057bdfb | 330 | struct ina3221_input *input = ina->inputs; |
d4b0166d | 331 | u8 reg = ina3221_curr_reg[attr][channel]; |
2057bdfb NC |
332 | int resistance_uo, voltage_nv; |
333 | int regval, ret; | |
334 | ||
335 | if (channel > INA3221_CHANNEL3) | |
336 | resistance_uo = ina->summation_shunt_resistor; | |
337 | else | |
338 | resistance_uo = input[channel].shunt_resistor; | |
d4b0166d NC |
339 | |
340 | switch (attr) { | |
341 | case hwmon_curr_input: | |
342 | if (!ina3221_is_enabled(ina, channel)) | |
343 | return -ENODATA; | |
4c0415a3 | 344 | |
43dece16 | 345 | /* Write CONFIG register to trigger a single-shot measurement */ |
6b6af854 | 346 | if (ina->single_shot) { |
43dece16 NC |
347 | regmap_write(ina->regmap, INA3221_CONFIG, |
348 | ina->reg_config); | |
349 | ||
6b6af854 NM |
350 | ret = ina3221_wait_for_data(ina); |
351 | if (ret) | |
352 | return ret; | |
353 | } | |
4c0415a3 | 354 | |
df561f66 | 355 | fallthrough; |
d4b0166d NC |
356 | case hwmon_curr_crit: |
357 | case hwmon_curr_max: | |
2057bdfb NC |
358 | if (!resistance_uo) |
359 | return -ENODATA; | |
360 | ||
d4b0166d NC |
361 | ret = ina3221_read_value(ina, reg, ®val); |
362 | if (ret) | |
363 | return ret; | |
a9e9dd9c | 364 | |
d4b0166d NC |
365 | /* Scale of shunt voltage: LSB is 40uV (40000nV) */ |
366 | voltage_nv = regval * 40000; | |
367 | /* Return current in mA */ | |
368 | *val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); | |
369 | return 0; | |
370 | case hwmon_curr_crit_alarm: | |
371 | case hwmon_curr_max_alarm: | |
efb0489e NC |
372 | /* No actual register read if channel is disabled */ |
373 | if (!ina3221_is_enabled(ina, channel)) { | |
374 | /* Return 0 for alert flags */ | |
375 | *val = 0; | |
376 | return 0; | |
377 | } | |
d4b0166d NC |
378 | ret = regmap_field_read(ina->fields[reg], ®val); |
379 | if (ret) | |
380 | return ret; | |
381 | *val = regval; | |
382 | return 0; | |
383 | default: | |
384 | return -EOPNOTSUPP; | |
385 | } | |
a9e9dd9c NC |
386 | } |
387 | ||
5c090abf NC |
388 | static int ina3221_write_chip(struct device *dev, u32 attr, long val) |
389 | { | |
390 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
391 | int ret, idx; | |
521c0b61 | 392 | u32 tmp; |
5c090abf NC |
393 | |
394 | switch (attr) { | |
395 | case hwmon_chip_samples: | |
396 | idx = find_closest(val, ina3221_avg_samples, | |
397 | ARRAY_SIZE(ina3221_avg_samples)); | |
398 | ||
521c0b61 NC |
399 | tmp = (ina->reg_config & ~INA3221_CONFIG_AVG_MASK) | |
400 | (idx << INA3221_CONFIG_AVG_SHIFT); | |
401 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
5c090abf NC |
402 | if (ret) |
403 | return ret; | |
404 | ||
023912db NC |
405 | /* Update reg_config accordingly */ |
406 | ina->reg_config = tmp; | |
407 | return 0; | |
408 | case hwmon_chip_update_interval: | |
409 | tmp = ina3221_interval_ms_to_conv_time(ina->reg_config, val); | |
410 | idx = find_closest(tmp, ina3221_conv_time, | |
411 | ARRAY_SIZE(ina3221_conv_time)); | |
412 | ||
413 | /* Update Bus and Shunt voltage conversion times */ | |
414 | tmp = INA3221_CONFIG_VBUS_CT_MASK | INA3221_CONFIG_VSH_CT_MASK; | |
415 | tmp = (ina->reg_config & ~tmp) | | |
416 | (idx << INA3221_CONFIG_VBUS_CT_SHIFT) | | |
417 | (idx << INA3221_CONFIG_VSH_CT_SHIFT); | |
418 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
419 | if (ret) | |
420 | return ret; | |
421 | ||
5c090abf | 422 | /* Update reg_config accordingly */ |
521c0b61 NC |
423 | ina->reg_config = tmp; |
424 | return 0; | |
5c090abf NC |
425 | default: |
426 | return -EOPNOTSUPP; | |
427 | } | |
428 | } | |
429 | ||
d4b0166d NC |
430 | static int ina3221_write_curr(struct device *dev, u32 attr, |
431 | int channel, long val) | |
a9e9dd9c | 432 | { |
a9e9dd9c | 433 | struct ina3221_data *ina = dev_get_drvdata(dev); |
2057bdfb | 434 | struct ina3221_input *input = ina->inputs; |
d4b0166d | 435 | u8 reg = ina3221_curr_reg[attr][channel]; |
2057bdfb NC |
436 | int resistance_uo, current_ma, voltage_uv; |
437 | int regval; | |
438 | ||
439 | if (channel > INA3221_CHANNEL3) | |
440 | resistance_uo = ina->summation_shunt_resistor; | |
441 | else | |
442 | resistance_uo = input[channel].shunt_resistor; | |
443 | ||
444 | if (!resistance_uo) | |
445 | return -EOPNOTSUPP; | |
d4b0166d NC |
446 | |
447 | /* clamp current */ | |
448 | current_ma = clamp_val(val, | |
449 | INT_MIN / resistance_uo, | |
450 | INT_MAX / resistance_uo); | |
451 | ||
452 | voltage_uv = DIV_ROUND_CLOSEST(current_ma * resistance_uo, 1000); | |
453 | ||
454 | /* clamp voltage */ | |
455 | voltage_uv = clamp_val(voltage_uv, -163800, 163800); | |
456 | ||
2057bdfb NC |
457 | /* |
458 | * Formula to convert voltage_uv to register value: | |
459 | * regval = (voltage_uv / scale) << shift | |
460 | * Note: | |
461 | * The scale is 40uV for all shunt voltage registers | |
462 | * Shunt Voltage Sum register left-shifts 1 bit | |
463 | * All other Shunt Voltage registers shift 3 bits | |
464 | * Results: | |
465 | * SHUNT_SUM: (1 / 40uV) << 1 = 1 / 20uV | |
466 | * SHUNT[1-3]: (1 / 40uV) << 3 = 1 / 5uV | |
467 | */ | |
468 | if (reg == INA3221_SHUNT_SUM) | |
469 | regval = DIV_ROUND_CLOSEST(voltage_uv, 20) & 0xfffe; | |
470 | else | |
471 | regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8; | |
a9e9dd9c | 472 | |
d4b0166d | 473 | return regmap_write(ina->regmap, reg, regval); |
a9e9dd9c NC |
474 | } |
475 | ||
d4b0166d | 476 | static int ina3221_write_enable(struct device *dev, int channel, bool enable) |
a9e9dd9c | 477 | { |
a9e9dd9c | 478 | struct ina3221_data *ina = dev_get_drvdata(dev); |
a9e9dd9c | 479 | u16 config, mask = INA3221_CONFIG_CHx_EN(channel); |
323aeb0e | 480 | u16 config_old = ina->reg_config & mask; |
521c0b61 | 481 | u32 tmp; |
a9e9dd9c NC |
482 | int ret; |
483 | ||
a9e9dd9c NC |
484 | config = enable ? mask : 0; |
485 | ||
323aeb0e NC |
486 | /* Bypass if enable status is not being changed */ |
487 | if (config_old == config) | |
488 | return 0; | |
489 | ||
490 | /* For enabling routine, increase refcount and resume() at first */ | |
491 | if (enable) { | |
bce776f1 | 492 | ret = pm_runtime_resume_and_get(ina->pm_dev); |
323aeb0e NC |
493 | if (ret < 0) { |
494 | dev_err(dev, "Failed to get PM runtime\n"); | |
495 | return ret; | |
496 | } | |
497 | } | |
498 | ||
a9e9dd9c | 499 | /* Enable or disable the channel */ |
521c0b61 NC |
500 | tmp = (ina->reg_config & ~mask) | (config & mask); |
501 | ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); | |
a9e9dd9c | 502 | if (ret) |
323aeb0e | 503 | goto fail; |
a9e9dd9c NC |
504 | |
505 | /* Cache the latest config register value */ | |
521c0b61 | 506 | ina->reg_config = tmp; |
323aeb0e NC |
507 | |
508 | /* For disabling routine, decrease refcount or suspend() at last */ | |
509 | if (!enable) | |
510 | pm_runtime_put_sync(ina->pm_dev); | |
a9e9dd9c | 511 | |
d4b0166d | 512 | return 0; |
323aeb0e NC |
513 | |
514 | fail: | |
515 | if (enable) { | |
516 | dev_err(dev, "Failed to enable channel %d: error %d\n", | |
517 | channel, ret); | |
518 | pm_runtime_put_sync(ina->pm_dev); | |
519 | } | |
520 | ||
521 | return ret; | |
a9e9dd9c NC |
522 | } |
523 | ||
d4b0166d NC |
524 | static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, |
525 | u32 attr, int channel, long *val) | |
7cb6dcff | 526 | { |
87625b24 NC |
527 | struct ina3221_data *ina = dev_get_drvdata(dev); |
528 | int ret; | |
529 | ||
530 | mutex_lock(&ina->lock); | |
531 | ||
d4b0166d | 532 | switch (type) { |
5c090abf NC |
533 | case hwmon_chip: |
534 | ret = ina3221_read_chip(dev, attr, val); | |
535 | break; | |
d4b0166d NC |
536 | case hwmon_in: |
537 | /* 0-align channel ID */ | |
87625b24 NC |
538 | ret = ina3221_read_in(dev, attr, channel - 1, val); |
539 | break; | |
d4b0166d | 540 | case hwmon_curr: |
87625b24 NC |
541 | ret = ina3221_read_curr(dev, attr, channel, val); |
542 | break; | |
d4b0166d | 543 | default: |
87625b24 NC |
544 | ret = -EOPNOTSUPP; |
545 | break; | |
d4b0166d | 546 | } |
87625b24 NC |
547 | |
548 | mutex_unlock(&ina->lock); | |
549 | ||
550 | return ret; | |
7cb6dcff AD |
551 | } |
552 | ||
d4b0166d NC |
553 | static int ina3221_write(struct device *dev, enum hwmon_sensor_types type, |
554 | u32 attr, int channel, long val) | |
7cb6dcff | 555 | { |
87625b24 NC |
556 | struct ina3221_data *ina = dev_get_drvdata(dev); |
557 | int ret; | |
558 | ||
559 | mutex_lock(&ina->lock); | |
560 | ||
d4b0166d | 561 | switch (type) { |
5c090abf NC |
562 | case hwmon_chip: |
563 | ret = ina3221_write_chip(dev, attr, val); | |
564 | break; | |
d4b0166d NC |
565 | case hwmon_in: |
566 | /* 0-align channel ID */ | |
87625b24 NC |
567 | ret = ina3221_write_enable(dev, channel - 1, val); |
568 | break; | |
d4b0166d | 569 | case hwmon_curr: |
87625b24 NC |
570 | ret = ina3221_write_curr(dev, attr, channel, val); |
571 | break; | |
d4b0166d | 572 | default: |
87625b24 NC |
573 | ret = -EOPNOTSUPP; |
574 | break; | |
d4b0166d | 575 | } |
87625b24 NC |
576 | |
577 | mutex_unlock(&ina->lock); | |
578 | ||
579 | return ret; | |
7cb6dcff AD |
580 | } |
581 | ||
d4b0166d NC |
582 | static int ina3221_read_string(struct device *dev, enum hwmon_sensor_types type, |
583 | u32 attr, int channel, const char **str) | |
7cb6dcff | 584 | { |
7cb6dcff | 585 | struct ina3221_data *ina = dev_get_drvdata(dev); |
d4b0166d | 586 | int index = channel - 1; |
7cb6dcff | 587 | |
2057bdfb NC |
588 | if (channel == 7) |
589 | *str = "sum of shunt voltages"; | |
590 | else | |
591 | *str = ina->inputs[index].label; | |
a9e9dd9c | 592 | |
d4b0166d | 593 | return 0; |
7cb6dcff AD |
594 | } |
595 | ||
d4b0166d NC |
596 | static umode_t ina3221_is_visible(const void *drvdata, |
597 | enum hwmon_sensor_types type, | |
598 | u32 attr, int channel) | |
7cb6dcff | 599 | { |
d4b0166d NC |
600 | const struct ina3221_data *ina = drvdata; |
601 | const struct ina3221_input *input = NULL; | |
602 | ||
603 | switch (type) { | |
5c090abf NC |
604 | case hwmon_chip: |
605 | switch (attr) { | |
606 | case hwmon_chip_samples: | |
023912db | 607 | case hwmon_chip_update_interval: |
5c090abf NC |
608 | return 0644; |
609 | default: | |
610 | return 0; | |
611 | } | |
d4b0166d NC |
612 | case hwmon_in: |
613 | /* Ignore in0_ */ | |
614 | if (channel == 0) | |
615 | return 0; | |
616 | ||
617 | switch (attr) { | |
618 | case hwmon_in_label: | |
619 | if (channel - 1 <= INA3221_CHANNEL3) | |
620 | input = &ina->inputs[channel - 1]; | |
2057bdfb NC |
621 | else if (channel == 7) |
622 | return 0444; | |
d4b0166d NC |
623 | /* Hide label node if label is not provided */ |
624 | return (input && input->label) ? 0444 : 0; | |
625 | case hwmon_in_input: | |
626 | return 0444; | |
627 | case hwmon_in_enable: | |
628 | return 0644; | |
629 | default: | |
630 | return 0; | |
631 | } | |
632 | case hwmon_curr: | |
633 | switch (attr) { | |
634 | case hwmon_curr_input: | |
635 | case hwmon_curr_crit_alarm: | |
636 | case hwmon_curr_max_alarm: | |
637 | return 0444; | |
638 | case hwmon_curr_crit: | |
639 | case hwmon_curr_max: | |
640 | return 0644; | |
641 | default: | |
642 | return 0; | |
643 | } | |
644 | default: | |
645 | return 0; | |
646 | } | |
7cb6dcff AD |
647 | } |
648 | ||
d4b0166d NC |
649 | #define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ |
650 | HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ | |
651 | HWMON_C_MAX | HWMON_C_MAX_ALARM) | |
7cb6dcff | 652 | |
d4b0166d | 653 | static const struct hwmon_channel_info *ina3221_info[] = { |
5c090abf | 654 | HWMON_CHANNEL_INFO(chip, |
023912db NC |
655 | HWMON_C_SAMPLES, |
656 | HWMON_C_UPDATE_INTERVAL), | |
6f307b7c GR |
657 | HWMON_CHANNEL_INFO(in, |
658 | /* 0: dummy, skipped in is_visible */ | |
659 | HWMON_I_INPUT, | |
660 | /* 1-3: input voltage Channels */ | |
661 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
662 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
663 | HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, | |
664 | /* 4-6: shunt voltage Channels */ | |
665 | HWMON_I_INPUT, | |
666 | HWMON_I_INPUT, | |
2057bdfb NC |
667 | HWMON_I_INPUT, |
668 | /* 7: summation of shunt voltage channels */ | |
669 | HWMON_I_INPUT | HWMON_I_LABEL), | |
6f307b7c | 670 | HWMON_CHANNEL_INFO(curr, |
2057bdfb NC |
671 | /* 1-3: current channels*/ |
672 | INA3221_HWMON_CURR_CONFIG, | |
6f307b7c GR |
673 | INA3221_HWMON_CURR_CONFIG, |
674 | INA3221_HWMON_CURR_CONFIG, | |
2057bdfb NC |
675 | /* 4: summation of current channels */ |
676 | HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM), | |
d4b0166d NC |
677 | NULL |
678 | }; | |
7cb6dcff | 679 | |
d4b0166d NC |
680 | static const struct hwmon_ops ina3221_hwmon_ops = { |
681 | .is_visible = ina3221_is_visible, | |
682 | .read_string = ina3221_read_string, | |
683 | .read = ina3221_read, | |
684 | .write = ina3221_write, | |
685 | }; | |
7cb6dcff | 686 | |
d4b0166d NC |
687 | static const struct hwmon_chip_info ina3221_chip_info = { |
688 | .ops = &ina3221_hwmon_ops, | |
689 | .info = ina3221_info, | |
690 | }; | |
7cb6dcff | 691 | |
d4b0166d | 692 | /* Extra attribute groups */ |
a4ec92ed | 693 | static ssize_t ina3221_shunt_show(struct device *dev, |
7cb6dcff AD |
694 | struct device_attribute *attr, char *buf) |
695 | { | |
696 | struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); | |
697 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
698 | unsigned int channel = sd_attr->index; | |
a9e9dd9c | 699 | struct ina3221_input *input = &ina->inputs[channel]; |
7cb6dcff | 700 | |
1f4d4af4 | 701 | return sysfs_emit(buf, "%d\n", input->shunt_resistor); |
7cb6dcff AD |
702 | } |
703 | ||
a4ec92ed GR |
704 | static ssize_t ina3221_shunt_store(struct device *dev, |
705 | struct device_attribute *attr, | |
706 | const char *buf, size_t count) | |
7cb6dcff AD |
707 | { |
708 | struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); | |
709 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
710 | unsigned int channel = sd_attr->index; | |
a9e9dd9c | 711 | struct ina3221_input *input = &ina->inputs[channel]; |
9ad0df1a | 712 | int val; |
7cb6dcff AD |
713 | int ret; |
714 | ||
9ad0df1a | 715 | ret = kstrtoint(buf, 0, &val); |
7cb6dcff AD |
716 | if (ret) |
717 | return ret; | |
718 | ||
9ad0df1a | 719 | val = clamp_val(val, 1, INT_MAX); |
7cb6dcff | 720 | |
a9e9dd9c | 721 | input->shunt_resistor = val; |
7cb6dcff | 722 | |
2057bdfb NC |
723 | /* Update summation_shunt_resistor for summation channel */ |
724 | ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina); | |
725 | ||
7cb6dcff AD |
726 | return count; |
727 | } | |
728 | ||
7cb6dcff | 729 | /* shunt resistance */ |
a4ec92ed GR |
730 | static SENSOR_DEVICE_ATTR_RW(shunt1_resistor, ina3221_shunt, INA3221_CHANNEL1); |
731 | static SENSOR_DEVICE_ATTR_RW(shunt2_resistor, ina3221_shunt, INA3221_CHANNEL2); | |
732 | static SENSOR_DEVICE_ATTR_RW(shunt3_resistor, ina3221_shunt, INA3221_CHANNEL3); | |
7cb6dcff | 733 | |
7cb6dcff | 734 | static struct attribute *ina3221_attrs[] = { |
7cb6dcff | 735 | &sensor_dev_attr_shunt1_resistor.dev_attr.attr, |
7cb6dcff | 736 | &sensor_dev_attr_shunt2_resistor.dev_attr.attr, |
7cb6dcff | 737 | &sensor_dev_attr_shunt3_resistor.dev_attr.attr, |
7cb6dcff AD |
738 | NULL, |
739 | }; | |
d4b0166d | 740 | ATTRIBUTE_GROUPS(ina3221); |
7cb6dcff AD |
741 | |
742 | static const struct regmap_range ina3221_yes_ranges[] = { | |
c20217b3 | 743 | regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), |
2057bdfb | 744 | regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM), |
7cb6dcff AD |
745 | regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), |
746 | }; | |
747 | ||
748 | static const struct regmap_access_table ina3221_volatile_table = { | |
749 | .yes_ranges = ina3221_yes_ranges, | |
750 | .n_yes_ranges = ARRAY_SIZE(ina3221_yes_ranges), | |
751 | }; | |
752 | ||
753 | static const struct regmap_config ina3221_regmap_config = { | |
754 | .reg_bits = 8, | |
755 | .val_bits = 16, | |
756 | ||
757 | .cache_type = REGCACHE_RBTREE, | |
758 | .volatile_table = &ina3221_volatile_table, | |
759 | }; | |
760 | ||
a9e9dd9c NC |
761 | static int ina3221_probe_child_from_dt(struct device *dev, |
762 | struct device_node *child, | |
763 | struct ina3221_data *ina) | |
764 | { | |
765 | struct ina3221_input *input; | |
766 | u32 val; | |
767 | int ret; | |
768 | ||
769 | ret = of_property_read_u32(child, "reg", &val); | |
770 | if (ret) { | |
1b1f4efa | 771 | dev_err(dev, "missing reg property of %pOFn\n", child); |
a9e9dd9c NC |
772 | return ret; |
773 | } else if (val > INA3221_CHANNEL3) { | |
1b1f4efa | 774 | dev_err(dev, "invalid reg %d of %pOFn\n", val, child); |
a9e9dd9c NC |
775 | return ret; |
776 | } | |
777 | ||
778 | input = &ina->inputs[val]; | |
779 | ||
780 | /* Log the disconnected channel input */ | |
781 | if (!of_device_is_available(child)) { | |
782 | input->disconnected = true; | |
783 | return 0; | |
784 | } | |
785 | ||
786 | /* Save the connected input label if available */ | |
787 | of_property_read_string(child, "label", &input->label); | |
788 | ||
789 | /* Overwrite default shunt resistor value optionally */ | |
a6e43263 NC |
790 | if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) { |
791 | if (val < 1 || val > INT_MAX) { | |
1b1f4efa RH |
792 | dev_err(dev, "invalid shunt resistor value %u of %pOFn\n", |
793 | val, child); | |
a6e43263 NC |
794 | return -EINVAL; |
795 | } | |
a9e9dd9c | 796 | input->shunt_resistor = val; |
a6e43263 | 797 | } |
a9e9dd9c NC |
798 | |
799 | return 0; | |
800 | } | |
801 | ||
802 | static int ina3221_probe_from_dt(struct device *dev, struct ina3221_data *ina) | |
803 | { | |
804 | const struct device_node *np = dev->of_node; | |
805 | struct device_node *child; | |
806 | int ret; | |
807 | ||
808 | /* Compatible with non-DT platforms */ | |
809 | if (!np) | |
810 | return 0; | |
811 | ||
43dece16 NC |
812 | ina->single_shot = of_property_read_bool(np, "ti,single-shot"); |
813 | ||
a9e9dd9c NC |
814 | for_each_child_of_node(np, child) { |
815 | ret = ina3221_probe_child_from_dt(dev, child, ina); | |
9f754657 ND |
816 | if (ret) { |
817 | of_node_put(child); | |
a9e9dd9c | 818 | return ret; |
9f754657 | 819 | } |
a9e9dd9c NC |
820 | } |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
67487038 | 825 | static int ina3221_probe(struct i2c_client *client) |
7cb6dcff AD |
826 | { |
827 | struct device *dev = &client->dev; | |
828 | struct ina3221_data *ina; | |
829 | struct device *hwmon_dev; | |
830 | int i, ret; | |
831 | ||
832 | ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); | |
833 | if (!ina) | |
834 | return -ENOMEM; | |
835 | ||
836 | ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config); | |
837 | if (IS_ERR(ina->regmap)) { | |
838 | dev_err(dev, "Unable to allocate register map\n"); | |
839 | return PTR_ERR(ina->regmap); | |
840 | } | |
841 | ||
842 | for (i = 0; i < F_MAX_FIELDS; i++) { | |
843 | ina->fields[i] = devm_regmap_field_alloc(dev, | |
844 | ina->regmap, | |
845 | ina3221_reg_fields[i]); | |
846 | if (IS_ERR(ina->fields[i])) { | |
847 | dev_err(dev, "Unable to allocate regmap fields\n"); | |
848 | return PTR_ERR(ina->fields[i]); | |
849 | } | |
850 | } | |
851 | ||
852 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
a9e9dd9c NC |
853 | ina->inputs[i].shunt_resistor = INA3221_RSHUNT_DEFAULT; |
854 | ||
855 | ret = ina3221_probe_from_dt(dev, ina); | |
856 | if (ret) { | |
857 | dev_err(dev, "Unable to probe from device tree\n"); | |
858 | return ret; | |
859 | } | |
7cb6dcff | 860 | |
323aeb0e NC |
861 | /* The driver will be reset, so use reset value */ |
862 | ina->reg_config = INA3221_CONFIG_DEFAULT; | |
a9e9dd9c | 863 | |
43dece16 NC |
864 | /* Clear continuous bit to use single-shot mode */ |
865 | if (ina->single_shot) | |
866 | ina->reg_config &= ~INA3221_CONFIG_MODE_CONTINUOUS; | |
867 | ||
a9e9dd9c NC |
868 | /* Disable channels if their inputs are disconnected */ |
869 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) { | |
870 | if (ina->inputs[i].disconnected) | |
871 | ina->reg_config &= ~INA3221_CONFIG_CHx_EN(i); | |
872 | } | |
a9e9dd9c | 873 | |
2057bdfb NC |
874 | /* Initialize summation_shunt_resistor for summation channel control */ |
875 | ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina); | |
876 | ||
323aeb0e | 877 | ina->pm_dev = dev; |
87625b24 | 878 | mutex_init(&ina->lock); |
59d608e1 NC |
879 | dev_set_drvdata(dev, ina); |
880 | ||
323aeb0e NC |
881 | /* Enable PM runtime -- status is suspended by default */ |
882 | pm_runtime_enable(ina->pm_dev); | |
883 | ||
884 | /* Initialize (resume) the device */ | |
885 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) { | |
886 | if (ina->inputs[i].disconnected) | |
887 | continue; | |
888 | /* Match the refcount with number of enabled channels */ | |
889 | ret = pm_runtime_get_sync(ina->pm_dev); | |
890 | if (ret < 0) | |
891 | goto fail; | |
892 | } | |
893 | ||
d4b0166d NC |
894 | hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, ina, |
895 | &ina3221_chip_info, | |
896 | ina3221_groups); | |
7cb6dcff AD |
897 | if (IS_ERR(hwmon_dev)) { |
898 | dev_err(dev, "Unable to register hwmon device\n"); | |
323aeb0e NC |
899 | ret = PTR_ERR(hwmon_dev); |
900 | goto fail; | |
7cb6dcff AD |
901 | } |
902 | ||
903 | return 0; | |
323aeb0e NC |
904 | |
905 | fail: | |
906 | pm_runtime_disable(ina->pm_dev); | |
907 | pm_runtime_set_suspended(ina->pm_dev); | |
908 | /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ | |
909 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
910 | pm_runtime_put_noidle(ina->pm_dev); | |
911 | mutex_destroy(&ina->lock); | |
912 | ||
913 | return ret; | |
7cb6dcff AD |
914 | } |
915 | ||
ed5c2f5f | 916 | static void ina3221_remove(struct i2c_client *client) |
87625b24 NC |
917 | { |
918 | struct ina3221_data *ina = dev_get_drvdata(&client->dev); | |
323aeb0e NC |
919 | int i; |
920 | ||
921 | pm_runtime_disable(ina->pm_dev); | |
922 | pm_runtime_set_suspended(ina->pm_dev); | |
923 | ||
924 | /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ | |
925 | for (i = 0; i < INA3221_NUM_CHANNELS; i++) | |
926 | pm_runtime_put_noidle(ina->pm_dev); | |
87625b24 NC |
927 | |
928 | mutex_destroy(&ina->lock); | |
87625b24 NC |
929 | } |
930 | ||
ead21c77 | 931 | static int __maybe_unused ina3221_suspend(struct device *dev) |
59d608e1 NC |
932 | { |
933 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
934 | int ret; | |
935 | ||
936 | /* Save config register value and enable cache-only */ | |
937 | ret = regmap_read(ina->regmap, INA3221_CONFIG, &ina->reg_config); | |
938 | if (ret) | |
939 | return ret; | |
940 | ||
941 | /* Set to power-down mode for power saving */ | |
942 | ret = regmap_update_bits(ina->regmap, INA3221_CONFIG, | |
943 | INA3221_CONFIG_MODE_MASK, | |
944 | INA3221_CONFIG_MODE_POWERDOWN); | |
945 | if (ret) | |
946 | return ret; | |
947 | ||
948 | regcache_cache_only(ina->regmap, true); | |
949 | regcache_mark_dirty(ina->regmap); | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
ead21c77 | 954 | static int __maybe_unused ina3221_resume(struct device *dev) |
59d608e1 NC |
955 | { |
956 | struct ina3221_data *ina = dev_get_drvdata(dev); | |
957 | int ret; | |
958 | ||
959 | regcache_cache_only(ina->regmap, false); | |
960 | ||
961 | /* Software reset the chip */ | |
962 | ret = regmap_field_write(ina->fields[F_RST], true); | |
963 | if (ret) { | |
964 | dev_err(dev, "Unable to reset device\n"); | |
965 | return ret; | |
966 | } | |
967 | ||
968 | /* Restore cached register values to hardware */ | |
969 | ret = regcache_sync(ina->regmap); | |
970 | if (ret) | |
971 | return ret; | |
972 | ||
973 | /* Restore config register value to hardware */ | |
974 | ret = regmap_write(ina->regmap, INA3221_CONFIG, ina->reg_config); | |
975 | if (ret) | |
976 | return ret; | |
977 | ||
2057bdfb NC |
978 | /* Initialize summation channel control */ |
979 | if (ina->summation_shunt_resistor) { | |
980 | /* | |
981 | * Take all three channels into summation by default | |
982 | * Shunt measurements of disconnected channels should | |
983 | * be 0, so it does not matter for summation. | |
984 | */ | |
985 | ret = regmap_update_bits(ina->regmap, INA3221_MASK_ENABLE, | |
986 | INA3221_MASK_ENABLE_SCC_MASK, | |
987 | INA3221_MASK_ENABLE_SCC_MASK); | |
988 | if (ret) { | |
989 | dev_err(dev, "Unable to control summation channel\n"); | |
990 | return ret; | |
991 | } | |
992 | } | |
993 | ||
59d608e1 NC |
994 | return 0; |
995 | } | |
59d608e1 NC |
996 | |
997 | static const struct dev_pm_ops ina3221_pm = { | |
323aeb0e NC |
998 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
999 | pm_runtime_force_resume) | |
1000 | SET_RUNTIME_PM_OPS(ina3221_suspend, ina3221_resume, NULL) | |
59d608e1 NC |
1001 | }; |
1002 | ||
7cb6dcff AD |
1003 | static const struct of_device_id ina3221_of_match_table[] = { |
1004 | { .compatible = "ti,ina3221", }, | |
1005 | { /* sentinel */ } | |
1006 | }; | |
1007 | MODULE_DEVICE_TABLE(of, ina3221_of_match_table); | |
1008 | ||
1009 | static const struct i2c_device_id ina3221_ids[] = { | |
1010 | { "ina3221", 0 }, | |
1011 | { /* sentinel */ } | |
1012 | }; | |
1013 | MODULE_DEVICE_TABLE(i2c, ina3221_ids); | |
1014 | ||
1015 | static struct i2c_driver ina3221_i2c_driver = { | |
67487038 | 1016 | .probe_new = ina3221_probe, |
87625b24 | 1017 | .remove = ina3221_remove, |
7cb6dcff AD |
1018 | .driver = { |
1019 | .name = INA3221_DRIVER_NAME, | |
1020 | .of_match_table = ina3221_of_match_table, | |
59d608e1 | 1021 | .pm = &ina3221_pm, |
7cb6dcff AD |
1022 | }, |
1023 | .id_table = ina3221_ids, | |
1024 | }; | |
1025 | module_i2c_driver(ina3221_i2c_driver); | |
1026 | ||
1027 | MODULE_AUTHOR("Andrew F. Davis <[email protected]>"); | |
1028 | MODULE_DESCRIPTION("Texas Instruments INA3221 HWMon Driver"); | |
1029 | MODULE_LICENSE("GPL v2"); |