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[linux.git] / drivers / net / smc911x.h
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0a0c72c9
DM		 1/*------------------------------------------------------------------------
2 . smc911x.h - macros for SMSC's LAN911{5,6,7,8} single-chip Ethernet device.
3 .
4 . Copyright (C) 2005 Sensoria Corp.
5 . Derived from the unified SMC91x driver by Nicolas Pitre
6 .
7 . This program is free software; you can redistribute it and/or modify
8 . it under the terms of the GNU General Public License as published by
9 . the Free Software Foundation; either version 2 of the License, or
10 . (at your option) any later version.
11 .
12 . This program is distributed in the hope that it will be useful,
13 . but WITHOUT ANY WARRANTY; without even the implied warranty of
14 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 . GNU General Public License for more details.
16 .
17 . You should have received a copy of the GNU General Public License
18 . along with this program; if not, write to the Free Software
19 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 .
21 . Information contained in this file was obtained from the LAN9118
22 . manual from SMC. To get a copy, if you really want one, you can find
23 . information under www.smsc.com.
24 .
25 . Authors
26 . Dustin McIntire <[email protected]>
27 .
28 ---------------------------------------------------------------------------*/
29#ifndef _SMC911X_H_
30#define _SMC911X_H_
31
12c03f59 32#include <linux/smc911x.h>
0a0c72c9
DM		 33/*
34 * Use the DMA feature on PXA chips
35 */
36#ifdef CONFIG_ARCH_PXA
37 #define SMC_USE_PXA_DMA 1
38 #define SMC_USE_16BIT 0
39 #define SMC_USE_32BIT 1
726d722e 40 #define SMC_IRQ_SENSE IRQF_TRIGGER_FALLING
d0c4581b 41#elif defined(CONFIG_SH_MAGIC_PANEL_R2)
726d722e
MB		 42 #define SMC_USE_16BIT 0
43 #define SMC_USE_32BIT 1
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
12c03f59
MD		 45#else
46/*
47 * Default configuration
48 */
49
50#define SMC_DYNAMIC_BUS_CONFIG
0a0c72c9
DM		 51#endif
52
d766a4ed
DB		 53#ifdef SMC_USE_PXA_DMA
54#define SMC_USE_DMA
55#endif
56
699559f8
MD		 57/* store this information for the driver.. */
58struct smc911x_local {
59 /*
60 * If I have to wait until the DMA is finished and ready to reload a
61 * packet, I will store the skbuff here. Then, the DMA will send it
62 * out and free it.
63 */
64 struct sk_buff *pending_tx_skb;
65
66 /* version/revision of the SMC911x chip */
67 u16 version;
68 u16 revision;
69
70 /* FIFO sizes */
71 int tx_fifo_kb;
72 int tx_fifo_size;
73 int rx_fifo_size;
74 int afc_cfg;
75
76 /* Contains the current active receive/phy mode */
77 int ctl_rfduplx;
78 int ctl_rspeed;
79
80 u32 msg_enable;
81 u32 phy_type;
82 struct mii_if_info mii;
83
84 /* work queue */
85 struct work_struct phy_configure;
699559f8
MD		 86
87 int tx_throttle;
88 spinlock_t lock;
89
90 struct net_device *netdev;
91
92#ifdef SMC_USE_DMA
93 /* DMA needs the physical address of the chip */
94 u_long physaddr;
95 int rxdma;
96 int txdma;
97 int rxdma_active;
98 int txdma_active;
99 struct sk_buff *current_rx_skb;
100 struct sk_buff *current_tx_skb;
101 struct device *dev;
102#endif
103 void __iomem *base;
12c03f59
MD		 104#ifdef SMC_DYNAMIC_BUS_CONFIG
105 struct smc911x_platdata cfg;
106#endif
699559f8 107};
0a0c72c9
DM		 108
109/*
110 * Define the bus width specific IO macros
111 */
112
12c03f59
MD		 113#ifdef SMC_DYNAMIC_BUS_CONFIG
114static inline unsigned int SMC_inl(struct smc911x_local *lp, int reg)
115{
116 void __iomem *ioaddr = lp->base + reg;
117
118 if (lp->cfg.flags & SMC911X_USE_32BIT)
119 return readl(ioaddr);
120
121 if (lp->cfg.flags & SMC911X_USE_16BIT)
122 return readw(ioaddr) | (readw(ioaddr + 2) << 16);
123
124 BUG();
125}
126
127static inline void SMC_outl(unsigned int value, struct smc911x_local *lp,
128 int reg)
129{
130 void __iomem *ioaddr = lp->base + reg;
131
132 if (lp->cfg.flags & SMC911X_USE_32BIT) {
133 writel(value, ioaddr);
134 return;
135 }
136
137 if (lp->cfg.flags & SMC911X_USE_16BIT) {
138 writew(value & 0xffff, ioaddr);
139 writew(value >> 16, ioaddr + 2);
140 return;
141 }
142
143 BUG();
144}
145
146static inline void SMC_insl(struct smc911x_local *lp, int reg,
147 void *addr, unsigned int count)
148{
149 void __iomem *ioaddr = lp->base + reg;
150
151 if (lp->cfg.flags & SMC911X_USE_32BIT) {
152 readsl(ioaddr, addr, count);
153 return;
154 }
155
156 if (lp->cfg.flags & SMC911X_USE_16BIT) {
157 readsw(ioaddr, addr, count * 2);
158 return;
159 }
160
161 BUG();
162}
163
164static inline void SMC_outsl(struct smc911x_local *lp, int reg,
165 void *addr, unsigned int count)
166{
167 void __iomem *ioaddr = lp->base + reg;
168
169 if (lp->cfg.flags & SMC911X_USE_32BIT) {
170 writesl(ioaddr, addr, count);
171 return;
172 }
173
174 if (lp->cfg.flags & SMC911X_USE_16BIT) {
175 writesw(ioaddr, addr, count * 2);
176 return;
177 }
178
179 BUG();
180}
181#else
0a0c72c9 182#if SMC_USE_16BIT
699559f8
MD		 183#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
184#define SMC_outl(v, lp, r) \
0a0c72c9 185 do{ \
699559f8
MD		 186 writew(v & 0xFFFF, (lp)->base + (r)); \
187 writew(v >> 16, (lp)->base + (r) + 2); \
0a0c72c9 188 } while (0)
699559f8
MD		 189#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
190#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
0a0c72c9
DM		 191
192#elif SMC_USE_32BIT
699559f8
MD		 193#define SMC_inl(lp, r) readl((lp)->base + (r))
194#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
195#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
196#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
0a0c72c9
DM		 197
198#endif /* SMC_USE_16BIT */
12c03f59
MD		 199#endif /* SMC_DYNAMIC_BUS_CONFIG */
200
0a0c72c9 201
b173079f 202#ifdef SMC_USE_PXA_DMA
d5498bef
JG		 203/*
204 * Define the request and free functions
0a0c72c9
DM		 205 * These are unfortunately architecture specific as no generic allocation
206 * mechanism exits
207 */
208#define SMC_DMA_REQUEST(dev, handler) \
d5498bef 209 pxa_request_dma(dev->name, DMA_PRIO_LOW, handler, dev)
0a0c72c9
DM		 210
211#define SMC_DMA_FREE(dev, dma) \
212 pxa_free_dma(dma)
213
214#define SMC_DMA_ACK_IRQ(dev, dma) \
215{ \
216 if (DCSR(dma) & DCSR_BUSERR) { \
217 printk("%s: DMA %d bus error!\n", dev->name, dma); \
218 } \
219 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \
220}
221
222/*
223 * Use a DMA for RX and TX packets.
224 */
225#include <linux/dma-mapping.h>
226#include <asm/dma.h>
a09e64fb 227#include <mach/pxa-regs.h>
0a0c72c9
DM		 228
229static dma_addr_t rx_dmabuf, tx_dmabuf;
230static int rx_dmalen, tx_dmalen;
d5498bef 231
0a0c72c9
DM		 232#ifdef SMC_insl
233#undef SMC_insl
699559f8
MD		 234#define SMC_insl(lp, r, p, l) \
235 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
0a0c72c9
DM		 236
237static inline void
699559f8 238smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
0a0c72c9
DM		 239 int reg, int dma, u_char *buf, int len)
240{
241 /* 64 bit alignment is required for memory to memory DMA */
242 if ((long)buf & 4) {
699559f8 243 *((u32 *)buf) = SMC_inl(lp, reg);
0a0c72c9
DM		 244 buf += 4;
245 len--;
246 }
247
248 len *= 4;
699559f8 249 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
0a0c72c9
DM		 250 rx_dmalen = len;
251 DCSR(dma) = DCSR_NODESC;
252 DTADR(dma) = rx_dmabuf;
253 DSADR(dma) = physaddr + reg;
254 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
255 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & rx_dmalen));
256 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
257}
258#endif
259
0a0c72c9
DM		 260#ifdef SMC_outsl
261#undef SMC_outsl
699559f8
MD		 262#define SMC_outsl(lp, r, p, l) \
263 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
0a0c72c9
DM		 264
265static inline void
699559f8 266smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
0a0c72c9
DM		 267 int reg, int dma, u_char *buf, int len)
268{
269 /* 64 bit alignment is required for memory to memory DMA */
270 if ((long)buf & 4) {
699559f8 271 SMC_outl(*((u32 *)buf), lp, reg);
0a0c72c9
DM		 272 buf += 4;
273 len--;
274 }
275
276 len *= 4;
699559f8 277 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
0a0c72c9
DM		 278 tx_dmalen = len;
279 DCSR(dma) = DCSR_NODESC;
280 DSADR(dma) = tx_dmabuf;
281 DTADR(dma) = physaddr + reg;
282 DCMD(dma) = (DCMD_INCSRCADDR | DCMD_BURST32 |
283 DCMD_WIDTH4 | DCMD_ENDIRQEN | (DCMD_LENGTH & tx_dmalen));
284 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
285}
286#endif
0a0c72c9
DM		 287#endif /* SMC_USE_PXA_DMA */
288
289
290/* Chip Parameters and Register Definitions */
291
292#define SMC911X_TX_FIFO_LOW_THRESHOLD (1536*2)
293
294#define SMC911X_IO_EXTENT 0x100
295
296#define SMC911X_EEPROM_LEN 7
297
298/* Below are the register offsets and bit definitions
299 * of the Lan911x memory space
300 */
301#define RX_DATA_FIFO (0x00)
302
303#define TX_DATA_FIFO (0x20)
304#define TX_CMD_A_INT_ON_COMP_ (0x80000000)
305#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000)
306#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000)
307#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000)
308#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000)
309#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000)
310#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000)
311#define TX_CMD_A_INT_LAST_SEG_ (0x00001000)
312#define TX_CMD_A_BUF_SIZE_ (0x000007FF)
313#define TX_CMD_B_PKT_TAG_ (0xFFFF0000)
314#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000)
315#define TX_CMD_B_DISABLE_PADDING_ (0x00001000)
316#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FF)
317
318#define RX_STATUS_FIFO (0x40)
319#define RX_STS_PKT_LEN_ (0x3FFF0000)
320#define RX_STS_ES_ (0x00008000)
321#define RX_STS_BCST_ (0x00002000)
322#define RX_STS_LEN_ERR_ (0x00001000)
323#define RX_STS_RUNT_ERR_ (0x00000800)
324#define RX_STS_MCAST_ (0x00000400)
325#define RX_STS_TOO_LONG_ (0x00000080)
326#define RX_STS_COLL_ (0x00000040)
327#define RX_STS_ETH_TYPE_ (0x00000020)
328#define RX_STS_WDOG_TMT_ (0x00000010)
329#define RX_STS_MII_ERR_ (0x00000008)
330#define RX_STS_DRIBBLING_ (0x00000004)
331#define RX_STS_CRC_ERR_ (0x00000002)
332#define RX_STATUS_FIFO_PEEK (0x44)
333#define TX_STATUS_FIFO (0x48)
334#define TX_STS_TAG_ (0xFFFF0000)
335#define TX_STS_ES_ (0x00008000)
336#define TX_STS_LOC_ (0x00000800)
337#define TX_STS_NO_CARR_ (0x00000400)
338#define TX_STS_LATE_COLL_ (0x00000200)
339#define TX_STS_MANY_COLL_ (0x00000100)
340#define TX_STS_COLL_CNT_ (0x00000078)
341#define TX_STS_MANY_DEFER_ (0x00000004)
342#define TX_STS_UNDERRUN_ (0x00000002)
343#define TX_STS_DEFERRED_ (0x00000001)
344#define TX_STATUS_FIFO_PEEK (0x4C)
345#define ID_REV (0x50)
346#define ID_REV_CHIP_ID_ (0xFFFF0000) /* RO */
347#define ID_REV_REV_ID_ (0x0000FFFF) /* RO */
348
349#define INT_CFG (0x54)
350#define INT_CFG_INT_DEAS_ (0xFF000000) /* R/W */
351#define INT_CFG_INT_DEAS_CLR_ (0x00004000)
352#define INT_CFG_INT_DEAS_STS_ (0x00002000)
353#define INT_CFG_IRQ_INT_ (0x00001000) /* RO */
354#define INT_CFG_IRQ_EN_ (0x00000100) /* R/W */
355#define INT_CFG_IRQ_POL_ (0x00000010) /* R/W Not Affected by SW Reset */
356#define INT_CFG_IRQ_TYPE_ (0x00000001) /* R/W Not Affected by SW Reset */
357
358#define INT_STS (0x58)
359#define INT_STS_SW_INT_ (0x80000000) /* R/WC */
360#define INT_STS_TXSTOP_INT_ (0x02000000) /* R/WC */
361#define INT_STS_RXSTOP_INT_ (0x01000000) /* R/WC */
362#define INT_STS_RXDFH_INT_ (0x00800000) /* R/WC */
363#define INT_STS_RXDF_INT_ (0x00400000) /* R/WC */
364#define INT_STS_TX_IOC_ (0x00200000) /* R/WC */
365#define INT_STS_RXD_INT_ (0x00100000) /* R/WC */
366#define INT_STS_GPT_INT_ (0x00080000) /* R/WC */
367#define INT_STS_PHY_INT_ (0x00040000) /* RO */
368#define INT_STS_PME_INT_ (0x00020000) /* R/WC */
369#define INT_STS_TXSO_ (0x00010000) /* R/WC */
370#define INT_STS_RWT_ (0x00008000) /* R/WC */
371#define INT_STS_RXE_ (0x00004000) /* R/WC */
372#define INT_STS_TXE_ (0x00002000) /* R/WC */
373//#define INT_STS_ERX_ (0x00001000) /* R/WC */
374#define INT_STS_TDFU_ (0x00000800) /* R/WC */
375#define INT_STS_TDFO_ (0x00000400) /* R/WC */
376#define INT_STS_TDFA_ (0x00000200) /* R/WC */
377#define INT_STS_TSFF_ (0x00000100) /* R/WC */
378#define INT_STS_TSFL_ (0x00000080) /* R/WC */
379//#define INT_STS_RXDF_ (0x00000040) /* R/WC */
380#define INT_STS_RDFO_ (0x00000040) /* R/WC */
381#define INT_STS_RDFL_ (0x00000020) /* R/WC */
382#define INT_STS_RSFF_ (0x00000010) /* R/WC */
383#define INT_STS_RSFL_ (0x00000008) /* R/WC */
384#define INT_STS_GPIO2_INT_ (0x00000004) /* R/WC */
385#define INT_STS_GPIO1_INT_ (0x00000002) /* R/WC */
386#define INT_STS_GPIO0_INT_ (0x00000001) /* R/WC */
387
388#define INT_EN (0x5C)
389#define INT_EN_SW_INT_EN_ (0x80000000) /* R/W */
390#define INT_EN_TXSTOP_INT_EN_ (0x02000000) /* R/W */
391#define INT_EN_RXSTOP_INT_EN_ (0x01000000) /* R/W */
392#define INT_EN_RXDFH_INT_EN_ (0x00800000) /* R/W */
393//#define INT_EN_RXDF_INT_EN_ (0x00400000) /* R/W */
394#define INT_EN_TIOC_INT_EN_ (0x00200000) /* R/W */
395#define INT_EN_RXD_INT_EN_ (0x00100000) /* R/W */
396#define INT_EN_GPT_INT_EN_ (0x00080000) /* R/W */
397#define INT_EN_PHY_INT_EN_ (0x00040000) /* R/W */
398#define INT_EN_PME_INT_EN_ (0x00020000) /* R/W */
399#define INT_EN_TXSO_EN_ (0x00010000) /* R/W */
400#define INT_EN_RWT_EN_ (0x00008000) /* R/W */
401#define INT_EN_RXE_EN_ (0x00004000) /* R/W */
402#define INT_EN_TXE_EN_ (0x00002000) /* R/W */
403//#define INT_EN_ERX_EN_ (0x00001000) /* R/W */
404#define INT_EN_TDFU_EN_ (0x00000800) /* R/W */
405#define INT_EN_TDFO_EN_ (0x00000400) /* R/W */
406#define INT_EN_TDFA_EN_ (0x00000200) /* R/W */
407#define INT_EN_TSFF_EN_ (0x00000100) /* R/W */
408#define INT_EN_TSFL_EN_ (0x00000080) /* R/W */
409//#define INT_EN_RXDF_EN_ (0x00000040) /* R/W */
410#define INT_EN_RDFO_EN_ (0x00000040) /* R/W */
411#define INT_EN_RDFL_EN_ (0x00000020) /* R/W */
412#define INT_EN_RSFF_EN_ (0x00000010) /* R/W */
413#define INT_EN_RSFL_EN_ (0x00000008) /* R/W */
414#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
415#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
416#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
417
418#define BYTE_TEST (0x64)
419#define FIFO_INT (0x68)
420#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
421#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
422#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
423#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
424
425#define RX_CFG (0x6C)
426#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
427#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
428#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
429#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
430#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
431#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
432#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
433//#define RX_CFG_RXBAD_ (0x00000001) /* R/W */
434
435#define TX_CFG (0x70)
436//#define TX_CFG_TX_DMA_LVL_ (0xE0000000) /* R/W */
437//#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000) /* R/W Self Clearing */
438#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
439#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
440#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
441#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
442#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
443
444#define HW_CFG (0x74)
445#define HW_CFG_TTM_ (0x00200000) /* R/W */
446#define HW_CFG_SF_ (0x00100000) /* R/W */
447#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
448#define HW_CFG_TR_ (0x00003000) /* R/W */
449#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
450#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
451#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
452#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
453#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
454#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
455#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
456#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
457#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
458#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
459
460#define RX_DP_CTRL (0x78)
461#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
462#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* RO */
463
464#define RX_FIFO_INF (0x7C)
465#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
466#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
467
468#define TX_FIFO_INF (0x80)
469#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
470#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
471
472#define PMT_CTRL (0x84)
473#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
474#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
475#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
476#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
477#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
478#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
479#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
480#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
481#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
482#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
483#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
484#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
485#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
486#define PMT_CTRL_READY_ (0x00000001) /* RO */
487
488#define GPIO_CFG (0x88)
489#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
490#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
491#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
492#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
493#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
494#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
495#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
496#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
497#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
498#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
499#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
500#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
501#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
502#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
503#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
504#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
505#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
506#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
507
508#define GPT_CFG (0x8C)
509#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
510#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
511
512#define GPT_CNT (0x90)
513#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
514
515#define ENDIAN (0x98)
516#define FREE_RUN (0x9C)
517#define RX_DROP (0xA0)
518#define MAC_CSR_CMD (0xA4)
519#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
520#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
521#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
522
523#define MAC_CSR_DATA (0xA8)
524#define AFC_CFG (0xAC)
525#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
526#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
527#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
528#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
529#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
530#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
531#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
532
533#define E2P_CMD (0xB0)
534#define E2P_CMD_EPC_BUSY_ (0x80000000) /* Self Clearing */
535#define E2P_CMD_EPC_CMD_ (0x70000000) /* R/W */
536#define E2P_CMD_EPC_CMD_READ_ (0x00000000) /* R/W */
537#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) /* R/W */
538#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) /* R/W */
539#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) /* R/W */
540#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) /* R/W */
541#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) /* R/W */
542#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) /* R/W */
543#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) /* R/W */
544#define E2P_CMD_EPC_TIMEOUT_ (0x00000200) /* RO */
545#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) /* RO */
546#define E2P_CMD_EPC_ADDR_ (0x000000FF) /* R/W */
547
548#define E2P_DATA (0xB4)
549#define E2P_DATA_EEPROM_DATA_ (0x000000FF) /* R/W */
550/* end of LAN register offsets and bit definitions */
551
552/*
553 ****************************************************************************
554 ****************************************************************************
555 * MAC Control and Status Register (Indirect Address)
556 * Offset (through the MAC_CSR CMD and DATA port)
557 ****************************************************************************
558 ****************************************************************************
559 *
560 */
561#define MAC_CR (0x01) /* R/W */
562
563/* MAC_CR - MAC Control Register */
564#define MAC_CR_RXALL_ (0x80000000)
565// TODO: delete this bit? It is not described in the data sheet.
566#define MAC_CR_HBDIS_ (0x10000000)
567#define MAC_CR_RCVOWN_ (0x00800000)
568#define MAC_CR_LOOPBK_ (0x00200000)
569#define MAC_CR_FDPX_ (0x00100000)
570#define MAC_CR_MCPAS_ (0x00080000)
571#define MAC_CR_PRMS_ (0x00040000)
572#define MAC_CR_INVFILT_ (0x00020000)
573#define MAC_CR_PASSBAD_ (0x00010000)
574#define MAC_CR_HFILT_ (0x00008000)
575#define MAC_CR_HPFILT_ (0x00002000)
576#define MAC_CR_LCOLL_ (0x00001000)
577#define MAC_CR_BCAST_ (0x00000800)
578#define MAC_CR_DISRTY_ (0x00000400)
579#define MAC_CR_PADSTR_ (0x00000100)
580#define MAC_CR_BOLMT_MASK_ (0x000000C0)
581#define MAC_CR_DFCHK_ (0x00000020)
582#define MAC_CR_TXEN_ (0x00000008)
583#define MAC_CR_RXEN_ (0x00000004)
584
585#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
586#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
587#define HASHH (0x04) /* R/W */
588#define HASHL (0x05) /* R/W */
589
590#define MII_ACC (0x06) /* R/W */
591#define MII_ACC_PHY_ADDR_ (0x0000F800)
592#define MII_ACC_MIIRINDA_ (0x000007C0)
593#define MII_ACC_MII_WRITE_ (0x00000002)
594#define MII_ACC_MII_BUSY_ (0x00000001)
595
596#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
597
598#define FLOW (0x08) /* R/W */
599#define FLOW_FCPT_ (0xFFFF0000)
600#define FLOW_FCPASS_ (0x00000004)
601#define FLOW_FCEN_ (0x00000002)
602#define FLOW_FCBSY_ (0x00000001)
603
604#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
605#define VLAN1_VTI1_ (0x0000ffff)
606
607#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
608#define VLAN2_VTI2_ (0x0000ffff)
609
610#define WUFF (0x0B) /* WO */
611
612#define WUCSR (0x0C) /* R/W */
613#define WUCSR_GUE_ (0x00000200)
614#define WUCSR_WUFR_ (0x00000040)
615#define WUCSR_MPR_ (0x00000020)
616#define WUCSR_WAKE_EN_ (0x00000004)
617#define WUCSR_MPEN_ (0x00000002)
618
619/*
620 ****************************************************************************
621 * Chip Specific MII Defines
622 ****************************************************************************
623 *
624 * Phy register offsets and bit definitions
625 *
626 */
627
628#define PHY_MODE_CTRL_STS ((u32)17) /* Mode Control/Status Register */
629//#define MODE_CTRL_STS_FASTRIP_ ((u16)0x4000)
630#define MODE_CTRL_STS_EDPWRDOWN_ ((u16)0x2000)
631//#define MODE_CTRL_STS_LOWSQEN_ ((u16)0x0800)
632//#define MODE_CTRL_STS_MDPREBP_ ((u16)0x0400)
633//#define MODE_CTRL_STS_FARLOOPBACK_ ((u16)0x0200)
634//#define MODE_CTRL_STS_FASTEST_ ((u16)0x0100)
635//#define MODE_CTRL_STS_REFCLKEN_ ((u16)0x0010)
636//#define MODE_CTRL_STS_PHYADBP_ ((u16)0x0008)
637//#define MODE_CTRL_STS_FORCE_G_LINK_ ((u16)0x0004)
638#define MODE_CTRL_STS_ENERGYON_ ((u16)0x0002)
639
640#define PHY_INT_SRC ((u32)29)
641#define PHY_INT_SRC_ENERGY_ON_ ((u16)0x0080)
642#define PHY_INT_SRC_ANEG_COMP_ ((u16)0x0040)
643#define PHY_INT_SRC_REMOTE_FAULT_ ((u16)0x0020)
644#define PHY_INT_SRC_LINK_DOWN_ ((u16)0x0010)
645#define PHY_INT_SRC_ANEG_LP_ACK_ ((u16)0x0008)
646#define PHY_INT_SRC_PAR_DET_FAULT_ ((u16)0x0004)
647#define PHY_INT_SRC_ANEG_PGRX_ ((u16)0x0002)
648
649#define PHY_INT_MASK ((u32)30)
650#define PHY_INT_MASK_ENERGY_ON_ ((u16)0x0080)
651#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
652#define PHY_INT_MASK_REMOTE_FAULT_ ((u16)0x0020)
653#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
654#define PHY_INT_MASK_ANEG_LP_ACK_ ((u16)0x0008)
655#define PHY_INT_MASK_PAR_DET_FAULT_ ((u16)0x0004)
656#define PHY_INT_MASK_ANEG_PGRX_ ((u16)0x0002)
657
658#define PHY_SPECIAL ((u32)31)
659#define PHY_SPECIAL_ANEG_DONE_ ((u16)0x1000)
660#define PHY_SPECIAL_RES_ ((u16)0x0040)
661#define PHY_SPECIAL_RES_MASK_ ((u16)0x0FE1)
662#define PHY_SPECIAL_SPD_ ((u16)0x001C)
663#define PHY_SPECIAL_SPD_10HALF_ ((u16)0x0004)
664#define PHY_SPECIAL_SPD_10FULL_ ((u16)0x0014)
665#define PHY_SPECIAL_SPD_100HALF_ ((u16)0x0008)
666#define PHY_SPECIAL_SPD_100FULL_ ((u16)0x0018)
667
668#define LAN911X_INTERNAL_PHY_ID (0x0007C000)
669
670/* Chip ID values */
c6dcb827
GL		 671#define CHIP_9115 0x0115
672#define CHIP_9116 0x0116
673#define CHIP_9117 0x0117
674#define CHIP_9118 0x0118
675#define CHIP_9215 0x115A
676#define CHIP_9217 0x117A
677#define CHIP_9218 0x118A
0a0c72c9
DM		 678
679struct chip_id {
680 u16 id;
681 char *name;
682};
d5498bef 683
0a0c72c9
DM		 684static const struct chip_id chip_ids[] = {
685 { CHIP_9115, "LAN9115" },
686 { CHIP_9116, "LAN9116" },
687 { CHIP_9117, "LAN9117" },
688 { CHIP_9118, "LAN9118" },
c6dcb827
GL		 689 { CHIP_9215, "LAN9215" },
690 { CHIP_9217, "LAN9217" },
691 { CHIP_9218, "LAN9218" },
0a0c72c9
DM		 692 { 0, NULL },
693};
694
695#define IS_REV_A(x) ((x & 0xFFFF)==0)
696
697/*
698 * Macros to abstract register access according to the data bus
699 * capabilities. Please use those and not the in/out primitives.
700 */
701/* FIFO read/write macros */
699559f8
MD		 702#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
703#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
704#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
705#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
0a0c72c9
DM		 706
707
708/* I/O mapped register read/write macros */
699559f8
MD		 709#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
710#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
711#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
712#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
713#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
714#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
715#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
716#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
717#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
718#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
719#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
720#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
721#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
722#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
723#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
724#define SMC_SET_FIFO_TDA(lp, x) \
0a0c72c9
DM		 725 do { \
726 unsigned long __flags; \
727 int __mask; \
728 local_irq_save(__flags); \
699559f8
MD		 729 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
730 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
0a0c72c9
DM		 731 local_irq_restore(__flags); \
732 } while (0)
699559f8 733#define SMC_SET_FIFO_TSL(lp, x) \
0a0c72c9
DM		 734 do { \
735 unsigned long __flags; \
736 int __mask; \
737 local_irq_save(__flags); \
699559f8
MD		 738 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
739 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
0a0c72c9
DM		 740 local_irq_restore(__flags); \
741 } while (0)
699559f8 742#define SMC_SET_FIFO_RSA(lp, x) \
0a0c72c9
DM		 743 do { \
744 unsigned long __flags; \
745 int __mask; \
746 local_irq_save(__flags); \
699559f8
MD		 747 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
748 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
0a0c72c9
DM		 749 local_irq_restore(__flags); \
750 } while (0)
699559f8 751#define SMC_SET_FIFO_RSL(lp, x) \
0a0c72c9
DM		 752 do { \
753 unsigned long __flags; \
754 int __mask; \
755 local_irq_save(__flags); \
699559f8
MD		 756 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
757 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
0a0c72c9
DM		 758 local_irq_restore(__flags); \
759 } while (0)
699559f8
MD		 760#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
761#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
762#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
763#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
764#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
765#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
766#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
767#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
768#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
769#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
770#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
771#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
772#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
773#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
774#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
775#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
776#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
777#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
778#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
779#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
780#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
781#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
782#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
783#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
784#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
785#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
786#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
787#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
788#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
789#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
0a0c72c9
DM		 790
791/* MAC register read/write macros */
699559f8 792#define SMC_GET_MAC_CSR(lp,a,v) \
0a0c72c9 793 do { \
699559f8
MD		 794 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
795 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
0a0c72c9 796 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
699559f8
MD		 797 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
798 v = SMC_GET_MAC_DATA((lp)); \
0a0c72c9 799 } while (0)
699559f8 800#define SMC_SET_MAC_CSR(lp,a,v) \
0a0c72c9 801 do { \
699559f8
MD		 802 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
803 SMC_SET_MAC_DATA((lp), v); \
804 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
805 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
0a0c72c9 806 } while (0)
699559f8
MD		 807#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
808#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
809#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
810#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
811#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
812#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
813#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
814#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
815#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
816#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
817#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
818#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
819#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
820#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
821#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
822#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
823#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
824#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
825#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
826#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
827#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
828#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
829#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
0a0c72c9
DM		 830
831/* PHY register read/write macros */
699559f8 832#define SMC_GET_MII(lp,a,phy,v) \
0a0c72c9
DM		 833 do { \
834 u32 __v; \
835 do { \
699559f8 836 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 837 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 838 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 839 MII_ACC_MII_BUSY_); \
840 do { \
699559f8 841 SMC_GET_MII_ACC( (lp), __v); \
0a0c72c9 842 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8 843 SMC_GET_MII_DATA((lp), v); \
0a0c72c9 844 } while (0)
699559f8 845#define SMC_SET_MII(lp,a,phy,v) \
0a0c72c9
DM		 846 do { \
847 u32 __v; \
848 do { \
699559f8 849 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9 850 } while ( __v & MII_ACC_MII_BUSY_ ); \
699559f8
MD		 851 SMC_SET_MII_DATA((lp), v); \
852 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
0a0c72c9
DM		 853 MII_ACC_MII_BUSY_ | \
854 MII_ACC_MII_WRITE_ ); \
855 do { \
699559f8 856 SMC_GET_MII_ACC((lp), __v); \
0a0c72c9
DM		 857 } while ( __v & MII_ACC_MII_BUSY_ ); \
858 } while (0)
699559f8
MD		 859#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
860#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
861#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
862#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
863#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
864#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
865#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
866#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
867#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
868#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
869#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
870#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
871#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
872#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
873#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
874#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
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DM		 875
876
877
878/* Misc read/write macros */
879
880#ifndef SMC_GET_MAC_ADDR
699559f8 881#define SMC_GET_MAC_ADDR(lp, addr) \
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DM		 882 do { \
883 unsigned int __v; \
884 \
699559f8 885 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
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DM		 886 addr[0] = __v; addr[1] = __v >> 8; \
887 addr[2] = __v >> 16; addr[3] = __v >> 24; \
699559f8 888 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
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DM		 889 addr[4] = __v; addr[5] = __v >> 8; \
890 } while (0)
891#endif
892
699559f8 893#define SMC_SET_MAC_ADDR(lp, addr) \
0a0c72c9 894 do { \
699559f8 895 SMC_SET_MAC_CSR((lp), ADDRL, \
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DM		 896 addr[0] | \
897 (addr[1] << 8) | \
898 (addr[2] << 16) | \
899 (addr[3] << 24)); \
699559f8 900 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
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DM		 901 } while (0)
902
903
699559f8 904#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
0a0c72c9 905 do { \
699559f8
MD		 906 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
907 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
908 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
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DM		 909 } while (0)
910
911#endif /* _SMC911X_H_ */
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