[linux.git] / drivers / clocksource / sh_mtu2.c

/*
 * SuperH Timer Support - MTU2
 *
 *  Copyright (C) 2009 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

struct sh_mtu2_priv {
	void __iomem *mapbase;
	struct clk *clk;
	struct irqaction irqaction;
	struct platform_device *pdev;
	unsigned long rate;
	unsigned long periodic;
	struct clock_event_device ced;
};

static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);

#define TSTR -1 /* shared register */
#define TCR  0 /* channel register */
#define TMDR 1 /* channel register */
#define TIOR 2 /* channel register */
#define TIER 3 /* channel register */
#define TSR  4 /* channel register */
#define TCNT 5 /* channel register */
#define TGR  6 /* channel register */

static unsigned long mtu2_reg_offs[] = {
	[TCR] = 0,
	[TMDR] = 1,
	[TIOR] = 2,
	[TIER] = 4,
	[TSR] = 5,
	[TCNT] = 6,
	[TGR] = 8,
};

static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR)
		return ioread8(base + cfg->channel_offset);

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		return ioread16(base + offs);
	else
		return ioread8(base + offs);
}

static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == TSTR) {
		iowrite8(value, base + cfg->channel_offset);
		return;
	}

	offs = mtu2_reg_offs[reg_nr];

	if ((reg_nr == TCNT) || (reg_nr == TGR))
		iowrite16(value, base + offs);
	else
		iowrite8(value, base + offs);
}

static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
	value = sh_mtu2_read(p, TSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_mtu2_write(p, TSTR, value);
	raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
}

static int sh_mtu2_enable(struct sh_mtu2_priv *p)
{
	int ret;

	pm_runtime_get_sync(&p->pdev->dev);
	dev_pm_syscore_device(&p->pdev->dev, true);

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		dev_err(&p->pdev->dev, "cannot enable clock\n");
		return ret;
	}

	/* make sure channel is disabled */
	sh_mtu2_start_stop_ch(p, 0);

	p->rate = clk_get_rate(p->clk) / 64;
	p->periodic = (p->rate + HZ/2) / HZ;

	/* "Periodic Counter Operation" */
	sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
	sh_mtu2_write(p, TIOR, 0);
	sh_mtu2_write(p, TGR, p->periodic);
	sh_mtu2_write(p, TCNT, 0);
	sh_mtu2_write(p, TMDR, 0);
	sh_mtu2_write(p, TIER, 0x01);

	/* enable channel */
	sh_mtu2_start_stop_ch(p, 1);

	return 0;
}

static void sh_mtu2_disable(struct sh_mtu2_priv *p)
{
	/* disable channel */
	sh_mtu2_start_stop_ch(p, 0);

	/* stop clock */
	clk_disable(p->clk);

	dev_pm_syscore_device(&p->pdev->dev, false);
	pm_runtime_put(&p->pdev->dev);
}

static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
{
	struct sh_mtu2_priv *p = dev_id;

	/* acknowledge interrupt */
	sh_mtu2_read(p, TSR);
	sh_mtu2_write(p, TSR, 0xfe);

	/* notify clockevent layer */
	p->ced.event_handler(&p->ced);
	return IRQ_HANDLED;
}

static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_mtu2_priv, ced);
}

static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
	int disabled = 0;

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		sh_mtu2_disable(p);
		disabled = 1;
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		dev_info(&p->pdev->dev, "used for periodic clock events\n");
		sh_mtu2_enable(p);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		if (!disabled)
			sh_mtu2_disable(p);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		break;
	}
}

static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->pdev->dev);
}

static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
{
	pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->pdev->dev);
}

static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;
	int ret;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_mode = sh_mtu2_clock_event_mode;
	ced->suspend = sh_mtu2_clock_event_suspend;
	ced->resume = sh_mtu2_clock_event_resume;

	dev_info(&p->pdev->dev, "used for clock events\n");
	clockevents_register_device(ced);

	ret = setup_irq(p->irqaction.irq, &p->irqaction);
	if (ret) {
		dev_err(&p->pdev->dev, "failed to request irq %d\n",
			p->irqaction.irq);
		return;
	}
}

static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
			    unsigned long clockevent_rating)
{
	if (clockevent_rating)
		sh_mtu2_register_clockevent(p, name, clockevent_rating);

	return 0;
}

static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
{
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
		goto err0;
	}

	/* setup data for setup_irq() (too early for request_irq()) */
	p->irqaction.name = dev_name(&p->pdev->dev);
	p->irqaction.handler = sh_mtu2_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.irq = irq;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
			     IRQF_IRQPOLL  | IRQF_NOBALANCING;

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
	if (IS_ERR(p->clk)) {
		dev_err(&p->pdev->dev, "cannot get clock\n");
		ret = PTR_ERR(p->clk);
		goto err1;
	}

	return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
				cfg->clockevent_rating);
 err1:
	iounmap(p->mapbase);
 err0:
	return ret;
}

static int sh_mtu2_probe(struct platform_device *pdev)
{
	struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
	struct sh_timer_config *cfg = pdev->dev.platform_data;
	int ret;

	if (!is_early_platform_device(pdev)) {
		pm_runtime_set_active(&pdev->dev);
		pm_runtime_enable(&pdev->dev);
	}

	if (p) {
		dev_info(&pdev->dev, "kept as earlytimer\n");
		goto out;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_mtu2_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
		pm_runtime_idle(&pdev->dev);
		return ret;
	}
	if (is_early_platform_device(pdev))
		return 0;

 out:
	if (cfg->clockevent_rating)
		pm_runtime_irq_safe(&pdev->dev);
	else
		pm_runtime_idle(&pdev->dev);

	return 0;
}

static int sh_mtu2_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent */
}

static struct platform_driver sh_mtu2_device_driver = {
	.probe		= sh_mtu2_probe,
	.remove		= sh_mtu2_remove,
	.driver		= {
		.name	= "sh_mtu2",
	}
};

static int __init sh_mtu2_init(void)
{
	return platform_driver_register(&sh_mtu2_device_driver);
}

static void __exit sh_mtu2_exit(void)
{
	platform_driver_unregister(&sh_mtu2_device_driver);
}

early_platform_init("earlytimer", &sh_mtu2_device_driver);
subsys_initcall(sh_mtu2_init);
module_exit(sh_mtu2_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d5ed4c2e MD	1	/*
	2	* SuperH Timer Support - MTU2
	3	*
	4	* Copyright (C) 2009 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/delay.h>
	26	#include <linux/io.h>
	27	#include <linux/clk.h>
	28	#include <linux/irq.h>
	29	#include <linux/err.h>
	30	#include <linux/clockchips.h>
46a12f74	31	#include <linux/sh_timer.h>
5a0e3ad6	32	#include <linux/slab.h>
7deeab5d	33	#include <linux/module.h>
57d13370	34	#include <linux/pm_domain.h>
3cb6f10a	35	#include <linux/pm_runtime.h>
d5ed4c2e MD	36
	37	struct sh_mtu2_priv {
	38	void __iomem *mapbase;
	39	struct clk *clk;
	40	struct irqaction irqaction;
	41	struct platform_device *pdev;
	42	unsigned long rate;
	43	unsigned long periodic;
	44	struct clock_event_device ced;
	45	};
	46
50393a92	47	static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
d5ed4c2e MD	48
	49	#define TSTR -1 /* shared register */
	50	#define TCR 0 /* channel register */
	51	#define TMDR 1 /* channel register */
	52	#define TIOR 2 /* channel register */
	53	#define TIER 3 /* channel register */
	54	#define TSR 4 /* channel register */
	55	#define TCNT 5 /* channel register */
	56	#define TGR 6 /* channel register */
	57
	58	static unsigned long mtu2_reg_offs[] = {
	59	[TCR] = 0,
	60	[TMDR] = 1,
	61	[TIOR] = 2,
	62	[TIER] = 4,
	63	[TSR] = 5,
	64	[TCNT] = 6,
	65	[TGR] = 8,
	66	};
	67
	68	static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
	69	{
46a12f74	70	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
d5ed4c2e MD	71	void __iomem *base = p->mapbase;
	72	unsigned long offs;
	73
	74	if (reg_nr == TSTR)
	75	return ioread8(base + cfg->channel_offset);
	76
	77	offs = mtu2_reg_offs[reg_nr];
	78
	79	if ((reg_nr == TCNT) \|\| (reg_nr == TGR))
	80	return ioread16(base + offs);
	81	else
	82	return ioread8(base + offs);
	83	}
	84
	85	static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
	86	unsigned long value)
	87	{
46a12f74	88	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
d5ed4c2e MD	89	void __iomem *base = p->mapbase;
	90	unsigned long offs;
	91
	92	if (reg_nr == TSTR) {
	93	iowrite8(value, base + cfg->channel_offset);
	94	return;
	95	}
	96
	97	offs = mtu2_reg_offs[reg_nr];
	98
	99	if ((reg_nr == TCNT) \|\| (reg_nr == TGR))
	100	iowrite16(value, base + offs);
	101	else
	102	iowrite8(value, base + offs);
	103	}
	104
	105	static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
	106	{
46a12f74	107	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
d5ed4c2e MD	108	unsigned long flags, value;
	109
	110	/* start stop register shared by multiple timer channels */
50393a92	111	raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
d5ed4c2e MD	112	value = sh_mtu2_read(p, TSTR);
	113
	114	if (start)
	115	value \|= 1 << cfg->timer_bit;
	116	else
	117	value &= ~(1 << cfg->timer_bit);
	118
	119	sh_mtu2_write(p, TSTR, value);
50393a92	120	raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
d5ed4c2e MD	121	}
	122
	123	static int sh_mtu2_enable(struct sh_mtu2_priv *p)
	124	{
d5ed4c2e MD	125	int ret;
d5ed4c2e MD	126
3cb6f10a RW	127	pm_runtime_get_sync(&p->pdev->dev);
	128	dev_pm_syscore_device(&p->pdev->dev, true);
	129
d5ed4c2e MD	130	/* enable clock */
	131	ret = clk_enable(p->clk);
	132	if (ret) {
214a607a	133	dev_err(&p->pdev->dev, "cannot enable clock\n");
d5ed4c2e MD	134	return ret;
	135	}
	136
	137	/* make sure channel is disabled */
	138	sh_mtu2_start_stop_ch(p, 0);
	139
	140	p->rate = clk_get_rate(p->clk) / 64;
	141	p->periodic = (p->rate + HZ/2) / HZ;
	142
	143	/* "Periodic Counter Operation" */
	144	sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
	145	sh_mtu2_write(p, TIOR, 0);
	146	sh_mtu2_write(p, TGR, p->periodic);
	147	sh_mtu2_write(p, TCNT, 0);
	148	sh_mtu2_write(p, TMDR, 0);
	149	sh_mtu2_write(p, TIER, 0x01);
	150
	151	/* enable channel */
	152	sh_mtu2_start_stop_ch(p, 1);
	153
	154	return 0;
	155	}
	156
	157	static void sh_mtu2_disable(struct sh_mtu2_priv *p)
	158	{
	159	/* disable channel */
	160	sh_mtu2_start_stop_ch(p, 0);
	161
	162	/* stop clock */
	163	clk_disable(p->clk);
3cb6f10a RW	164
	165	dev_pm_syscore_device(&p->pdev->dev, false);
	166	pm_runtime_put(&p->pdev->dev);
d5ed4c2e MD	167	}
	168
	169	static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
	170	{
	171	struct sh_mtu2_priv *p = dev_id;
	172
	173	/* acknowledge interrupt */
	174	sh_mtu2_read(p, TSR);
	175	sh_mtu2_write(p, TSR, 0xfe);
	176
	177	/* notify clockevent layer */
	178	p->ced.event_handler(&p->ced);
	179	return IRQ_HANDLED;
	180	}
	181
	182	static struct sh_mtu2_priv ced_to_sh_mtu2(struct clock_event_device ced)
	183	{
	184	return container_of(ced, struct sh_mtu2_priv, ced);
	185	}
	186
	187	static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
	188	struct clock_event_device *ced)
	189	{
	190	struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
	191	int disabled = 0;
	192
	193	/* deal with old setting first */
	194	switch (ced->mode) {
	195	case CLOCK_EVT_MODE_PERIODIC:
	196	sh_mtu2_disable(p);
	197	disabled = 1;
	198	break;
	199	default:
	200	break;
	201	}
	202
	203	switch (mode) {
	204	case CLOCK_EVT_MODE_PERIODIC:
214a607a	205	dev_info(&p->pdev->dev, "used for periodic clock events\n");
d5ed4c2e MD	206	sh_mtu2_enable(p);
	207	break;
	208	case CLOCK_EVT_MODE_UNUSED:
	209	if (!disabled)
	210	sh_mtu2_disable(p);
	211	break;
	212	case CLOCK_EVT_MODE_SHUTDOWN:
	213	default:
	214	break;
	215	}
	216	}
	217
cc7ad456 RW	218	static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
	219	{
	220	pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->pdev->dev);
	221	}
	222
	223	static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
	224	{
	225	pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->pdev->dev);
	226	}
	227
d5ed4c2e MD	228	static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
	229	char *name, unsigned long rating)
	230	{
	231	struct clock_event_device *ced = &p->ced;
	232	int ret;
	233
	234	memset(ced, 0, sizeof(*ced));
	235
	236	ced->name = name;
	237	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	238	ced->rating = rating;
	239	ced->cpumask = cpumask_of(0);
	240	ced->set_mode = sh_mtu2_clock_event_mode;
cc7ad456 RW	241	ced->suspend = sh_mtu2_clock_event_suspend;
cc7ad456 RW	242	ced->resume = sh_mtu2_clock_event_resume;
d5ed4c2e	243
214a607a	244	dev_info(&p->pdev->dev, "used for clock events\n");
da64c2a8 PM	245	clockevents_register_device(ced);
da64c2a8 PM	246
d5ed4c2e MD	247	ret = setup_irq(p->irqaction.irq, &p->irqaction);
d5ed4c2e MD	248	if (ret) {
214a607a PM	249	dev_err(&p->pdev->dev, "failed to request irq %d\n",
214a607a PM	250	p->irqaction.irq);
d5ed4c2e MD	251	return;
d5ed4c2e MD	252	}
d5ed4c2e MD	253	}
d5ed4c2e MD	254
d1fcc0a8 PM	255	static int sh_mtu2_register(struct sh_mtu2_priv p, char name,
d1fcc0a8 PM	256	unsigned long clockevent_rating)
d5ed4c2e MD	257	{
	258	if (clockevent_rating)
	259	sh_mtu2_register_clockevent(p, name, clockevent_rating);
	260
	261	return 0;
	262	}
	263
	264	static int sh_mtu2_setup(struct sh_mtu2_priv p, struct platform_device pdev)
	265	{
46a12f74	266	struct sh_timer_config *cfg = pdev->dev.platform_data;
d5ed4c2e MD	267	struct resource *res;
	268	int irq, ret;
	269	ret = -ENXIO;
	270
	271	memset(p, 0, sizeof(*p));
	272	p->pdev = pdev;
	273
	274	if (!cfg) {
	275	dev_err(&p->pdev->dev, "missing platform data\n");
	276	goto err0;
	277	}
	278
	279	platform_set_drvdata(pdev, p);
	280
	281	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	282	if (!res) {
	283	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	284	goto err0;
	285	}
	286
	287	irq = platform_get_irq(p->pdev, 0);
	288	if (irq < 0) {
	289	dev_err(&p->pdev->dev, "failed to get irq\n");
	290	goto err0;
	291	}
	292
	293	/* map memory, let mapbase point to our channel */
	294	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	295	if (p->mapbase == NULL) {
214a607a	296	dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
d5ed4c2e MD	297	goto err0;
	298	}
	299
	300	/* setup data for setup_irq() (too early for request_irq()) */
214a607a	301	p->irqaction.name = dev_name(&p->pdev->dev);
d5ed4c2e MD	302	p->irqaction.handler = sh_mtu2_interrupt;
	303	p->irqaction.dev_id = p;
	304	p->irqaction.irq = irq;
fecf066c PM	305	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| \
fecf066c PM	306	IRQF_IRQPOLL \| IRQF_NOBALANCING;
d5ed4c2e MD	307
d5ed4c2e MD	308	/* get hold of clock */
c2a25e81	309	p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
d5ed4c2e	310	if (IS_ERR(p->clk)) {
03ff858c MD	311	dev_err(&p->pdev->dev, "cannot get clock\n");
	312	ret = PTR_ERR(p->clk);
	313	goto err1;
d5ed4c2e MD	314	}
d5ed4c2e MD	315
214a607a PM	316	return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
214a607a PM	317	cfg->clockevent_rating);
d5ed4c2e MD	318	err1:
	319	iounmap(p->mapbase);
	320	err0:
	321	return ret;
	322	}
	323
1850514b	324	static int sh_mtu2_probe(struct platform_device *pdev)
d5ed4c2e MD	325	{
d5ed4c2e MD	326	struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
3cb6f10a	327	struct sh_timer_config *cfg = pdev->dev.platform_data;
d5ed4c2e	328	int ret;
57d13370	329
cc7ad456	330	if (!is_early_platform_device(pdev)) {
3cb6f10a RW	331	pm_runtime_set_active(&pdev->dev);
3cb6f10a RW	332	pm_runtime_enable(&pdev->dev);
cc7ad456	333	}
d5ed4c2e MD	334
d5ed4c2e MD	335	if (p) {
214a607a	336	dev_info(&pdev->dev, "kept as earlytimer\n");
3cb6f10a	337	goto out;
d5ed4c2e MD	338	}
	339
	340	p = kmalloc(sizeof(*p), GFP_KERNEL);
	341	if (p == NULL) {
	342	dev_err(&pdev->dev, "failed to allocate driver data\n");
	343	return -ENOMEM;
	344	}
	345
	346	ret = sh_mtu2_setup(p, pdev);
	347	if (ret) {
	348	kfree(p);
	349	platform_set_drvdata(pdev, NULL);
3cb6f10a RW	350	pm_runtime_idle(&pdev->dev);
3cb6f10a RW	351	return ret;
d5ed4c2e	352	}
3cb6f10a RW	353	if (is_early_platform_device(pdev))
	354	return 0;
	355
	356	out:
	357	if (cfg->clockevent_rating)
	358	pm_runtime_irq_safe(&pdev->dev);
	359	else
	360	pm_runtime_idle(&pdev->dev);
	361
	362	return 0;
d5ed4c2e MD	363	}
d5ed4c2e MD	364
1850514b	365	static int sh_mtu2_remove(struct platform_device *pdev)
d5ed4c2e MD	366	{
	367	return -EBUSY; /* cannot unregister clockevent */
	368	}
	369
	370	static struct platform_driver sh_mtu2_device_driver = {
	371	.probe = sh_mtu2_probe,
1850514b	372	.remove = sh_mtu2_remove,
d5ed4c2e MD	373	.driver = {
	374	.name = "sh_mtu2",
	375	}
	376	};
	377
	378	static int __init sh_mtu2_init(void)
	379	{
	380	return platform_driver_register(&sh_mtu2_device_driver);
	381	}
	382
	383	static void __exit sh_mtu2_exit(void)
	384	{
	385	platform_driver_unregister(&sh_mtu2_device_driver);
	386	}
	387
	388	early_platform_init("earlytimer", &sh_mtu2_device_driver);
342896a5	389	subsys_initcall(sh_mtu2_init);
d5ed4c2e MD	390	module_exit(sh_mtu2_exit);
	391
	392	MODULE_AUTHOR("Magnus Damm");
	393	MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
	394	MODULE_LICENSE("GPL v2");