]> Git Repo - linux.git/blame - drivers/ata/sata_dwc_460ex.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
[linux.git] / drivers / ata / sata_dwc_460ex.c
CommitLineData
62936009
RS		 1/*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <[email protected]>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <[email protected]>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#ifdef CONFIG_SATA_DWC_DEBUG
22#define DEBUG
23#endif
24
25#ifdef CONFIG_SATA_DWC_VDEBUG
26#define VERBOSE_DEBUG
27#define DEBUG_NCQ
28#endif
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/device.h>
34#include <linux/of_platform.h>
35#include <linux/platform_device.h>
36#include <linux/libata.h>
37#include <linux/slab.h>
38#include "libata.h"
39
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_cmnd.h>
42
c211962d
SS		 43/* These two are defined in "libata.h" */
44#undef DRV_NAME
45#undef DRV_VERSION
72d5f2da 46
62936009 47#define DRV_NAME "sata-dwc"
84b47e3b 48#define DRV_VERSION "1.3"
62936009
RS		 49
50/* SATA DMA driver Globals */
51#define DMA_NUM_CHANS 1
52#define DMA_NUM_CHAN_REGS 8
53
54/* SATA DMA Register definitions */
55#define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
56
57struct dmareg {
58 u32 low; /* Low bits 0-31 */
59 u32 high; /* High bits 32-63 */
60};
61
62/* DMA Per Channel registers */
63struct dma_chan_regs {
64 struct dmareg sar; /* Source Address */
65 struct dmareg dar; /* Destination address */
66 struct dmareg llp; /* Linked List Pointer */
67 struct dmareg ctl; /* Control */
68 struct dmareg sstat; /* Source Status not implemented in core */
69 struct dmareg dstat; /* Destination Status not implemented in core*/
70 struct dmareg sstatar; /* Source Status Address not impl in core */
71 struct dmareg dstatar; /* Destination Status Address not implemente */
72 struct dmareg cfg; /* Config */
73 struct dmareg sgr; /* Source Gather */
74 struct dmareg dsr; /* Destination Scatter */
75};
76
77/* Generic Interrupt Registers */
78struct dma_interrupt_regs {
79 struct dmareg tfr; /* Transfer Interrupt */
80 struct dmareg block; /* Block Interrupt */
81 struct dmareg srctran; /* Source Transfer Interrupt */
82 struct dmareg dsttran; /* Dest Transfer Interrupt */
83 struct dmareg error; /* Error */
84};
85
86struct ahb_dma_regs {
87 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
88 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
89 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
90 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
91 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
92 struct dmareg statusInt; /* Interrupt combined*/
93 struct dmareg rq_srcreg; /* Src Trans Req */
94 struct dmareg rq_dstreg; /* Dst Trans Req */
95 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
96 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
97 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
98 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
99 struct dmareg dma_cfg; /* DMA Config */
100 struct dmareg dma_chan_en; /* DMA Channel Enable*/
101 struct dmareg dma_id; /* DMA ID */
102 struct dmareg dma_test; /* DMA Test */
103 struct dmareg res1; /* reserved */
104 struct dmareg res2; /* reserved */
105 /*
106 * DMA Comp Params
107 * Param 6 = dma_param[0], Param 5 = dma_param[1],
108 * Param 4 = dma_param[2] ...
109 */
110 struct dmareg dma_params[6];
111};
112
113/* Data structure for linked list item */
114struct lli {
115 u32 sar; /* Source Address */
116 u32 dar; /* Destination address */
117 u32 llp; /* Linked List Pointer */
118 struct dmareg ctl; /* Control */
119 struct dmareg dstat; /* Destination Status */
120};
121
122enum {
123 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
124 SATA_DWC_DMAC_LLI_NUM = 256,
125 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
126 SATA_DWC_DMAC_LLI_NUM),
127 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
128 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
129 SATA_DWC_DMAC_TWIDTH_BYTES),
130};
131
132/* DMA Register Operation Bits */
133enum {
134 DMA_EN = 0x00000001, /* Enable AHB DMA */
135 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
136 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
137};
138
139#define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
140#define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
141 /* Enable channel */
142#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
143 ((0x000000001 << (ch)) << 8))
144 /* Disable channel */
145#define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
146 /* Transfer Type & Flow Controller */
147#define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
148#define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
149#define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
150 /* Src Burst Transaction Length */
151#define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
152 /* Dst Burst Transaction Length */
153#define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
154 /* Source Transfer Width */
155#define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
156 /* Destination Transfer Width */
157#define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
158
159/* Assign HW handshaking interface (x) to destination / source peripheral */
160#define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
161#define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
dc7f71f4 162#define DMA_CFG_HW_CH_PRIOR(int_num) (((int_num) & 0xF) << 5)
62936009
RS		 163#define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
164
165/*
166 * This define is used to set block chaining disabled in the control low
167 * register. It is already in little endian format so it can be &'d dirctly.
168 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
169 */
170enum {
171 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
172 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
173 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
174 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
175 DMA_CTL_SINC_DEC = 0x00000200,
176 DMA_CTL_SINC_NOCHANGE = 0x00000400,
177 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
178 DMA_CTL_DINC_DEC = 0x00000080,
179 DMA_CTL_DINC_NOCHANGE = 0x00000100,
180 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
181
182/* Channel Configuration Register high bits */
183 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
184 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
185
186/* Channel Configuration Register low bits */
187 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
188 DMA_CFG_RELD_SRC = 0x40000000,
189 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
190 DMA_CFG_HS_SELDST = 0x00000400,
191 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
192
193/* Channel Linked List Pointer Register */
194 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
195 DMA_LLP_AHBMASTER2 = 1,
196
197 SATA_DWC_MAX_PORTS = 1,
198
199 SATA_DWC_SCR_OFFSET = 0x24,
200 SATA_DWC_REG_OFFSET = 0x64,
201};
202
203/* DWC SATA Registers */
204struct sata_dwc_regs {
205 u32 fptagr; /* 1st party DMA tag */
206 u32 fpbor; /* 1st party DMA buffer offset */
207 u32 fptcr; /* 1st party DMA Xfr count */
208 u32 dmacr; /* DMA Control */
209 u32 dbtsr; /* DMA Burst Transac size */
210 u32 intpr; /* Interrupt Pending */
211 u32 intmr; /* Interrupt Mask */
212 u32 errmr; /* Error Mask */
213 u32 llcr; /* Link Layer Control */
214 u32 phycr; /* PHY Control */
215 u32 physr; /* PHY Status */
216 u32 rxbistpd; /* Recvd BIST pattern def register */
217 u32 rxbistpd1; /* Recvd BIST data dword1 */
218 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
219 u32 txbistpd; /* Trans BIST pattern def register */
220 u32 txbistpd1; /* Trans BIST data dword1 */
221 u32 txbistpd2; /* Trans BIST data dword2 */
222 u32 bistcr; /* BIST Control Register */
223 u32 bistfctr; /* BIST FIS Count Register */
224 u32 bistsr; /* BIST Status Register */
225 u32 bistdecr; /* BIST Dword Error count register */
226 u32 res[15]; /* Reserved locations */
227 u32 testr; /* Test Register */
228 u32 versionr; /* Version Register */
229 u32 idr; /* ID Register */
230 u32 unimpl[192]; /* Unimplemented */
231 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
232};
233
234enum {
235 SCR_SCONTROL_DET_ENABLE = 0x00000001,
236 SCR_SSTATUS_DET_PRESENT = 0x00000001,
237 SCR_SERROR_DIAG_X = 0x04000000,
238/* DWC SATA Register Operations */
239 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
240 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
241 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
242 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
243 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
244 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
245 SATA_DWC_INTPR_DMAT = 0x00000001,
246 SATA_DWC_INTPR_NEWFP = 0x00000002,
247 SATA_DWC_INTPR_PMABRT = 0x00000004,
248 SATA_DWC_INTPR_ERR = 0x00000008,
249 SATA_DWC_INTPR_NEWBIST = 0x00000010,
250 SATA_DWC_INTPR_IPF = 0x10000000,
251 SATA_DWC_INTMR_DMATM = 0x00000001,
252 SATA_DWC_INTMR_NEWFPM = 0x00000002,
253 SATA_DWC_INTMR_PMABRTM = 0x00000004,
254 SATA_DWC_INTMR_ERRM = 0x00000008,
255 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
256 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
257 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
258 SATA_DWC_LLCR_RPDEN = 0x00000004,
259/* This is all error bits, zero's are reserved fields. */
260 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
261};
262
263#define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
264#define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
265 SATA_DWC_DMACR_TMOD_TXCHEN)
266#define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
267 SATA_DWC_DMACR_TMOD_TXCHEN)
268#define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
269#define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
270 << 16)
271struct sata_dwc_device {
272 struct device *dev; /* generic device struct */
273 struct ata_probe_ent *pe; /* ptr to probe-ent */
274 struct ata_host *host;
275 u8 *reg_base;
276 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
277 int irq_dma;
278};
279
280#define SATA_DWC_QCMD_MAX 32
281
282struct sata_dwc_device_port {
283 struct sata_dwc_device *hsdev;
284 int cmd_issued[SATA_DWC_QCMD_MAX];
285 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
286 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
287 u32 dma_chan[SATA_DWC_QCMD_MAX];
288 int dma_pending[SATA_DWC_QCMD_MAX];
289};
290
291/*
292 * Commonly used DWC SATA driver Macros
293 */
294#define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
295 (host)->private_data)
296#define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
297 (ap)->host->private_data)
298#define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
299 (ap)->private_data)
300#define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
301 (qc)->ap->host->private_data)
302#define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
303 (hsdevp)->hsdev)
304
305enum {
306 SATA_DWC_CMD_ISSUED_NOT = 0,
307 SATA_DWC_CMD_ISSUED_PEND = 1,
308 SATA_DWC_CMD_ISSUED_EXEC = 2,
309 SATA_DWC_CMD_ISSUED_NODATA = 3,
310
311 SATA_DWC_DMA_PENDING_NONE = 0,
312 SATA_DWC_DMA_PENDING_TX = 1,
313 SATA_DWC_DMA_PENDING_RX = 2,
314};
315
316struct sata_dwc_host_priv {
317 void __iomem *scr_addr_sstatus;
318 u32 sata_dwc_sactive_issued ;
319 u32 sata_dwc_sactive_queued ;
320 u32 dma_interrupt_count;
321 struct ahb_dma_regs *sata_dma_regs;
322 struct device *dwc_dev;
dc7f71f4 323 int dma_channel;
62936009
RS		 324};
325struct sata_dwc_host_priv host_pvt;
326/*
327 * Prototypes
328 */
329static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
330static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
331 u32 check_status);
332static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
333static void sata_dwc_port_stop(struct ata_port *ap);
334static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
335static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
336static void dma_dwc_exit(struct sata_dwc_device *hsdev);
337static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
338 struct lli *lli, dma_addr_t dma_lli,
339 void __iomem *addr, int dir);
340static void dma_dwc_xfer_start(int dma_ch);
341
84b47e3b
SS		 342static const char *get_prot_descript(u8 protocol)
343{
344 switch ((enum ata_tf_protocols)protocol) {
345 case ATA_PROT_NODATA:
346 return "ATA no data";
347 case ATA_PROT_PIO:
348 return "ATA PIO";
349 case ATA_PROT_DMA:
350 return "ATA DMA";
351 case ATA_PROT_NCQ:
352 return "ATA NCQ";
353 case ATAPI_PROT_NODATA:
354 return "ATAPI no data";
355 case ATAPI_PROT_PIO:
356 return "ATAPI PIO";
357 case ATAPI_PROT_DMA:
358 return "ATAPI DMA";
359 default:
360 return "unknown";
361 }
362}
363
364static const char *get_dma_dir_descript(int dma_dir)
365{
366 switch ((enum dma_data_direction)dma_dir) {
367 case DMA_BIDIRECTIONAL:
368 return "bidirectional";
369 case DMA_TO_DEVICE:
370 return "to device";
371 case DMA_FROM_DEVICE:
372 return "from device";
373 default:
374 return "none";
375 }
376}
377
62936009
RS		 378static void sata_dwc_tf_dump(struct ata_taskfile *tf)
379{
380 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
84b47e3b
SS		 381 "0x%lx device: %x\n", tf->command,
382 get_prot_descript(tf->protocol), tf->flags, tf->device);
62936009
RS		 383 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
384 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
385 tf->lbam, tf->lbah);
386 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
387 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
388 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
389 tf->hob_lbah);
390}
391
392/*
393 * Function: get_burst_length_encode
394 * arguments: datalength: length in bytes of data
8618ccd3 395 * returns value to be programmed in register corresponding to data length
62936009
RS		 396 * This value is effectively the log(base 2) of the length
397 */
398static int get_burst_length_encode(int datalength)
399{
400 int items = datalength >> 2; /* div by 4 to get lword count */
401
402 if (items >= 64)
403 return 5;
404
405 if (items >= 32)
406 return 4;
407
408 if (items >= 16)
409 return 3;
410
411 if (items >= 8)
412 return 2;
413
414 if (items >= 4)
415 return 1;
416
417 return 0;
418}
419
420static void clear_chan_interrupts(int c)
421{
422 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
423 DMA_CHANNEL(c));
424 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
425 DMA_CHANNEL(c));
426 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
427 DMA_CHANNEL(c));
428 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
429 DMA_CHANNEL(c));
430 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
431 DMA_CHANNEL(c));
432}
433
434/*
435 * Function: dma_request_channel
436 * arguments: None
437 * returns channel number if available else -1
438 * This function assigns the next available DMA channel from the list to the
439 * requester
440 */
441static int dma_request_channel(void)
442{
dc7f71f4
TN		 443 /* Check if the channel is not currently in use */
444 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &
445 DMA_CHANNEL(host_pvt.dma_channel)))
446 return host_pvt.dma_channel;
447 dev_err(host_pvt.dwc_dev, "%s Channel %d is currently in use\n",
448 __func__, host_pvt.dma_channel);
62936009
RS		 449 return -1;
450}
451
452/*
453 * Function: dma_dwc_interrupt
454 * arguments: irq, dev_id, pt_regs
455 * returns channel number if available else -1
456 * Interrupt Handler for DW AHB SATA DMA
457 */
458static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
459{
460 int chan;
461 u32 tfr_reg, err_reg;
462 unsigned long flags;
463 struct sata_dwc_device *hsdev =
464 (struct sata_dwc_device *)hsdev_instance;
465 struct ata_host *host = (struct ata_host *)hsdev->host;
466 struct ata_port *ap;
467 struct sata_dwc_device_port *hsdevp;
468 u8 tag = 0;
469 unsigned int port = 0;
470
471 spin_lock_irqsave(&host->lock, flags);
472 ap = host->ports[port];
473 hsdevp = HSDEVP_FROM_AP(ap);
474 tag = ap->link.active_tag;
475
476 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
477 .low));
478 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
479 .low));
480
481 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
482 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
483
dc7f71f4
TN		 484 chan = host_pvt.dma_channel;
485 if (chan >= 0) {
62936009
RS		 486 /* Check for end-of-transfer interrupt. */
487 if (tfr_reg & DMA_CHANNEL(chan)) {
488 /*
489 * Each DMA command produces 2 interrupts. Only
490 * complete the command after both interrupts have been
491 * seen. (See sata_dwc_isr())
492 */
493 host_pvt.dma_interrupt_count++;
494 sata_dwc_clear_dmacr(hsdevp, tag);
495
496 if (hsdevp->dma_pending[tag] ==
497 SATA_DWC_DMA_PENDING_NONE) {
498 dev_err(ap->dev, "DMA not pending eot=0x%08x "
499 "err=0x%08x tag=0x%02x pending=%d\n",
500 tfr_reg, err_reg, tag,
501 hsdevp->dma_pending[tag]);
502 }
503
504 if ((host_pvt.dma_interrupt_count % 2) == 0)
505 sata_dwc_dma_xfer_complete(ap, 1);
506
507 /* Clear the interrupt */
508 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
509 .tfr.low),
510 DMA_CHANNEL(chan));
511 }
512
513 /* Check for error interrupt. */
514 if (err_reg & DMA_CHANNEL(chan)) {
515 /* TODO Need error handler ! */
516 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
517 err_reg);
518
519 /* Clear the interrupt. */
520 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
521 .error.low),
522 DMA_CHANNEL(chan));
523 }
524 }
525 spin_unlock_irqrestore(&host->lock, flags);
526 return IRQ_HANDLED;
527}
528
529/*
530 * Function: dma_request_interrupts
531 * arguments: hsdev
532 * returns status
533 * This function registers ISR for a particular DMA channel interrupt
534 */
535static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
536{
537 int retval = 0;
dc7f71f4 538 int chan = host_pvt.dma_channel;
62936009 539
dc7f71f4 540 if (chan >= 0) {
62936009
RS		 541 /* Unmask error interrupt */
542 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
543 DMA_ENABLE_CHAN(chan));
544
545 /* Unmask end-of-transfer interrupt */
546 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
547 DMA_ENABLE_CHAN(chan));
548 }
549
550 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
551 if (retval) {
552 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
553 __func__, irq);
554 return -ENODEV;
555 }
556
557 /* Mark this interrupt as requested */
558 hsdev->irq_dma = irq;
559 return 0;
560}
561
562/*
563 * Function: map_sg_to_lli
564 * The Synopsis driver has a comment proposing that better performance
565 * is possible by only enabling interrupts on the last item in the linked list.
566 * However, it seems that could be a problem if an error happened on one of the
567 * first items. The transfer would halt, but no error interrupt would occur.
568 * Currently this function sets interrupts enabled for each linked list item:
569 * DMA_CTL_INT_EN.
570 */
571static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
572 struct lli *lli, dma_addr_t dma_lli,
573 void __iomem *dmadr_addr, int dir)
574{
575 int i, idx = 0;
576 int fis_len = 0;
577 dma_addr_t next_llp;
578 int bl;
dc7f71f4 579 int sms_val, dms_val;
62936009 580
dc7f71f4
TN		 581 sms_val = 0;
582 dms_val = 1 + host_pvt.dma_channel;
62936009
RS		 583 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
584 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
585 (u32)dmadr_addr);
586
587 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
588
589 for (i = 0; i < num_elems; i++, sg++) {
590 u32 addr, offset;
591 u32 sg_len, len;
592
593 addr = (u32) sg_dma_address(sg);
594 sg_len = sg_dma_len(sg);
595
596 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
597 "=%d\n", __func__, i, addr, sg_len);
598
599 while (sg_len) {
600 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
601 /* The LLI table is not large enough. */
602 dev_err(host_pvt.dwc_dev, "LLI table overrun "
603 "(idx=%d)\n", idx);
604 break;
605 }
606 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
607 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
608
609 offset = addr & 0xffff;
610 if ((offset + sg_len) > 0x10000)
611 len = 0x10000 - offset;
612
613 /*
614 * Make sure a LLI block is not created that will span
615 * 8K max FIS boundary. If the block spans such a FIS
616 * boundary, there is a chance that a DMA burst will
617 * cross that boundary -- this results in an error in
618 * the host controller.
619 */
620 if (fis_len + len > 8192) {
621 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
622 "%d(0x%x) len=%d(0x%x)\n", fis_len,
623 fis_len, len, len);
624 len = 8192 - fis_len;
625 fis_len = 0;
626 } else {
627 fis_len += len;
628 }
629 if (fis_len == 8192)
630 fis_len = 0;
631
632 /*
633 * Set DMA addresses and lower half of control register
634 * based on direction.
635 */
636 if (dir == DMA_FROM_DEVICE) {
637 lli[idx].dar = cpu_to_le32(addr);
638 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
639
640 lli[idx].ctl.low = cpu_to_le32(
641 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
dc7f71f4
TN		 642 DMA_CTL_SMS(sms_val) |
643 DMA_CTL_DMS(dms_val) |
62936009
RS		 644 DMA_CTL_SRC_MSIZE(bl) |
645 DMA_CTL_DST_MSIZE(bl) |
646 DMA_CTL_SINC_NOCHANGE |
647 DMA_CTL_SRC_TRWID(2) |
648 DMA_CTL_DST_TRWID(2) |
649 DMA_CTL_INT_EN |
650 DMA_CTL_LLP_SRCEN |
651 DMA_CTL_LLP_DSTEN);
652 } else { /* DMA_TO_DEVICE */
653 lli[idx].sar = cpu_to_le32(addr);
654 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
655
656 lli[idx].ctl.low = cpu_to_le32(
657 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
dc7f71f4
TN		 658 DMA_CTL_SMS(dms_val) |
659 DMA_CTL_DMS(sms_val) |
62936009
RS		 660 DMA_CTL_SRC_MSIZE(bl) |
661 DMA_CTL_DST_MSIZE(bl) |
662 DMA_CTL_DINC_NOCHANGE |
663 DMA_CTL_SRC_TRWID(2) |
664 DMA_CTL_DST_TRWID(2) |
665 DMA_CTL_INT_EN |
666 DMA_CTL_LLP_SRCEN |
667 DMA_CTL_LLP_DSTEN);
668 }
669
670 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
671 "0x%08x val: 0x%08x\n", __func__,
672 len, DMA_CTL_BLK_TS(len / 4));
673
674 /* Program the LLI CTL high register */
675 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
676 (len / 4));
677
678 /* Program the next pointer. The next pointer must be
679 * the physical address, not the virtual address.
680 */
681 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
682 lli)));
683
684 /* The last 2 bits encode the list master select. */
685 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
686
687 lli[idx].llp = cpu_to_le32(next_llp);
688 idx++;
689 sg_len -= len;
690 addr += len;
691 }
692 }
693
694 /*
695 * The last next ptr has to be zero and the last control low register
696 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
697 * and destination enable) set back to 0 (disabled.) This is what tells
698 * the core that this is the last item in the linked list.
699 */
700 if (idx) {
701 lli[idx-1].llp = 0x00000000;
702 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
703
704 /* Flush cache to memory */
705 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
706 DMA_BIDIRECTIONAL);
707 }
708
709 return idx;
710}
711
712/*
713 * Function: dma_dwc_xfer_start
714 * arguments: Channel number
715 * Return : None
716 * Enables the DMA channel
717 */
718static void dma_dwc_xfer_start(int dma_ch)
719{
720 /* Enable the DMA channel */
721 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
722 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
723 DMA_ENABLE_CHAN(dma_ch));
724}
725
726static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
727 struct lli *lli, dma_addr_t dma_lli,
728 void __iomem *addr, int dir)
729{
730 int dma_ch;
731 int num_lli;
732 /* Acquire DMA channel */
733 dma_ch = dma_request_channel();
734 if (dma_ch == -1) {
735 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
736 __func__);
737 return -EAGAIN;
738 }
739
740 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
741 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
742
743 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
744 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
745 lli, (u32)dma_lli, addr, num_lli);
746
747 clear_chan_interrupts(dma_ch);
748
749 /* Program the CFG register. */
750 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
dc7f71f4 751 DMA_CFG_HW_HS_SRC(dma_ch) | DMA_CFG_HW_HS_DEST(dma_ch) |
62936009 752 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
dc7f71f4
TN		 753 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low),
754 DMA_CFG_HW_CH_PRIOR(dma_ch));
62936009
RS		 755
756 /* Program the address of the linked list */
757 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
758 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
759
760 /* Program the CTL register with src enable / dst enable */
761 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
762 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
d285e8bf 763 return dma_ch;
62936009
RS		 764}
765
766/*
767 * Function: dma_dwc_exit
768 * arguments: None
769 * returns status
770 * This function exits the SATA DMA driver
771 */
772static void dma_dwc_exit(struct sata_dwc_device *hsdev)
773{
774 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
04e506b5 775 if (host_pvt.sata_dma_regs) {
62936009 776 iounmap(host_pvt.sata_dma_regs);
04e506b5
VK		 777 host_pvt.sata_dma_regs = NULL;
778 }
62936009 779
04e506b5 780 if (hsdev->irq_dma) {
62936009 781 free_irq(hsdev->irq_dma, hsdev);
04e506b5
VK		 782 hsdev->irq_dma = 0;
783 }
62936009
RS		 784}
785
786/*
787 * Function: dma_dwc_init
788 * arguments: hsdev
789 * returns status
790 * This function initializes the SATA DMA driver
791 */
792static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
793{
794 int err;
795
796 err = dma_request_interrupts(hsdev, irq);
797 if (err) {
798 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
799 " %d\n", __func__, err);
800 goto error_out;
801 }
802
803 /* Enabe DMA */
804 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
805
806 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
807 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
808 sata_dma_regs);
809
810 return 0;
811
812error_out:
813 dma_dwc_exit(hsdev);
814
815 return err;
816}
817
818static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
819{
820 if (scr > SCR_NOTIFICATION) {
821 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
822 __func__, scr);
823 return -EINVAL;
824 }
825
826 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
827 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
828 __func__, link->ap->print_id, scr, *val);
829
830 return 0;
831}
832
833static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
834{
835 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
836 __func__, link->ap->print_id, scr, val);
837 if (scr > SCR_NOTIFICATION) {
838 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
839 __func__, scr);
840 return -EINVAL;
841 }
842 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
843
844 return 0;
845}
846
847static u32 core_scr_read(unsigned int scr)
848{
849 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
850 (scr * 4));
851}
852
853static void core_scr_write(unsigned int scr, u32 val)
854{
855 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
856 val);
857}
858
859static void clear_serror(void)
860{
861 u32 val;
862 val = core_scr_read(SCR_ERROR);
863 core_scr_write(SCR_ERROR, val);
864
865}
866
867static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
868{
869 out_le32(&hsdev->sata_dwc_regs->intpr,
870 in_le32(&hsdev->sata_dwc_regs->intpr));
871}
872
873static u32 qcmd_tag_to_mask(u8 tag)
874{
875 return 0x00000001 << (tag & 0x1f);
876}
877
878/* See ahci.c */
879static void sata_dwc_error_intr(struct ata_port *ap,
880 struct sata_dwc_device *hsdev, uint intpr)
881{
882 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
883 struct ata_eh_info *ehi = &ap->link.eh_info;
884 unsigned int err_mask = 0, action = 0;
885 struct ata_queued_cmd *qc;
886 u32 serror;
887 u8 status, tag;
888 u32 err_reg;
889
890 ata_ehi_clear_desc(ehi);
891
892 serror = core_scr_read(SCR_ERROR);
893 status = ap->ops->sff_check_status(ap);
894
895 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
896 low));
897 tag = ap->link.active_tag;
898
899 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
900 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
901 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
902 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
903
904 /* Clear error register and interrupt bit */
905 clear_serror();
906 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
907
908 /* This is the only error happening now. TODO check for exact error */
909
910 err_mask |= AC_ERR_HOST_BUS;
911 action |= ATA_EH_RESET;
912
913 /* Pass this on to EH */
914 ehi->serror |= serror;
915 ehi->action |= action;
916
917 qc = ata_qc_from_tag(ap, tag);
918 if (qc)
919 qc->err_mask |= err_mask;
920 else
921 ehi->err_mask |= err_mask;
922
923 ata_port_abort(ap);
924}
925
926/*
927 * Function : sata_dwc_isr
928 * arguments : irq, void *dev_instance, struct pt_regs *regs
929 * Return value : irqreturn_t - status of IRQ
930 * This Interrupt handler called via port ops registered function.
931 * .irq_handler = sata_dwc_isr
932 */
933static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
934{
935 struct ata_host *host = (struct ata_host *)dev_instance;
936 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
937 struct ata_port *ap;
938 struct ata_queued_cmd *qc;
939 unsigned long flags;
940 u8 status, tag;
941 int handled, num_processed, port = 0;
942 uint intpr, sactive, sactive2, tag_mask;
943 struct sata_dwc_device_port *hsdevp;
944 host_pvt.sata_dwc_sactive_issued = 0;
945
946 spin_lock_irqsave(&host->lock, flags);
947
948 /* Read the interrupt register */
949 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
950
951 ap = host->ports[port];
952 hsdevp = HSDEVP_FROM_AP(ap);
953
954 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
955 ap->link.active_tag);
956
957 /* Check for error interrupt */
958 if (intpr & SATA_DWC_INTPR_ERR) {
959 sata_dwc_error_intr(ap, hsdev, intpr);
960 handled = 1;
961 goto DONE;
962 }
963
964 /* Check for DMA SETUP FIS (FP DMA) interrupt */
965 if (intpr & SATA_DWC_INTPR_NEWFP) {
966 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
967
968 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
969 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
970 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
971 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
972
973 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
974
975 qc = ata_qc_from_tag(ap, tag);
976 /*
977 * Start FP DMA for NCQ command. At this point the tag is the
978 * active tag. It is the tag that matches the command about to
979 * be completed.
980 */
981 qc->ap->link.active_tag = tag;
982 sata_dwc_bmdma_start_by_tag(qc, tag);
983
984 handled = 1;
985 goto DONE;
986 }
987 sactive = core_scr_read(SCR_ACTIVE);
988 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
989
990 /* If no sactive issued and tag_mask is zero then this is not NCQ */
991 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
992 if (ap->link.active_tag == ATA_TAG_POISON)
993 tag = 0;
994 else
995 tag = ap->link.active_tag;
996 qc = ata_qc_from_tag(ap, tag);
997
998 /* DEV interrupt w/ no active qc? */
999 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
1000 dev_err(ap->dev, "%s interrupt with no active qc "
1001 "qc=%p\n", __func__, qc);
1002 ap->ops->sff_check_status(ap);
1003 handled = 1;
1004 goto DONE;
1005 }
1006 status = ap->ops->sff_check_status(ap);
1007
1008 qc->ap->link.active_tag = tag;
1009 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1010
1011 if (status & ATA_ERR) {
1012 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1013 sata_dwc_qc_complete(ap, qc, 1);
1014 handled = 1;
1015 goto DONE;
1016 }
1017
1018 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
84b47e3b 1019 __func__, get_prot_descript(qc->tf.protocol));
62936009
RS		 1020DRVSTILLBUSY:
1021 if (ata_is_dma(qc->tf.protocol)) {
1022 /*
1023 * Each DMA transaction produces 2 interrupts. The DMAC
1024 * transfer complete interrupt and the SATA controller
1025 * operation done interrupt. The command should be
1026 * completed only after both interrupts are seen.
1027 */
1028 host_pvt.dma_interrupt_count++;
1029 if (hsdevp->dma_pending[tag] == \
1030 SATA_DWC_DMA_PENDING_NONE) {
1031 dev_err(ap->dev, "%s: DMA not pending "
1032 "intpr=0x%08x status=0x%08x pending"
1033 "=%d\n", __func__, intpr, status,
1034 hsdevp->dma_pending[tag]);
1035 }
1036
1037 if ((host_pvt.dma_interrupt_count % 2) == 0)
1038 sata_dwc_dma_xfer_complete(ap, 1);
1039 } else if (ata_is_pio(qc->tf.protocol)) {
1040 ata_sff_hsm_move(ap, qc, status, 0);
1041 handled = 1;
1042 goto DONE;
1043 } else {
1044 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1045 goto DRVSTILLBUSY;
1046 }
1047
1048 handled = 1;
1049 goto DONE;
1050 }
1051
1052 /*
1053 * This is a NCQ command. At this point we need to figure out for which
1054 * tags we have gotten a completion interrupt. One interrupt may serve
1055 * as completion for more than one operation when commands are queued
1056 * (NCQ). We need to process each completed command.
1057 */
1058
1059 /* process completed commands */
1060 sactive = core_scr_read(SCR_ACTIVE);
1061 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1062
1063 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1064 tag_mask > 1) {
1065 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1066 "tag_mask=0x%08x\n", __func__, sactive,
1067 host_pvt.sata_dwc_sactive_issued, tag_mask);
1068 }
1069
1070 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1071 (host_pvt.sata_dwc_sactive_issued)) {
1072 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1073 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1074 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1075 tag_mask);
1076 }
1077
1078 /* read just to clear ... not bad if currently still busy */
1079 status = ap->ops->sff_check_status(ap);
1080 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1081
1082 tag = 0;
1083 num_processed = 0;
1084 while (tag_mask) {
1085 num_processed++;
1086 while (!(tag_mask & 0x00000001)) {
1087 tag++;
1088 tag_mask <<= 1;
1089 }
1090
1091 tag_mask &= (~0x00000001);
1092 qc = ata_qc_from_tag(ap, tag);
1093
1094 /* To be picked up by completion functions */
1095 qc->ap->link.active_tag = tag;
1096 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1097
1098 /* Let libata/scsi layers handle error */
1099 if (status & ATA_ERR) {
1100 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1101 status);
1102 sata_dwc_qc_complete(ap, qc, 1);
1103 handled = 1;
1104 goto DONE;
1105 }
1106
1107 /* Process completed command */
1108 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
84b47e3b 1109 get_prot_descript(qc->tf.protocol));
62936009
RS		 1110 if (ata_is_dma(qc->tf.protocol)) {
1111 host_pvt.dma_interrupt_count++;
1112 if (hsdevp->dma_pending[tag] == \
1113 SATA_DWC_DMA_PENDING_NONE)
1114 dev_warn(ap->dev, "%s: DMA not pending?\n",
1115 __func__);
1116 if ((host_pvt.dma_interrupt_count % 2) == 0)
1117 sata_dwc_dma_xfer_complete(ap, 1);
1118 } else {
1119 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1120 goto STILLBUSY;
1121 }
1122 continue;
1123
1124STILLBUSY:
1125 ap->stats.idle_irq++;
1126 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1127 ap->print_id);
1128 } /* while tag_mask */
1129
1130 /*
1131 * Check to see if any commands completed while we were processing our
1132 * initial set of completed commands (read status clears interrupts,
1133 * so we might miss a completed command interrupt if one came in while
1134 * we were processing --we read status as part of processing a completed
1135 * command).
1136 */
1137 sactive2 = core_scr_read(SCR_ACTIVE);
1138 if (sactive2 != sactive) {
1139 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1140 "=0x%x\n", sactive, sactive2);
1141 }
1142 handled = 1;
1143
1144DONE:
1145 spin_unlock_irqrestore(&host->lock, flags);
1146 return IRQ_RETVAL(handled);
1147}
1148
1149static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1150{
1151 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1152
1153 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1154 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1155 SATA_DWC_DMACR_RX_CLEAR(
1156 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1157 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1158 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1159 SATA_DWC_DMACR_TX_CLEAR(
1160 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1161 } else {
1162 /*
1163 * This should not happen, it indicates the driver is out of
1164 * sync. If it does happen, clear dmacr anyway.
1165 */
1166 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1167 "TX DMA not pending tag=0x%02x pending=%d"
1168 " dmacr: 0x%08x\n", __func__, tag,
1169 hsdevp->dma_pending[tag],
1170 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1171 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1172 SATA_DWC_DMACR_TXRXCH_CLEAR);
1173 }
1174}
1175
1176static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1177{
1178 struct ata_queued_cmd *qc;
1179 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1180 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1181 u8 tag = 0;
1182
1183 tag = ap->link.active_tag;
1184 qc = ata_qc_from_tag(ap, tag);
1185 if (!qc) {
1186 dev_err(ap->dev, "failed to get qc");
1187 return;
1188 }
1189
1190#ifdef DEBUG_NCQ
1191 if (tag > 0) {
1192 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1193 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
84b47e3b
SS		 1194 get_dma_dir_descript(qc->dma_dir),
1195 get_prot_descript(qc->tf.protocol),
62936009
RS		 1196 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1197 }
1198#endif
1199
1200 if (ata_is_dma(qc->tf.protocol)) {
1201 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1202 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1203 "pending dmacr: 0x%08x\n", __func__,
1204 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1205 }
1206
1207 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1208 sata_dwc_qc_complete(ap, qc, check_status);
1209 ap->link.active_tag = ATA_TAG_POISON;
1210 } else {
1211 sata_dwc_qc_complete(ap, qc, check_status);
1212 }
1213}
1214
1215static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1216 u32 check_status)
1217{
1218 u8 status = 0;
1219 u32 mask = 0x0;
1220 u8 tag = qc->tag;
1221 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1222 host_pvt.sata_dwc_sactive_queued = 0;
1223 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1224
1225 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1226 dev_err(ap->dev, "TX DMA PENDING\n");
1227 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1228 dev_err(ap->dev, "RX DMA PENDING\n");
1229 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1230 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1231 qc->tf.protocol);
1232
1233 /* clear active bit */
1234 mask = (~(qcmd_tag_to_mask(tag)));
1235 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1236 & mask;
1237 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1238 & mask;
1239 ata_qc_complete(qc);
1240 return 0;
1241}
1242
1243static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1244{
1245 /* Enable selective interrupts by setting the interrupt maskregister*/
1246 out_le32(&hsdev->sata_dwc_regs->intmr,
1247 SATA_DWC_INTMR_ERRM |
1248 SATA_DWC_INTMR_NEWFPM |
1249 SATA_DWC_INTMR_PMABRTM |
1250 SATA_DWC_INTMR_DMATM);
1251 /*
1252 * Unmask the error bits that should trigger an error interrupt by
1253 * setting the error mask register.
1254 */
1255 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1256
1257 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1258 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1259 in_le32(&hsdev->sata_dwc_regs->errmr));
1260}
1261
1262static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1263{
1264 port->cmd_addr = (void *)base + 0x00;
1265 port->data_addr = (void *)base + 0x00;
1266
1267 port->error_addr = (void *)base + 0x04;
1268 port->feature_addr = (void *)base + 0x04;
1269
1270 port->nsect_addr = (void *)base + 0x08;
1271
1272 port->lbal_addr = (void *)base + 0x0c;
1273 port->lbam_addr = (void *)base + 0x10;
1274 port->lbah_addr = (void *)base + 0x14;
1275
1276 port->device_addr = (void *)base + 0x18;
1277 port->command_addr = (void *)base + 0x1c;
1278 port->status_addr = (void *)base + 0x1c;
1279
1280 port->altstatus_addr = (void *)base + 0x20;
1281 port->ctl_addr = (void *)base + 0x20;
1282}
1283
1284/*
1285 * Function : sata_dwc_port_start
1286 * arguments : struct ata_ioports *port
1287 * Return value : returns 0 if success, error code otherwise
1288 * This function allocates the scatter gather LLI table for AHB DMA
1289 */
1290static int sata_dwc_port_start(struct ata_port *ap)
1291{
1292 int err = 0;
1293 struct sata_dwc_device *hsdev;
1294 struct sata_dwc_device_port *hsdevp = NULL;
1295 struct device *pdev;
1296 int i;
1297
1298 hsdev = HSDEV_FROM_AP(ap);
1299
1300 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1301
1302 hsdev->host = ap->host;
1303 pdev = ap->host->dev;
1304 if (!pdev) {
1305 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1306 err = -ENODEV;
1307 goto CLEANUP;
1308 }
1309
1310 /* Allocate Port Struct */
1311 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1312 if (!hsdevp) {
1313 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1314 err = -ENOMEM;
1315 goto CLEANUP;
1316 }
1317 hsdevp->hsdev = hsdev;
1318
1319 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1320 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1321
1322 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1323 ap->bmdma_prd_dma = 0;
1324
1325 /*
1326 * DMA - Assign scatter gather LLI table. We can't use the libata
1327 * version since it's PRD is IDE PCI specific.
1328 */
1329 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1330 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1331 SATA_DWC_DMAC_LLI_TBL_SZ,
1332 &(hsdevp->llit_dma[i]),
1333 GFP_ATOMIC);
1334 if (!hsdevp->llit[i]) {
1335 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1336 __func__);
1337 err = -ENOMEM;
a081da63 1338 goto CLEANUP_ALLOC;
62936009
RS		 1339 }
1340 }
1341
1342 if (ap->port_no == 0) {
1343 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1344 __func__);
1345 out_le32(&hsdev->sata_dwc_regs->dmacr,
1346 SATA_DWC_DMACR_TXRXCH_CLEAR);
1347
1348 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1349 __func__);
1350 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1351 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1352 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1353 }
1354
1355 /* Clear any error bits before libata starts issuing commands */
1356 clear_serror();
1357 ap->private_data = hsdevp;
a081da63
JL		 1358 dev_dbg(ap->dev, "%s: done\n", __func__);
1359 return 0;
62936009 1360
a081da63
JL		 1361CLEANUP_ALLOC:
1362 kfree(hsdevp);
62936009 1363CLEANUP:
a081da63 1364 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
62936009
RS		 1365 return err;
1366}
1367
1368static void sata_dwc_port_stop(struct ata_port *ap)
1369{
1370 int i;
1371 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1372 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1373
1374 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1375
1376 if (hsdevp && hsdev) {
1377 /* deallocate LLI table */
1378 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1379 dma_free_coherent(ap->host->dev,
1380 SATA_DWC_DMAC_LLI_TBL_SZ,
1381 hsdevp->llit[i], hsdevp->llit_dma[i]);
1382 }
1383
1384 kfree(hsdevp);
1385 }
1386 ap->private_data = NULL;
1387}
1388
1389/*
1390 * Function : sata_dwc_exec_command_by_tag
1391 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1392 * Return value : None
1393 * This function keeps track of individual command tag ids and calls
1394 * ata_exec_command in libata
1395 */
1396static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1397 struct ata_taskfile *tf,
1398 u8 tag, u32 cmd_issued)
1399{
1400 unsigned long flags;
1401 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1402
1403 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
c211962d 1404 ata_get_cmd_descript(tf->command), tag);
62936009
RS		 1405
1406 spin_lock_irqsave(&ap->host->lock, flags);
1407 hsdevp->cmd_issued[tag] = cmd_issued;
1408 spin_unlock_irqrestore(&ap->host->lock, flags);
1409 /*
1410 * Clear SError before executing a new command.
1411 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1412 * managed SError register for the disk needs to be done before the
1413 * task file is loaded.
1414 */
1415 clear_serror();
1416 ata_sff_exec_command(ap, tf);
1417}
1418
1419static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1420{
1421 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1422 SATA_DWC_CMD_ISSUED_PEND);
1423}
1424
1425static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1426{
1427 u8 tag = qc->tag;
1428
1429 if (ata_is_ncq(qc->tf.protocol)) {
1430 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1431 __func__, qc->ap->link.sactive, tag);
1432 } else {
1433 tag = 0;
1434 }
1435 sata_dwc_bmdma_setup_by_tag(qc, tag);
1436}
1437
1438static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1439{
1440 int start_dma;
1441 u32 reg, dma_chan;
1442 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1443 struct ata_port *ap = qc->ap;
1444 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1445 int dir = qc->dma_dir;
1446 dma_chan = hsdevp->dma_chan[tag];
1447
1448 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1449 start_dma = 1;
1450 if (dir == DMA_TO_DEVICE)
1451 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1452 else
1453 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1454 } else {
1455 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1456 "(tag=%d) DMA NOT started\n", __func__,
1457 hsdevp->cmd_issued[tag], tag);
1458 start_dma = 0;
1459 }
1460
1461 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1462 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
84b47e3b 1463 get_dma_dir_descript(qc->dma_dir), start_dma);
62936009
RS		 1464 sata_dwc_tf_dump(&(qc->tf));
1465
1466 if (start_dma) {
1467 reg = core_scr_read(SCR_ERROR);
1468 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1469 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1470 __func__, reg);
1471 }
1472
1473 if (dir == DMA_TO_DEVICE)
1474 out_le32(&hsdev->sata_dwc_regs->dmacr,
1475 SATA_DWC_DMACR_TXCHEN);
1476 else
1477 out_le32(&hsdev->sata_dwc_regs->dmacr,
1478 SATA_DWC_DMACR_RXCHEN);
1479
1480 /* Enable AHB DMA transfer on the specified channel */
1481 dma_dwc_xfer_start(dma_chan);
1482 }
1483}
1484
1485static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1486{
1487 u8 tag = qc->tag;
1488
1489 if (ata_is_ncq(qc->tf.protocol)) {
1490 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1491 __func__, qc->ap->link.sactive, tag);
1492 } else {
1493 tag = 0;
1494 }
1495 dev_dbg(qc->ap->dev, "%s\n", __func__);
1496 sata_dwc_bmdma_start_by_tag(qc, tag);
1497}
1498
1499/*
1500 * Function : sata_dwc_qc_prep_by_tag
1501 * arguments : ata_queued_cmd *qc, u8 tag
1502 * Return value : None
1503 * qc_prep for a particular queued command based on tag
1504 */
1505static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1506{
1507 struct scatterlist *sg = qc->sg;
1508 struct ata_port *ap = qc->ap;
d26377b8 1509 int dma_chan;
62936009
RS		 1510 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1511 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
62936009
RS		 1512
1513 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
84b47e3b 1514 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
62936009
RS		 1515 qc->n_elem);
1516
1517 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1518 hsdevp->llit_dma[tag],
1519 (void *__iomem)(&hsdev->sata_dwc_regs->\
1520 dmadr), qc->dma_dir);
1521 if (dma_chan < 0) {
1522 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
c211962d 1523 __func__, dma_chan);
62936009
RS		 1524 return;
1525 }
1526 hsdevp->dma_chan[tag] = dma_chan;
1527}
1528
1529static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1530{
1531 u32 sactive;
1532 u8 tag = qc->tag;
1533 struct ata_port *ap = qc->ap;
1534
1535#ifdef DEBUG_NCQ
1536 if (qc->tag > 0 || ap->link.sactive > 1)
1537 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1538 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1539 __func__, ap->print_id, qc->tf.command,
c211962d 1540 ata_get_cmd_descript(qc->tf.command),
84b47e3b 1541 qc->tag, get_prot_descript(qc->tf.protocol),
62936009
RS		 1542 ap->link.active_tag, ap->link.sactive);
1543#endif
1544
1545 if (!ata_is_ncq(qc->tf.protocol))
1546 tag = 0;
1547 sata_dwc_qc_prep_by_tag(qc, tag);
1548
1549 if (ata_is_ncq(qc->tf.protocol)) {
1550 sactive = core_scr_read(SCR_ACTIVE);
1551 sactive |= (0x00000001 << tag);
1552 core_scr_write(SCR_ACTIVE, sactive);
1553
1554 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1555 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1556 sactive);
1557
1558 ap->ops->sff_tf_load(ap, &qc->tf);
1559 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1560 SATA_DWC_CMD_ISSUED_PEND);
1561 } else {
1562 ata_sff_qc_issue(qc);
1563 }
1564 return 0;
1565}
1566
1567/*
1568 * Function : sata_dwc_qc_prep
1569 * arguments : ata_queued_cmd *qc
1570 * Return value : None
1571 * qc_prep for a particular queued command
1572 */
1573
1574static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1575{
1576 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1577 return;
1578
1579#ifdef DEBUG_NCQ
1580 if (qc->tag > 0)
1581 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
c211962d 1582 __func__, qc->tag, qc->ap->link.active_tag);
62936009
RS		 1583
1584 return ;
1585#endif
1586}
1587
1588static void sata_dwc_error_handler(struct ata_port *ap)
1589{
62936009
RS		 1590 ata_sff_error_handler(ap);
1591}
1592
3a8b788f
TN		 1593int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1594 unsigned long deadline)
1595{
1596 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1597 int ret;
1598
1599 ret = sata_sff_hardreset(link, class, deadline);
1600
1601 sata_dwc_enable_interrupts(hsdev);
1602
1603 /* Reconfigure the DMA control register */
1604 out_le32(&hsdev->sata_dwc_regs->dmacr,
1605 SATA_DWC_DMACR_TXRXCH_CLEAR);
1606
1607 /* Reconfigure the DMA Burst Transaction Size register */
1608 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1609 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1610 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1611
1612 return ret;
1613}
1614
62936009
RS		 1615/*
1616 * scsi mid-layer and libata interface structures
1617 */
1618static struct scsi_host_template sata_dwc_sht = {
1619 ATA_NCQ_SHT(DRV_NAME),
1620 /*
1621 * test-only: Currently this driver doesn't handle NCQ
1622 * correctly. We enable NCQ but set the queue depth to a
1623 * max of 1. This will get fixed in in a future release.
1624 */
1625 .sg_tablesize = LIBATA_MAX_PRD,
1626 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1627 .dma_boundary = ATA_DMA_BOUNDARY,
1628};
1629
1630static struct ata_port_operations sata_dwc_ops = {
1631 .inherits = &ata_sff_port_ops,
1632
1633 .error_handler = sata_dwc_error_handler,
3a8b788f 1634 .hardreset = sata_dwc_hardreset,
62936009
RS		 1635
1636 .qc_prep = sata_dwc_qc_prep,
1637 .qc_issue = sata_dwc_qc_issue,
1638
1639 .scr_read = sata_dwc_scr_read,
1640 .scr_write = sata_dwc_scr_write,
1641
1642 .port_start = sata_dwc_port_start,
1643 .port_stop = sata_dwc_port_stop,
1644
1645 .bmdma_setup = sata_dwc_bmdma_setup,
1646 .bmdma_start = sata_dwc_bmdma_start,
1647};
1648
1649static const struct ata_port_info sata_dwc_port_info[] = {
1650 {
9cbe056f 1651 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
b83a4c39 1652 .pio_mask = ATA_PIO4,
62936009
RS		 1653 .udma_mask = ATA_UDMA6,
1654 .port_ops = &sata_dwc_ops,
1655 },
1656};
1657
1c48a5c9 1658static int sata_dwc_probe(struct platform_device *ofdev)
62936009
RS		 1659{
1660 struct sata_dwc_device *hsdev;
1661 u32 idr, versionr;
1662 char *ver = (char *)&versionr;
1663 u8 *base = NULL;
1664 int err = 0;
1665 int irq, rc;
1666 struct ata_host *host;
1667 struct ata_port_info pi = sata_dwc_port_info[0];
1668 const struct ata_port_info *ppi[] = { &pi, NULL };
dc7f71f4
TN		 1669 struct device_node *np = ofdev->dev.of_node;
1670 u32 dma_chan;
62936009
RS		 1671
1672 /* Allocate DWC SATA device */
f35119d6 1673 hsdev = kzalloc(sizeof(*hsdev), GFP_KERNEL);
62936009
RS		 1674 if (hsdev == NULL) {
1675 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1676 err = -ENOMEM;
04e506b5 1677 goto error;
62936009 1678 }
62936009 1679
dc7f71f4
TN		 1680 if (of_property_read_u32(np, "dma-channel", &dma_chan)) {
1681 dev_warn(&ofdev->dev, "no dma-channel property set."
1682 " Use channel 0\n");
1683 dma_chan = 0;
1684 }
1685 host_pvt.dma_channel = dma_chan;
1686
62936009
RS		 1687 /* Ioremap SATA registers */
1688 base = of_iomap(ofdev->dev.of_node, 0);
1689 if (!base) {
1690 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1691 " address\n");
1692 err = -ENODEV;
04e506b5 1693 goto error_kmalloc;
62936009
RS		 1694 }
1695 hsdev->reg_base = base;
1696 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1697
1698 /* Synopsys DWC SATA specific Registers */
1699 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1700
1701 /* Allocate and fill host */
1702 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1703 if (!host) {
1704 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1705 err = -ENOMEM;
04e506b5 1706 goto error_iomap;
62936009
RS		 1707 }
1708
1709 host->private_data = hsdev;
1710
1711 /* Setup port */
1712 host->ports[0]->ioaddr.cmd_addr = base;
1713 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1714 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1715 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1716
1717 /* Read the ID and Version Registers */
1718 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1719 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1720 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1721 idr, ver[0], ver[1], ver[2]);
1722
1723 /* Get SATA DMA interrupt number */
1724 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1725 if (irq == NO_IRQ) {
1726 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1727 err = -ENODEV;
1728 goto error_out;
1729 }
1730
1731 /* Get physical SATA DMA register base address */
1732 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1733 if (!(host_pvt.sata_dma_regs)) {
1734 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1735 " address\n");
1736 err = -ENODEV;
1737 goto error_out;
1738 }
1739
1740 /* Save dev for later use in dev_xxx() routines */
1741 host_pvt.dwc_dev = &ofdev->dev;
1742
1743 /* Initialize AHB DMAC */
1744 dma_dwc_init(hsdev, irq);
1745
1746 /* Enable SATA Interrupts */
1747 sata_dwc_enable_interrupts(hsdev);
1748
1749 /* Get SATA interrupt number */
1750 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1751 if (irq == NO_IRQ) {
1752 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1753 err = -ENODEV;
1754 goto error_out;
1755 }
1756
1757 /*
1758 * Now, register with libATA core, this will also initiate the
1759 * device discovery process, invoking our port_start() handler &
1760 * error_handler() to execute a dummy Softreset EH session
1761 */
1762 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1763
1764 if (rc != 0)
1765 dev_err(&ofdev->dev, "failed to activate host");
1766
1767 dev_set_drvdata(&ofdev->dev, host);
1768 return 0;
1769
1770error_out:
1771 /* Free SATA DMA resources */
1772 dma_dwc_exit(hsdev);
1773
04e506b5
VK		 1774error_iomap:
1775 iounmap(base);
1776error_kmalloc:
1777 kfree(hsdev);
1778error:
62936009
RS		 1779 return err;
1780}
1781
60652d07 1782static int sata_dwc_remove(struct platform_device *ofdev)
62936009
RS		 1783{
1784 struct device *dev = &ofdev->dev;
1785 struct ata_host *host = dev_get_drvdata(dev);
1786 struct sata_dwc_device *hsdev = host->private_data;
1787
1788 ata_host_detach(host);
1789 dev_set_drvdata(dev, NULL);
1790
1791 /* Free SATA DMA resources */
1792 dma_dwc_exit(hsdev);
1793
1794 iounmap(hsdev->reg_base);
1795 kfree(hsdev);
1796 kfree(host);
1797 dev_dbg(&ofdev->dev, "done\n");
1798 return 0;
1799}
1800
1801static const struct of_device_id sata_dwc_match[] = {
1802 { .compatible = "amcc,sata-460ex", },
1803 {}
1804};
1805MODULE_DEVICE_TABLE(of, sata_dwc_match);
1806
1c48a5c9 1807static struct platform_driver sata_dwc_driver = {
62936009
RS		 1808 .driver = {
1809 .name = DRV_NAME,
1810 .owner = THIS_MODULE,
1811 .of_match_table = sata_dwc_match,
1812 },
1813 .probe = sata_dwc_probe,
1814 .remove = sata_dwc_remove,
1815};
1816
99c8ea3e 1817module_platform_driver(sata_dwc_driver);
62936009
RS		 1818
1819MODULE_LICENSE("GPL");
1820MODULE_AUTHOR("Mark Miesfeld <[email protected]>");
1821MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1822MODULE_VERSION(DRV_VERSION);
Empty description
This page took 0.519455 seconds and 4 git commands to generate.