[linux.git] / drivers / ide / cs5535.c

/*
 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
 * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
 *
 * History:
 * 09/20/2005 - Jaya Kumar <[email protected]>
 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
 * - Work was sponsored by CIS (M) Sdn Bhd.
 * Ported to Kernel 2.6.11 on June 26, 2005 by
 *   Wolfgang Zuleger <[email protected]>
 *   Alexander Kiausch <[email protected]>
 * Originally developed by AMD for 2.4/2.6
 *
 * Development of this chipset driver was funded
 * by the nice folks at National Semiconductor/AMD.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * Documentation:
 *  CS5535 documentation available from AMD
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/ide.h>

#define DRV_NAME "cs5535"

#define MSR_ATAC_BASE		0x51300000
#define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
#define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
#define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
#define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
#define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
#define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
#define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
#define ATAC_RESET		(MSR_ATAC_BASE+0x10)
#define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
#define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
#define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
#define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
#define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
#define ATAC_BM0_CMD_PRIM	0x00
#define ATAC_BM0_STS_PRIM	0x02
#define ATAC_BM0_PRD		0x04
#define CS5535_CABLE_DETECT	0x48

/* Format I PIO settings. We separate out cmd and data for safer timings */

static unsigned int cs5535_pio_cmd_timings[5] =
{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
static unsigned int cs5535_pio_dta_timings[5] =
{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };

static unsigned int cs5535_mwdma_timings[3] =
{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };

static unsigned int cs5535_udma_timings[5] =
{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };

/* Macros to check if the register is the reset value -  reset value is an
   invalid timing and indicates the register has not been set previously */

#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )

/****
 *	cs5535_set_speed         -     Configure the chipset to the new speed
 *	@drive: Drive to set up
 *	@speed: desired speed
 *
 *	cs5535_set_speed() configures the chipset to a new speed.
 */
static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
{
	u32 reg = 0, dummy;
	u8 unit = drive->dn & 1;

	/* Set the PIO timings */
	if (speed < XFER_SW_DMA_0) {
		ide_drive_t *pair = ide_get_pair_dev(drive);
		u8 cmd, pioa;

		cmd = pioa = speed - XFER_PIO_0;

		if (pair) {
			u8 piob = pair->pio_mode - XFER_PIO_0;

			if (piob < cmd)
				cmd = piob;
		}

		/* Write the speed of the current drive */
		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
			cs5535_pio_dta_timings[pioa];
		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);

		/* And if nessesary - change the speed of the other drive */
		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);

		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
			cs5535_pio_cmd_timings[cmd]) {
			reg &= 0x0000FFFF;
			reg |= cs5535_pio_cmd_timings[cmd] << 16;
			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
		}

		/* Set bit 31 of the DMA register for PIO format 1 timings */
		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
					reg | 0x80000000UL, 0);
	} else {
		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);

		reg &= 0x80000000UL;  /* Preserve the PIO format bit */

		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
		else
			return;

		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	}
}

/**
 *	cs5535_set_dma_mode	-	set host controller for DMA mode
 *	@hwif: port
 *	@drive: drive
 *
 *	Programs the chipset for DMA mode.
 */

static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	cs5535_set_speed(drive, drive->dma_mode);
}

/**
 *	cs5535_set_pio_mode	-	set host controller for PIO mode
 *	@hwif: port
 *	@drive: drive
 *
 *	A callback from the upper layers for PIO-only tuning.
 */

static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
{
	cs5535_set_speed(drive, drive->pio_mode);
}

static u8 cs5535_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	u8 bit;

	/* if a 80 wire cable was detected */
	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);

	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
}

static const struct ide_port_ops cs5535_port_ops = {
	.set_pio_mode		= cs5535_set_pio_mode,
	.set_dma_mode		= cs5535_set_dma_mode,
	.cable_detect		= cs5535_cable_detect,
};

static const struct ide_port_info cs5535_chipset = {
	.name		= DRV_NAME,
	.port_ops	= &cs5535_port_ops,
	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA4,
};

static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
}

static const struct pci_device_id cs5535_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
	{ 0, },
};

MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);

static struct pci_driver cs5535_pci_driver = {
	.name		= "CS5535_IDE",
	.id_table	= cs5535_pci_tbl,
	.probe		= cs5535_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init cs5535_ide_init(void)
{
	return ide_pci_register_driver(&cs5535_pci_driver);
}

static void __exit cs5535_ide_exit(void)
{
	pci_unregister_driver(&cs5535_pci_driver);
}

module_init(cs5535_ide_init);
module_exit(cs5535_ide_exit);

MODULE_AUTHOR("AMD");
MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
f5b2d8b4	1	/*
f5b2d8b4	2	* Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
bc0b0b5c	3	* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
f5b2d8b4 JK	4	*
	5	* History:
	6	* 09/20/2005 - Jaya Kumar <[email protected]>
	7	* - Reworked tuneproc, set_drive, misc mods to prep for mainline
	8	* - Work was sponsored by CIS (M) Sdn Bhd.
	9	* Ported to Kernel 2.6.11 on June 26, 2005 by
	10	* Wolfgang Zuleger <[email protected]>
	11	* Alexander Kiausch <[email protected]>
	12	* Originally developed by AMD for 2.4/2.6
	13	*
	14	* Development of this chipset driver was funded
	15	* by the nice folks at National Semiconductor/AMD.
	16	*
	17	* This program is free software; you can redistribute it and/or modify it
	18	* under the terms of the GNU General Public License version 2 as published by
	19	* the Free Software Foundation.
	20	*
	21	* Documentation:
	22	* CS5535 documentation available from AMD
	23	*/
	24
f5b2d8b4 JK	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/ide.h>
	28
ced3ec8a BZ	29	#define DRV_NAME "cs5535"
ced3ec8a BZ	30
f5b2d8b4 JK	31	#define MSR_ATAC_BASE 0x51300000
	32	#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
	33	#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
	34	#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
	35	#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
	36	#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
	37	#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
	38	#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
	39	#define ATAC_RESET (MSR_ATAC_BASE+0x10)
	40	#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
	41	#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
	42	#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
	43	#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
	44	#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
	45	#define ATAC_BM0_CMD_PRIM 0x00
	46	#define ATAC_BM0_STS_PRIM 0x02
	47	#define ATAC_BM0_PRD 0x04
	48	#define CS5535_CABLE_DETECT 0x48
	49
a1c6d28c	50	/* Format I PIO settings. We separate out cmd and data for safer timings */
f5b2d8b4 JK	51
	52	static unsigned int cs5535_pio_cmd_timings[5] =
	53	{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
	54	static unsigned int cs5535_pio_dta_timings[5] =
	55	{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
	56
	57	static unsigned int cs5535_mwdma_timings[3] =
	58	{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
	59
	60	static unsigned int cs5535_udma_timings[5] =
	61	{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
	62
	63	/* Macros to check if the register is the reset value - reset value is an
	64	invalid timing and indicates the register has not been set previously */
	65
	66	#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
	67	#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
	68
	69	/****
	70	* cs5535_set_speed - Configure the chipset to the new speed
	71	* @drive: Drive to set up
	72	* @speed: desired speed
	73	*
	74	* cs5535_set_speed() configures the chipset to a new speed.
	75	*/
f212ff28	76	static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
f5b2d8b4	77	{
f5b2d8b4	78	u32 reg = 0, dummy;
123995b9	79	u8 unit = drive->dn & 1;
f5b2d8b4	80
f5b2d8b4	81	/* Set the PIO timings */
bd887f72	82	if (speed < XFER_SW_DMA_0) {
7e59ea21	83	ide_drive_t *pair = ide_get_pair_dev(drive);
bc0b0b5c	84	u8 cmd, pioa;
f5b2d8b4	85
bc0b0b5c BZ	86	cmd = pioa = speed - XFER_PIO_0;
bc0b0b5c BZ	87
7e59ea21	88	if (pair) {
a298dc02	89	u8 piob = pair->pio_mode - XFER_PIO_0;
bc0b0b5c BZ	90
	91	if (piob < cmd)
	92	cmd = piob;
	93	}
f5b2d8b4 JK	94
	95	/* Write the speed of the current drive */
	96	reg = (cs5535_pio_cmd_timings[cmd] << 16) \|
	97	cs5535_pio_dta_timings[pioa];
	98	wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
	99
	100	/* And if nessesary - change the speed of the other drive */
	101	rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
	102
	103	if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
	104	cs5535_pio_cmd_timings[cmd]) {
	105	reg &= 0x0000FFFF;
	106	reg \|= cs5535_pio_cmd_timings[cmd] << 16;
	107	wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
	108	}
	109
	110	/* Set bit 31 of the DMA register for PIO format 1 timings */
	111	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	112	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
	113	reg \| 0x80000000UL, 0);
	114	} else {
	115	rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
	116
	117	reg &= 0x80000000UL; /* Preserve the PIO format bit */
	118
32a70a81	119	if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
f5b2d8b4 JK	120	reg \|= cs5535_udma_timings[speed - XFER_UDMA_0];
	121	else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
	122	reg \|= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
	123	else
	124	return;
	125
	126	wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
	127	}
	128	}
	129
88b2b32b BZ	130	/**
88b2b32b BZ	131	* cs5535_set_dma_mode - set host controller for DMA mode
8776168c	132	* @hwif: port
88b2b32b	133	* @drive: drive
f5b2d8b4	134	*
88b2b32b	135	* Programs the chipset for DMA mode.
f5b2d8b4	136	*/
249aa4ff	137
8776168c	138	static void cs5535_set_dma_mode(ide_hwif_t hwif, ide_drive_t drive)
88b2b32b	139	{
8776168c	140	cs5535_set_speed(drive, drive->dma_mode);
f5b2d8b4 JK	141	}
f5b2d8b4 JK	142
26bcb879	143	/**
88b2b32b	144	* cs5535_set_pio_mode - set host controller for PIO mode
e085b3ca	145	* @hwif: port
26bcb879	146	* @drive: drive
f5b2d8b4 JK	147	*
	148	* A callback from the upper layers for PIO-only tuning.
	149	*/
26bcb879	150
e085b3ca	151	static void cs5535_set_pio_mode(ide_hwif_t hwif, ide_drive_t drive)
f5b2d8b4	152	{
e085b3ca	153	cs5535_set_speed(drive, drive->pio_mode);
f5b2d8b4 JK	154	}
f5b2d8b4 JK	155
f454cbe8	156	static u8 cs5535_cable_detect(ide_hwif_t *hwif)
f5b2d8b4	157	{
b4d1c73d	158	struct pci_dev *dev = to_pci_dev(hwif->dev);
f5b2d8b4 JK	159	u8 bit;
	160
	161	/* if a 80 wire cable was detected */
	162	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
49521f97 BZ	163
49521f97 BZ	164	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
f5b2d8b4 JK	165	}
f5b2d8b4 JK	166
ac95beed BZ	167	static const struct ide_port_ops cs5535_port_ops = {
	168	.set_pio_mode = cs5535_set_pio_mode,
	169	.set_dma_mode = cs5535_set_dma_mode,
	170	.cable_detect = cs5535_cable_detect,
	171	};
f5b2d8b4	172
fe31edc8	173	static const struct ide_port_info cs5535_chipset = {
ced3ec8a	174	.name = DRV_NAME,
ac95beed	175	.port_ops = &cs5535_port_ops,
3b2a5c71	176	.host_flags = IDE_HFLAG_SINGLE \| IDE_HFLAG_POST_SET_MODE,
4099d143	177	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	178	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	179	.udma_mask = ATA_UDMA4,
f5b2d8b4 JK	180	};
f5b2d8b4 JK	181
fe31edc8	182	static int cs5535_init_one(struct pci_dev dev, const struct pci_device_id id)
f5b2d8b4	183	{
6cdf6eb3	184	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
f5b2d8b4 JK	185	}
f5b2d8b4 JK	186
9cbcc5e3 BZ	187	static const struct pci_device_id cs5535_pci_tbl[] = {
9cbcc5e3 BZ	188	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
10ca3028	189	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
f5b2d8b4 JK	190	{ 0, },
	191	};
	192
	193	MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
	194
a9ab09e2	195	static struct pci_driver cs5535_pci_driver = {
feb22b7f BZ	196	.name = "CS5535_IDE",
	197	.id_table = cs5535_pci_tbl,
	198	.probe = cs5535_init_one,
	199	.remove = ide_pci_remove,
	200	.suspend = ide_pci_suspend,
	201	.resume = ide_pci_resume,
f5b2d8b4 JK	202	};
	203
	204	static int __init cs5535_ide_init(void)
	205	{
a9ab09e2	206	return ide_pci_register_driver(&cs5535_pci_driver);
f5b2d8b4 JK	207	}
f5b2d8b4 JK	208
40c8a7f6 BZ	209	static void __exit cs5535_ide_exit(void)
40c8a7f6 BZ	210	{
a9ab09e2	211	pci_unregister_driver(&cs5535_pci_driver);
40c8a7f6 BZ	212	}
40c8a7f6 BZ	213
f5b2d8b4	214	module_init(cs5535_ide_init);
40c8a7f6	215	module_exit(cs5535_ide_exit);
f5b2d8b4 JK	216
	217	MODULE_AUTHOR("AMD");
	218	MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
	219	MODULE_LICENSE("GPL");