[linux.git] / drivers / clocksource / timer-prima2.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>
#include <asm/mach/time.h>

#define PRIMA2_CLOCK_FREQ 1000000

#define SIRFSOC_TIMER_COUNTER_LO	0x0000
#define SIRFSOC_TIMER_COUNTER_HI	0x0004
#define SIRFSOC_TIMER_MATCH_0		0x0008
#define SIRFSOC_TIMER_MATCH_1		0x000C
#define SIRFSOC_TIMER_MATCH_2		0x0010
#define SIRFSOC_TIMER_MATCH_3		0x0014
#define SIRFSOC_TIMER_MATCH_4		0x0018
#define SIRFSOC_TIMER_MATCH_5		0x001C
#define SIRFSOC_TIMER_STATUS		0x0020
#define SIRFSOC_TIMER_INT_EN		0x0024
#define SIRFSOC_TIMER_WATCHDOG_EN	0x0028
#define SIRFSOC_TIMER_DIV		0x002C
#define SIRFSOC_TIMER_LATCH		0x0030
#define SIRFSOC_TIMER_LATCHED_LO	0x0034
#define SIRFSOC_TIMER_LATCHED_HI	0x0038

#define SIRFSOC_TIMER_WDT_INDEX		5

#define SIRFSOC_TIMER_LATCH_BIT	 BIT(0)

#define SIRFSOC_TIMER_REG_CNT 11

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* timer0 interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
		BIT(0)));

	/* clear timer0 interrupt */
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	/* latch the 64-bit timer counter */
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
	cycles = (cycles << 32) |
		readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	unsigned long now, next;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	next = now + delta;
	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return next - now > delta ? -ETIME : 0;
}

static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	struct clock_event_device *ce)
{
	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		WARN_ON(1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		writel_relaxed(val | BIT(0),
			sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
		writel_relaxed(val & ~BIT(0),
			sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] =
			readl_relaxed(sirfsoc_timer_base +
				sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i],
			sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
}

static struct clock_event_device sirfsoc_clockevent = {
	.name = "sirfsoc_clockevent",
	.rating = 200,
	.features = CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sirfsoc_timer_set_mode,
	.set_next_event = sirfsoc_timer_set_next_event,
};

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER,
	.irq = 0,
	.handler = sirfsoc_timer_interrupt,
	.dev_id = &sirfsoc_clockevent,
};

/* Overwrite weak default sched_clock with more precise one */
static u64 notrace sirfsoc_read_sched_clock(void)
{
	return sirfsoc_timer_read(NULL);
}

static void __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
					2, -2);
}

/* initialize the kernel jiffy timer source */
static void __init sirfsoc_prima2_timer_init(struct device_node *np)
{
	unsigned long rate;
	struct clk *clk;

	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));

	BUG_ON(clk_prepare_enable(clk));

	rate = clk_get_rate(clk);

	BUG_ON(rate < PRIMA2_CLOCK_FREQ);
	BUG_ON(rate % PRIMA2_CLOCK_FREQ);

	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base)
		panic("unable to map timer cpu registers\n");

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);

	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
		sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
				       PRIMA2_CLOCK_FREQ));

	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);

	BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));

	sirfsoc_clockevent_init();
}
CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
	"sirf,prima2-tick", sirfsoc_prima2_timer_init);
Commit	Line	Data
02c981c0 BD	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
	13	#include <linux/bitops.h>
	14	#include <linux/irq.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
67d71344	19	#include <linux/of_irq.h>
02c981c0	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
02c981c0 BD	22	#include <asm/mach/time.h>
02c981c0 BD	23
980c51ab UKK	24	#define PRIMA2_CLOCK_FREQ 1000000
980c51ab UKK	25
02c981c0 BD	26	#define SIRFSOC_TIMER_COUNTER_LO 0x0000
	27	#define SIRFSOC_TIMER_COUNTER_HI 0x0004
	28	#define SIRFSOC_TIMER_MATCH_0 0x0008
	29	#define SIRFSOC_TIMER_MATCH_1 0x000C
	30	#define SIRFSOC_TIMER_MATCH_2 0x0010
	31	#define SIRFSOC_TIMER_MATCH_3 0x0014
	32	#define SIRFSOC_TIMER_MATCH_4 0x0018
	33	#define SIRFSOC_TIMER_MATCH_5 0x001C
	34	#define SIRFSOC_TIMER_STATUS 0x0020
	35	#define SIRFSOC_TIMER_INT_EN 0x0024
	36	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
	37	#define SIRFSOC_TIMER_DIV 0x002C
	38	#define SIRFSOC_TIMER_LATCH 0x0030
	39	#define SIRFSOC_TIMER_LATCHED_LO 0x0034
	40	#define SIRFSOC_TIMER_LATCHED_HI 0x0038
	41
	42	#define SIRFSOC_TIMER_WDT_INDEX 5
	43
	44	#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
	45
e5598a85 BS	46	#define SIRFSOC_TIMER_REG_CNT 11
	47
	48	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	49	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	50	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	51	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	52	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
	53	};
	54
	55	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	56
02c981c0	57	static void __iomem *sirfsoc_timer_base;
02c981c0 BD	58
	59	/* timer0 interrupt handler */
	60	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	61	{
	62	struct clock_event_device *ce = dev_id;
	63
4c1ad709 BS	64	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
4c1ad709 BS	65	BIT(0)));
02c981c0 BD	66
	67	/* clear timer0 interrupt */
	68	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	69
	70	ce->event_handler(ce);
	71
	72	return IRQ_HANDLED;
	73	}
	74
	75	/* read 64-bit timer counter */
	76	static cycle_t sirfsoc_timer_read(struct clocksource *cs)
	77	{
	78	u64 cycles;
	79
	80	/* latch the 64-bit timer counter */
4c1ad709 BS	81	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	82	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0	83	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
4c1ad709 BS	84	cycles = (cycles << 32) \|
4c1ad709 BS	85	readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
02c981c0 BD	86
	87	return cycles;
	88	}
	89
	90	static int sirfsoc_timer_set_next_event(unsigned long delta,
	91	struct clock_event_device *ce)
	92	{
	93	unsigned long now, next;
	94
4c1ad709 BS	95	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	96	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	97	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	98	next = now + delta;
	99	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
4c1ad709 BS	100	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	101	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	102	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	103
	104	return next - now > delta ? -ETIME : 0;
	105	}
	106
	107	static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	108	struct clock_event_device *ce)
	109	{
	110	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	111	switch (mode) {
	112	case CLOCK_EVT_MODE_PERIODIC:
	113	WARN_ON(1);
	114	break;
	115	case CLOCK_EVT_MODE_ONESHOT:
4c1ad709 BS	116	writel_relaxed(val \| BIT(0),
4c1ad709 BS	117	sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
02c981c0 BD	118	break;
02c981c0 BD	119	case CLOCK_EVT_MODE_SHUTDOWN:
4c1ad709 BS	120	writel_relaxed(val & ~BIT(0),
4c1ad709 BS	121	sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
02c981c0 BD	122	break;
	123	case CLOCK_EVT_MODE_UNUSED:
	124	case CLOCK_EVT_MODE_RESUME:
	125	break;
	126	}
	127	}
	128
e5598a85 BS	129	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	130	{
	131	int i;
	132
4c1ad709 BS	133	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	134	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
e5598a85 BS	135
e5598a85 BS	136	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
4c1ad709 BS	137	sirfsoc_timer_reg_val[i] =
	138	readl_relaxed(sirfsoc_timer_base +
	139	sirfsoc_timer_reg_list[i]);
e5598a85 BS	140	}
	141
	142	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	143	{
	144	int i;
	145
debeaf6c	146	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
4c1ad709 BS	147	writel_relaxed(sirfsoc_timer_reg_val[i],
4c1ad709 BS	148	sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
e5598a85	149
4c1ad709 BS	150	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	151	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	152	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	153	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
e5598a85 BS	154	}
e5598a85 BS	155
02c981c0 BD	156	static struct clock_event_device sirfsoc_clockevent = {
	157	.name = "sirfsoc_clockevent",
	158	.rating = 200,
	159	.features = CLOCK_EVT_FEAT_ONESHOT,
	160	.set_mode = sirfsoc_timer_set_mode,
	161	.set_next_event = sirfsoc_timer_set_next_event,
	162	};
	163
	164	static struct clocksource sirfsoc_clocksource = {
	165	.name = "sirfsoc_clocksource",
	166	.rating = 200,
	167	.mask = CLOCKSOURCE_MASK(64),
	168	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	169	.read = sirfsoc_timer_read,
e5598a85 BS	170	.suspend = sirfsoc_clocksource_suspend,
e5598a85 BS	171	.resume = sirfsoc_clocksource_resume,
02c981c0 BD	172	};
	173
	174	static struct irqaction sirfsoc_timer_irq = {
	175	.name = "sirfsoc_timer0",
	176	.flags = IRQF_TIMER,
	177	.irq = 0,
	178	.handler = sirfsoc_timer_interrupt,
	179	.dev_id = &sirfsoc_clockevent,
	180	};
	181
	182	/* Overwrite weak default sched_clock with more precise one */
130e6b25	183	static u64 notrace sirfsoc_read_sched_clock(void)
02c981c0	184	{
130e6b25	185	return sirfsoc_timer_read(NULL);
02c981c0 BD	186	}
	187
	188	static void __init sirfsoc_clockevent_init(void)
	189	{
02c981c0	190	sirfsoc_clockevent.cpumask = cpumask_of(0);
980c51ab	191	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
838a2ae8	192	2, -2);
02c981c0 BD	193	}
	194
	195	/* initialize the kernel jiffy timer source */
275786b7	196	static void __init sirfsoc_prima2_timer_init(struct device_node *np)
02c981c0 BD	197	{
02c981c0 BD	198	unsigned long rate;
198678b0 BD	199	struct clk *clk;
198678b0 BD	200
c7cff54d	201	clk = of_clk_get(np, 0);
02c981c0	202	BUG_ON(IS_ERR(clk));
38941522 ZS	203
	204	BUG_ON(clk_prepare_enable(clk));
	205
02c981c0 BD	206	rate = clk_get_rate(clk);
02c981c0 BD	207
980c51ab UKK	208	BUG_ON(rate < PRIMA2_CLOCK_FREQ);
980c51ab UKK	209	BUG_ON(rate % PRIMA2_CLOCK_FREQ);
02c981c0	210
275786b7 AB	211	sirfsoc_timer_base = of_iomap(np, 0);
	212	if (!sirfsoc_timer_base)
	213	panic("unable to map timer cpu registers\n");
	214
	215	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
bc8d849d	216
980c51ab	217	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
4c1ad709	218	sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
02c981c0 BD	219	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	220	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	221	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	222
980c51ab UKK	223	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
980c51ab UKK	224	PRIMA2_CLOCK_FREQ));
02c981c0	225
980c51ab	226	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
bc8d849d	227
02c981c0 BD	228	BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
	229
	230	sirfsoc_clockevent_init();
	231	}
4c1ad709 BS	232	CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
4c1ad709 BS	233	"sirf,prima2-tick", sirfsoc_prima2_timer_init);