[linux.git] / drivers / ide / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <[email protected]>
 * Copyright (C) 1998		Eddie C. Dost <[email protected]>
 * Copyright (C) 1999-2000	Andre Hedrick <[email protected]>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <[email protected]>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "ns87415"

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	u8 tmp;
	int retries = SUPERIO_IDE_MAX_RETRIES;

	/* printk(" [ reading port 0x%x with retry ] ", port); */

	do {
		tmp = inb(port);
		if (tmp == 0)
			udelay(50);
	} while (tmp == 0 && retries-- > 0);

	return tmp;
}

static u8 superio_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->io_ports.status_addr);
}

static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
			    u8 valid)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;

	if (valid & IDE_VALID_ERROR)
		tf->error  = inb(io_ports->feature_addr);
	if (valid & IDE_VALID_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (valid & IDE_VALID_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (valid & IDE_VALID_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (valid & IDE_VALID_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (valid & IDE_VALID_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);
}

static void ns87415_dev_select(ide_drive_t *drive);

static const struct ide_tp_ops superio_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= superio_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ns87415_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= superio_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static void superio_init_iops(struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 dma_stat;
	u8 port = hwif->channel, tmp;

	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(dma_stat);
	outb(tmp | 0x66, dma_stat);
}
#else
#define superio_dma_sff_read_status ide_dma_sff_read_status
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
 * the IRQ associated with the port,
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);

	if (drive->dev_flags & IDE_DFLAG_PRESENT)
		new &= ~bit;
	else
		new |= bit;

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_dev_select(ide_drive_t *drive)
{
	ns87415_prepare_drive(drive,
			      !!(drive->dev_flags & IDE_DFLAG_USING_DMA));

	outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
}

static void ns87415_dma_start(ide_drive_t *drive)
{
	ns87415_prepare_drive(drive, 1);
	ide_dma_start(drive);
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);

	ns87415_prepare_drive(drive, 0);

	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static void init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in dev_select() when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      dev_select() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->tp_ops->read_status(hwif);
			if (stat == 0xff)
				break;
		} while ((stat & ATA_BUSY) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_tp_ops ns87415_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= ide_read_status,
	.read_altstatus		= ide_read_altstatus,
	.write_devctl		= ide_write_devctl,

	.dev_select		= ns87415_dev_select,
	.tf_load		= ide_tf_load,
	.tf_read		= ide_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ide_dma_setup,
	.dma_start		= ns87415_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
	.dma_sff_read_status	= superio_dma_sff_read_status,
};

static const struct ide_port_info ns87415_chipset = {
	.name		= DRV_NAME,
	.init_hwif	= init_hwif_ns87415,
	.tp_ops 	= &ns87415_tp_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d = ns87415_chipset;

#ifdef CONFIG_SUPERIO
	if (PCI_SLOT(dev->devfn) == 0xE) {
		/* Built-in - assume it's under superio. */
		d.init_iops = superio_init_iops;
		d.tp_ops = &superio_tp_ops;
	}
#endif
	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver ns87415_pci_driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&ns87415_pci_driver);
}

static void __exit ns87415_ide_exit(void)
{
	pci_unregister_driver(&ns87415_pci_driver);
}

module_init(ns87415_ide_init);
module_exit(ns87415_ide_exit);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <[email protected]>
	3	* Copyright (C) 1998 Eddie C. Dost <[email protected]>
	4	* Copyright (C) 1999-2000 Andre Hedrick <[email protected]>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <[email protected]>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/pci.h>
	15	#include <linux/delay.h>
	16	#include <linux/ide.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
ced3ec8a BZ	21	#define DRV_NAME "ns87415"
ced3ec8a BZ	22
1da177e4 LT	23	#ifdef CONFIG_SUPERIO
	24	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	25	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	26	* which use the integrated NS87514 cell for CD-ROM support.
	27	* i.e we have to support for CD-ROM installs.
	28	* See drivers/parisc/superio.c for more gory details.
	29	*/
	30	#include <asm/superio.h>
	31
1da177e4 LT	32	#define SUPERIO_IDE_MAX_RETRIES 25
	33
	34	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	35	* registers, IDE status register and the IDE select register need to be
	36	* retried
	37	*/
	38	static u8 superio_ide_inb (unsigned long port)
	39	{
761052e6 BZ	40	u8 tmp;
	41	int retries = SUPERIO_IDE_MAX_RETRIES;
	42
	43	/* printk(" [ reading port 0x%x with retry ] ", port); */
1da177e4	44
761052e6 BZ	45	do {
	46	tmp = inb(port);
	47	if (tmp == 0)
	48	udelay(50);
	49	} while (tmp == 0 && retries-- > 0);
	50
	51	return tmp;
1da177e4 LT	52	}
1da177e4 LT	53
b73c7ee2 BZ	54	static u8 superio_read_status(ide_hwif_t *hwif)
	55	{
	56	return superio_ide_inb(hwif->io_ports.status_addr);
	57	}
	58
592b5315	59	static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
b2f951aa	60	{
cab7f8ed	61	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	62	}
b2f951aa BZ	63
3153c26b SS	64	static void superio_tf_read(ide_drive_t drive, struct ide_taskfile tf,
3153c26b SS	65	u8 valid)
ea23b8ba BZ	66	{
ea23b8ba BZ	67	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
ea23b8ba	68
60f85019	69	if (valid & IDE_VALID_ERROR)
67625119	70	tf->error = inb(io_ports->feature_addr);
60f85019	71	if (valid & IDE_VALID_NSECT)
ea23b8ba	72	tf->nsect = inb(io_ports->nsect_addr);
60f85019	73	if (valid & IDE_VALID_LBAL)
ea23b8ba	74	tf->lbal = inb(io_ports->lbal_addr);
60f85019	75	if (valid & IDE_VALID_LBAM)
ea23b8ba	76	tf->lbam = inb(io_ports->lbam_addr);
60f85019	77	if (valid & IDE_VALID_LBAH)
ea23b8ba	78	tf->lbah = inb(io_ports->lbah_addr);
60f85019	79	if (valid & IDE_VALID_DEVICE)
ea23b8ba	80	tf->device = superio_ide_inb(io_ports->device_addr);
ea23b8ba BZ	81	}
ea23b8ba BZ	82
abb596b2 SS	83	static void ns87415_dev_select(ide_drive_t *drive);
abb596b2 SS	84
374e042c BZ	85	static const struct ide_tp_ops superio_tp_ops = {
	86	.exec_command = ide_exec_command,
	87	.read_status = superio_read_status,
	88	.read_altstatus = ide_read_altstatus,
ecf3a31d	89	.write_devctl = ide_write_devctl,
374e042c	90
abb596b2	91	.dev_select = ns87415_dev_select,
374e042c BZ	92	.tf_load = ide_tf_load,
	93	.tf_read = superio_tf_read,
	94
	95	.input_data = ide_input_data,
	96	.output_data = ide_output_data,
	97	};
	98
fe31edc8	99	static void superio_init_iops(struct hwif_s *hwif)
1da177e4	100	{
36501650	101	struct pci_dev *pdev = to_pci_dev(hwif->dev);
761052e6	102	u32 dma_stat;
36501650	103	u8 port = hwif->channel, tmp;
1da177e4	104
761052e6	105	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
1da177e4 LT	106
1da177e4 LT	107	/* Clear error/interrupt, enable dma */
761052e6 BZ	108	tmp = superio_ide_inb(dma_stat);
761052e6 BZ	109	outb(tmp \| 0x66, dma_stat);
1da177e4	110	}
592b5315 SS	111	#else
592b5315 SS	112	#define superio_dma_sff_read_status ide_dma_sff_read_status
1da177e4 LT	113	#endif
	114
	115	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	116
	117	/*
97100fc8	118	* This routine either enables/disables (according to IDE_DFLAG_PRESENT)
898ec223	119	* the IRQ associated with the port,
1da177e4 LT	120	* and selects either PIO or DMA handshaking for the next I/O operation.
	121	*/
	122	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	123	{
898ec223	124	ide_hwif_t *hwif = drive->hwif;
36501650	125	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	126	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	127	unsigned long flags;
	128
	129	local_irq_save(flags);
	130	new = *old;
	131
	132	/* Adjust IRQ enable bit */
	133	bit = 1 << (8 + hwif->channel);
97100fc8 BZ	134
	135	if (drive->dev_flags & IDE_DFLAG_PRESENT)
	136	new &= ~bit;
	137	else
	138	new \|= bit;
1da177e4 LT	139
1da177e4 LT	140	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
123995b9 BZ	141	bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
123995b9 BZ	142	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
1da177e4 LT	143	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	144
	145	if (new != *old) {
	146	unsigned char stat;
	147
	148	/*
	149	* Don't change DMA engine settings while Write Buffers
	150	* are busy.
	151	*/
	152	(void) pci_read_config_byte(dev, 0x43, &stat);
	153	while (stat & 0x03) {
	154	udelay(1);
	155	(void) pci_read_config_byte(dev, 0x43, &stat);
	156	}
	157
	158	*old = new;
	159	(void) pci_write_config_dword(dev, 0x40, new);
	160
	161	/*
	162	* And let things settle...
	163	*/
	164	udelay(10);
	165	}
	166
	167	local_irq_restore(flags);
	168	}
	169
abb596b2	170	static void ns87415_dev_select(ide_drive_t *drive)
1da177e4	171	{
97100fc8 BZ	172	ns87415_prepare_drive(drive,
97100fc8 BZ	173	!!(drive->dev_flags & IDE_DFLAG_USING_DMA));
abb596b2 SS	174
abb596b2 SS	175	outb(drive->select \| ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
1da177e4 LT	176	}
1da177e4 LT	177
a6d67ffa BZ	178	static void ns87415_dma_start(ide_drive_t *drive)
	179	{
	180	ns87415_prepare_drive(drive, 1);
	181	ide_dma_start(drive);
	182	}
	183
5e37bdc0	184	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4	185	{
898ec223	186	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	187	u8 dma_stat = 0, dma_cmd = 0;
1da177e4 LT	188
592b5315	189	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
cab7f8ed BZ	190	/* get DMA command mode */
cab7f8ed BZ	191	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	192	/* stop DMA */
cab7f8ed	193	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	194	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	195	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	196	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4	197
1da177e4	198	ns87415_prepare_drive(drive, 0);
a6d67ffa BZ	199
	200	/* verify good DMA status */
	201	return (dma_stat & 7) != 4;
1da177e4 LT	202	}
1da177e4 LT	203
fe31edc8	204	static void init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	205	{
36501650	206	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	207	unsigned int ctrl, using_inta;
	208	u8 progif;
	209	#ifdef __sparc_v9__
	210	int timeout;
	211	u8 stat;
	212	#endif
	213
1da177e4 LT	214	/*
	215	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	216	* Also, leave IRQ masked during drive probing, to prevent infinite
	217	* interrupts from a potentially floating INTA..
	218	*
abb596b2	219	* IRQs get unmasked in dev_select() when drive is first used.
1da177e4 LT	220	*/
	221	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	222	(void) pci_read_config_byte(dev, 0x09, &progif);
	223	/* is irq in "native" mode? */
	224	using_inta = progif & (1 << (hwif->channel << 1));
	225	if (!using_inta)
	226	using_inta = ctrl & (1 << (4 + hwif->channel));
	227	if (hwif->mate) {
	228	hwif->select_data = hwif->mate->select_data;
	229	} else {
	230	hwif->select_data = (unsigned long)
	231	&ns87415_control[ns87415_count++];
	232	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	233	if (using_inta)
	234	ctrl &= ~(1 << 6); /* unmask INTA */
	235	((unsigned int )hwif->select_data) = ctrl;
	236	(void) pci_write_config_dword(dev, 0x40, ctrl);
	237
	238	/*
	239	* Set prefetch size to 512 bytes for both ports,
	240	* but don't turn on/off prefetching here.
	241	*/
	242	pci_write_config_byte(dev, 0x55, 0xee);
	243
	244	#ifdef __sparc_v9__
	245	/*
9d501529	246	* XXX: Reset the device, if we don't it will not respond to
fdd88f0a	247	* dev_select() properly during first ide_probe_port().
1da177e4 LT	248	*/
1da177e4 LT	249	timeout = 10000;
4c3032d8	250	outb(12, hwif->io_ports.ctl_addr);
1da177e4	251	udelay(10);
4c3032d8	252	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	253	do {
1da177e4 LT	254	udelay(50);
374e042c	255	stat = hwif->tp_ops->read_status(hwif);
3a7d2484 BZ	256	if (stat == 0xff)
	257	break;
	258	} while ((stat & ATA_BUSY) && --timeout);
1da177e4 LT	259	#endif
	260	}
	261
	262	if (!using_inta)
973d9e74	263	hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
1da177e4 LT	264
	265	if (!hwif->dma_base)
	266	return;
	267
cab7f8ed	268	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	269	}
1da177e4 LT	270
abb596b2 SS	271	static const struct ide_tp_ops ns87415_tp_ops = {
	272	.exec_command = ide_exec_command,
	273	.read_status = ide_read_status,
	274	.read_altstatus = ide_read_altstatus,
	275	.write_devctl = ide_write_devctl,
	276
	277	.dev_select = ns87415_dev_select,
	278	.tf_load = ide_tf_load,
	279	.tf_read = ide_tf_read,
	280
	281	.input_data = ide_input_data,
	282	.output_data = ide_output_data,
ac95beed BZ	283	};
ac95beed BZ	284
f37afdac BZ	285	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	286	.dma_host_set = ide_dma_host_set,
a6d67ffa BZ	287	.dma_setup = ide_dma_setup,
a6d67ffa BZ	288	.dma_start = ns87415_dma_start,
5e37bdc0	289	.dma_end = ns87415_dma_end,
f37afdac BZ	290	.dma_test_irq = ide_dma_test_irq,
f37afdac BZ	291	.dma_lost_irq = ide_dma_lost_irq,
22117d6e	292	.dma_timer_expiry = ide_dma_sff_timer_expiry,
592b5315	293	.dma_sff_read_status = superio_dma_sff_read_status,
5e37bdc0 BZ	294	};
5e37bdc0 BZ	295
fe31edc8	296	static const struct ide_port_info ns87415_chipset = {
ced3ec8a	297	.name = DRV_NAME,
1da177e4	298	.init_hwif = init_hwif_ns87415,
abb596b2	299	.tp_ops = &ns87415_tp_ops,
5e37bdc0	300	.dma_ops = &ns87415_dma_ops,
33c1002e	301	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	302	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	303	};
1da177e4 LT	304
fe31edc8	305	static int ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
1da177e4	306	{
374e042c BZ	307	struct ide_port_info d = ns87415_chipset;
	308
	309	#ifdef CONFIG_SUPERIO
	310	if (PCI_SLOT(dev->devfn) == 0xE) {
	311	/* Built-in - assume it's under superio. */
	312	d.init_iops = superio_init_iops;
	313	d.tp_ops = &superio_tp_ops;
	314	}
	315	#endif
6cdf6eb3	316	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	317	}
1da177e4 LT	318
9cbcc5e3 BZ	319	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	320	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	321	{ 0, },
	322	};
	323	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	324
a9ab09e2	325	static struct pci_driver ns87415_pci_driver = {
1da177e4 LT	326	.name = "NS87415_IDE",
	327	.id_table = ns87415_pci_tbl,
	328	.probe = ns87415_init_one,
aa6e518d	329	.remove = ide_pci_remove,
feb22b7f BZ	330	.suspend = ide_pci_suspend,
feb22b7f BZ	331	.resume = ide_pci_resume,
1da177e4 LT	332	};
1da177e4 LT	333
82ab1eec	334	static int __init ns87415_ide_init(void)
1da177e4	335	{
a9ab09e2	336	return ide_pci_register_driver(&ns87415_pci_driver);
1da177e4 LT	337	}
1da177e4 LT	338
aa6e518d BZ	339	static void __exit ns87415_ide_exit(void)
aa6e518d BZ	340	{
a9ab09e2	341	pci_unregister_driver(&ns87415_pci_driver);
aa6e518d BZ	342	}
aa6e518d BZ	343
1da177e4	344	module_init(ns87415_ide_init);
aa6e518d	345	module_exit(ns87415_ide_exit);
1da177e4 LT	346
	347	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	348	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	349	MODULE_LICENSE("GPL");