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drm/i915/gvt: Add 64K huge gtt support
[linux.git] / drivers / gpu / drm / i915 / gvt / gtt.c
CommitLineData
2707e444
ZW		 1/*
2 * GTT virtualization
3 *
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Zhi Wang <[email protected]>
27 * Zhenyu Wang <[email protected]>
28 * Xiao Zheng <[email protected]>
29 *
30 * Contributors:
31 * Min He <[email protected]>
32 * Bing Niu <[email protected]>
33 *
34 */
35
36#include "i915_drv.h"
feddf6e8
ZW		 37#include "gvt.h"
38#include "i915_pvinfo.h"
2707e444
ZW		 39#include "trace.h"
40
bc37ab56
CD		 41#if defined(VERBOSE_DEBUG)
42#define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
43#else
44#define gvt_vdbg_mm(fmt, args...)
45#endif
46
2707e444
ZW		 47static bool enable_out_of_sync = false;
48static int preallocated_oos_pages = 8192;
49
50/*
51 * validate a gm address and related range size,
52 * translate it to host gm address
53 */
54bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
55{
56 if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
57 && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
695fbc08
TZ		 58 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
59 addr, size);
2707e444
ZW		 60 return false;
61 }
62 return true;
63}
64
65/* translate a guest gmadr to host gmadr */
66int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
67{
68 if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
69 "invalid guest gmadr %llx\n", g_addr))
70 return -EACCES;
71
72 if (vgpu_gmadr_is_aperture(vgpu, g_addr))
73 *h_addr = vgpu_aperture_gmadr_base(vgpu)
74 + (g_addr - vgpu_aperture_offset(vgpu));
75 else
76 *h_addr = vgpu_hidden_gmadr_base(vgpu)
77 + (g_addr - vgpu_hidden_offset(vgpu));
78 return 0;
79}
80
81/* translate a host gmadr to guest gmadr */
82int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
83{
84 if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
85 "invalid host gmadr %llx\n", h_addr))
86 return -EACCES;
87
88 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
89 *g_addr = vgpu_aperture_gmadr_base(vgpu)
90 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
91 else
92 *g_addr = vgpu_hidden_gmadr_base(vgpu)
93 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
94 return 0;
95}
96
97int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
98 unsigned long *h_index)
99{
100 u64 h_addr;
101 int ret;
102
9556e118 103 ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 104 &h_addr);
105 if (ret)
106 return ret;
107
9556e118 108 *h_index = h_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 109 return 0;
110}
111
112int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
113 unsigned long *g_index)
114{
115 u64 g_addr;
116 int ret;
117
9556e118 118 ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 119 &g_addr);
120 if (ret)
121 return ret;
122
9556e118 123 *g_index = g_addr >> I915_GTT_PAGE_SHIFT;
2707e444
ZW		 124 return 0;
125}
126
127#define gtt_type_is_entry(type) \
128 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
129 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
130 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
131
132#define gtt_type_is_pt(type) \
133 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
134
135#define gtt_type_is_pte_pt(type) \
136 (type == GTT_TYPE_PPGTT_PTE_PT)
137
138#define gtt_type_is_root_pointer(type) \
139 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
140
141#define gtt_init_entry(e, t, p, v) do { \
142 (e)->type = t; \
143 (e)->pdev = p; \
144 memcpy(&(e)->val64, &v, sizeof(v)); \
145} while (0)
146
2707e444
ZW		 147/*
148 * Mappings between GTT_TYPE* enumerations.
149 * Following information can be found according to the given type:
150 * - type of next level page table
151 * - type of entry inside this level page table
152 * - type of entry with PSE set
153 *
154 * If the given type doesn't have such a kind of information,
155 * e.g. give a l4 root entry type, then request to get its PSE type,
156 * give a PTE page table type, then request to get its next level page
157 * table type, as we know l4 root entry doesn't have a PSE bit,
158 * and a PTE page table doesn't have a next level page table type,
159 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
160 * page table.
161 */
162
163struct gtt_type_table_entry {
164 int entry_type;
054f4eba 165 int pt_type;
2707e444
ZW		 166 int next_pt_type;
167 int pse_entry_type;
168};
169
054f4eba 170#define GTT_TYPE_TABLE_ENTRY(type, e_type, cpt_type, npt_type, pse_type) \
2707e444
ZW		 171 [type] = { \
172 .entry_type = e_type, \
054f4eba 173 .pt_type = cpt_type, \
2707e444
ZW		 174 .next_pt_type = npt_type, \
175 .pse_entry_type = pse_type, \
176 }
177
178static struct gtt_type_table_entry gtt_type_table[] = {
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
180 GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
054f4eba 181 GTT_TYPE_INVALID,
2707e444
ZW		 182 GTT_TYPE_PPGTT_PML4_PT,
183 GTT_TYPE_INVALID),
184 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT,
185 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 186 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 187 GTT_TYPE_PPGTT_PDP_PT,
188 GTT_TYPE_INVALID),
189 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY,
190 GTT_TYPE_PPGTT_PML4_ENTRY,
054f4eba 191 GTT_TYPE_PPGTT_PML4_PT,
2707e444
ZW		 192 GTT_TYPE_PPGTT_PDP_PT,
193 GTT_TYPE_INVALID),
194 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT,
195 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 196 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 197 GTT_TYPE_PPGTT_PDE_PT,
198 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
200 GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
054f4eba 201 GTT_TYPE_INVALID,
2707e444
ZW		 202 GTT_TYPE_PPGTT_PDE_PT,
203 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
204 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY,
205 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 206 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 207 GTT_TYPE_PPGTT_PDE_PT,
208 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
209 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT,
210 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 211 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 212 GTT_TYPE_PPGTT_PTE_PT,
213 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
214 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY,
215 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 216 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 217 GTT_TYPE_PPGTT_PTE_PT,
218 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
b294657d 219 /* We take IPS bit as 'PSE' for PTE level. */
2707e444
ZW		 220 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT,
221 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 222 GTT_TYPE_PPGTT_PTE_PT,
2707e444 223 GTT_TYPE_INVALID,
b294657d 224 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 225 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY,
226 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
054f4eba 227 GTT_TYPE_PPGTT_PTE_PT,
2707e444 228 GTT_TYPE_INVALID,
b294657d
CD		 229 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
230 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_64K_ENTRY,
231 GTT_TYPE_PPGTT_PTE_4K_ENTRY,
232 GTT_TYPE_PPGTT_PTE_PT,
233 GTT_TYPE_INVALID,
234 GTT_TYPE_PPGTT_PTE_64K_ENTRY),
2707e444
ZW		 235 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY,
236 GTT_TYPE_PPGTT_PDE_ENTRY,
054f4eba 237 GTT_TYPE_PPGTT_PDE_PT,
2707e444
ZW		 238 GTT_TYPE_INVALID,
239 GTT_TYPE_PPGTT_PTE_2M_ENTRY),
240 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY,
241 GTT_TYPE_PPGTT_PDP_ENTRY,
054f4eba 242 GTT_TYPE_PPGTT_PDP_PT,
2707e444
ZW		 243 GTT_TYPE_INVALID,
244 GTT_TYPE_PPGTT_PTE_1G_ENTRY),
245 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE,
246 GTT_TYPE_GGTT_PTE,
247 GTT_TYPE_INVALID,
054f4eba 248 GTT_TYPE_INVALID,
2707e444
ZW		 249 GTT_TYPE_INVALID),
250};
251
252static inline int get_next_pt_type(int type)
253{
254 return gtt_type_table[type].next_pt_type;
255}
256
054f4eba
ZW		 257static inline int get_pt_type(int type)
258{
259 return gtt_type_table[type].pt_type;
260}
261
2707e444
ZW		 262static inline int get_entry_type(int type)
263{
264 return gtt_type_table[type].entry_type;
265}
266
267static inline int get_pse_type(int type)
268{
269 return gtt_type_table[type].pse_entry_type;
270}
271
272static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
273{
321927db 274 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
905a5035
CD		 275
276 return readq(addr);
2707e444
ZW		 277}
278
a143cef7 279static void ggtt_invalidate(struct drm_i915_private *dev_priv)
af2c6399
CD		 280{
281 mmio_hw_access_pre(dev_priv);
282 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
283 mmio_hw_access_post(dev_priv);
284}
285
2707e444
ZW		 286static void write_pte64(struct drm_i915_private *dev_priv,
287 unsigned long index, u64 pte)
288{
321927db 289 void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
2707e444 290
2707e444 291 writeq(pte, addr);
2707e444
ZW		 292}
293
4b2dbbc2 294static inline int gtt_get_entry64(void *pt,
2707e444
ZW		 295 struct intel_gvt_gtt_entry *e,
296 unsigned long index, bool hypervisor_access, unsigned long gpa,
297 struct intel_vgpu *vgpu)
298{
299 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
300 int ret;
301
302 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 303 return -EINVAL;
2707e444
ZW		 304
305 if (hypervisor_access) {
306 ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa +
307 (index << info->gtt_entry_size_shift),
308 &e->val64, 8);
4b2dbbc2
CD		 309 if (WARN_ON(ret))
310 return ret;
2707e444
ZW		 311 } else if (!pt) {
312 e->val64 = read_pte64(vgpu->gvt->dev_priv, index);
313 } else {
314 e->val64 = *((u64 *)pt + index);
315 }
4b2dbbc2 316 return 0;
2707e444
ZW		 317}
318
4b2dbbc2 319static inline int gtt_set_entry64(void *pt,
2707e444
ZW		 320 struct intel_gvt_gtt_entry *e,
321 unsigned long index, bool hypervisor_access, unsigned long gpa,
322 struct intel_vgpu *vgpu)
323{
324 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
325 int ret;
326
327 if (WARN_ON(info->gtt_entry_size != 8))
4b2dbbc2 328 return -EINVAL;
2707e444
ZW		 329
330 if (hypervisor_access) {
331 ret = intel_gvt_hypervisor_write_gpa(vgpu, gpa +
332 (index << info->gtt_entry_size_shift),
333 &e->val64, 8);
4b2dbbc2
CD		 334 if (WARN_ON(ret))
335 return ret;
2707e444
ZW		 336 } else if (!pt) {
337 write_pte64(vgpu->gvt->dev_priv, index, e->val64);
338 } else {
339 *((u64 *)pt + index) = e->val64;
340 }
4b2dbbc2 341 return 0;
2707e444
ZW		 342}
343
344#define GTT_HAW 46
345
420fba78
CD		 346#define ADDR_1G_MASK GENMASK_ULL(GTT_HAW - 1, 30)
347#define ADDR_2M_MASK GENMASK_ULL(GTT_HAW - 1, 21)
b294657d 348#define ADDR_64K_MASK GENMASK_ULL(GTT_HAW - 1, 16)
420fba78 349#define ADDR_4K_MASK GENMASK_ULL(GTT_HAW - 1, 12)
2707e444 350
71634848
CD		 351#define GTT_SPTE_FLAG_MASK GENMASK_ULL(62, 52)
352#define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
353
4c9414d7
CD		 354#define GTT_64K_PTE_STRIDE 16
355
2707e444
ZW		 356static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
357{
358 unsigned long pfn;
359
360 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY)
d861ca23 361 pfn = (e->val64 & ADDR_1G_MASK) >> PAGE_SHIFT;
2707e444 362 else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY)
d861ca23 363 pfn = (e->val64 & ADDR_2M_MASK) >> PAGE_SHIFT;
b294657d
CD		 364 else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY)
365 pfn = (e->val64 & ADDR_64K_MASK) >> PAGE_SHIFT;
2707e444 366 else
d861ca23 367 pfn = (e->val64 & ADDR_4K_MASK) >> PAGE_SHIFT;
2707e444
ZW		 368 return pfn;
369}
370
371static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry *e, unsigned long pfn)
372{
373 if (e->type == GTT_TYPE_PPGTT_PTE_1G_ENTRY) {
374 e->val64 &= ~ADDR_1G_MASK;
d861ca23 375 pfn &= (ADDR_1G_MASK >> PAGE_SHIFT);
2707e444
ZW		 376 } else if (e->type == GTT_TYPE_PPGTT_PTE_2M_ENTRY) {
377 e->val64 &= ~ADDR_2M_MASK;
d861ca23 378 pfn &= (ADDR_2M_MASK >> PAGE_SHIFT);
b294657d
CD		 379 } else if (e->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY) {
380 e->val64 &= ~ADDR_64K_MASK;
381 pfn &= (ADDR_64K_MASK >> PAGE_SHIFT);
2707e444
ZW		 382 } else {
383 e->val64 &= ~ADDR_4K_MASK;
d861ca23 384 pfn &= (ADDR_4K_MASK >> PAGE_SHIFT);
2707e444
ZW		 385 }
386
d861ca23 387 e->val64 |= (pfn << PAGE_SHIFT);
2707e444
ZW		 388}
389
390static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry *e)
391{
40b27176 392 return !!(e->val64 & _PAGE_PSE);
2707e444
ZW		 393}
394
c3e69763
CD		 395static void gen8_gtt_clear_pse(struct intel_gvt_gtt_entry *e)
396{
397 if (gen8_gtt_test_pse(e)) {
398 switch (e->type) {
399 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
400 e->val64 &= ~_PAGE_PSE;
401 e->type = GTT_TYPE_PPGTT_PDE_ENTRY;
402 break;
403 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
404 e->type = GTT_TYPE_PPGTT_PDP_ENTRY;
405 e->val64 &= ~_PAGE_PSE;
406 break;
407 default:
408 WARN_ON(1);
409 }
410 }
411}
412
6fd79378
CD		 413static bool gen8_gtt_test_ips(struct intel_gvt_gtt_entry *e)
414{
415 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
416 return false;
417
418 return !!(e->val64 & GEN8_PDE_IPS_64K);
419}
420
421static void gen8_gtt_clear_ips(struct intel_gvt_gtt_entry *e)
422{
423 if (GEM_WARN_ON(e->type != GTT_TYPE_PPGTT_PDE_ENTRY))
424 return;
425
426 e->val64 &= ~GEN8_PDE_IPS_64K;
427}
428
2707e444
ZW		 429static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
430{
431 /*
432 * i915 writes PDP root pointer registers without present bit,
433 * it also works, so we need to treat root pointer entry
434 * specifically.
435 */
436 if (e->type == GTT_TYPE_PPGTT_ROOT_L3_ENTRY
437 || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
438 return (e->val64 != 0);
439 else
d861ca23 440 return (e->val64 & _PAGE_PRESENT);
2707e444
ZW		 441}
442
443static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
444{
d861ca23 445 e->val64 &= ~_PAGE_PRESENT;
2707e444
ZW		 446}
447
655c64ef
ZW		 448static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
449{
d861ca23 450 e->val64 |= _PAGE_PRESENT;
2707e444
ZW		 451}
452
71634848
CD		 453static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
454{
455 return !!(e->val64 & GTT_SPTE_FLAG_64K_SPLITED);
456}
457
458static void gen8_gtt_set_64k_splited(struct intel_gvt_gtt_entry *e)
459{
460 e->val64 |= GTT_SPTE_FLAG_64K_SPLITED;
461}
462
463static void gen8_gtt_clear_64k_splited(struct intel_gvt_gtt_entry *e)
464{
465 e->val64 &= ~GTT_SPTE_FLAG_64K_SPLITED;
466}
467
2707e444
ZW		 468/*
469 * Per-platform GMA routines.
470 */
471static unsigned long gma_to_ggtt_pte_index(unsigned long gma)
472{
9556e118 473 unsigned long x = (gma >> I915_GTT_PAGE_SHIFT);
2707e444
ZW		 474
475 trace_gma_index(__func__, gma, x);
476 return x;
477}
478
479#define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
480static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
481{ \
482 unsigned long x = (exp); \
483 trace_gma_index(__func__, gma, x); \
484 return x; \
485}
486
487DEFINE_PPGTT_GMA_TO_INDEX(gen8, pte, (gma >> 12 & 0x1ff));
488DEFINE_PPGTT_GMA_TO_INDEX(gen8, pde, (gma >> 21 & 0x1ff));
489DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
490DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
491DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
492
493static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
494 .get_entry = gtt_get_entry64,
495 .set_entry = gtt_set_entry64,
496 .clear_present = gtt_entry_clear_present,
655c64ef 497 .set_present = gtt_entry_set_present,
2707e444
ZW		 498 .test_present = gen8_gtt_test_present,
499 .test_pse = gen8_gtt_test_pse,
c3e69763 500 .clear_pse = gen8_gtt_clear_pse,
6fd79378
CD		 501 .clear_ips = gen8_gtt_clear_ips,
502 .test_ips = gen8_gtt_test_ips,
71634848
CD		 503 .clear_64k_splited = gen8_gtt_clear_64k_splited,
504 .set_64k_splited = gen8_gtt_set_64k_splited,
505 .test_64k_splited = gen8_gtt_test_64k_splited,
2707e444
ZW		 506 .get_pfn = gen8_gtt_get_pfn,
507 .set_pfn = gen8_gtt_set_pfn,
508};
509
510static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
511 .gma_to_ggtt_pte_index = gma_to_ggtt_pte_index,
512 .gma_to_pte_index = gen8_gma_to_pte_index,
513 .gma_to_pde_index = gen8_gma_to_pde_index,
514 .gma_to_l3_pdp_index = gen8_gma_to_l3_pdp_index,
515 .gma_to_l4_pdp_index = gen8_gma_to_l4_pdp_index,
516 .gma_to_pml4_index = gen8_gma_to_pml4_index,
517};
518
40b27176
CD		 519/* Update entry type per pse and ips bit. */
520static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
521 struct intel_gvt_gtt_entry *entry, bool ips)
522{
523 switch (entry->type) {
524 case GTT_TYPE_PPGTT_PDE_ENTRY:
525 case GTT_TYPE_PPGTT_PDP_ENTRY:
526 if (pte_ops->test_pse(entry))
527 entry->type = get_pse_type(entry->type);
528 break;
529 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
530 if (ips)
531 entry->type = get_pse_type(entry->type);
532 break;
533 default:
534 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
535 }
536
537 GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
538}
539
2707e444
ZW		 540/*
541 * MM helpers.
542 */
3aff3512
CD		 543static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
544 struct intel_gvt_gtt_entry *entry, unsigned long index,
545 bool guest)
2707e444 546{
3aff3512 547 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
2707e444 548
3aff3512 549 GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
2707e444 550
3aff3512
CD		 551 entry->type = mm->ppgtt_mm.root_entry_type;
552 pte_ops->get_entry(guest ? mm->ppgtt_mm.guest_pdps :
553 mm->ppgtt_mm.shadow_pdps,
554 entry, index, false, 0, mm->vgpu);
40b27176 555 update_entry_type_for_real(pte_ops, entry, false);
2707e444
ZW		 556}
557
3aff3512
CD		 558static inline void ppgtt_get_guest_root_entry(struct intel_vgpu_mm *mm,
559 struct intel_gvt_gtt_entry *entry, unsigned long index)
2707e444 560{
3aff3512
CD		 561 _ppgtt_get_root_entry(mm, entry, index, true);
562}
563
564static inline void ppgtt_get_shadow_root_entry(struct intel_vgpu_mm *mm,
565 struct intel_gvt_gtt_entry *entry, unsigned long index)
566{
567 _ppgtt_get_root_entry(mm, entry, index, false);
568}
569
570static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
571 struct intel_gvt_gtt_entry *entry, unsigned long index,
572 bool guest)
573{
574 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
575
576 pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
577 mm->ppgtt_mm.shadow_pdps,
578 entry, index, false, 0, mm->vgpu);
579}
580
581static inline void ppgtt_set_guest_root_entry(struct intel_vgpu_mm *mm,
582 struct intel_gvt_gtt_entry *entry, unsigned long index)
583{
584 _ppgtt_set_root_entry(mm, entry, index, true);
585}
586
587static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
588 struct intel_gvt_gtt_entry *entry, unsigned long index)
589{
590 _ppgtt_set_root_entry(mm, entry, index, false);
591}
592
593static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
594 struct intel_gvt_gtt_entry *entry, unsigned long index)
595{
596 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
597
598 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
599
600 entry->type = GTT_TYPE_GGTT_PTE;
601 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
602 false, 0, mm->vgpu);
603}
604
605static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
606 struct intel_gvt_gtt_entry *entry, unsigned long index)
607{
608 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
609
610 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
611
612 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
613 false, 0, mm->vgpu);
614}
615
7598e870
CD		 616static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
617 struct intel_gvt_gtt_entry *entry, unsigned long index)
618{
619 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
620
621 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
622
623 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
624}
625
3aff3512
CD		 626static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
627 struct intel_gvt_gtt_entry *entry, unsigned long index)
628{
629 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
630
631 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
2707e444 632
3aff3512 633 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
2707e444
ZW		 634}
635
636/*
637 * PPGTT shadow page table helpers.
638 */
4b2dbbc2 639static inline int ppgtt_spt_get_entry(
2707e444
ZW		 640 struct intel_vgpu_ppgtt_spt *spt,
641 void *page_table, int type,
642 struct intel_gvt_gtt_entry *e, unsigned long index,
643 bool guest)
644{
645 struct intel_gvt *gvt = spt->vgpu->gvt;
646 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
4b2dbbc2 647 int ret;
2707e444
ZW		 648
649 e->type = get_entry_type(type);
650
651 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 652 return -EINVAL;
2707e444 653
4b2dbbc2 654 ret = ops->get_entry(page_table, e, index, guest,
e502a2af 655 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444 656 spt->vgpu);
4b2dbbc2
CD		 657 if (ret)
658 return ret;
659
40b27176
CD		 660 update_entry_type_for_real(ops, e, guest ?
661 spt->guest_page.pde_ips : false);
bc37ab56
CD		 662
663 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
664 type, e->type, index, e->val64);
4b2dbbc2 665 return 0;
2707e444
ZW		 666}
667
4b2dbbc2 668static inline int ppgtt_spt_set_entry(
2707e444
ZW		 669 struct intel_vgpu_ppgtt_spt *spt,
670 void *page_table, int type,
671 struct intel_gvt_gtt_entry *e, unsigned long index,
672 bool guest)
673{
674 struct intel_gvt *gvt = spt->vgpu->gvt;
675 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
676
677 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
4b2dbbc2 678 return -EINVAL;
2707e444 679
bc37ab56
CD		 680 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
681 type, e->type, index, e->val64);
682
2707e444 683 return ops->set_entry(page_table, e, index, guest,
e502a2af 684 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
2707e444
ZW		 685 spt->vgpu);
686}
687
688#define ppgtt_get_guest_entry(spt, e, index) \
689 ppgtt_spt_get_entry(spt, NULL, \
44b46733 690 spt->guest_page.type, e, index, true)
2707e444
ZW		 691
692#define ppgtt_set_guest_entry(spt, e, index) \
693 ppgtt_spt_set_entry(spt, NULL, \
44b46733 694 spt->guest_page.type, e, index, true)
2707e444
ZW		 695
696#define ppgtt_get_shadow_entry(spt, e, index) \
697 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
698 spt->shadow_page.type, e, index, false)
699
700#define ppgtt_set_shadow_entry(spt, e, index) \
701 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
702 spt->shadow_page.type, e, index, false)
703
44b46733 704static void *alloc_spt(gfp_t gfp_mask)
2707e444 705{
44b46733 706 struct intel_vgpu_ppgtt_spt *spt;
2707e444 707
44b46733
CD		 708 spt = kzalloc(sizeof(*spt), gfp_mask);
709 if (!spt)
710 return NULL;
2707e444 711
44b46733
CD		 712 spt->shadow_page.page = alloc_page(gfp_mask);
713 if (!spt->shadow_page.page) {
714 kfree(spt);
715 return NULL;
716 }
717 return spt;
2707e444
ZW		 718}
719
44b46733 720static void free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 721{
44b46733
CD		 722 __free_page(spt->shadow_page.page);
723 kfree(spt);
2707e444
ZW		 724}
725
7d1e5cdf
ZW		 726static int detach_oos_page(struct intel_vgpu *vgpu,
727 struct intel_vgpu_oos_page *oos_page);
728
d87f5ff3 729static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 730{
44b46733 731 struct device *kdev = &spt->vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 732
44b46733 733 trace_spt_free(spt->vgpu->id, spt, spt->guest_page.type);
7d1e5cdf 734
44b46733
CD		 735 dma_unmap_page(kdev, spt->shadow_page.mfn << I915_GTT_PAGE_SHIFT, 4096,
736 PCI_DMA_BIDIRECTIONAL);
b6c126a3
CD		 737
738 radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
2707e444 739
155521c9
CD		 740 if (spt->guest_page.gfn) {
741 if (spt->guest_page.oos_page)
742 detach_oos_page(spt->vgpu, spt->guest_page.oos_page);
2707e444 743
155521c9
CD		 744 intel_vgpu_unregister_page_track(spt->vgpu, spt->guest_page.gfn);
745 }
2707e444 746
2707e444 747 list_del_init(&spt->post_shadow_list);
2707e444
ZW		 748 free_spt(spt);
749}
750
d87f5ff3 751static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)
2707e444 752{
44b46733 753 struct intel_vgpu_ppgtt_spt *spt;
b6c126a3
CD		 754 struct radix_tree_iter iter;
755 void **slot;
2707e444 756
b6c126a3
CD		 757 radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
758 spt = radix_tree_deref_slot(slot);
d87f5ff3 759 ppgtt_free_spt(spt);
b6c126a3 760 }
2707e444
ZW		 761}
762
7d1e5cdf 763static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 764 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 765 u64 pa, void *p_data, int bytes);
766
e502a2af
CD		 767static int ppgtt_write_protection_handler(
768 struct intel_vgpu_page_track *page_track,
769 u64 gpa, void *data, int bytes)
2707e444 770{
e502a2af
CD		 771 struct intel_vgpu_ppgtt_spt *spt = page_track->priv_data;
772
2707e444
ZW		 773 int ret;
774
775 if (bytes != 4 && bytes != 8)
776 return -EINVAL;
777
e502a2af 778 ret = ppgtt_handle_guest_write_page_table_bytes(spt, gpa, data, bytes);
2707e444
ZW		 779 if (ret)
780 return ret;
781 return ret;
782}
783
44b46733
CD		 784/* Find a spt by guest gfn. */
785static struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_gfn(
786 struct intel_vgpu *vgpu, unsigned long gfn)
787{
788 struct intel_vgpu_page_track *track;
789
e502a2af
CD		 790 track = intel_vgpu_find_page_track(vgpu, gfn);
791 if (track && track->handler == ppgtt_write_protection_handler)
792 return track->priv_data;
44b46733
CD		 793
794 return NULL;
795}
796
797/* Find the spt by shadow page mfn. */
b6c126a3 798static inline struct intel_vgpu_ppgtt_spt *intel_vgpu_find_spt_by_mfn(
44b46733
CD		 799 struct intel_vgpu *vgpu, unsigned long mfn)
800{
b6c126a3 801 return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
44b46733
CD		 802}
803
ede9d0cf 804static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
2707e444 805
155521c9 806/* Allocate shadow page table without guest page. */
d87f5ff3 807static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt(
155521c9 808 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type)
2707e444 809{
44b46733 810 struct device *kdev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2707e444 811 struct intel_vgpu_ppgtt_spt *spt = NULL;
44b46733 812 dma_addr_t daddr;
e502a2af 813 int ret;
2707e444
ZW		 814
815retry:
816 spt = alloc_spt(GFP_KERNEL | __GFP_ZERO);
817 if (!spt) {
ede9d0cf 818 if (reclaim_one_ppgtt_mm(vgpu->gvt))
2707e444
ZW		 819 goto retry;
820
695fbc08 821 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
2707e444
ZW		 822 return ERR_PTR(-ENOMEM);
823 }
824
825 spt->vgpu = vgpu;
2707e444
ZW		 826 atomic_set(&spt->refcount, 1);
827 INIT_LIST_HEAD(&spt->post_shadow_list);
828
829 /*
44b46733 830 * Init shadow_page.
2707e444 831 */
44b46733
CD		 832 spt->shadow_page.type = type;
833 daddr = dma_map_page(kdev, spt->shadow_page.page,
834 0, 4096, PCI_DMA_BIDIRECTIONAL);
835 if (dma_mapping_error(kdev, daddr)) {
836 gvt_vgpu_err("fail to map dma addr\n");
b6c126a3
CD		 837 ret = -EINVAL;
838 goto err_free_spt;
2707e444 839 }
44b46733
CD		 840 spt->shadow_page.vaddr = page_address(spt->shadow_page.page);
841 spt->shadow_page.mfn = daddr >> I915_GTT_PAGE_SHIFT;
2707e444 842
b6c126a3
CD		 843 ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
844 if (ret)
155521c9 845 goto err_unmap_dma;
2707e444 846
44b46733 847 return spt;
b6c126a3 848
b6c126a3
CD		 849err_unmap_dma:
850 dma_unmap_page(kdev, daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
851err_free_spt:
852 free_spt(spt);
853 return ERR_PTR(ret);
2707e444
ZW		 854}
855
155521c9
CD		 856/* Allocate shadow page table associated with specific gfn. */
857static struct intel_vgpu_ppgtt_spt *ppgtt_alloc_spt_gfn(
858 struct intel_vgpu *vgpu, intel_gvt_gtt_type_t type,
859 unsigned long gfn, bool guest_pde_ips)
860{
861 struct intel_vgpu_ppgtt_spt *spt;
862 int ret;
863
864 spt = ppgtt_alloc_spt(vgpu, type);
865 if (IS_ERR(spt))
866 return spt;
867
868 /*
869 * Init guest_page.
870 */
871 ret = intel_vgpu_register_page_track(vgpu, gfn,
872 ppgtt_write_protection_handler, spt);
873 if (ret) {
874 ppgtt_free_spt(spt);
875 return ERR_PTR(ret);
876 }
877
878 spt->guest_page.type = type;
879 spt->guest_page.gfn = gfn;
880 spt->guest_page.pde_ips = guest_pde_ips;
881
882 trace_spt_alloc(vgpu->id, spt, type, spt->shadow_page.mfn, gfn);
883
884 return spt;
885}
886
2707e444
ZW		 887#define pt_entry_size_shift(spt) \
888 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
889
890#define pt_entries(spt) \
9556e118 891 (I915_GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
2707e444
ZW		 892
893#define for_each_present_guest_entry(spt, e, i) \
4c9414d7
CD		 894 for (i = 0; i < pt_entries(spt); \
895 i += spt->guest_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
4b2dbbc2
CD		 896 if (!ppgtt_get_guest_entry(spt, e, i) && \
897 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444
ZW		 898
899#define for_each_present_shadow_entry(spt, e, i) \
4c9414d7
CD		 900 for (i = 0; i < pt_entries(spt); \
901 i += spt->shadow_page.pde_ips ? GTT_64K_PTE_STRIDE : 1) \
4b2dbbc2
CD		 902 if (!ppgtt_get_shadow_entry(spt, e, i) && \
903 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
2707e444 904
d87f5ff3 905static void ppgtt_get_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 906{
907 int v = atomic_read(&spt->refcount);
908
909 trace_spt_refcount(spt->vgpu->id, "inc", spt, v, (v + 1));
910
911 atomic_inc(&spt->refcount);
912}
913
d87f5ff3 914static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 915
d87f5ff3 916static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
2707e444
ZW		 917 struct intel_gvt_gtt_entry *e)
918{
919 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
920 struct intel_vgpu_ppgtt_spt *s;
3b6411c2 921 intel_gvt_gtt_type_t cur_pt_type;
2707e444 922
72f03d7e 923 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(e->type)));
2707e444 924
3b6411c2
PG		 925 if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
926 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
927 cur_pt_type = get_next_pt_type(e->type) + 1;
928 if (ops->get_pfn(e) ==
929 vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
930 return 0;
931 }
44b46733 932 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444 933 if (!s) {
695fbc08
TZ		 934 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
935 ops->get_pfn(e));
2707e444
ZW		 936 return -ENXIO;
937 }
d87f5ff3 938 return ppgtt_invalidate_spt(s);
2707e444
ZW		 939}
940
cf4ee73f
CD		 941static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
942 struct intel_gvt_gtt_entry *entry)
943{
944 struct intel_vgpu *vgpu = spt->vgpu;
945 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
946 unsigned long pfn;
947 int type;
948
949 pfn = ops->get_pfn(entry);
950 type = spt->shadow_page.type;
951
952 if (pfn == vgpu->gtt.scratch_pt[type].page_mfn)
953 return;
954
955 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
956}
957
d87f5ff3 958static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444 959{
695fbc08 960 struct intel_vgpu *vgpu = spt->vgpu;
2707e444
ZW		 961 struct intel_gvt_gtt_entry e;
962 unsigned long index;
963 int ret;
964 int v = atomic_read(&spt->refcount);
965
966 trace_spt_change(spt->vgpu->id, "die", spt,
44b46733 967 spt->guest_page.gfn, spt->shadow_page.type);
2707e444
ZW		 968
969 trace_spt_refcount(spt->vgpu->id, "dec", spt, v, (v - 1));
970
971 if (atomic_dec_return(&spt->refcount) > 0)
972 return 0;
973
2707e444 974 for_each_present_shadow_entry(spt, &e, index) {
72f03d7e
CD		 975 switch (e.type) {
976 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
977 gvt_vdbg_mm("invalidate 4K entry\n");
cf4ee73f
CD		 978 ppgtt_invalidate_pte(spt, &e);
979 break;
b294657d 980 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
eb3a3530
CD		 981 /* We don't setup 64K shadow entry so far. */
982 WARN(1, "suspicious 64K gtt entry\n");
983 continue;
72f03d7e
CD		 984 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
985 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
eb3a3530 986 WARN(1, "GVT doesn't support 2M/1GB page\n");
72f03d7e
CD		 987 continue;
988 case GTT_TYPE_PPGTT_PML4_ENTRY:
989 case GTT_TYPE_PPGTT_PDP_ENTRY:
990 case GTT_TYPE_PPGTT_PDE_ENTRY:
991 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
d87f5ff3 992 ret = ppgtt_invalidate_spt_by_shadow_entry(
72f03d7e
CD		 993 spt->vgpu, &e);
994 if (ret)
995 goto fail;
996 break;
997 default:
998 GEM_BUG_ON(1);
2707e444 999 }
2707e444 1000 }
cf4ee73f 1001
2707e444 1002 trace_spt_change(spt->vgpu->id, "release", spt,
44b46733 1003 spt->guest_page.gfn, spt->shadow_page.type);
d87f5ff3 1004 ppgtt_free_spt(spt);
2707e444
ZW		 1005 return 0;
1006fail:
695fbc08
TZ		 1007 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1008 spt, e.val64, e.type);
2707e444
ZW		 1009 return ret;
1010}
1011
40b27176
CD		 1012static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
1013{
1014 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1015
1016 if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
1017 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
1018 GAMW_ECO_ENABLE_64K_IPS_FIELD;
1019
1020 return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
1021 } else if (INTEL_GEN(dev_priv) >= 11) {
1022 /* 64K paging only controlled by IPS bit in PTE now. */
1023 return true;
1024 } else
1025 return false;
1026}
1027
d87f5ff3 1028static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
2707e444 1029
d87f5ff3 1030static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
2707e444
ZW		 1031 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
1032{
1033 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
44b46733 1034 struct intel_vgpu_ppgtt_spt *spt = NULL;
40b27176 1035 bool ips = false;
2707e444
ZW		 1036 int ret;
1037
72f03d7e 1038 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type)));
2707e444 1039
44b46733
CD		 1040 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we));
1041 if (spt)
d87f5ff3 1042 ppgtt_get_spt(spt);
44b46733 1043 else {
2707e444
ZW		 1044 int type = get_next_pt_type(we->type);
1045
40b27176
CD		 1046 if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1047 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we);
1048
155521c9 1049 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips);
44b46733
CD		 1050 if (IS_ERR(spt)) {
1051 ret = PTR_ERR(spt);
2707e444
ZW		 1052 goto fail;
1053 }
1054
e502a2af 1055 ret = intel_vgpu_enable_page_track(vgpu, spt->guest_page.gfn);
2707e444
ZW		 1056 if (ret)
1057 goto fail;
1058
d87f5ff3 1059 ret = ppgtt_populate_spt(spt);
2707e444
ZW		 1060 if (ret)
1061 goto fail;
1062
44b46733
CD		 1063 trace_spt_change(vgpu->id, "new", spt, spt->guest_page.gfn,
1064 spt->shadow_page.type);
2707e444 1065 }
44b46733 1066 return spt;
2707e444 1067fail:
695fbc08 1068 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
44b46733 1069 spt, we->val64, we->type);
2707e444
ZW		 1070 return ERR_PTR(ret);
1071}
1072
1073static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
1074 struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
1075{
1076 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1077
1078 se->type = ge->type;
1079 se->val64 = ge->val64;
1080
eb3a3530
CD		 1081 /* Because we always split 64KB pages, so clear IPS in shadow PDE. */
1082 if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY)
1083 ops->clear_ips(se);
1084
2707e444
ZW		 1085 ops->set_pfn(se, s->shadow_page.mfn);
1086}
1087
eb3a3530
CD		 1088static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
1089 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1090 struct intel_gvt_gtt_entry *se)
1091{
1092 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1093 struct intel_gvt_gtt_entry entry = *se;
1094 unsigned long start_gfn;
1095 dma_addr_t dma_addr;
1096 int i, ret;
1097
1098 gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1099
1100 GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1101
1102 start_gfn = ops->get_pfn(se);
1103
1104 entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1105 ops->set_64k_splited(&entry);
1106
1107 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1108 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu,
1109 start_gfn + i, &dma_addr);
1110 if (ret)
1111 return ret;
1112
1113 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1114 ppgtt_set_shadow_entry(spt, &entry, index + i);
1115 }
1116 return 0;
1117}
1118
72f03d7e
CD		 1119static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
1120 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1121 struct intel_gvt_gtt_entry *ge)
1122{
1123 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1124 struct intel_gvt_gtt_entry se = *ge;
cf4ee73f
CD		 1125 unsigned long gfn;
1126 dma_addr_t dma_addr;
1127 int ret;
72f03d7e
CD		 1128
1129 if (!pte_ops->test_present(ge))
1130 return 0;
1131
1132 gfn = pte_ops->get_pfn(ge);
1133
1134 switch (ge->type) {
1135 case GTT_TYPE_PPGTT_PTE_4K_ENTRY:
1136 gvt_vdbg_mm("shadow 4K gtt entry\n");
1137 break;
b294657d 1138 case GTT_TYPE_PPGTT_PTE_64K_ENTRY:
eb3a3530
CD		 1139 gvt_vdbg_mm("shadow 64K gtt entry\n");
1140 /*
1141 * The layout of 64K page is special, the page size is
1142 * controlled by uper PDE. To be simple, we always split
1143 * 64K page to smaller 4K pages in shadow PT.
1144 */
1145 return split_64KB_gtt_entry(vgpu, spt, index, &se);
72f03d7e
CD		 1146 case GTT_TYPE_PPGTT_PTE_2M_ENTRY:
1147 case GTT_TYPE_PPGTT_PTE_1G_ENTRY:
eb3a3530 1148 gvt_vgpu_err("GVT doesn't support 2M/1GB entry\n");
72f03d7e
CD		 1149 return -EINVAL;
1150 default:
1151 GEM_BUG_ON(1);
1152 };
1153
1154 /* direct shadow */
cf4ee73f
CD		 1155 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn, &dma_addr);
1156 if (ret)
72f03d7e
CD		 1157 return -ENXIO;
1158
cf4ee73f 1159 pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT);
72f03d7e
CD		 1160 ppgtt_set_shadow_entry(spt, &se, index);
1161 return 0;
1162}
1163
d87f5ff3 1164static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1165{
1166 struct intel_vgpu *vgpu = spt->vgpu;
cc753fbe
HY		 1167 struct intel_gvt *gvt = vgpu->gvt;
1168 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2707e444
ZW		 1169 struct intel_vgpu_ppgtt_spt *s;
1170 struct intel_gvt_gtt_entry se, ge;
cc753fbe 1171 unsigned long gfn, i;
2707e444
ZW		 1172 int ret;
1173
1174 trace_spt_change(spt->vgpu->id, "born", spt,
e502a2af 1175 spt->guest_page.gfn, spt->shadow_page.type);
2707e444 1176
72f03d7e
CD		 1177 for_each_present_guest_entry(spt, &ge, i) {
1178 if (gtt_type_is_pt(get_next_pt_type(ge.type))) {
d87f5ff3 1179 s = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
72f03d7e
CD		 1180 if (IS_ERR(s)) {
1181 ret = PTR_ERR(s);
1182 goto fail;
1183 }
1184 ppgtt_get_shadow_entry(spt, &se, i);
1185 ppgtt_generate_shadow_entry(&se, s, &ge);
1186 ppgtt_set_shadow_entry(spt, &se, i);
1187 } else {
cc753fbe 1188 gfn = ops->get_pfn(&ge);
72f03d7e 1189 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
cc753fbe 1190 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
72f03d7e
CD		 1191 ppgtt_set_shadow_entry(spt, &se, i);
1192 continue;
1193 }
2707e444 1194
72f03d7e
CD		 1195 ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge);
1196 if (ret)
1197 goto fail;
2707e444 1198 }
2707e444
ZW		 1199 }
1200 return 0;
1201fail:
695fbc08
TZ		 1202 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1203 spt, ge.val64, ge.type);
2707e444
ZW		 1204 return ret;
1205}
1206
44b46733 1207static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
6b3816d6 1208 struct intel_gvt_gtt_entry *se, unsigned long index)
2707e444 1209{
2707e444
ZW		 1210 struct intel_vgpu *vgpu = spt->vgpu;
1211 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2707e444
ZW		 1212 int ret;
1213
44b46733
CD		 1214 trace_spt_guest_change(spt->vgpu->id, "remove", spt,
1215 spt->shadow_page.type, se->val64, index);
9baf0920 1216
bc37ab56
CD		 1217 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1218 se->type, index, se->val64);
1219
6b3816d6 1220 if (!ops->test_present(se))
2707e444
ZW		 1221 return 0;
1222
44b46733
CD		 1223 if (ops->get_pfn(se) ==
1224 vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
2707e444
ZW		 1225 return 0;
1226
6b3816d6 1227 if (gtt_type_is_pt(get_next_pt_type(se->type))) {
9baf0920 1228 struct intel_vgpu_ppgtt_spt *s =
44b46733 1229 intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(se));
9baf0920 1230 if (!s) {
695fbc08 1231 gvt_vgpu_err("fail to find guest page\n");
2707e444
ZW		 1232 ret = -ENXIO;
1233 goto fail;
1234 }
d87f5ff3 1235 ret = ppgtt_invalidate_spt(s);
2707e444
ZW		 1236 if (ret)
1237 goto fail;
eb3a3530
CD		 1238 } else {
1239 /* We don't setup 64K shadow entry so far. */
1240 WARN(se->type == GTT_TYPE_PPGTT_PTE_64K_ENTRY,
1241 "suspicious 64K entry\n");
cf4ee73f 1242 ppgtt_invalidate_pte(spt, se);
eb3a3530 1243 }
cf4ee73f 1244
2707e444
ZW		 1245 return 0;
1246fail:
695fbc08 1247 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
6b3816d6 1248 spt, se->val64, se->type);
2707e444
ZW		 1249 return ret;
1250}
1251
44b46733 1252static int ppgtt_handle_guest_entry_add(struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1253 struct intel_gvt_gtt_entry *we, unsigned long index)
1254{
2707e444
ZW		 1255 struct intel_vgpu *vgpu = spt->vgpu;
1256 struct intel_gvt_gtt_entry m;
1257 struct intel_vgpu_ppgtt_spt *s;
1258 int ret;
1259
44b46733
CD		 1260 trace_spt_guest_change(spt->vgpu->id, "add", spt, spt->shadow_page.type,
1261 we->val64, index);
2707e444 1262
bc37ab56
CD		 1263 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1264 we->type, index, we->val64);
1265
2707e444 1266 if (gtt_type_is_pt(get_next_pt_type(we->type))) {
d87f5ff3 1267 s = ppgtt_populate_spt_by_guest_entry(vgpu, we);
2707e444
ZW		 1268 if (IS_ERR(s)) {
1269 ret = PTR_ERR(s);
1270 goto fail;
1271 }
1272 ppgtt_get_shadow_entry(spt, &m, index);
1273 ppgtt_generate_shadow_entry(&m, s, we);
1274 ppgtt_set_shadow_entry(spt, &m, index);
1275 } else {
72f03d7e 1276 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
2707e444
ZW		 1277 if (ret)
1278 goto fail;
2707e444
ZW		 1279 }
1280 return 0;
1281fail:
695fbc08
TZ		 1282 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1283 spt, we->val64, we->type);
2707e444
ZW		 1284 return ret;
1285}
1286
1287static int sync_oos_page(struct intel_vgpu *vgpu,
1288 struct intel_vgpu_oos_page *oos_page)
1289{
1290 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1291 struct intel_gvt *gvt = vgpu->gvt;
1292 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
44b46733 1293 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
72f03d7e 1294 struct intel_gvt_gtt_entry old, new;
2707e444
ZW		 1295 int index;
1296 int ret;
1297
1298 trace_oos_change(vgpu->id, "sync", oos_page->id,
44b46733 1299 spt, spt->guest_page.type);
2707e444 1300
44b46733 1301 old.type = new.type = get_entry_type(spt->guest_page.type);
2707e444
ZW		 1302 old.val64 = new.val64 = 0;
1303
9556e118
ZW		 1304 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1305 info->gtt_entry_size_shift); index++) {
2707e444
ZW		 1306 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1307 ops->get_entry(NULL, &new, index, true,
44b46733 1308 spt->guest_page.gfn << PAGE_SHIFT, vgpu);
2707e444
ZW		 1309
1310 if (old.val64 == new.val64
1311 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1312 continue;
1313
1314 trace_oos_sync(vgpu->id, oos_page->id,
44b46733 1315 spt, spt->guest_page.type,
2707e444
ZW		 1316 new.val64, index);
1317
72f03d7e 1318 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
2707e444
ZW		 1319 if (ret)
1320 return ret;
1321
1322 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
2707e444
ZW		 1323 }
1324
44b46733 1325 spt->guest_page.write_cnt = 0;
2707e444
ZW		 1326 list_del_init(&spt->post_shadow_list);
1327 return 0;
1328}
1329
1330static int detach_oos_page(struct intel_vgpu *vgpu,
1331 struct intel_vgpu_oos_page *oos_page)
1332{
1333 struct intel_gvt *gvt = vgpu->gvt;
44b46733 1334 struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
2707e444
ZW		 1335
1336 trace_oos_change(vgpu->id, "detach", oos_page->id,
44b46733 1337 spt, spt->guest_page.type);
2707e444 1338
44b46733
CD		 1339 spt->guest_page.write_cnt = 0;
1340 spt->guest_page.oos_page = NULL;
1341 oos_page->spt = NULL;
2707e444
ZW		 1342
1343 list_del_init(&oos_page->vm_list);
1344 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1345
1346 return 0;
1347}
1348
44b46733
CD		 1349static int attach_oos_page(struct intel_vgpu_oos_page *oos_page,
1350 struct intel_vgpu_ppgtt_spt *spt)
2707e444 1351{
44b46733 1352 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444
ZW		 1353 int ret;
1354
44b46733
CD		 1355 ret = intel_gvt_hypervisor_read_gpa(spt->vgpu,
1356 spt->guest_page.gfn << I915_GTT_PAGE_SHIFT,
9556e118 1357 oos_page->mem, I915_GTT_PAGE_SIZE);
2707e444
ZW		 1358 if (ret)
1359 return ret;
1360
44b46733
CD		 1361 oos_page->spt = spt;
1362 spt->guest_page.oos_page = oos_page;
2707e444
ZW		 1363
1364 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1365
44b46733
CD		 1366 trace_oos_change(spt->vgpu->id, "attach", oos_page->id,
1367 spt, spt->guest_page.type);
2707e444
ZW		 1368 return 0;
1369}
1370
44b46733 1371static int ppgtt_set_guest_page_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1372{
44b46733 1373 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1374 int ret;
1375
e502a2af 1376 ret = intel_vgpu_enable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1377 if (ret)
1378 return ret;
1379
44b46733
CD		 1380 trace_oos_change(spt->vgpu->id, "set page sync", oos_page->id,
1381 spt, spt->guest_page.type);
2707e444 1382
44b46733
CD		 1383 list_del_init(&oos_page->vm_list);
1384 return sync_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1385}
1386
44b46733 1387static int ppgtt_allocate_oos_page(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1388{
44b46733 1389 struct intel_gvt *gvt = spt->vgpu->gvt;
2707e444 1390 struct intel_gvt_gtt *gtt = &gvt->gtt;
44b46733 1391 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1392 int ret;
1393
1394 WARN(oos_page, "shadow PPGTT page has already has a oos page\n");
1395
1396 if (list_empty(&gtt->oos_page_free_list_head)) {
1397 oos_page = container_of(gtt->oos_page_use_list_head.next,
1398 struct intel_vgpu_oos_page, list);
44b46733 1399 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1400 if (ret)
1401 return ret;
44b46733 1402 ret = detach_oos_page(spt->vgpu, oos_page);
2707e444
ZW		 1403 if (ret)
1404 return ret;
1405 } else
1406 oos_page = container_of(gtt->oos_page_free_list_head.next,
1407 struct intel_vgpu_oos_page, list);
44b46733 1408 return attach_oos_page(oos_page, spt);
2707e444
ZW		 1409}
1410
44b46733 1411static int ppgtt_set_guest_page_oos(struct intel_vgpu_ppgtt_spt *spt)
2707e444 1412{
44b46733 1413 struct intel_vgpu_oos_page *oos_page = spt->guest_page.oos_page;
2707e444
ZW		 1414
1415 if (WARN(!oos_page, "shadow PPGTT page should have a oos page\n"))
1416 return -EINVAL;
1417
44b46733
CD		 1418 trace_oos_change(spt->vgpu->id, "set page out of sync", oos_page->id,
1419 spt, spt->guest_page.type);
2707e444 1420
44b46733 1421 list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
e502a2af 1422 return intel_vgpu_disable_page_track(spt->vgpu, spt->guest_page.gfn);
2707e444
ZW		 1423}
1424
1425/**
1426 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1427 * @vgpu: a vGPU
1428 *
1429 * This function is called before submitting a guest workload to host,
1430 * to sync all the out-of-synced shadow for vGPU
1431 *
1432 * Returns:
1433 * Zero on success, negative error code if failed.
1434 */
1435int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu)
1436{
1437 struct list_head *pos, *n;
1438 struct intel_vgpu_oos_page *oos_page;
1439 int ret;
1440
1441 if (!enable_out_of_sync)
1442 return 0;
1443
1444 list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1445 oos_page = container_of(pos,
1446 struct intel_vgpu_oos_page, vm_list);
44b46733 1447 ret = ppgtt_set_guest_page_sync(oos_page->spt);
2707e444
ZW		 1448 if (ret)
1449 return ret;
1450 }
1451 return 0;
1452}
1453
1454/*
1455 * The heart of PPGTT shadow page table.
1456 */
1457static int ppgtt_handle_guest_write_page_table(
44b46733 1458 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1459 struct intel_gvt_gtt_entry *we, unsigned long index)
1460{
2707e444 1461 struct intel_vgpu *vgpu = spt->vgpu;
6b3816d6 1462 int type = spt->shadow_page.type;
2707e444 1463 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
72f03d7e 1464 struct intel_gvt_gtt_entry old_se;
9baf0920 1465 int new_present;
eb3a3530 1466 int i, ret;
2707e444 1467
2707e444
ZW		 1468 new_present = ops->test_present(we);
1469
6b3816d6
TZ		 1470 /*
1471 * Adding the new entry first and then removing the old one, that can
1472 * guarantee the ppgtt table is validated during the window between
1473 * adding and removal.
1474 */
72f03d7e 1475 ppgtt_get_shadow_entry(spt, &old_se, index);
2707e444 1476
2707e444 1477 if (new_present) {
44b46733 1478 ret = ppgtt_handle_guest_entry_add(spt, we, index);
2707e444
ZW		 1479 if (ret)
1480 goto fail;
1481 }
6b3816d6 1482
44b46733 1483 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
6b3816d6
TZ		 1484 if (ret)
1485 goto fail;
1486
1487 if (!new_present) {
eb3a3530
CD		 1488 /* For 64KB splited entries, we need clear them all. */
1489 if (ops->test_64k_splited(&old_se) &&
1490 !(index % GTT_64K_PTE_STRIDE)) {
1491 gvt_vdbg_mm("remove splited 64K shadow entries\n");
1492 for (i = 0; i < GTT_64K_PTE_STRIDE; i++) {
1493 ops->clear_64k_splited(&old_se);
1494 ops->set_pfn(&old_se,
1495 vgpu->gtt.scratch_pt[type].page_mfn);
1496 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1497 }
1498 } else {
1499 ops->set_pfn(&old_se,
1500 vgpu->gtt.scratch_pt[type].page_mfn);
1501 ppgtt_set_shadow_entry(spt, &old_se, index);
1502 }
6b3816d6
TZ		 1503 }
1504
2707e444
ZW		 1505 return 0;
1506fail:
695fbc08
TZ		 1507 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1508 spt, we->val64, we->type);
2707e444
ZW		 1509 return ret;
1510}
1511
72f03d7e
CD		 1512
1513
44b46733 1514static inline bool can_do_out_of_sync(struct intel_vgpu_ppgtt_spt *spt)
2707e444
ZW		 1515{
1516 return enable_out_of_sync
44b46733
CD		 1517 && gtt_type_is_pte_pt(spt->guest_page.type)
1518 && spt->guest_page.write_cnt >= 2;
2707e444
ZW		 1519}
1520
1521static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt *spt,
1522 unsigned long index)
1523{
1524 set_bit(index, spt->post_shadow_bitmap);
1525 if (!list_empty(&spt->post_shadow_list))
1526 return;
1527
1528 list_add_tail(&spt->post_shadow_list,
1529 &spt->vgpu->gtt.post_shadow_list_head);
1530}
1531
1532/**
1533 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1534 * @vgpu: a vGPU
1535 *
1536 * This function is called before submitting a guest workload to host,
1537 * to flush all the post shadows for a vGPU.
1538 *
1539 * Returns:
1540 * Zero on success, negative error code if failed.
1541 */
1542int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu)
1543{
1544 struct list_head *pos, *n;
1545 struct intel_vgpu_ppgtt_spt *spt;
9baf0920 1546 struct intel_gvt_gtt_entry ge;
2707e444
ZW		 1547 unsigned long index;
1548 int ret;
1549
1550 list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1551 spt = container_of(pos, struct intel_vgpu_ppgtt_spt,
1552 post_shadow_list);
1553
1554 for_each_set_bit(index, spt->post_shadow_bitmap,
1555 GTT_ENTRY_NUM_IN_ONE_PAGE) {
1556 ppgtt_get_guest_entry(spt, &ge, index);
2707e444 1557
44b46733
CD		 1558 ret = ppgtt_handle_guest_write_page_table(spt,
1559 &ge, index);
2707e444
ZW		 1560 if (ret)
1561 return ret;
1562 clear_bit(index, spt->post_shadow_bitmap);
1563 }
1564 list_del_init(&spt->post_shadow_list);
1565 }
1566 return 0;
1567}
1568
7d1e5cdf 1569static int ppgtt_handle_guest_write_page_table_bytes(
44b46733 1570 struct intel_vgpu_ppgtt_spt *spt,
2707e444
ZW		 1571 u64 pa, void *p_data, int bytes)
1572{
2707e444
ZW		 1573 struct intel_vgpu *vgpu = spt->vgpu;
1574 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1575 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
6b3816d6 1576 struct intel_gvt_gtt_entry we, se;
2707e444
ZW		 1577 unsigned long index;
1578 int ret;
1579
1580 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1581
1582 ppgtt_get_guest_entry(spt, &we, index);
2707e444 1583
eb3a3530
CD		 1584 /*
1585 * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1586 * PTE#32, ... PTE#496 are used. Unused PTEs update should be
1587 * ignored.
1588 */
1589 if (we.type == GTT_TYPE_PPGTT_PTE_64K_ENTRY &&
1590 (index % GTT_64K_PTE_STRIDE)) {
1591 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1592 index);
1593 return 0;
1594 }
1595
2707e444 1596 if (bytes == info->gtt_entry_size) {
44b46733 1597 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
2707e444
ZW		 1598 if (ret)
1599 return ret;
1600 } else {
2707e444 1601 if (!test_bit(index, spt->post_shadow_bitmap)) {
121d760d
ZW		 1602 int type = spt->shadow_page.type;
1603
6b3816d6 1604 ppgtt_get_shadow_entry(spt, &se, index);
44b46733 1605 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
2707e444
ZW		 1606 if (ret)
1607 return ret;
121d760d
ZW		 1608 ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1609 ppgtt_set_shadow_entry(spt, &se, index);
2707e444 1610 }
2707e444 1611 ppgtt_set_post_shadow(spt, index);
2707e444
ZW		 1612 }
1613
1614 if (!enable_out_of_sync)
1615 return 0;
1616
44b46733 1617 spt->guest_page.write_cnt++;
2707e444 1618
44b46733
CD		 1619 if (spt->guest_page.oos_page)
1620 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
2707e444
ZW		 1621 false, 0, vgpu);
1622
44b46733
CD		 1623 if (can_do_out_of_sync(spt)) {
1624 if (!spt->guest_page.oos_page)
1625 ppgtt_allocate_oos_page(spt);
2707e444 1626
44b46733 1627 ret = ppgtt_set_guest_page_oos(spt);
2707e444
ZW		 1628 if (ret < 0)
1629 return ret;
1630 }
1631 return 0;
1632}
1633
ede9d0cf 1634static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1635{
1636 struct intel_vgpu *vgpu = mm->vgpu;
1637 struct intel_gvt *gvt = vgpu->gvt;
1638 struct intel_gvt_gtt *gtt = &gvt->gtt;
1639 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1640 struct intel_gvt_gtt_entry se;
ede9d0cf 1641 int index;
2707e444 1642
ede9d0cf 1643 if (!mm->ppgtt_mm.shadowed)
2707e444
ZW		 1644 return;
1645
ede9d0cf
CD		 1646 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1647 ppgtt_get_shadow_root_entry(mm, &se, index);
1648
2707e444
ZW		 1649 if (!ops->test_present(&se))
1650 continue;
ede9d0cf 1651
d87f5ff3 1652 ppgtt_invalidate_spt_by_shadow_entry(vgpu, &se);
2707e444 1653 se.val64 = 0;
ede9d0cf 1654 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1655
44b46733
CD		 1656 trace_spt_guest_change(vgpu->id, "destroy root pointer",
1657 NULL, se.type, se.val64, index);
2707e444 1658 }
2707e444 1659
ede9d0cf 1660 mm->ppgtt_mm.shadowed = false;
2707e444
ZW		 1661}
1662
ede9d0cf
CD		 1663
1664static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
2707e444
ZW		 1665{
1666 struct intel_vgpu *vgpu = mm->vgpu;
1667 struct intel_gvt *gvt = vgpu->gvt;
1668 struct intel_gvt_gtt *gtt = &gvt->gtt;
1669 struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1670 struct intel_vgpu_ppgtt_spt *spt;
1671 struct intel_gvt_gtt_entry ge, se;
ede9d0cf 1672 int index, ret;
2707e444 1673
ede9d0cf 1674 if (mm->ppgtt_mm.shadowed)
2707e444
ZW		 1675 return 0;
1676
ede9d0cf
CD		 1677 mm->ppgtt_mm.shadowed = true;
1678
1679 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1680 ppgtt_get_guest_root_entry(mm, &ge, index);
2707e444 1681
2707e444
ZW		 1682 if (!ops->test_present(&ge))
1683 continue;
1684
44b46733
CD		 1685 trace_spt_guest_change(vgpu->id, __func__, NULL,
1686 ge.type, ge.val64, index);
2707e444 1687
d87f5ff3 1688 spt = ppgtt_populate_spt_by_guest_entry(vgpu, &ge);
2707e444 1689 if (IS_ERR(spt)) {
695fbc08 1690 gvt_vgpu_err("fail to populate guest root pointer\n");
2707e444
ZW		 1691 ret = PTR_ERR(spt);
1692 goto fail;
1693 }
1694 ppgtt_generate_shadow_entry(&se, spt, &ge);
ede9d0cf 1695 ppgtt_set_shadow_root_entry(mm, &se, index);
2707e444 1696
44b46733
CD		 1697 trace_spt_guest_change(vgpu->id, "populate root pointer",
1698 NULL, se.type, se.val64, index);
2707e444 1699 }
ede9d0cf 1700
2707e444
ZW		 1701 return 0;
1702fail:
ede9d0cf 1703 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1704 return ret;
1705}
1706
ede9d0cf
CD		 1707static struct intel_vgpu_mm *vgpu_alloc_mm(struct intel_vgpu *vgpu)
1708{
1709 struct intel_vgpu_mm *mm;
1710
1711 mm = kzalloc(sizeof(*mm), GFP_KERNEL);
1712 if (!mm)
1713 return NULL;
1714
1715 mm->vgpu = vgpu;
1716 kref_init(&mm->ref);
1717 atomic_set(&mm->pincount, 0);
1718
1719 return mm;
1720}
1721
1722static void vgpu_free_mm(struct intel_vgpu_mm *mm)
1723{
1724 kfree(mm);
1725}
1726
2707e444 1727/**
ede9d0cf 1728 * intel_vgpu_create_ppgtt_mm - create a ppgtt mm object for a vGPU
2707e444 1729 * @vgpu: a vGPU
ede9d0cf
CD		 1730 * @root_entry_type: ppgtt root entry type
1731 * @pdps: guest pdps.
2707e444 1732 *
ede9d0cf 1733 * This function is used to create a ppgtt mm object for a vGPU.
2707e444
ZW		 1734 *
1735 * Returns:
1736 * Zero on success, negative error code in pointer if failed.
1737 */
ede9d0cf
CD		 1738struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
1739 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444
ZW		 1740{
1741 struct intel_gvt *gvt = vgpu->gvt;
2707e444
ZW		 1742 struct intel_vgpu_mm *mm;
1743 int ret;
1744
ede9d0cf
CD		 1745 mm = vgpu_alloc_mm(vgpu);
1746 if (!mm)
1747 return ERR_PTR(-ENOMEM);
2707e444 1748
ede9d0cf 1749 mm->type = INTEL_GVT_MM_PPGTT;
2707e444 1750
ede9d0cf
CD		 1751 GEM_BUG_ON(root_entry_type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY &&
1752 root_entry_type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY);
1753 mm->ppgtt_mm.root_entry_type = root_entry_type;
2707e444 1754
ede9d0cf
CD		 1755 INIT_LIST_HEAD(&mm->ppgtt_mm.list);
1756 INIT_LIST_HEAD(&mm->ppgtt_mm.lru_list);
2707e444 1757
ede9d0cf
CD		 1758 if (root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
1759 mm->ppgtt_mm.guest_pdps[0] = pdps[0];
1760 else
1761 memcpy(mm->ppgtt_mm.guest_pdps, pdps,
1762 sizeof(mm->ppgtt_mm.guest_pdps));
2707e444 1763
ede9d0cf 1764 ret = shadow_ppgtt_mm(mm);
2707e444 1765 if (ret) {
ede9d0cf
CD		 1766 gvt_vgpu_err("failed to shadow ppgtt mm\n");
1767 vgpu_free_mm(mm);
1768 return ERR_PTR(ret);
2707e444
ZW		 1769 }
1770
ede9d0cf
CD		 1771 list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1772 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1773 return mm;
1774}
2707e444 1775
ede9d0cf
CD		 1776static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
1777{
1778 struct intel_vgpu_mm *mm;
1779 unsigned long nr_entries;
2707e444 1780
ede9d0cf
CD		 1781 mm = vgpu_alloc_mm(vgpu);
1782 if (!mm)
1783 return ERR_PTR(-ENOMEM);
1784
1785 mm->type = INTEL_GVT_MM_GGTT;
1786
1787 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1788 mm->ggtt_mm.virtual_ggtt = vzalloc(nr_entries *
1789 vgpu->gvt->device_info.gtt_entry_size);
1790 if (!mm->ggtt_mm.virtual_ggtt) {
1791 vgpu_free_mm(mm);
1792 return ERR_PTR(-ENOMEM);
2707e444 1793 }
ede9d0cf 1794
2707e444 1795 return mm;
ede9d0cf
CD		 1796}
1797
1798/**
1bc25851 1799 * _intel_vgpu_mm_release - destroy a mm object
ede9d0cf
CD		 1800 * @mm_ref: a kref object
1801 *
1802 * This function is used to destroy a mm object for vGPU
1803 *
1804 */
1bc25851 1805void _intel_vgpu_mm_release(struct kref *mm_ref)
ede9d0cf
CD		 1806{
1807 struct intel_vgpu_mm *mm = container_of(mm_ref, typeof(*mm), ref);
1808
1809 if (GEM_WARN_ON(atomic_read(&mm->pincount)))
1810 gvt_err("vgpu mm pin count bug detected\n");
1811
1812 if (mm->type == INTEL_GVT_MM_PPGTT) {
1813 list_del(&mm->ppgtt_mm.list);
1814 list_del(&mm->ppgtt_mm.lru_list);
1815 invalidate_ppgtt_mm(mm);
1816 } else {
1817 vfree(mm->ggtt_mm.virtual_ggtt);
1818 }
1819
1820 vgpu_free_mm(mm);
2707e444
ZW		 1821}
1822
1823/**
1824 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1825 * @mm: a vGPU mm object
1826 *
1827 * This function is called when user doesn't want to use a vGPU mm object
1828 */
1829void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
1830{
2707e444
ZW		 1831 atomic_dec(&mm->pincount);
1832}
1833
1834/**
1835 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1836 * @vgpu: a vGPU
1837 *
1838 * This function is called when user wants to use a vGPU mm object. If this
1839 * mm object hasn't been shadowed yet, the shadow will be populated at this
1840 * time.
1841 *
1842 * Returns:
1843 * Zero on success, negative error code if failed.
1844 */
1845int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm)
1846{
1847 int ret;
1848
ede9d0cf 1849 atomic_inc(&mm->pincount);
2707e444 1850
ede9d0cf
CD		 1851 if (mm->type == INTEL_GVT_MM_PPGTT) {
1852 ret = shadow_ppgtt_mm(mm);
2707e444
ZW		 1853 if (ret)
1854 return ret;
ede9d0cf
CD		 1855
1856 list_move_tail(&mm->ppgtt_mm.lru_list,
1857 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
1858
2707e444
ZW		 1859 }
1860
2707e444
ZW		 1861 return 0;
1862}
1863
ede9d0cf 1864static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2707e444
ZW		 1865{
1866 struct intel_vgpu_mm *mm;
1867 struct list_head *pos, *n;
1868
ede9d0cf
CD		 1869 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
1870 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.lru_list);
2707e444 1871
2707e444
ZW		 1872 if (atomic_read(&mm->pincount))
1873 continue;
1874
ede9d0cf
CD		 1875 list_del_init(&mm->ppgtt_mm.lru_list);
1876 invalidate_ppgtt_mm(mm);
2707e444
ZW		 1877 return 1;
1878 }
1879 return 0;
1880}
1881
1882/*
1883 * GMA translation APIs.
1884 */
1885static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
1886 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
1887{
1888 struct intel_vgpu *vgpu = mm->vgpu;
1889 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1890 struct intel_vgpu_ppgtt_spt *s;
1891
44b46733 1892 s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
2707e444
ZW		 1893 if (!s)
1894 return -ENXIO;
1895
1896 if (!guest)
1897 ppgtt_get_shadow_entry(s, e, index);
1898 else
1899 ppgtt_get_guest_entry(s, e, index);
1900 return 0;
1901}
1902
1903/**
1904 * intel_vgpu_gma_to_gpa - translate a gma to GPA
1905 * @mm: mm object. could be a PPGTT or GGTT mm object
1906 * @gma: graphics memory address in this mm object
1907 *
1908 * This function is used to translate a graphics memory address in specific
1909 * graphics memory space to guest physical address.
1910 *
1911 * Returns:
1912 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
1913 */
1914unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
1915{
1916 struct intel_vgpu *vgpu = mm->vgpu;
1917 struct intel_gvt *gvt = vgpu->gvt;
1918 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
1919 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
1920 unsigned long gpa = INTEL_GVT_INVALID_ADDR;
1921 unsigned long gma_index[4];
1922 struct intel_gvt_gtt_entry e;
ede9d0cf 1923 int i, levels = 0;
2707e444
ZW		 1924 int ret;
1925
ede9d0cf
CD		 1926 GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT &&
1927 mm->type != INTEL_GVT_MM_PPGTT);
2707e444
ZW		 1928
1929 if (mm->type == INTEL_GVT_MM_GGTT) {
1930 if (!vgpu_gmadr_is_valid(vgpu, gma))
1931 goto err;
1932
ede9d0cf
CD		 1933 ggtt_get_guest_entry(mm, &e,
1934 gma_ops->gma_to_ggtt_pte_index(gma));
1935
9556e118
ZW		 1936 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT)
1937 + (gma & ~I915_GTT_PAGE_MASK);
2707e444
ZW		 1938
1939 trace_gma_translate(vgpu->id, "ggtt", 0, 0, gma, gpa);
ede9d0cf
CD		 1940 } else {
1941 switch (mm->ppgtt_mm.root_entry_type) {
1942 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
1943 ppgtt_get_shadow_root_entry(mm, &e, 0);
1944
1945 gma_index[0] = gma_ops->gma_to_pml4_index(gma);
1946 gma_index[1] = gma_ops->gma_to_l4_pdp_index(gma);
1947 gma_index[2] = gma_ops->gma_to_pde_index(gma);
1948 gma_index[3] = gma_ops->gma_to_pte_index(gma);
1949 levels = 4;
1950 break;
1951 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
1952 ppgtt_get_shadow_root_entry(mm, &e,
1953 gma_ops->gma_to_l3_pdp_index(gma));
1954
1955 gma_index[0] = gma_ops->gma_to_pde_index(gma);
1956 gma_index[1] = gma_ops->gma_to_pte_index(gma);
1957 levels = 2;
1958 break;
1959 default:
1960 GEM_BUG_ON(1);
1961 }
2707e444 1962
ede9d0cf
CD		 1963 /* walk the shadow page table and get gpa from guest entry */
1964 for (i = 0; i < levels; i++) {
1965 ret = ppgtt_get_next_level_entry(mm, &e, gma_index[i],
1966 (i == levels - 1));
1967 if (ret)
1968 goto err;
4b2dbbc2 1969
ede9d0cf
CD		 1970 if (!pte_ops->test_present(&e)) {
1971 gvt_dbg_core("GMA 0x%lx is not present\n", gma);
1972 goto err;
1973 }
4b2dbbc2 1974 }
2707e444 1975
ede9d0cf
CD		 1976 gpa = (pte_ops->get_pfn(&e) << I915_GTT_PAGE_SHIFT) +
1977 (gma & ~I915_GTT_PAGE_MASK);
1978 trace_gma_translate(vgpu->id, "ppgtt", 0,
1979 mm->ppgtt_mm.root_entry_type, gma, gpa);
1980 }
2707e444 1981
2707e444
ZW		 1982 return gpa;
1983err:
695fbc08 1984 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm->type, gma);
2707e444
ZW		 1985 return INTEL_GVT_INVALID_ADDR;
1986}
1987
a143cef7 1988static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
2707e444
ZW		 1989 unsigned int off, void *p_data, unsigned int bytes)
1990{
1991 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
1992 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1993 unsigned long index = off >> info->gtt_entry_size_shift;
1994 struct intel_gvt_gtt_entry e;
1995
1996 if (bytes != 4 && bytes != 8)
1997 return -EINVAL;
1998
1999 ggtt_get_guest_entry(ggtt_mm, &e, index);
2000 memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
2001 bytes);
2002 return 0;
2003}
2004
2005/**
2006 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
2007 * @vgpu: a vGPU
2008 * @off: register offset
2009 * @p_data: data will be returned to guest
2010 * @bytes: data length
2011 *
2012 * This function is used to emulate the GTT MMIO register read
2013 *
2014 * Returns:
2015 * Zero on success, error code if failed.
2016 */
a143cef7 2017int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 2018 void *p_data, unsigned int bytes)
2019{
2020 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2021 int ret;
2022
2023 if (bytes != 4 && bytes != 8)
2024 return -EINVAL;
2025
2026 off -= info->gtt_start_offset;
a143cef7 2027 ret = emulate_ggtt_mmio_read(vgpu, off, p_data, bytes);
2707e444
ZW		 2028 return ret;
2029}
2030
7598e870
CD		 2031static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
2032 struct intel_gvt_gtt_entry *entry)
2033{
2034 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2035 unsigned long pfn;
2036
2037 pfn = pte_ops->get_pfn(entry);
2038 if (pfn != vgpu->gvt->gtt.scratch_mfn)
2039 intel_gvt_hypervisor_dma_unmap_guest_page(vgpu,
2040 pfn << PAGE_SHIFT);
2041}
2042
a143cef7 2043static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
2707e444
ZW		 2044 void *p_data, unsigned int bytes)
2045{
2046 struct intel_gvt *gvt = vgpu->gvt;
2047 const struct intel_gvt_device_info *info = &gvt->device_info;
2048 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2049 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2050 unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
cf4ee73f 2051 unsigned long gma, gfn;
2707e444 2052 struct intel_gvt_gtt_entry e, m;
cf4ee73f
CD		 2053 dma_addr_t dma_addr;
2054 int ret;
2707e444
ZW		 2055
2056 if (bytes != 4 && bytes != 8)
2057 return -EINVAL;
2058
9556e118 2059 gma = g_gtt_index << I915_GTT_PAGE_SHIFT;
2707e444
ZW		 2060
2061 /* the VM may configure the whole GM space when ballooning is used */
7c28135c 2062 if (!vgpu_gmadr_is_valid(vgpu, gma))
2707e444 2063 return 0;
2707e444
ZW		 2064
2065 ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
2066
2067 memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
2068 bytes);
2069
2070 if (ops->test_present(&e)) {
cc753fbe 2071 gfn = ops->get_pfn(&e);
7598e870 2072 m = e;
cc753fbe
HY		 2073
2074 /* one PTE update may be issued in multiple writes and the
2075 * first write may not construct a valid gfn
2076 */
2077 if (!intel_gvt_hypervisor_is_valid_gfn(vgpu, gfn)) {
2078 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2079 goto out;
2080 }
2081
cf4ee73f
CD		 2082 ret = intel_gvt_hypervisor_dma_map_guest_page(vgpu, gfn,
2083 &dma_addr);
2084 if (ret) {
72f03d7e 2085 gvt_vgpu_err("fail to populate guest ggtt entry\n");
359b6931
XC		 2086 /* guest driver may read/write the entry when partial
2087 * update the entry in this situation p2m will fail
2088 * settting the shadow entry to point to a scratch page
2089 */
22115cef 2090 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
72f03d7e 2091 } else
cf4ee73f 2092 ops->set_pfn(&m, dma_addr >> PAGE_SHIFT);
7598e870
CD		 2093 } else {
2094 ggtt_get_host_entry(ggtt_mm, &m, g_gtt_index);
2095 ggtt_invalidate_pte(vgpu, &m);
22115cef 2096 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
7598e870
CD		 2097 ops->clear_present(&m);
2098 }
2707e444 2099
cc753fbe 2100out:
3aff3512 2101 ggtt_set_host_entry(ggtt_mm, &m, g_gtt_index);
a143cef7 2102 ggtt_invalidate(gvt->dev_priv);
2707e444
ZW		 2103 ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index);
2104 return 0;
2105}
2106
2107/*
a143cef7 2108 * intel_vgpu_emulate_ggtt_mmio_write - emulate GTT MMIO register write
2707e444
ZW		 2109 * @vgpu: a vGPU
2110 * @off: register offset
2111 * @p_data: data from guest write
2112 * @bytes: data length
2113 *
2114 * This function is used to emulate the GTT MMIO register write
2115 *
2116 * Returns:
2117 * Zero on success, error code if failed.
2118 */
a143cef7
CD		 2119int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
2120 unsigned int off, void *p_data, unsigned int bytes)
2707e444
ZW		 2121{
2122 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2123 int ret;
2124
2125 if (bytes != 4 && bytes != 8)
2126 return -EINVAL;
2127
2128 off -= info->gtt_start_offset;
a143cef7 2129 ret = emulate_ggtt_mmio_write(vgpu, off, p_data, bytes);
2707e444
ZW		 2130 return ret;
2131}
2132
3b6411c2
PG		 2133static int alloc_scratch_pages(struct intel_vgpu *vgpu,
2134 intel_gvt_gtt_type_t type)
2707e444
ZW		 2135{
2136 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
3b6411c2 2137 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
5c35258d 2138 int page_entry_num = I915_GTT_PAGE_SIZE >>
3b6411c2 2139 vgpu->gvt->device_info.gtt_entry_size_shift;
9631739f 2140 void *scratch_pt;
3b6411c2 2141 int i;
5de6bd4c
CD		 2142 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2143 dma_addr_t daddr;
2707e444 2144
3b6411c2
PG		 2145 if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2146 return -EINVAL;
2147
9631739f 2148 scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
3b6411c2 2149 if (!scratch_pt) {
695fbc08 2150 gvt_vgpu_err("fail to allocate scratch page\n");
2707e444
ZW		 2151 return -ENOMEM;
2152 }
2153
5de6bd4c
CD		 2154 daddr = dma_map_page(dev, virt_to_page(scratch_pt), 0,
2155 4096, PCI_DMA_BIDIRECTIONAL);
2156 if (dma_mapping_error(dev, daddr)) {
695fbc08 2157 gvt_vgpu_err("fail to dmamap scratch_pt\n");
5de6bd4c
CD		 2158 __free_page(virt_to_page(scratch_pt));
2159 return -ENOMEM;
3b6411c2 2160 }
5de6bd4c 2161 gtt->scratch_pt[type].page_mfn =
5c35258d 2162 (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
9631739f 2163 gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
3b6411c2 2164 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
5de6bd4c 2165 vgpu->id, type, gtt->scratch_pt[type].page_mfn);
3b6411c2
PG		 2166
2167 /* Build the tree by full filled the scratch pt with the entries which
2168 * point to the next level scratch pt or scratch page. The
2169 * scratch_pt[type] indicate the scratch pt/scratch page used by the
2170 * 'type' pt.
2171 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
9631739f 2172 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
3b6411c2
PG		 2173 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
2174 */
65957195 2175 if (type > GTT_TYPE_PPGTT_PTE_PT) {
3b6411c2
PG		 2176 struct intel_gvt_gtt_entry se;
2177
2178 memset(&se, 0, sizeof(struct intel_gvt_gtt_entry));
2179 se.type = get_entry_type(type - 1);
2180 ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2181
2182 /* The entry parameters like present/writeable/cache type
2183 * set to the same as i915's scratch page tree.
2184 */
2185 se.val64 |= _PAGE_PRESENT | _PAGE_RW;
2186 if (type == GTT_TYPE_PPGTT_PDE_PT)
c095b97c 2187 se.val64 |= PPAT_CACHED;
3b6411c2
PG		 2188
2189 for (i = 0; i < page_entry_num; i++)
9631739f 2190 ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
3b6411c2
PG		 2191 }
2192
3b6411c2
PG		 2193 return 0;
2194}
2707e444 2195
3b6411c2
PG		 2196static int release_scratch_page_tree(struct intel_vgpu *vgpu)
2197{
2198 int i;
5de6bd4c
CD		 2199 struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
2200 dma_addr_t daddr;
3b6411c2
PG		 2201
2202 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2203 if (vgpu->gtt.scratch_pt[i].page != NULL) {
5de6bd4c 2204 daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
5c35258d 2205 I915_GTT_PAGE_SHIFT);
5de6bd4c 2206 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
3b6411c2
PG		 2207 __free_page(vgpu->gtt.scratch_pt[i].page);
2208 vgpu->gtt.scratch_pt[i].page = NULL;
2209 vgpu->gtt.scratch_pt[i].page_mfn = 0;
2210 }
2707e444
ZW		 2211 }
2212
2707e444
ZW		 2213 return 0;
2214}
2215
3b6411c2 2216static int create_scratch_page_tree(struct intel_vgpu *vgpu)
2707e444 2217{
3b6411c2
PG		 2218 int i, ret;
2219
2220 for (i = GTT_TYPE_PPGTT_PTE_PT; i < GTT_TYPE_MAX; i++) {
2221 ret = alloc_scratch_pages(vgpu, i);
2222 if (ret)
2223 goto err;
2707e444 2224 }
3b6411c2
PG		 2225
2226 return 0;
2227
2228err:
2229 release_scratch_page_tree(vgpu);
2230 return ret;
2707e444
ZW		 2231}
2232
2233/**
2234 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2235 * @vgpu: a vGPU
2236 *
2237 * This function is used to initialize per-vGPU graphics memory virtualization
2238 * components.
2239 *
2240 * Returns:
2241 * Zero on success, error code if failed.
2242 */
2243int intel_vgpu_init_gtt(struct intel_vgpu *vgpu)
2244{
2245 struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2707e444 2246
b6c126a3 2247 INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2707e444 2248
ede9d0cf 2249 INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2707e444
ZW		 2250 INIT_LIST_HEAD(&gtt->oos_page_list_head);
2251 INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2252
ede9d0cf
CD		 2253 gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2254 if (IS_ERR(gtt->ggtt_mm)) {
695fbc08 2255 gvt_vgpu_err("fail to create mm for ggtt.\n");
ede9d0cf 2256 return PTR_ERR(gtt->ggtt_mm);
2707e444
ZW		 2257 }
2258
f4c43db3 2259 intel_vgpu_reset_ggtt(vgpu, false);
2707e444 2260
3b6411c2 2261 return create_scratch_page_tree(vgpu);
2707e444
ZW		 2262}
2263
ede9d0cf 2264static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
da9cc8de
PG		 2265{
2266 struct list_head *pos, *n;
2267 struct intel_vgpu_mm *mm;
2268
ede9d0cf
CD		 2269 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2270 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
1bc25851 2271 intel_vgpu_destroy_mm(mm);
da9cc8de 2272 }
ede9d0cf
CD		 2273
2274 if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
84f69ba0 2275 gvt_err("vgpu ppgtt mm is not fully destroyed\n");
ede9d0cf 2276
b6c126a3 2277 if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
ede9d0cf 2278 gvt_err("Why we still has spt not freed?\n");
d87f5ff3 2279 ppgtt_free_all_spt(vgpu);
ede9d0cf
CD		 2280 }
2281}
2282
2283static void intel_vgpu_destroy_ggtt_mm(struct intel_vgpu *vgpu)
2284{
1bc25851 2285 intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
ede9d0cf 2286 vgpu->gtt.ggtt_mm = NULL;
da9cc8de
PG		 2287}
2288
2707e444
ZW		 2289/**
2290 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2291 * @vgpu: a vGPU
2292 *
2293 * This function is used to clean up per-vGPU graphics memory virtualization
2294 * components.
2295 *
2296 * Returns:
2297 * Zero on success, error code if failed.
2298 */
2299void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)
2300{
ede9d0cf
CD		 2301 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
2302 intel_vgpu_destroy_ggtt_mm(vgpu);
3b6411c2 2303 release_scratch_page_tree(vgpu);
2707e444
ZW		 2304}
2305
2306static void clean_spt_oos(struct intel_gvt *gvt)
2307{
2308 struct intel_gvt_gtt *gtt = &gvt->gtt;
2309 struct list_head *pos, *n;
2310 struct intel_vgpu_oos_page *oos_page;
2311
2312 WARN(!list_empty(&gtt->oos_page_use_list_head),
2313 "someone is still using oos page\n");
2314
2315 list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2316 oos_page = container_of(pos, struct intel_vgpu_oos_page, list);
2317 list_del(&oos_page->list);
2318 kfree(oos_page);
2319 }
2320}
2321
2322static int setup_spt_oos(struct intel_gvt *gvt)
2323{
2324 struct intel_gvt_gtt *gtt = &gvt->gtt;
2325 struct intel_vgpu_oos_page *oos_page;
2326 int i;
2327 int ret;
2328
2329 INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2330 INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2331
2332 for (i = 0; i < preallocated_oos_pages; i++) {
2333 oos_page = kzalloc(sizeof(*oos_page), GFP_KERNEL);
2334 if (!oos_page) {
2707e444
ZW		 2335 ret = -ENOMEM;
2336 goto fail;
2337 }
2338
2339 INIT_LIST_HEAD(&oos_page->list);
2340 INIT_LIST_HEAD(&oos_page->vm_list);
2341 oos_page->id = i;
2342 list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2343 }
2344
2345 gvt_dbg_mm("%d oos pages preallocated\n", i);
2346
2347 return 0;
2348fail:
2349 clean_spt_oos(gvt);
2350 return ret;
2351}
2352
2353/**
2354 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2355 * @vgpu: a vGPU
2356 * @page_table_level: PPGTT page table level
2357 * @root_entry: PPGTT page table root pointers
2358 *
2359 * This function is used to find a PPGTT mm object from mm object pool
2360 *
2361 * Returns:
2362 * pointer to mm object on success, NULL if failed.
2363 */
2364struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2365 u64 pdps[])
2707e444 2366{
2707e444 2367 struct intel_vgpu_mm *mm;
ede9d0cf 2368 struct list_head *pos;
2707e444 2369
ede9d0cf
CD		 2370 list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2371 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2707e444 2372
ede9d0cf
CD		 2373 switch (mm->ppgtt_mm.root_entry_type) {
2374 case GTT_TYPE_PPGTT_ROOT_L4_ENTRY:
2375 if (pdps[0] == mm->ppgtt_mm.guest_pdps[0])
2707e444 2376 return mm;
ede9d0cf
CD		 2377 break;
2378 case GTT_TYPE_PPGTT_ROOT_L3_ENTRY:
2379 if (!memcmp(pdps, mm->ppgtt_mm.guest_pdps,
2380 sizeof(mm->ppgtt_mm.guest_pdps)))
2707e444 2381 return mm;
ede9d0cf
CD		 2382 break;
2383 default:
2384 GEM_BUG_ON(1);
2707e444
ZW		 2385 }
2386 }
2387 return NULL;
2388}
2389
2390/**
e6e9c46f 2391 * intel_vgpu_get_ppgtt_mm - get or create a PPGTT mm object.
2707e444 2392 * @vgpu: a vGPU
ede9d0cf
CD		 2393 * @root_entry_type: ppgtt root entry type
2394 * @pdps: guest pdps
2707e444 2395 *
e6e9c46f 2396 * This function is used to find or create a PPGTT mm object from a guest.
2707e444
ZW		 2397 *
2398 * Returns:
2399 * Zero on success, negative error code if failed.
2400 */
e6e9c46f 2401struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
ede9d0cf 2402 intel_gvt_gtt_type_t root_entry_type, u64 pdps[])
2707e444 2403{
2707e444
ZW		 2404 struct intel_vgpu_mm *mm;
2405
ede9d0cf 2406 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2407 if (mm) {
1bc25851 2408 intel_vgpu_mm_get(mm);
2707e444 2409 } else {
ede9d0cf 2410 mm = intel_vgpu_create_ppgtt_mm(vgpu, root_entry_type, pdps);
e6e9c46f 2411 if (IS_ERR(mm))
695fbc08 2412 gvt_vgpu_err("fail to create mm\n");
2707e444 2413 }
e6e9c46f 2414 return mm;
2707e444
ZW		 2415}
2416
2417/**
e6e9c46f 2418 * intel_vgpu_put_ppgtt_mm - find and put a PPGTT mm object.
2707e444 2419 * @vgpu: a vGPU
ede9d0cf 2420 * @pdps: guest pdps
2707e444 2421 *
e6e9c46f 2422 * This function is used to find a PPGTT mm object from a guest and destroy it.
2707e444
ZW		 2423 *
2424 * Returns:
2425 * Zero on success, negative error code if failed.
2426 */
e6e9c46f 2427int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[])
2707e444 2428{
2707e444
ZW		 2429 struct intel_vgpu_mm *mm;
2430
ede9d0cf 2431 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
2707e444 2432 if (!mm) {
695fbc08 2433 gvt_vgpu_err("fail to find ppgtt instance.\n");
2707e444
ZW		 2434 return -EINVAL;
2435 }
1bc25851 2436 intel_vgpu_mm_put(mm);
2707e444
ZW		 2437 return 0;
2438}
2439
2440/**
2441 * intel_gvt_init_gtt - initialize mm components of a GVT device
2442 * @gvt: GVT device
2443 *
2444 * This function is called at the initialization stage, to initialize
2445 * the mm components of a GVT device.
2446 *
2447 * Returns:
2448 * zero on success, negative error code if failed.
2449 */
2450int intel_gvt_init_gtt(struct intel_gvt *gvt)
2451{
2452 int ret;
9631739f 2453 void *page;
5de6bd4c
CD		 2454 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
2455 dma_addr_t daddr;
2707e444
ZW		 2456
2457 gvt_dbg_core("init gtt\n");
2458
665004b8
CX		 2459 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2460 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2707e444 2461
9631739f
JS		 2462 page = (void *)get_zeroed_page(GFP_KERNEL);
2463 if (!page) {
d650ac06
PG		 2464 gvt_err("fail to allocate scratch ggtt page\n");
2465 return -ENOMEM;
2466 }
2467
5de6bd4c
CD		 2468 daddr = dma_map_page(dev, virt_to_page(page), 0,
2469 4096, PCI_DMA_BIDIRECTIONAL);
2470 if (dma_mapping_error(dev, daddr)) {
2471 gvt_err("fail to dmamap scratch ggtt page\n");
2472 __free_page(virt_to_page(page));
2473 return -ENOMEM;
d650ac06 2474 }
22115cef
ZW		 2475
2476 gvt->gtt.scratch_page = virt_to_page(page);
2477 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
d650ac06 2478
2707e444
ZW		 2479 if (enable_out_of_sync) {
2480 ret = setup_spt_oos(gvt);
2481 if (ret) {
2482 gvt_err("fail to initialize SPT oos\n");
0de98709 2483 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
22115cef 2484 __free_page(gvt->gtt.scratch_page);
2707e444
ZW		 2485 return ret;
2486 }
2487 }
ede9d0cf 2488 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2707e444
ZW		 2489 return 0;
2490}
2491
2492/**
2493 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2494 * @gvt: GVT device
2495 *
2496 * This function is called at the driver unloading stage, to clean up the
2497 * the mm components of a GVT device.
2498 *
2499 */
2500void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2501{
5de6bd4c 2502 struct device *dev = &gvt->dev_priv->drm.pdev->dev;
22115cef 2503 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
9556e118 2504 I915_GTT_PAGE_SHIFT);
5de6bd4c
CD		 2505
2506 dma_unmap_page(dev, daddr, 4096, PCI_DMA_BIDIRECTIONAL);
2507
22115cef 2508 __free_page(gvt->gtt.scratch_page);
d650ac06 2509
2707e444
ZW		 2510 if (enable_out_of_sync)
2511 clean_spt_oos(gvt);
2512}
d650ac06 2513
730c8ead
ZW		 2514/**
2515 * intel_vgpu_invalidate_ppgtt - invalidate PPGTT instances
2516 * @vgpu: a vGPU
2517 *
2518 * This function is called when invalidate all PPGTT instances of a vGPU.
2519 *
2520 */
2521void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
2522{
2523 struct list_head *pos, *n;
2524 struct intel_vgpu_mm *mm;
2525
2526 list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2527 mm = container_of(pos, struct intel_vgpu_mm, ppgtt_mm.list);
2528 if (mm->type == INTEL_GVT_MM_PPGTT) {
2529 list_del_init(&mm->ppgtt_mm.lru_list);
2530 if (mm->ppgtt_mm.shadowed)
2531 invalidate_ppgtt_mm(mm);
2532 }
2533 }
2534}
2535
d650ac06
PG		 2536/**
2537 * intel_vgpu_reset_ggtt - reset the GGTT entry
2538 * @vgpu: a vGPU
f4c43db3 2539 * @invalidate_old: invalidate old entries
d650ac06
PG		 2540 *
2541 * This function is called at the vGPU create stage
2542 * to reset all the GGTT entries.
2543 *
2544 */
f4c43db3 2545void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
d650ac06
PG		 2546{
2547 struct intel_gvt *gvt = vgpu->gvt;
5ad59bf0 2548 struct drm_i915_private *dev_priv = gvt->dev_priv;
b0c766bf
CD		 2549 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2550 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
f4c43db3 2551 struct intel_gvt_gtt_entry old_entry;
d650ac06 2552 u32 index;
d650ac06 2553 u32 num_entries;
d650ac06 2554
b0c766bf
CD		 2555 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2556 pte_ops->set_present(&entry);
d650ac06
PG		 2557
2558 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2559 num_entries = vgpu_aperture_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2560 while (num_entries--) {
2561 if (invalidate_old) {
2562 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2563 ggtt_invalidate_pte(vgpu, &old_entry);
2564 }
b0c766bf 2565 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2566 }
d650ac06
PG		 2567
2568 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2569 num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
f4c43db3
CD		 2570 while (num_entries--) {
2571 if (invalidate_old) {
2572 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2573 ggtt_invalidate_pte(vgpu, &old_entry);
2574 }
b0c766bf 2575 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
f4c43db3 2576 }
5ad59bf0 2577
a143cef7 2578 ggtt_invalidate(dev_priv);
d650ac06 2579}
b611581b
CD		 2580
2581/**
2582 * intel_vgpu_reset_gtt - reset the all GTT related status
2583 * @vgpu: a vGPU
b611581b
CD		 2584 *
2585 * This function is called from vfio core to reset reset all
2586 * GTT related status, including GGTT, PPGTT, scratch page.
2587 *
2588 */
4d3e67bb 2589void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
b611581b 2590{
da9cc8de
PG		 2591 /* Shadow pages are only created when there is no page
2592 * table tracking data, so remove page tracking data after
2593 * removing the shadow pages.
2594 */
ede9d0cf 2595 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
f4c43db3 2596 intel_vgpu_reset_ggtt(vgpu, true);
b611581b 2597}
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