[linux.git] / drivers / clk / bcm / clk-iproc-asiu.c

/*
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>
#include <linux/delay.h>

#include "clk-iproc.h"

struct iproc_asiu;

struct iproc_asiu_clk {
	struct clk_hw hw;
	const char *name;
	struct iproc_asiu *asiu;
	unsigned long rate;
	struct iproc_asiu_div div;
	struct iproc_asiu_gate gate;
};

struct iproc_asiu {
	void __iomem *div_base;
	void __iomem *gate_base;

	struct clk_hw_onecell_data *clk_data;
	struct iproc_asiu_clk *clks;
};

#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)

static int iproc_asiu_clk_enable(struct clk_hw *hw)
{
	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	struct iproc_asiu *asiu = clk->asiu;
	u32 val;

	/* some clocks at the ASIU level are always enabled */
	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
		return 0;

	val = readl(asiu->gate_base + clk->gate.offset);
	val |= (1 << clk->gate.en_shift);
	writel(val, asiu->gate_base + clk->gate.offset);

	return 0;
}

static void iproc_asiu_clk_disable(struct clk_hw *hw)
{
	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	struct iproc_asiu *asiu = clk->asiu;
	u32 val;

	/* some clocks at the ASIU level are always enabled */
	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
		return;

	val = readl(asiu->gate_base + clk->gate.offset);
	val &= ~(1 << clk->gate.en_shift);
	writel(val, asiu->gate_base + clk->gate.offset);
}

static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	struct iproc_asiu *asiu = clk->asiu;
	u32 val;
	unsigned int div_h, div_l;

	if (parent_rate == 0) {
		clk->rate = 0;
		return 0;
	}

	/* if clock divisor is not enabled, simply return parent rate */
	val = readl(asiu->div_base + clk->div.offset);
	if ((val & (1 << clk->div.en_shift)) == 0) {
		clk->rate = parent_rate;
		return parent_rate;
	}

	/* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
	div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
	div_h++;
	div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
	div_l++;

	clk->rate = parent_rate / (div_h + div_l);
	pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
		 __func__, clk->rate, parent_rate, div_h, div_l);

	return clk->rate;
}

static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *parent_rate)
{
	unsigned int div;

	if (rate == 0 || *parent_rate == 0)
		return -EINVAL;

	if (rate == *parent_rate)
		return *parent_rate;

	div = DIV_ROUND_UP(*parent_rate, rate);
	if (div < 2)
		return *parent_rate;

	return *parent_rate / div;
}

static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	struct iproc_asiu *asiu = clk->asiu;
	unsigned int div, div_h, div_l;
	u32 val;

	if (rate == 0 || parent_rate == 0)
		return -EINVAL;

	/* simply disable the divisor if one wants the same rate as parent */
	if (rate == parent_rate) {
		val = readl(asiu->div_base + clk->div.offset);
		val &= ~(1 << clk->div.en_shift);
		writel(val, asiu->div_base + clk->div.offset);
		return 0;
	}

	div = DIV_ROUND_UP(parent_rate, rate);
	if (div < 2)
		return -EINVAL;

	div_h = div_l = div >> 1;
	div_h--;
	div_l--;

	val = readl(asiu->div_base + clk->div.offset);
	val |= 1 << clk->div.en_shift;
	if (div_h) {
		val &= ~(bit_mask(clk->div.high_width)
			 << clk->div.high_shift);
		val |= div_h << clk->div.high_shift;
	} else {
		val &= ~(bit_mask(clk->div.high_width)
			 << clk->div.high_shift);
	}
	if (div_l) {
		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
		val |= div_l << clk->div.low_shift;
	} else {
		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
	}
	writel(val, asiu->div_base + clk->div.offset);

	return 0;
}

static const struct clk_ops iproc_asiu_ops = {
	.enable = iproc_asiu_clk_enable,
	.disable = iproc_asiu_clk_disable,
	.recalc_rate = iproc_asiu_clk_recalc_rate,
	.round_rate = iproc_asiu_clk_round_rate,
	.set_rate = iproc_asiu_clk_set_rate,
};

void __init iproc_asiu_setup(struct device_node *node,
			     const struct iproc_asiu_div *div,
			     const struct iproc_asiu_gate *gate,
			     unsigned int num_clks)
{
	int i, ret;
	struct iproc_asiu *asiu;

	if (WARN_ON(!gate || !div))
		return;

	asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
	if (WARN_ON(!asiu))
		return;

	asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
				 GFP_KERNEL);
	if (WARN_ON(!asiu->clk_data))
		goto err_clks;
	asiu->clk_data->num = num_clks;

	asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
	if (WARN_ON(!asiu->clks))
		goto err_asiu_clks;

	asiu->div_base = of_iomap(node, 0);
	if (WARN_ON(!asiu->div_base))
		goto err_iomap_div;

	asiu->gate_base = of_iomap(node, 1);
	if (WARN_ON(!asiu->gate_base))
		goto err_iomap_gate;

	for (i = 0; i < num_clks; i++) {
		struct clk_init_data init;
		const char *parent_name;
		struct iproc_asiu_clk *asiu_clk;
		const char *clk_name;

		ret = of_property_read_string_index(node, "clock-output-names",
						    i, &clk_name);
		if (WARN_ON(ret))
			goto err_clk_register;

		asiu_clk = &asiu->clks[i];
		asiu_clk->name = clk_name;
		asiu_clk->asiu = asiu;
		asiu_clk->div = div[i];
		asiu_clk->gate = gate[i];
		init.name = clk_name;
		init.ops = &iproc_asiu_ops;
		init.flags = 0;
		parent_name = of_clk_get_parent_name(node, 0);
		init.parent_names = (parent_name ? &parent_name : NULL);
		init.num_parents = (parent_name ? 1 : 0);
		asiu_clk->hw.init = &init;

		ret = clk_hw_register(NULL, &asiu_clk->hw);
		if (WARN_ON(ret))
			goto err_clk_register;
		asiu->clk_data->hws[i] = &asiu_clk->hw;
	}

	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
				     asiu->clk_data);
	if (WARN_ON(ret))
		goto err_clk_register;

	return;

err_clk_register:
	while (--i >= 0)
		clk_hw_unregister(asiu->clk_data->hws[i]);
	iounmap(asiu->gate_base);

err_iomap_gate:
	iounmap(asiu->div_base);

err_iomap_div:
	kfree(asiu->clks);

err_asiu_clks:
	kfree(asiu->clk_data);

err_clks:
	kfree(asiu);
}
Commit	Line	Data
5fe225c1 RJ	1	/*
	2	* Copyright (C) 2014 Broadcom Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation version 2.
	7	*
	8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	* kind, whether express or implied; without even the implied warranty
	10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/err.h>
	16	#include <linux/clk-provider.h>
	17	#include <linux/io.h>
	18	#include <linux/of.h>
	19	#include <linux/clkdev.h>
	20	#include <linux/of_address.h>
	21	#include <linux/delay.h>
	22
	23	#include "clk-iproc.h"
	24
	25	struct iproc_asiu;
	26
	27	struct iproc_asiu_clk {
	28	struct clk_hw hw;
	29	const char *name;
	30	struct iproc_asiu *asiu;
	31	unsigned long rate;
	32	struct iproc_asiu_div div;
	33	struct iproc_asiu_gate gate;
	34	};
	35
	36	struct iproc_asiu {
	37	void __iomem *div_base;
	38	void __iomem *gate_base;
	39
ff02c6c0	40	struct clk_hw_onecell_data *clk_data;
5fe225c1 RJ	41	struct iproc_asiu_clk *clks;
	42	};
	43
	44	#define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
	45
	46	static int iproc_asiu_clk_enable(struct clk_hw *hw)
	47	{
	48	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	49	struct iproc_asiu *asiu = clk->asiu;
	50	u32 val;
	51
	52	/* some clocks at the ASIU level are always enabled */
	53	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
	54	return 0;
	55
	56	val = readl(asiu->gate_base + clk->gate.offset);
	57	val \|= (1 << clk->gate.en_shift);
	58	writel(val, asiu->gate_base + clk->gate.offset);
	59
	60	return 0;
	61	}
	62
	63	static void iproc_asiu_clk_disable(struct clk_hw *hw)
	64	{
	65	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	66	struct iproc_asiu *asiu = clk->asiu;
	67	u32 val;
	68
	69	/* some clocks at the ASIU level are always enabled */
	70	if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
	71	return;
	72
	73	val = readl(asiu->gate_base + clk->gate.offset);
	74	val &= ~(1 << clk->gate.en_shift);
	75	writel(val, asiu->gate_base + clk->gate.offset);
	76	}
	77
	78	static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
	79	unsigned long parent_rate)
	80	{
	81	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
	82	struct iproc_asiu *asiu = clk->asiu;
	83	u32 val;
	84	unsigned int div_h, div_l;
	85
	86	if (parent_rate == 0) {
	87	clk->rate = 0;
	88	return 0;
	89	}
	90
	91	/* if clock divisor is not enabled, simply return parent rate */
	92	val = readl(asiu->div_base + clk->div.offset);
	93	if ((val & (1 << clk->div.en_shift)) == 0) {
	94	clk->rate = parent_rate;
	95	return parent_rate;
	96	}
	97
	98	/* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
	99	div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
	100	div_h++;
	101	div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
	102	div_l++;
	103
	104	clk->rate = parent_rate / (div_h + div_l);
105	pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
106	__func__, clk->rate, parent_rate, div_h, div_l);
107
108	return clk->rate;
109	}
110
111	static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
112	unsigned long *parent_rate)
113	{
114	unsigned int div;
115
116	if (rate == 0 \|\| *parent_rate == 0)
117	return -EINVAL;
118
119	if (rate == *parent_rate)
120	return *parent_rate;
121
122	div = DIV_ROUND_UP(*parent_rate, rate);
123	if (div < 2)
124	return *parent_rate;
125
126	return *parent_rate / div;
127	}
128
129	static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
130	unsigned long parent_rate)
131	{
132	struct iproc_asiu_clk *clk = to_asiu_clk(hw);
133	struct iproc_asiu *asiu = clk->asiu;
134	unsigned int div, div_h, div_l;
135	u32 val;
136
137	if (rate == 0 \|\| parent_rate == 0)
138	return -EINVAL;
139
140	/* simply disable the divisor if one wants the same rate as parent */
141	if (rate == parent_rate) {
142	val = readl(asiu->div_base + clk->div.offset);
143	val &= ~(1 << clk->div.en_shift);
144	writel(val, asiu->div_base + clk->div.offset);
145	return 0;
146	}
147
148	div = DIV_ROUND_UP(parent_rate, rate);
149	if (div < 2)
150	return -EINVAL;
151
152	div_h = div_l = div >> 1;
153	div_h--;
154	div_l--;
155
156	val = readl(asiu->div_base + clk->div.offset);
157	val \|= 1 << clk->div.en_shift;
158	if (div_h) {
159	val &= ~(bit_mask(clk->div.high_width)
160	<< clk->div.high_shift);
161	val \|= div_h << clk->div.high_shift;
162	} else {
163	val &= ~(bit_mask(clk->div.high_width)
164	<< clk->div.high_shift);
165	}
166	if (div_l) {
167	val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
168	val \|= div_l << clk->div.low_shift;
169	} else {
170	val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
171	}
172	writel(val, asiu->div_base + clk->div.offset);
173
174	return 0;
175	}
176
177	static const struct clk_ops iproc_asiu_ops = {
178	.enable = iproc_asiu_clk_enable,
179	.disable = iproc_asiu_clk_disable,
180	.recalc_rate = iproc_asiu_clk_recalc_rate,
181	.round_rate = iproc_asiu_clk_round_rate,
182	.set_rate = iproc_asiu_clk_set_rate,
183	};
184
185	void __init iproc_asiu_setup(struct device_node *node,
186	const struct iproc_asiu_div *div,
187	const struct iproc_asiu_gate *gate,
188	unsigned int num_clks)
189	{
190	int i, ret;
191	struct iproc_asiu *asiu;
192
193	if (WARN_ON(!gate \|\| !div))
194	return;
195
196	asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
197	if (WARN_ON(!asiu))
198	return;
199
acafe7e3 KC	200	asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
acafe7e3 KC	201	GFP_KERNEL);
ff02c6c0	202	if (WARN_ON(!asiu->clk_data))
5fe225c1	203	goto err_clks;
ff02c6c0	204	asiu->clk_data->num = num_clks;
5fe225c1 RJ	205
	206	asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
	207	if (WARN_ON(!asiu->clks))
	208	goto err_asiu_clks;
	209
	210	asiu->div_base = of_iomap(node, 0);
	211	if (WARN_ON(!asiu->div_base))
	212	goto err_iomap_div;
	213
	214	asiu->gate_base = of_iomap(node, 1);
	215	if (WARN_ON(!asiu->gate_base))
	216	goto err_iomap_gate;
	217
	218	for (i = 0; i < num_clks; i++) {
	219	struct clk_init_data init;
5fe225c1 RJ	220	const char *parent_name;
	221	struct iproc_asiu_clk *asiu_clk;
	222	const char *clk_name;
	223
5fe225c1 RJ	224	ret = of_property_read_string_index(node, "clock-output-names",
	225	i, &clk_name);
	226	if (WARN_ON(ret))
	227	goto err_clk_register;
	228
	229	asiu_clk = &asiu->clks[i];
	230	asiu_clk->name = clk_name;
	231	asiu_clk->asiu = asiu;
	232	asiu_clk->div = div[i];
	233	asiu_clk->gate = gate[i];
	234	init.name = clk_name;
	235	init.ops = &iproc_asiu_ops;
	236	init.flags = 0;
	237	parent_name = of_clk_get_parent_name(node, 0);
	238	init.parent_names = (parent_name ? &parent_name : NULL);
	239	init.num_parents = (parent_name ? 1 : 0);
	240	asiu_clk->hw.init = &init;
	241
ff02c6c0 SB	242	ret = clk_hw_register(NULL, &asiu_clk->hw);
ff02c6c0 SB	243	if (WARN_ON(ret))
5fe225c1	244	goto err_clk_register;
ff02c6c0	245	asiu->clk_data->hws[i] = &asiu_clk->hw;
5fe225c1 RJ	246	}
5fe225c1 RJ	247
ff02c6c0 SB	248	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
ff02c6c0 SB	249	asiu->clk_data);
5fe225c1 RJ	250	if (WARN_ON(ret))
	251	goto err_clk_register;
	252
	253	return;
	254
	255	err_clk_register:
ff02c6c0 SB	256	while (--i >= 0)
ff02c6c0 SB	257	clk_hw_unregister(asiu->clk_data->hws[i]);
5fe225c1 RJ	258	iounmap(asiu->gate_base);
	259
	260	err_iomap_gate:
	261	iounmap(asiu->div_base);
	262
	263	err_iomap_div:
	264	kfree(asiu->clks);
	265
	266	err_asiu_clks:
ff02c6c0	267	kfree(asiu->clk_data);
5fe225c1 RJ	268
	269	err_clks:
	270	kfree(asiu);
	271	}