]> Git Repo - linux.git/blame - drivers/scsi/gdth.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[NET]: remove unused header file: drivers/net/wan/lmc/lmc_media.h
[linux.git] / drivers / scsi / gdth.c
CommitLineData
1da177e4
LT		 1/************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
cbd5f69b 7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
1da177e4 8 * Copyright (C) 2002-04 Intel Corporation *
cbd5f69b 9 * Copyright (C) 2003-06 Adaptec Inc. *
1da177e4
LT		 10 * <[email protected]> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <[email protected]> *
14 * Johannes Dinner <[email protected]> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
cbd5f69b 30 * Linux kernel 2.4.x, 2.6.x supported *
1da177e4
LT		 31 * *
32 * $Log: gdth.c,v $
cbd5f69b
LA		 33 * Revision 1.74 2006/04/10 13:44:47 achim
34 * Community changes for 2.6.x
35 * Kernel 2.2.x no longer supported
36 * scsi_request interface removed, thanks to Christoph Hellwig
37 *
1da177e4
LT		 38 * Revision 1.73 2004/03/31 13:33:03 achim
39 * Special command 0xfd implemented to detect 64-bit DMA support
40 *
41 * Revision 1.72 2004/03/17 08:56:04 achim
42 * 64-bit DMA only enabled if FW >= x.43
43 *
44 * Revision 1.71 2004/03/05 15:51:29 achim
45 * Screen service: separate message buffer, bugfixes
46 *
47 * Revision 1.70 2004/02/27 12:19:07 achim
48 * Bugfix: Reset bit in config (0xfe) call removed
49 *
50 * Revision 1.69 2004/02/20 09:50:24 achim
51 * Compatibility changes for kernels < 2.4.20
52 * Bugfix screen service command size
53 * pci_set_dma_mask() error handling added
54 *
55 * Revision 1.68 2004/02/19 15:46:54 achim
56 * 64-bit DMA bugfixes
57 * Drive size bugfix for drives > 1TB
58 *
59 * Revision 1.67 2004/01/14 13:11:57 achim
60 * Tool access over /proc no longer supported
61 * Bugfixes IOCTLs
62 *
63 * Revision 1.66 2003/12/19 15:04:06 achim
64 * Bugfixes support for drives > 2TB
65 *
66 * Revision 1.65 2003/12/15 11:21:56 achim
67 * 64-bit DMA support added
68 * Support for drives > 2 TB implemented
69 * Kernels 2.2.x, 2.4.x, 2.6.x supported
70 *
71 * Revision 1.64 2003/09/17 08:30:26 achim
72 * EISA/ISA controller scan disabled
73 * Command line switch probe_eisa_isa added
74 *
75 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <[email protected]>
76 * Minor cleanups in gdth_ioctl.
77 *
78 * Revision 1.62 2003/02/27 15:01:59 achim
79 * Dynamic DMA mapping implemented
80 * New (character device) IOCTL interface added
81 * Other controller related changes made
82 *
83 * Revision 1.61 2002/11/08 13:09:52 boji
84 * Added support for XSCALE based RAID Controllers
85 * Fixed SCREENSERVICE initialization in SMP cases
86 * Added checks for gdth_polling before GDTH_HA_LOCK
87 *
88 * Revision 1.60 2002/02/05 09:35:22 achim
89 * MODULE_LICENSE only if kernel >= 2.4.11
90 *
91 * Revision 1.59 2002/01/30 09:46:33 achim
92 * Small changes
93 *
94 * Revision 1.58 2002/01/29 15:30:02 achim
95 * Set default value of shared_access to Y
96 * New status S_CACHE_RESERV for clustering added
97 *
98 * Revision 1.57 2001/08/21 11:16:35 achim
99 * Bugfix free_irq()
100 *
101 * Revision 1.56 2001/08/09 11:19:39 achim
cbd5f69b 102 * Scsi_Host_Template changes
1da177e4
LT		 103 *
104 * Revision 1.55 2001/08/09 10:11:28 achim
105 * Command HOST_UNFREEZE_IO before cache service init.
106 *
107 * Revision 1.54 2001/07/20 13:48:12 achim
108 * Expand: gdth_analyse_hdrive() removed
109 *
110 * Revision 1.53 2001/07/17 09:52:49 achim
111 * Small OEM related change
112 *
113 * Revision 1.52 2001/06/19 15:06:20 achim
114 * New host command GDT_UNFREEZE_IO added
115 *
116 * Revision 1.51 2001/05/22 06:42:37 achim
117 * PCI: Subdevice ID added
118 *
119 * Revision 1.50 2001/05/17 13:42:16 achim
120 * Support for Intel Storage RAID Controllers added
121 *
122 * Revision 1.50 2001/05/17 12:12:34 achim
123 * Support for Intel Storage RAID Controllers added
124 *
125 * Revision 1.49 2001/03/15 15:07:17 achim
126 * New __setup interface for boot command line options added
127 *
128 * Revision 1.48 2001/02/06 12:36:28 achim
129 * Bugfix Cluster protocol
130 *
131 * Revision 1.47 2001/01/10 14:42:06 achim
132 * New switch shared_access added
133 *
134 * Revision 1.46 2001/01/09 08:11:35 achim
135 * gdth_command() removed
136 * meaning of Scsi_Pointer members changed
137 *
138 * Revision 1.45 2000/11/16 12:02:24 achim
139 * Changes for kernel 2.4
140 *
141 * Revision 1.44 2000/10/11 08:44:10 achim
142 * Clustering changes: New flag media_changed added
143 *
144 * Revision 1.43 2000/09/20 12:59:01 achim
145 * DPMEM remap functions for all PCI controller types implemented
146 * Small changes for ia64 platform
147 *
148 * Revision 1.42 2000/07/20 09:04:50 achim
149 * Small changes for kernel 2.4
150 *
151 * Revision 1.41 2000/07/04 14:11:11 achim
152 * gdth_analyse_hdrive() added to rescan drives after online expansion
153 *
154 * Revision 1.40 2000/06/27 11:24:16 achim
155 * Changes Clustering, Screenservice
156 *
157 * Revision 1.39 2000/06/15 13:09:04 achim
158 * Changes for gdth_do_cmd()
159 *
160 * Revision 1.38 2000/06/15 12:08:43 achim
161 * Bugfix gdth_sync_event(), service SCREENSERVICE
162 * Data direction for command 0xc2 changed to DOU
163 *
164 * Revision 1.37 2000/05/25 13:50:10 achim
165 * New driver parameter virt_ctr added
166 *
167 * Revision 1.36 2000/05/04 08:50:46 achim
168 * Event buffer now in gdth_ha_str
169 *
170 * Revision 1.35 2000/03/03 10:44:08 achim
171 * New event_string only valid for the RP controller family
172 *
173 * Revision 1.34 2000/03/02 14:55:29 achim
174 * New mechanism for async. event handling implemented
175 *
176 * Revision 1.33 2000/02/21 15:37:37 achim
177 * Bugfix Alpha platform + DPMEM above 4GB
178 *
179 * Revision 1.32 2000/02/14 16:17:37 achim
180 * Bugfix sense_buffer[] + raw devices
181 *
182 * Revision 1.31 2000/02/10 10:29:00 achim
183 * Delete sense_buffer[0], if command OK
184 *
185 * Revision 1.30 1999/11/02 13:42:39 achim
186 * ARRAY_DRV_LIST2 implemented
187 * Now 255 log. and 100 host drives supported
188 *
189 * Revision 1.29 1999/10/05 13:28:47 achim
190 * GDT_CLUST_RESET added
191 *
192 * Revision 1.28 1999/08/12 13:44:54 achim
193 * MOUNTALL removed
194 * Cluster drives -> removeable drives
195 *
196 * Revision 1.27 1999/06/22 07:22:38 achim
197 * Small changes
198 *
199 * Revision 1.26 1999/06/10 16:09:12 achim
200 * Cluster Host Drive support: Bugfixes
201 *
202 * Revision 1.25 1999/06/01 16:03:56 achim
203 * gdth_init_pci(): Manipulate config. space to start RP controller
204 *
205 * Revision 1.24 1999/05/26 11:53:06 achim
206 * Cluster Host Drive support added
207 *
208 * Revision 1.23 1999/03/26 09:12:31 achim
209 * Default value for hdr_channel set to 0
210 *
211 * Revision 1.22 1999/03/22 16:27:16 achim
212 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
213 *
214 * Revision 1.21 1999/03/16 13:40:34 achim
215 * Problems with reserved drives solved
216 * gdth_eh_bus_reset() implemented
217 *
218 * Revision 1.20 1999/03/10 09:08:13 achim
219 * Bugfix: Corrections in gdth_direction_tab[] made
220 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
221 *
222 * Revision 1.19 1999/03/05 14:38:16 achim
223 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
224 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
225 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
226 * with BIOS disabled and memory test set to Intensive
227 * Enhanced /proc support
228 *
229 * Revision 1.18 1999/02/24 09:54:33 achim
230 * Command line parameter hdr_channel implemented
231 * Bugfix for EISA controllers + Linux 2.2.x
232 *
233 * Revision 1.17 1998/12/17 15:58:11 achim
234 * Command line parameters implemented
235 * Changes for Alpha platforms
236 * PCI controller scan changed
237 * SMP support improved (spin_lock_irqsave(),...)
238 * New async. events, new scan/reserve commands included
239 *
240 * Revision 1.16 1998/09/28 16:08:46 achim
241 * GDT_PCIMPR: DPMEM remapping, if required
242 * mdelay() added
243 *
244 * Revision 1.15 1998/06/03 14:54:06 achim
245 * gdth_delay(), gdth_flush() implemented
246 * Bugfix: gdth_release() changed
247 *
248 * Revision 1.14 1998/05/22 10:01:17 achim
249 * mj: pcibios_strerror() removed
250 * Improved SMP support (if version >= 2.1.95)
251 * gdth_halt(): halt_called flag added (if version < 2.1)
252 *
253 * Revision 1.13 1998/04/16 09:14:57 achim
254 * Reserve drives (for raw service) implemented
255 * New error handling code enabled
256 * Get controller name from board_info() IOCTL
257 * Final round of PCI device driver patches by Martin Mares
258 *
259 * Revision 1.12 1998/03/03 09:32:37 achim
260 * Fibre channel controller support added
261 *
262 * Revision 1.11 1998/01/27 16:19:14 achim
263 * SA_SHIRQ added
264 * add_timer()/del_timer() instead of GDTH_TIMER
265 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
266 * New error handling included
267 *
268 * Revision 1.10 1997/10/31 12:29:57 achim
269 * Read heads/sectors from host drive
270 *
271 * Revision 1.9 1997/09/04 10:07:25 achim
272 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
273 * register_reboot_notifier() to get a notify on shutown used
274 *
275 * Revision 1.8 1997/04/02 12:14:30 achim
276 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
277 *
278 * Revision 1.7 1997/03/12 13:33:37 achim
279 * gdth_reset() changed, new async. events
280 *
281 * Revision 1.6 1997/03/04 14:01:11 achim
282 * Shutdown routine gdth_halt() implemented
283 *
284 * Revision 1.5 1997/02/21 09:08:36 achim
285 * New controller included (RP, RP1, RP2 series)
286 * IOCTL interface implemented
287 *
288 * Revision 1.4 1996/07/05 12:48:55 achim
289 * Function gdth_bios_param() implemented
290 * New constant GDTH_MAXC_P_L inserted
291 * GDT_WRITE_THR, GDT_EXT_INFO implemented
292 * Function gdth_reset() changed
293 *
294 * Revision 1.3 1996/05/10 09:04:41 achim
295 * Small changes for Linux 1.2.13
296 *
297 * Revision 1.2 1996/05/09 12:45:27 achim
298 * Loadable module support implemented
299 * /proc support corrections made
300 *
301 * Revision 1.1 1996/04/11 07:35:57 achim
302 * Initial revision
303 *
304 ************************************************************************/
305
306/* All GDT Disk Array Controllers are fully supported by this driver.
307 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
308 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
309 * list of all controller types.
310 *
311 * If you have one or more GDT3000/3020 EISA controllers with
312 * controller BIOS disabled, you have to set the IRQ values with the
313 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
314 * the IRQ values for the EISA controllers.
315 *
316 * After the optional list of IRQ values, other possible
317 * command line options are:
318 * disable:Y disable driver
319 * disable:N enable driver
320 * reserve_mode:0 reserve no drives for the raw service
321 * reserve_mode:1 reserve all not init., removable drives
322 * reserve_mode:2 reserve all not init. drives
323 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
324 * h- controller no., b- channel no.,
325 * t- target ID, l- LUN
326 * reverse_scan:Y reverse scan order for PCI controllers
327 * reverse_scan:N scan PCI controllers like BIOS
328 * max_ids:x x - target ID count per channel (1..MAXID)
329 * rescan:Y rescan all channels/IDs
330 * rescan:N use all devices found until now
331 * virt_ctr:Y map every channel to a virtual controller
332 * virt_ctr:N use multi channel support
333 * hdr_channel:x x - number of virtual bus for host drives
334 * shared_access:Y disable driver reserve/release protocol to
335 * access a shared resource from several nodes,
575c9687 336 * appropriate controller firmware required
1da177e4
LT		 337 * shared_access:N enable driver reserve/release protocol
338 * probe_eisa_isa:Y scan for EISA/ISA controllers
339 * probe_eisa_isa:N do not scan for EISA/ISA controllers
340 * force_dma32:Y use only 32 bit DMA mode
341 * force_dma32:N use 64 bit DMA mode, if supported
342 *
343 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
344 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
345 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
346 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
347 *
348 * When loading the gdth driver as a module, the same options are available.
349 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
350 * options changes slightly. You must replace all ',' between options
351 * with ' ' and all ':' with '=' and you must use
352 * '1' in place of 'Y' and '0' in place of 'N'.
353 *
354 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
355 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
356 * probe_eisa_isa=0 force_dma32=0"
357 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
358 */
359
360/* The meaning of the Scsi_Pointer members in this driver is as follows:
361 * ptr: Chaining
362 * this_residual: Command priority
363 * buffer: phys. DMA sense buffer
364 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
365 * buffers_residual: Timeout value
366 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
367 * Message: Additional info (gdth_do_cmd()), DMA direction
368 * have_data_in: Flag for gdth_wait_completion()
369 * sent_command: Opcode special command
370 * phase: Service/parameter/return code special command
371 */
372
373
374/* interrupt coalescing */
375/* #define INT_COAL */
376
377/* statistics */
378#define GDTH_STATISTICS
379
380#include <linux/module.h>
381
382#include <linux/version.h>
383#include <linux/kernel.h>
384#include <linux/types.h>
385#include <linux/pci.h>
386#include <linux/string.h>
387#include <linux/ctype.h>
388#include <linux/ioport.h>
389#include <linux/delay.h>
1da177e4
LT		 390#include <linux/interrupt.h>
391#include <linux/in.h>
392#include <linux/proc_fs.h>
393#include <linux/time.h>
394#include <linux/timer.h>
cbd5f69b 395#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
910638ae 396#include <linux/dma-mapping.h>
cbd5f69b
LA		 397#else
398#define DMA_32BIT_MASK 0x00000000ffffffffULL
399#define DMA_64BIT_MASK 0xffffffffffffffffULL
400#endif
401
1da177e4
LT		 402#ifdef GDTH_RTC
403#include <linux/mc146818rtc.h>
404#endif
405#include <linux/reboot.h>
406
407#include <asm/dma.h>
408#include <asm/system.h>
409#include <asm/io.h>
410#include <asm/uaccess.h>
411#include <linux/spinlock.h>
412#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
413#include <linux/blkdev.h>
414#else
415#include <linux/blk.h>
416#include "sd.h"
417#endif
418
419#include "scsi.h"
420#include <scsi/scsi_host.h>
1da177e4 421#include "gdth_kcompat.h"
cbd5f69b 422#include "gdth.h"
1da177e4
LT		 423
424static void gdth_delay(int milliseconds);
425static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
7d12e780 426static irqreturn_t gdth_interrupt(int irq, void *dev_id);
1da177e4
LT		 427static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
428static int gdth_async_event(int hanum);
429static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
430
431static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
432static void gdth_next(int hanum);
433static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
434static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
435static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
436 ushort idx, gdth_evt_data *evt);
437static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
438static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
439 gdth_evt_str *estr);
440static void gdth_clear_events(void);
441
442static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
443 char *buffer,ushort count);
444static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
445static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
446
447static int gdth_search_eisa(ushort eisa_adr);
448static int gdth_search_isa(ulong32 bios_adr);
449static int gdth_search_pci(gdth_pci_str *pcistr);
450static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
451 ushort vendor, ushort dev);
452static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
453static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
454static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
455static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
456
457static void gdth_enable_int(int hanum);
458static int gdth_get_status(unchar *pIStatus,int irq);
459static int gdth_test_busy(int hanum);
460static int gdth_get_cmd_index(int hanum);
461static void gdth_release_event(int hanum);
462static int gdth_wait(int hanum,int index,ulong32 time);
463static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
464 ulong64 p2,ulong64 p3);
465static int gdth_search_drives(int hanum);
466static int gdth_analyse_hdrive(int hanum, ushort hdrive);
467
468static const char *gdth_ctr_name(int hanum);
469
470static int gdth_open(struct inode *inode, struct file *filep);
471static int gdth_close(struct inode *inode, struct file *filep);
472static int gdth_ioctl(struct inode *inode, struct file *filep,
473 unsigned int cmd, unsigned long arg);
474
475static void gdth_flush(int hanum);
476static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
cbd5f69b
LA		 477static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
478static void gdth_scsi_done(struct scsi_cmnd *scp);
1da177e4
LT		 479
480#ifdef DEBUG_GDTH
481static unchar DebugState = DEBUG_GDTH;
482
483#ifdef __SERIAL__
484#define MAX_SERBUF 160
485static void ser_init(void);
486static void ser_puts(char *str);
487static void ser_putc(char c);
488static int ser_printk(const char *fmt, ...);
489static char strbuf[MAX_SERBUF+1];
490#ifdef __COM2__
491#define COM_BASE 0x2f8
492#else
493#define COM_BASE 0x3f8
494#endif
495static void ser_init()
496{
497 unsigned port=COM_BASE;
498
499 outb(0x80,port+3);
500 outb(0,port+1);
501 /* 19200 Baud, if 9600: outb(12,port) */
502 outb(6, port);
503 outb(3,port+3);
504 outb(0,port+1);
505 /*
506 ser_putc('I');
507 ser_putc(' ');
508 */
509}
510
511static void ser_puts(char *str)
512{
513 char *ptr;
514
515 ser_init();
516 for (ptr=str;*ptr;++ptr)
517 ser_putc(*ptr);
518}
519
520static void ser_putc(char c)
521{
522 unsigned port=COM_BASE;
523
524 while ((inb(port+5) & 0x20)==0);
525 outb(c,port);
526 if (c==0x0a)
527 {
528 while ((inb(port+5) & 0x20)==0);
529 outb(0x0d,port);
530 }
531}
532
533static int ser_printk(const char *fmt, ...)
534{
535 va_list args;
536 int i;
537
538 va_start(args,fmt);
539 i = vsprintf(strbuf,fmt,args);
540 ser_puts(strbuf);
541 va_end(args);
542 return i;
543}
544
545#define TRACE(a) {if (DebugState==1) {ser_printk a;}}
546#define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
547#define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
548
549#else /* !__SERIAL__ */
550#define TRACE(a) {if (DebugState==1) {printk a;}}
551#define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
552#define TRACE3(a) {if (DebugState!=0) {printk a;}}
553#endif
554
555#else /* !DEBUG */
556#define TRACE(a)
557#define TRACE2(a)
558#define TRACE3(a)
559#endif
560
561#ifdef GDTH_STATISTICS
562static ulong32 max_rq=0, max_index=0, max_sg=0;
563#ifdef INT_COAL
564static ulong32 max_int_coal=0;
565#endif
566static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
567static struct timer_list gdth_timer;
568#endif
569
570#define PTR2USHORT(a) (ushort)(ulong)(a)
6391a113
TK		 571#define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
572#define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
1da177e4
LT		 573
574#define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
575#define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
576#define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
577
578#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
579
580#define gdth_readb(addr) readb(addr)
581#define gdth_readw(addr) readw(addr)
582#define gdth_readl(addr) readl(addr)
583#define gdth_writeb(b,addr) writeb((b),(addr))
584#define gdth_writew(b,addr) writew((b),(addr))
585#define gdth_writel(b,addr) writel((b),(addr))
586
587static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
588static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
589static unchar gdth_polling; /* polling if TRUE */
590static unchar gdth_from_wait = FALSE; /* gdth_wait() */
591static int wait_index,wait_hanum; /* gdth_wait() */
592static int gdth_ctr_count = 0; /* controller count */
593static int gdth_ctr_vcount = 0; /* virt. ctr. count */
594static int gdth_ctr_released = 0; /* gdth_release() */
595static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
596static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
597static unchar gdth_write_through = FALSE; /* write through */
598static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
599static int elastidx;
600static int eoldidx;
601static int major;
602
603#define DIN 1 /* IN data direction */
604#define DOU 2 /* OUT data direction */
605#define DNO DIN /* no data transfer */
606#define DUN DIN /* unknown data direction */
607static unchar gdth_direction_tab[0x100] = {
608 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
609 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
610 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
611 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
612 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
613 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
614 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
615 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
616 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
617 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
618 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
619 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
620 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
621 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
622 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
623 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
624};
625
626/* LILO and modprobe/insmod parameters */
627/* IRQ list for GDT3000/3020 EISA controllers */
628static int irq[MAXHA] __initdata =
629{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
630 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
631/* disable driver flag */
632static int disable __initdata = 0;
633/* reserve flag */
634static int reserve_mode = 1;
635/* reserve list */
636static int reserve_list[MAX_RES_ARGS] =
637{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
638 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
639 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
640/* scan order for PCI controllers */
641static int reverse_scan = 0;
642/* virtual channel for the host drives */
643static int hdr_channel = 0;
644/* max. IDs per channel */
645static int max_ids = MAXID;
646/* rescan all IDs */
647static int rescan = 0;
648/* map channels to virtual controllers */
649static int virt_ctr = 0;
650/* shared access */
651static int shared_access = 1;
652/* enable support for EISA and ISA controllers */
653static int probe_eisa_isa = 0;
654/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
655static int force_dma32 = 0;
656
657/* parameters for modprobe/insmod */
cbd5f69b 658#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
1da177e4
LT		 659module_param_array(irq, int, NULL, 0);
660module_param(disable, int, 0);
661module_param(reserve_mode, int, 0);
662module_param_array(reserve_list, int, NULL, 0);
663module_param(reverse_scan, int, 0);
664module_param(hdr_channel, int, 0);
665module_param(max_ids, int, 0);
666module_param(rescan, int, 0);
667module_param(virt_ctr, int, 0);
668module_param(shared_access, int, 0);
669module_param(probe_eisa_isa, int, 0);
670module_param(force_dma32, int, 0);
cbd5f69b
LA		 671#else
672MODULE_PARM(irq, "i");
673MODULE_PARM(disable, "i");
674MODULE_PARM(reserve_mode, "i");
675MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
676MODULE_PARM(reverse_scan, "i");
677MODULE_PARM(hdr_channel, "i");
678MODULE_PARM(max_ids, "i");
679MODULE_PARM(rescan, "i");
680MODULE_PARM(virt_ctr, "i");
681MODULE_PARM(shared_access, "i");
682MODULE_PARM(probe_eisa_isa, "i");
683MODULE_PARM(force_dma32, "i");
684#endif
1da177e4
LT		 685MODULE_AUTHOR("Achim Leubner");
686MODULE_LICENSE("GPL");
687
688/* ioctl interface */
00977a59 689static const struct file_operations gdth_fops = {
1da177e4
LT		 690 .ioctl = gdth_ioctl,
691 .open = gdth_open,
692 .release = gdth_close,
693};
694
695#include "gdth_proc.h"
696#include "gdth_proc.c"
697
698/* notifier block to get a notify on system shutdown/halt/reboot */
699static struct notifier_block gdth_notifier = {
700 gdth_halt, NULL, 0
701};
e041c683 702static int notifier_disabled = 0;
1da177e4
LT		 703
704static void gdth_delay(int milliseconds)
705{
706 if (milliseconds == 0) {
707 udelay(1);
708 } else {
709 mdelay(milliseconds);
710 }
711}
712
cbd5f69b
LA		 713#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
714static void gdth_scsi_done(struct scsi_cmnd *scp)
715{
716 TRACE2(("gdth_scsi_done()\n"));
717
beb40487
CH		 718 if (scp->request)
719 complete((struct completion *)scp->request);
cbd5f69b
LA		 720}
721
722int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
723 int timeout, u32 *info)
724{
725 Scsi_Cmnd *scp;
6e9a4738 726 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 727 int rval;
728
729 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
730 if (!scp)
731 return -ENOMEM;
732 memset(scp, 0, sizeof(*scp));
733 scp->device = sdev;
beb40487
CH		 734 /* use request field to save the ptr. to completion struct. */
735 scp->request = (struct request *)&wait;
cbd5f69b
LA		 736 scp->timeout_per_command = timeout*HZ;
737 scp->request_buffer = gdtcmd;
738 scp->cmd_len = 12;
739 memcpy(scp->cmnd, cmnd, 12);
740 scp->SCp.this_residual = IOCTL_PRI; /* priority */
741 scp->done = gdth_scsi_done; /* some fn. test this */
742 gdth_queuecommand(scp, gdth_scsi_done);
743 wait_for_completion(&wait);
744
745 rval = scp->SCp.Status;
746 if (info)
747 *info = scp->SCp.Message;
748 kfree(scp);
749 return rval;
750}
751#else
752static void gdth_scsi_done(Scsi_Cmnd *scp)
753{
754 TRACE2(("gdth_scsi_done()\n"));
755
756 scp->request.rq_status = RQ_SCSI_DONE;
757 if (scp->request.waiting)
758 complete(scp->request.waiting);
759}
760
761int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
762 int timeout, u32 *info)
763{
764 Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
765 unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
6e9a4738 766 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 767 int rval;
768
769 if (!scp)
770 return -ENOMEM;
771 scp->cmd_len = 12;
772 scp->use_sg = 0;
773 scp->SCp.this_residual = IOCTL_PRI; /* priority */
774 scp->request.rq_status = RQ_SCSI_BUSY;
775 scp->request.waiting = &wait;
776 scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
777 wait_for_completion(&wait);
778
779 rval = scp->SCp.Status;
780 if (info)
781 *info = scp->SCp.Message;
782
783 scsi_release_command(scp);
784 return rval;
785}
786#endif
787
788int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
789 int timeout, u32 *info)
790{
791 struct scsi_device *sdev = scsi_get_host_dev(shost);
792 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
793
794 scsi_free_host_dev(sdev);
795 return rval;
796}
797
1da177e4
LT		 798static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
799{
800 *cyls = size /HEADS/SECS;
801 if (*cyls <= MAXCYLS) {
802 *heads = HEADS;
803 *secs = SECS;
804 } else { /* too high for 64*32 */
805 *cyls = size /MEDHEADS/MEDSECS;
806 if (*cyls <= MAXCYLS) {
807 *heads = MEDHEADS;
808 *secs = MEDSECS;
809 } else { /* too high for 127*63 */
810 *cyls = size /BIGHEADS/BIGSECS;
811 *heads = BIGHEADS;
812 *secs = BIGSECS;
813 }
814 }
815}
816
817/* controller search and initialization functions */
818
819static int __init gdth_search_eisa(ushort eisa_adr)
820{
821 ulong32 id;
822
823 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
824 id = inl(eisa_adr+ID0REG);
825 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
826 if ((inb(eisa_adr+EISAREG) & 8) == 0)
827 return 0; /* not EISA configured */
828 return 1;
829 }
830 if (id == GDT3_ID) /* GDT3000 */
831 return 1;
832
833 return 0;
834}
835
836
837static int __init gdth_search_isa(ulong32 bios_adr)
838{
839 void __iomem *addr;
840 ulong32 id;
841
842 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
843 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
844 id = gdth_readl(addr);
845 iounmap(addr);
846 if (id == GDT2_ID) /* GDT2000 */
847 return 1;
848 }
849 return 0;
850}
851
852
853static int __init gdth_search_pci(gdth_pci_str *pcistr)
854{
855 ushort device, cnt;
856
857 TRACE(("gdth_search_pci()\n"));
858
859 cnt = 0;
860 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
861 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
862 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
863 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
864 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
865 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
866 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
867 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
868 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
869 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
870 PCI_DEVICE_ID_INTEL_SRC);
871 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
872 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
873 return cnt;
874}
875
876/* Vortex only makes RAID controllers.
877 * We do not really want to specify all 550 ids here, so wildcard match.
878 */
879static struct pci_device_id gdthtable[] __attribute_used__ = {
880 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
881 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
882 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
883 {0}
884};
885MODULE_DEVICE_TABLE(pci,gdthtable);
886
887static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
cbd5f69b 888 ushort vendor, ushort device)
1da177e4
LT		 889{
890 ulong base0, base1, base2;
891 struct pci_dev *pdev;
892
893 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
894 *cnt, vendor, device));
895
896 pdev = NULL;
897 while ((pdev = pci_find_device(vendor, device, pdev))
898 != NULL) {
899 if (pci_enable_device(pdev))
900 continue;
901 if (*cnt >= MAXHA)
902 return;
903 /* GDT PCI controller found, resources are already in pdev */
904 pcistr[*cnt].pdev = pdev;
905 pcistr[*cnt].vendor_id = vendor;
906 pcistr[*cnt].device_id = device;
907 pcistr[*cnt].subdevice_id = pdev->subsystem_device;
908 pcistr[*cnt].bus = pdev->bus->number;
909 pcistr[*cnt].device_fn = pdev->devfn;
910 pcistr[*cnt].irq = pdev->irq;
911 base0 = pci_resource_flags(pdev, 0);
912 base1 = pci_resource_flags(pdev, 1);
913 base2 = pci_resource_flags(pdev, 2);
914 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
915 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
916 if (!(base0 & IORESOURCE_MEM))
917 continue;
918 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
919 } else { /* GDT6110, GDT6120, .. */
920 if (!(base0 & IORESOURCE_MEM) ||
921 !(base2 & IORESOURCE_MEM) ||
922 !(base1 & IORESOURCE_IO))
923 continue;
924 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
925 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
926 pcistr[*cnt].io = pci_resource_start(pdev, 1);
927 }
928 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
929 pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
930 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
931 (*cnt)++;
932 }
933}
934
935
936static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
937{
938 gdth_pci_str temp;
939 int i, changed;
940
941 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
942 if (cnt == 0)
943 return;
944
945 do {
946 changed = FALSE;
947 for (i = 0; i < cnt-1; ++i) {
948 if (!reverse_scan) {
949 if ((pcistr[i].bus > pcistr[i+1].bus) ||
950 (pcistr[i].bus == pcistr[i+1].bus &&
951 PCI_SLOT(pcistr[i].device_fn) >
952 PCI_SLOT(pcistr[i+1].device_fn))) {
953 temp = pcistr[i];
954 pcistr[i] = pcistr[i+1];
955 pcistr[i+1] = temp;
956 changed = TRUE;
957 }
958 } else {
959 if ((pcistr[i].bus < pcistr[i+1].bus) ||
960 (pcistr[i].bus == pcistr[i+1].bus &&
961 PCI_SLOT(pcistr[i].device_fn) <
962 PCI_SLOT(pcistr[i+1].device_fn))) {
963 temp = pcistr[i];
964 pcistr[i] = pcistr[i+1];
965 pcistr[i+1] = temp;
966 changed = TRUE;
967 }
968 }
969 }
970 } while (changed);
971}
972
973
974static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
975{
976 ulong32 retries,id;
977 unchar prot_ver,eisacf,i,irq_found;
978
979 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
980
981 /* disable board interrupts, deinitialize services */
982 outb(0xff,eisa_adr+EDOORREG);
983 outb(0x00,eisa_adr+EDENABREG);
984 outb(0x00,eisa_adr+EINTENABREG);
985
986 outb(0xff,eisa_adr+LDOORREG);
987 retries = INIT_RETRIES;
988 gdth_delay(20);
989 while (inb(eisa_adr+EDOORREG) != 0xff) {
990 if (--retries == 0) {
991 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
992 return 0;
993 }
994 gdth_delay(1);
995 TRACE2(("wait for DEINIT: retries=%d\n",retries));
996 }
997 prot_ver = inb(eisa_adr+MAILBOXREG);
998 outb(0xff,eisa_adr+EDOORREG);
999 if (prot_ver != PROTOCOL_VERSION) {
1000 printk("GDT-EISA: Illegal protocol version\n");
1001 return 0;
1002 }
1003 ha->bmic = eisa_adr;
1004 ha->brd_phys = (ulong32)eisa_adr >> 12;
1005
1006 outl(0,eisa_adr+MAILBOXREG);
1007 outl(0,eisa_adr+MAILBOXREG+4);
1008 outl(0,eisa_adr+MAILBOXREG+8);
1009 outl(0,eisa_adr+MAILBOXREG+12);
1010
1011 /* detect IRQ */
1012 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
1013 ha->oem_id = OEM_ID_ICP;
1014 ha->type = GDT_EISA;
1015 ha->stype = id;
1016 outl(1,eisa_adr+MAILBOXREG+8);
1017 outb(0xfe,eisa_adr+LDOORREG);
1018 retries = INIT_RETRIES;
1019 gdth_delay(20);
1020 while (inb(eisa_adr+EDOORREG) != 0xfe) {
1021 if (--retries == 0) {
1022 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
1023 return 0;
1024 }
1025 gdth_delay(1);
1026 }
1027 ha->irq = inb(eisa_adr+MAILBOXREG);
1028 outb(0xff,eisa_adr+EDOORREG);
1029 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
1030 /* check the result */
1031 if (ha->irq == 0) {
1032 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
1033 for (i = 0, irq_found = FALSE;
1034 i < MAXHA && irq[i] != 0xff; ++i) {
1035 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
1036 irq_found = TRUE;
1037 break;
1038 }
1039 }
1040 if (irq_found) {
1041 ha->irq = irq[i];
1042 irq[i] = 0;
1043 printk("GDT-EISA: Can not detect controller IRQ,\n");
1044 printk("Use IRQ setting from command line (IRQ = %d)\n",
1045 ha->irq);
1046 } else {
1047 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
1048 printk("the controller BIOS or use command line parameters\n");
1049 return 0;
1050 }
1051 }
1052 } else {
1053 eisacf = inb(eisa_adr+EISAREG) & 7;
1054 if (eisacf > 4) /* level triggered */
1055 eisacf -= 4;
1056 ha->irq = gdth_irq_tab[eisacf];
1057 ha->oem_id = OEM_ID_ICP;
1058 ha->type = GDT_EISA;
1059 ha->stype = id;
1060 }
1061
1062 ha->dma64_support = 0;
1063 return 1;
1064}
1065
1066
1067static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
1068{
1069 register gdt2_dpram_str __iomem *dp2_ptr;
1070 int i;
1071 unchar irq_drq,prot_ver;
1072 ulong32 retries;
1073
1074 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
1075
1076 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
1077 if (ha->brd == NULL) {
1078 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
1079 return 0;
1080 }
1081 dp2_ptr = ha->brd;
1082 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1083 /* reset interface area */
1084 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
1085 if (gdth_readl(&dp2_ptr->u) != 0) {
1086 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
1087 iounmap(ha->brd);
1088 return 0;
1089 }
1090
1091 /* disable board interrupts, read DRQ and IRQ */
1092 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1093 gdth_writeb(0x00, &dp2_ptr->io.irqen);
1094 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
1095 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1096
1097 irq_drq = gdth_readb(&dp2_ptr->io.rq);
1098 for (i=0; i<3; ++i) {
1099 if ((irq_drq & 1)==0)
1100 break;
1101 irq_drq >>= 1;
1102 }
1103 ha->drq = gdth_drq_tab[i];
1104
1105 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
1106 for (i=1; i<5; ++i) {
1107 if ((irq_drq & 1)==0)
1108 break;
1109 irq_drq >>= 1;
1110 }
1111 ha->irq = gdth_irq_tab[i];
1112
1113 /* deinitialize services */
1114 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1115 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1116 gdth_writeb(0, &dp2_ptr->io.event);
1117 retries = INIT_RETRIES;
1118 gdth_delay(20);
1119 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1120 if (--retries == 0) {
1121 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1122 iounmap(ha->brd);
1123 return 0;
1124 }
1125 gdth_delay(1);
1126 }
1127 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1128 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1129 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1130 if (prot_ver != PROTOCOL_VERSION) {
1131 printk("GDT-ISA: Illegal protocol version\n");
1132 iounmap(ha->brd);
1133 return 0;
1134 }
1135
1136 ha->oem_id = OEM_ID_ICP;
1137 ha->type = GDT_ISA;
1138 ha->ic_all_size = sizeof(dp2_ptr->u);
1139 ha->stype= GDT2_ID;
1140 ha->brd_phys = bios_adr >> 4;
1141
1142 /* special request to controller BIOS */
1143 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1144 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1145 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1146 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1147 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1148 gdth_writeb(0, &dp2_ptr->io.event);
1149 retries = INIT_RETRIES;
1150 gdth_delay(20);
1151 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1152 if (--retries == 0) {
1153 printk("GDT-ISA: Initialization error\n");
1154 iounmap(ha->brd);
1155 return 0;
1156 }
1157 gdth_delay(1);
1158 }
1159 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1160 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1161
1162 ha->dma64_support = 0;
1163 return 1;
1164}
1165
1166
1167static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1168{
1169 register gdt6_dpram_str __iomem *dp6_ptr;
1170 register gdt6c_dpram_str __iomem *dp6c_ptr;
1171 register gdt6m_dpram_str __iomem *dp6m_ptr;
1172 ulong32 retries;
1173 unchar prot_ver;
1174 ushort command;
1175 int i, found = FALSE;
1176
1177 TRACE(("gdth_init_pci()\n"));
1178
1179 if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
1180 ha->oem_id = OEM_ID_INTEL;
1181 else
1182 ha->oem_id = OEM_ID_ICP;
1183 ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
1184 ha->stype = (ulong32)pcistr->device_id;
1185 ha->subdevice_id = pcistr->subdevice_id;
1186 ha->irq = pcistr->irq;
1187 ha->pdev = pcistr->pdev;
1188
1189 if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1190 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1191 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1192 if (ha->brd == NULL) {
1193 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1194 return 0;
1195 }
1196 /* check and reset interface area */
1197 dp6_ptr = ha->brd;
1198 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1199 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1200 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1201 pcistr->dpmem);
1202 found = FALSE;
1203 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1204 iounmap(ha->brd);
1205 ha->brd = ioremap(i, sizeof(ushort));
1206 if (ha->brd == NULL) {
1207 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1208 return 0;
1209 }
1210 if (gdth_readw(ha->brd) != 0xffff) {
1211 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1212 continue;
1213 }
1214 iounmap(ha->brd);
1215 pci_write_config_dword(pcistr->pdev,
1216 PCI_BASE_ADDRESS_0, i);
1217 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1218 if (ha->brd == NULL) {
1219 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1220 return 0;
1221 }
1222 dp6_ptr = ha->brd;
1223 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1224 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1225 printk("GDT-PCI: Use free address at 0x%x\n", i);
1226 found = TRUE;
1227 break;
1228 }
1229 }
1230 if (!found) {
1231 printk("GDT-PCI: No free address found!\n");
1232 iounmap(ha->brd);
1233 return 0;
1234 }
1235 }
1236 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1237 if (gdth_readl(&dp6_ptr->u) != 0) {
1238 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1239 iounmap(ha->brd);
1240 return 0;
1241 }
1242
1243 /* disable board interrupts, deinit services */
1244 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1245 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1246 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1247 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1248
1249 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1250 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1251 gdth_writeb(0, &dp6_ptr->io.event);
1252 retries = INIT_RETRIES;
1253 gdth_delay(20);
1254 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1255 if (--retries == 0) {
1256 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1257 iounmap(ha->brd);
1258 return 0;
1259 }
1260 gdth_delay(1);
1261 }
1262 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1263 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1264 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1265 if (prot_ver != PROTOCOL_VERSION) {
1266 printk("GDT-PCI: Illegal protocol version\n");
1267 iounmap(ha->brd);
1268 return 0;
1269 }
1270
1271 ha->type = GDT_PCI;
1272 ha->ic_all_size = sizeof(dp6_ptr->u);
1273
1274 /* special command to controller BIOS */
1275 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1276 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1277 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1278 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1279 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1280 gdth_writeb(0, &dp6_ptr->io.event);
1281 retries = INIT_RETRIES;
1282 gdth_delay(20);
1283 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1284 if (--retries == 0) {
1285 printk("GDT-PCI: Initialization error\n");
1286 iounmap(ha->brd);
1287 return 0;
1288 }
1289 gdth_delay(1);
1290 }
1291 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1292 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1293
1294 ha->dma64_support = 0;
1295
1296 } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1297 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1298 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1299 pcistr->dpmem,ha->irq));
1300 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1301 if (ha->brd == NULL) {
1302 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1303 iounmap(ha->brd);
1304 return 0;
1305 }
1306 /* check and reset interface area */
1307 dp6c_ptr = ha->brd;
1308 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1309 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1310 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1311 pcistr->dpmem);
1312 found = FALSE;
1313 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1314 iounmap(ha->brd);
1315 ha->brd = ioremap(i, sizeof(ushort));
1316 if (ha->brd == NULL) {
1317 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1318 return 0;
1319 }
1320 if (gdth_readw(ha->brd) != 0xffff) {
1321 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1322 continue;
1323 }
1324 iounmap(ha->brd);
1325 pci_write_config_dword(pcistr->pdev,
1326 PCI_BASE_ADDRESS_2, i);
1327 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1328 if (ha->brd == NULL) {
1329 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1330 return 0;
1331 }
1332 dp6c_ptr = ha->brd;
1333 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1334 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1335 printk("GDT-PCI: Use free address at 0x%x\n", i);
1336 found = TRUE;
1337 break;
1338 }
1339 }
1340 if (!found) {
1341 printk("GDT-PCI: No free address found!\n");
1342 iounmap(ha->brd);
1343 return 0;
1344 }
1345 }
1346 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1347 if (gdth_readl(&dp6c_ptr->u) != 0) {
1348 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1349 iounmap(ha->brd);
1350 return 0;
1351 }
1352
1353 /* disable board interrupts, deinit services */
1354 outb(0x00,PTR2USHORT(&ha->plx->control1));
1355 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1356
1357 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1358 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1359
1360 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1361 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1362
1363 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1364
1365 retries = INIT_RETRIES;
1366 gdth_delay(20);
1367 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1368 if (--retries == 0) {
1369 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1370 iounmap(ha->brd);
1371 return 0;
1372 }
1373 gdth_delay(1);
1374 }
1375 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1376 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1377 if (prot_ver != PROTOCOL_VERSION) {
1378 printk("GDT-PCI: Illegal protocol version\n");
1379 iounmap(ha->brd);
1380 return 0;
1381 }
1382
1383 ha->type = GDT_PCINEW;
1384 ha->ic_all_size = sizeof(dp6c_ptr->u);
1385
1386 /* special command to controller BIOS */
1387 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1388 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1389 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1390 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1391 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1392
1393 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1394
1395 retries = INIT_RETRIES;
1396 gdth_delay(20);
1397 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1398 if (--retries == 0) {
1399 printk("GDT-PCI: Initialization error\n");
1400 iounmap(ha->brd);
1401 return 0;
1402 }
1403 gdth_delay(1);
1404 }
1405 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1406
1407 ha->dma64_support = 0;
1408
1409 } else { /* MPR */
1410 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1411 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1412 if (ha->brd == NULL) {
1413 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1414 return 0;
1415 }
1416
1417 /* manipulate config. space to enable DPMEM, start RP controller */
1418 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1419 command |= 6;
1420 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1421 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1422 pci_resource_start(pcistr->pdev, 8) = 0UL;
1423 i = 0xFEFF0001UL;
1424 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1425 gdth_delay(1);
1426 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1427 pci_resource_start(pcistr->pdev, 8));
1428
1429 dp6m_ptr = ha->brd;
1430
1431 /* Ensure that it is safe to access the non HW portions of DPMEM.
1432 * Aditional check needed for Xscale based RAID controllers */
1433 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1434 gdth_delay(1);
1435
1436 /* check and reset interface area */
1437 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1438 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1439 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1440 pcistr->dpmem);
1441 found = FALSE;
1442 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1443 iounmap(ha->brd);
1444 ha->brd = ioremap(i, sizeof(ushort));
1445 if (ha->brd == NULL) {
1446 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1447 return 0;
1448 }
1449 if (gdth_readw(ha->brd) != 0xffff) {
1450 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1451 continue;
1452 }
1453 iounmap(ha->brd);
1454 pci_write_config_dword(pcistr->pdev,
1455 PCI_BASE_ADDRESS_0, i);
1456 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1457 if (ha->brd == NULL) {
1458 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1459 return 0;
1460 }
1461 dp6m_ptr = ha->brd;
1462 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1463 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1464 printk("GDT-PCI: Use free address at 0x%x\n", i);
1465 found = TRUE;
1466 break;
1467 }
1468 }
1469 if (!found) {
1470 printk("GDT-PCI: No free address found!\n");
1471 iounmap(ha->brd);
1472 return 0;
1473 }
1474 }
1475 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1476
1477 /* disable board interrupts, deinit services */
1478 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1479 &dp6m_ptr->i960r.edoor_en_reg);
1480 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1481 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1482 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1483
1484 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1485 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1486 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1487 retries = INIT_RETRIES;
1488 gdth_delay(20);
1489 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1490 if (--retries == 0) {
1491 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1492 iounmap(ha->brd);
1493 return 0;
1494 }
1495 gdth_delay(1);
1496 }
1497 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1498 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1499 if (prot_ver != PROTOCOL_VERSION) {
1500 printk("GDT-PCI: Illegal protocol version\n");
1501 iounmap(ha->brd);
1502 return 0;
1503 }
1504
1505 ha->type = GDT_PCIMPR;
1506 ha->ic_all_size = sizeof(dp6m_ptr->u);
1507
1508 /* special command to controller BIOS */
1509 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1510 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1511 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1512 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1513 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1514 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1515 retries = INIT_RETRIES;
1516 gdth_delay(20);
1517 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1518 if (--retries == 0) {
1519 printk("GDT-PCI: Initialization error\n");
1520 iounmap(ha->brd);
1521 return 0;
1522 }
1523 gdth_delay(1);
1524 }
1525 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1526
1527 /* read FW version to detect 64-bit DMA support */
1528 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1529 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1530 retries = INIT_RETRIES;
1531 gdth_delay(20);
1532 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1533 if (--retries == 0) {
1534 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1535 iounmap(ha->brd);
1536 return 0;
1537 }
1538 gdth_delay(1);
1539 }
1540 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1541 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1542 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1543 ha->dma64_support = 0;
1544 else
1545 ha->dma64_support = 1;
1546 }
1547
1548 return 1;
1549}
1550
1551
1552/* controller protocol functions */
1553
1554static void __init gdth_enable_int(int hanum)
1555{
1556 gdth_ha_str *ha;
1557 ulong flags;
1558 gdt2_dpram_str __iomem *dp2_ptr;
1559 gdt6_dpram_str __iomem *dp6_ptr;
1560 gdt6m_dpram_str __iomem *dp6m_ptr;
1561
1562 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1563 ha = HADATA(gdth_ctr_tab[hanum]);
1564 spin_lock_irqsave(&ha->smp_lock, flags);
1565
1566 if (ha->type == GDT_EISA) {
1567 outb(0xff, ha->bmic + EDOORREG);
1568 outb(0xff, ha->bmic + EDENABREG);
1569 outb(0x01, ha->bmic + EINTENABREG);
1570 } else if (ha->type == GDT_ISA) {
1571 dp2_ptr = ha->brd;
1572 gdth_writeb(1, &dp2_ptr->io.irqdel);
1573 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1574 gdth_writeb(1, &dp2_ptr->io.irqen);
1575 } else if (ha->type == GDT_PCI) {
1576 dp6_ptr = ha->brd;
1577 gdth_writeb(1, &dp6_ptr->io.irqdel);
1578 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1579 gdth_writeb(1, &dp6_ptr->io.irqen);
1580 } else if (ha->type == GDT_PCINEW) {
1581 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1582 outb(0x03, PTR2USHORT(&ha->plx->control1));
1583 } else if (ha->type == GDT_PCIMPR) {
1584 dp6m_ptr = ha->brd;
1585 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1586 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1587 &dp6m_ptr->i960r.edoor_en_reg);
1588 }
1589 spin_unlock_irqrestore(&ha->smp_lock, flags);
1590}
1591
1592
1593static int gdth_get_status(unchar *pIStatus,int irq)
1594{
1595 register gdth_ha_str *ha;
1596 int i;
1597
1598 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1599 irq,gdth_ctr_count));
1600
1601 *pIStatus = 0;
1602 for (i=0; i<gdth_ctr_count; ++i) {
1603 ha = HADATA(gdth_ctr_tab[i]);
1604 if (ha->irq != (unchar)irq) /* check IRQ */
1605 continue;
1606 if (ha->type == GDT_EISA)
1607 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1608 else if (ha->type == GDT_ISA)
1609 *pIStatus =
1610 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1611 else if (ha->type == GDT_PCI)
1612 *pIStatus =
1613 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1614 else if (ha->type == GDT_PCINEW)
1615 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1616 else if (ha->type == GDT_PCIMPR)
1617 *pIStatus =
1618 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1619
1620 if (*pIStatus)
1621 return i; /* board found */
1622 }
1623 return -1;
1624}
1625
1626
1627static int gdth_test_busy(int hanum)
1628{
1629 register gdth_ha_str *ha;
1630 register int gdtsema0 = 0;
1631
1632 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1633
1634 ha = HADATA(gdth_ctr_tab[hanum]);
1635 if (ha->type == GDT_EISA)
1636 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1637 else if (ha->type == GDT_ISA)
1638 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1639 else if (ha->type == GDT_PCI)
1640 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1641 else if (ha->type == GDT_PCINEW)
1642 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1643 else if (ha->type == GDT_PCIMPR)
1644 gdtsema0 =
1645 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1646
1647 return (gdtsema0 & 1);
1648}
1649
1650
1651static int gdth_get_cmd_index(int hanum)
1652{
1653 register gdth_ha_str *ha;
1654 int i;
1655
1656 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1657
1658 ha = HADATA(gdth_ctr_tab[hanum]);
1659 for (i=0; i<GDTH_MAXCMDS; ++i) {
1660 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1661 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1662 ha->cmd_tab[i].service = ha->pccb->Service;
1663 ha->pccb->CommandIndex = (ulong32)i+2;
1664 return (i+2);
1665 }
1666 }
1667 return 0;
1668}
1669
1670
1671static void gdth_set_sema0(int hanum)
1672{
1673 register gdth_ha_str *ha;
1674
1675 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1676
1677 ha = HADATA(gdth_ctr_tab[hanum]);
1678 if (ha->type == GDT_EISA) {
1679 outb(1, ha->bmic + SEMA0REG);
1680 } else if (ha->type == GDT_ISA) {
1681 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1682 } else if (ha->type == GDT_PCI) {
1683 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1684 } else if (ha->type == GDT_PCINEW) {
1685 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1686 } else if (ha->type == GDT_PCIMPR) {
1687 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1688 }
1689}
1690
1691
1692static void gdth_copy_command(int hanum)
1693{
1694 register gdth_ha_str *ha;
1695 register gdth_cmd_str *cmd_ptr;
1696 register gdt6m_dpram_str __iomem *dp6m_ptr;
1697 register gdt6c_dpram_str __iomem *dp6c_ptr;
1698 gdt6_dpram_str __iomem *dp6_ptr;
1699 gdt2_dpram_str __iomem *dp2_ptr;
1700 ushort cp_count,dp_offset,cmd_no;
1701
1702 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1703
1704 ha = HADATA(gdth_ctr_tab[hanum]);
1705 cp_count = ha->cmd_len;
1706 dp_offset= ha->cmd_offs_dpmem;
1707 cmd_no = ha->cmd_cnt;
1708 cmd_ptr = ha->pccb;
1709
1710 ++ha->cmd_cnt;
1711 if (ha->type == GDT_EISA)
1712 return; /* no DPMEM, no copy */
1713
1714 /* set cpcount dword aligned */
1715 if (cp_count & 3)
1716 cp_count += (4 - (cp_count & 3));
1717
1718 ha->cmd_offs_dpmem += cp_count;
1719
1720 /* set offset and service, copy command to DPMEM */
1721 if (ha->type == GDT_ISA) {
1722 dp2_ptr = ha->brd;
1723 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1724 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1725 gdth_writew((ushort)cmd_ptr->Service,
1726 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1727 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1728 } else if (ha->type == GDT_PCI) {
1729 dp6_ptr = ha->brd;
1730 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1731 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1732 gdth_writew((ushort)cmd_ptr->Service,
1733 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1734 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1735 } else if (ha->type == GDT_PCINEW) {
1736 dp6c_ptr = ha->brd;
1737 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1738 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1739 gdth_writew((ushort)cmd_ptr->Service,
1740 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1741 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1742 } else if (ha->type == GDT_PCIMPR) {
1743 dp6m_ptr = ha->brd;
1744 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1745 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1746 gdth_writew((ushort)cmd_ptr->Service,
1747 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1748 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1749 }
1750}
1751
1752
1753static void gdth_release_event(int hanum)
1754{
1755 register gdth_ha_str *ha;
1756
1757 TRACE(("gdth_release_event() hanum %d\n",hanum));
1758 ha = HADATA(gdth_ctr_tab[hanum]);
1759
1760#ifdef GDTH_STATISTICS
1761 {
1762 ulong32 i,j;
1763 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1764 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1765 ++i;
1766 }
1767 if (max_index < i) {
1768 max_index = i;
1769 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1770 }
1771 }
1772#endif
1773
1774 if (ha->pccb->OpCode == GDT_INIT)
1775 ha->pccb->Service |= 0x80;
1776
1777 if (ha->type == GDT_EISA) {
1778 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1779 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1780 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1781 } else if (ha->type == GDT_ISA) {
1782 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1783 } else if (ha->type == GDT_PCI) {
1784 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1785 } else if (ha->type == GDT_PCINEW) {
1786 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1787 } else if (ha->type == GDT_PCIMPR) {
1788 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1789 }
1790}
1791
1792
1793static int gdth_wait(int hanum,int index,ulong32 time)
1794{
1795 gdth_ha_str *ha;
1796 int answer_found = FALSE;
1797
1798 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1799
1800 ha = HADATA(gdth_ctr_tab[hanum]);
1801 if (index == 0)
1802 return 1; /* no wait required */
1803
1804 gdth_from_wait = TRUE;
1805 do {
7d12e780 1806 gdth_interrupt((int)ha->irq,ha);
1da177e4
LT		 1807 if (wait_hanum==hanum && wait_index==index) {
1808 answer_found = TRUE;
1809 break;
1810 }
1811 gdth_delay(1);
1812 } while (--time);
1813 gdth_from_wait = FALSE;
1814
1815 while (gdth_test_busy(hanum))
1816 gdth_delay(0);
1817
1818 return (answer_found);
1819}
1820
1821
1822static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1823 ulong64 p2,ulong64 p3)
1824{
1825 register gdth_ha_str *ha;
1826 register gdth_cmd_str *cmd_ptr;
1827 int retries,index;
1828
1829 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1830
1831 ha = HADATA(gdth_ctr_tab[hanum]);
1832 cmd_ptr = ha->pccb;
1833 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1834
1835 /* make command */
1836 for (retries = INIT_RETRIES;;) {
1837 cmd_ptr->Service = service;
1838 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1839 if (!(index=gdth_get_cmd_index(hanum))) {
1840 TRACE(("GDT: No free command index found\n"));
1841 return 0;
1842 }
1843 gdth_set_sema0(hanum);
1844 cmd_ptr->OpCode = opcode;
1845 cmd_ptr->BoardNode = LOCALBOARD;
1846 if (service == CACHESERVICE) {
1847 if (opcode == GDT_IOCTL) {
1848 cmd_ptr->u.ioctl.subfunc = p1;
1849 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1850 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1851 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1852 } else {
1853 if (ha->cache_feat & GDT_64BIT) {
1854 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1855 cmd_ptr->u.cache64.BlockNo = p2;
1856 } else {
1857 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1858 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1859 }
1860 }
1861 } else if (service == SCSIRAWSERVICE) {
1862 if (ha->raw_feat & GDT_64BIT) {
1863 cmd_ptr->u.raw64.direction = p1;
1864 cmd_ptr->u.raw64.bus = (unchar)p2;
1865 cmd_ptr->u.raw64.target = (unchar)p3;
1866 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1867 } else {
1868 cmd_ptr->u.raw.direction = p1;
1869 cmd_ptr->u.raw.bus = (unchar)p2;
1870 cmd_ptr->u.raw.target = (unchar)p3;
1871 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1872 }
1873 } else if (service == SCREENSERVICE) {
1874 if (opcode == GDT_REALTIME) {
1875 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1876 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1877 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1878 }
1879 }
1880 ha->cmd_len = sizeof(gdth_cmd_str);
1881 ha->cmd_offs_dpmem = 0;
1882 ha->cmd_cnt = 0;
1883 gdth_copy_command(hanum);
1884 gdth_release_event(hanum);
1885 gdth_delay(20);
1886 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1887 printk("GDT: Initialization error (timeout service %d)\n",service);
1888 return 0;
1889 }
1890 if (ha->status != S_BSY || --retries == 0)
1891 break;
1892 gdth_delay(1);
1893 }
1894
1895 return (ha->status != S_OK ? 0:1);
1896}
1897
1898
1899/* search for devices */
1900
1901static int __init gdth_search_drives(int hanum)
1902{
1903 register gdth_ha_str *ha;
1904 ushort cdev_cnt, i;
1905 int ok;
1906 ulong32 bus_no, drv_cnt, drv_no, j;
1907 gdth_getch_str *chn;
1908 gdth_drlist_str *drl;
1909 gdth_iochan_str *ioc;
1910 gdth_raw_iochan_str *iocr;
1911 gdth_arcdl_str *alst;
1912 gdth_alist_str *alst2;
1913 gdth_oem_str_ioctl *oemstr;
1914#ifdef INT_COAL
1915 gdth_perf_modes *pmod;
1916#endif
1917
1918#ifdef GDTH_RTC
1919 unchar rtc[12];
1920 ulong flags;
1921#endif
1922
1923 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1924 ha = HADATA(gdth_ctr_tab[hanum]);
1925 ok = 0;
1926
1927 /* initialize controller services, at first: screen service */
1928 ha->screen_feat = 0;
1929 if (!force_dma32) {
1930 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1931 if (ok)
1932 ha->screen_feat = GDT_64BIT;
1933 }
1934 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1935 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1936 if (!ok) {
1937 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1938 hanum, ha->status);
1939 return 0;
1940 }
1941 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1942
1943#ifdef GDTH_RTC
1944 /* read realtime clock info, send to controller */
1945 /* 1. wait for the falling edge of update flag */
1946 spin_lock_irqsave(&rtc_lock, flags);
1947 for (j = 0; j < 1000000; ++j)
1948 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1949 break;
1950 for (j = 0; j < 1000000; ++j)
1951 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1952 break;
1953 /* 2. read info */
1954 do {
1955 for (j = 0; j < 12; ++j)
1956 rtc[j] = CMOS_READ(j);
1957 } while (rtc[0] != CMOS_READ(0));
1958 spin_lock_irqrestore(&rtc_lock, flags);
1959 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1960 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1961 /* 3. send to controller firmware */
1962 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1963 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1964#endif
1965
1966 /* unfreeze all IOs */
1967 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1968
1969 /* initialize cache service */
1970 ha->cache_feat = 0;
1971 if (!force_dma32) {
1972 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1973 if (ok)
1974 ha->cache_feat = GDT_64BIT;
1975 }
1976 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1977 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1978 if (!ok) {
1979 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1980 hanum, ha->status);
1981 return 0;
1982 }
1983 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1984 cdev_cnt = (ushort)ha->info;
1985 ha->fw_vers = ha->service;
1986
1987#ifdef INT_COAL
1988 if (ha->type == GDT_PCIMPR) {
1989 /* set perf. modes */
1990 pmod = (gdth_perf_modes *)ha->pscratch;
1991 pmod->version = 1;
1992 pmod->st_mode = 1; /* enable one status buffer */
1993 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1994 pmod->st_buff_indx1 = COALINDEX;
1995 pmod->st_buff_addr2 = 0;
1996 pmod->st_buff_u_addr2 = 0;
1997 pmod->st_buff_indx2 = 0;
1998 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1999 pmod->cmd_mode = 0; // disable all cmd buffers
2000 pmod->cmd_buff_addr1 = 0;
2001 pmod->cmd_buff_u_addr1 = 0;
2002 pmod->cmd_buff_indx1 = 0;
2003 pmod->cmd_buff_addr2 = 0;
2004 pmod->cmd_buff_u_addr2 = 0;
2005 pmod->cmd_buff_indx2 = 0;
2006 pmod->cmd_buff_size = 0;
2007 pmod->reserved1 = 0;
2008 pmod->reserved2 = 0;
2009 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
2010 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
2011 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
2012 }
2013 }
2014#endif
2015
2016 /* detect number of buses - try new IOCTL */
2017 iocr = (gdth_raw_iochan_str *)ha->pscratch;
2018 iocr->hdr.version = 0xffffffff;
2019 iocr->hdr.list_entries = MAXBUS;
2020 iocr->hdr.first_chan = 0;
2021 iocr->hdr.last_chan = MAXBUS-1;
2022 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
2023 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
2024 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
2025 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
2026 ha->bus_cnt = iocr->hdr.chan_count;
2027 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2028 if (iocr->list[bus_no].proc_id < MAXID)
2029 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
2030 else
2031 ha->bus_id[bus_no] = 0xff;
2032 }
2033 } else {
2034 /* old method */
2035 chn = (gdth_getch_str *)ha->pscratch;
2036 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
2037 chn->channel_no = bus_no;
2038 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2039 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2040 IO_CHANNEL | INVALID_CHANNEL,
2041 sizeof(gdth_getch_str))) {
2042 if (bus_no == 0) {
2043 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
2044 hanum, ha->status);
2045 return 0;
2046 }
2047 break;
2048 }
2049 if (chn->siop_id < MAXID)
2050 ha->bus_id[bus_no] = chn->siop_id;
2051 else
2052 ha->bus_id[bus_no] = 0xff;
2053 }
2054 ha->bus_cnt = (unchar)bus_no;
2055 }
2056 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
2057
2058 /* read cache configuration */
2059 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
2060 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
2061 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
2062 hanum, ha->status);
2063 return 0;
2064 }
2065 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
2066 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
2067 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
2068 ha->cpar.write_back,ha->cpar.block_size));
2069
2070 /* read board info and features */
2071 ha->more_proc = FALSE;
2072 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
2073 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
2074 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
2075 sizeof(gdth_binfo_str));
2076 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
2077 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
2078 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
2079 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
2080 ha->more_proc = TRUE;
2081 }
2082 } else {
2083 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
2084 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
2085 }
2086 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
2087
2088 /* read more informations */
2089 if (ha->more_proc) {
2090 /* physical drives, channel addresses */
2091 ioc = (gdth_iochan_str *)ha->pscratch;
2092 ioc->hdr.version = 0xffffffff;
2093 ioc->hdr.list_entries = MAXBUS;
2094 ioc->hdr.first_chan = 0;
2095 ioc->hdr.last_chan = MAXBUS-1;
2096 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
2097 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
2098 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
2099 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2100 ha->raw[bus_no].address = ioc->list[bus_no].address;
2101 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
2102 }
2103 } else {
2104 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2105 ha->raw[bus_no].address = IO_CHANNEL;
2106 ha->raw[bus_no].local_no = bus_no;
2107 }
2108 }
2109 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2110 chn = (gdth_getch_str *)ha->pscratch;
2111 chn->channel_no = ha->raw[bus_no].local_no;
2112 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2113 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2114 ha->raw[bus_no].address | INVALID_CHANNEL,
2115 sizeof(gdth_getch_str))) {
2116 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2117 TRACE2(("Channel %d: %d phys. drives\n",
2118 bus_no,chn->drive_cnt));
2119 }
2120 if (ha->raw[bus_no].pdev_cnt > 0) {
2121 drl = (gdth_drlist_str *)ha->pscratch;
2122 drl->sc_no = ha->raw[bus_no].local_no;
2123 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2124 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2125 SCSI_DR_LIST | L_CTRL_PATTERN,
2126 ha->raw[bus_no].address | INVALID_CHANNEL,
2127 sizeof(gdth_drlist_str))) {
2128 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2129 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2130 } else {
2131 ha->raw[bus_no].pdev_cnt = 0;
2132 }
2133 }
2134 }
2135
2136 /* logical drives */
2137 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2138 INVALID_CHANNEL,sizeof(ulong32))) {
2139 drv_cnt = *(ulong32 *)ha->pscratch;
2140 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2141 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2142 for (j = 0; j < drv_cnt; ++j) {
2143 drv_no = ((ulong32 *)ha->pscratch)[j];
2144 if (drv_no < MAX_LDRIVES) {
2145 ha->hdr[drv_no].is_logdrv = TRUE;
2146 TRACE2(("Drive %d is log. drive\n",drv_no));
2147 }
2148 }
2149 }
2150 alst = (gdth_arcdl_str *)ha->pscratch;
2151 alst->entries_avail = MAX_LDRIVES;
2152 alst->first_entry = 0;
2153 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2154 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2155 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2156 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2157 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2158 for (j = 0; j < alst->entries_init; ++j) {
2159 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2160 ha->hdr[j].is_master = alst->list[j].is_master;
2161 ha->hdr[j].is_parity = alst->list[j].is_parity;
2162 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2163 ha->hdr[j].master_no = alst->list[j].cd_handle;
2164 }
2165 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2166 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2167 0, 35 * sizeof(gdth_alist_str))) {
2168 for (j = 0; j < 35; ++j) {
2169 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2170 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2171 ha->hdr[j].is_master = alst2->is_master;
2172 ha->hdr[j].is_parity = alst2->is_parity;
2173 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2174 ha->hdr[j].master_no = alst2->cd_handle;
2175 }
2176 }
2177 }
2178 }
2179
2180 /* initialize raw service */
2181 ha->raw_feat = 0;
2182 if (!force_dma32) {
2183 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2184 if (ok)
2185 ha->raw_feat = GDT_64BIT;
2186 }
2187 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2188 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2189 if (!ok) {
2190 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2191 hanum, ha->status);
2192 return 0;
2193 }
2194 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2195
2196 /* set/get features raw service (scatter/gather) */
2197 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2198 0,0)) {
2199 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2200 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2201 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2202 ha->info));
2203 ha->raw_feat |= (ushort)ha->info;
2204 }
2205 }
2206
2207 /* set/get features cache service (equal to raw service) */
2208 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2209 SCATTER_GATHER,0)) {
2210 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2211 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2212 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2213 ha->info));
2214 ha->cache_feat |= (ushort)ha->info;
2215 }
2216 }
2217
2218 /* reserve drives for raw service */
2219 if (reserve_mode != 0) {
2220 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2221 reserve_mode == 1 ? 1 : 3, 0, 0);
2222 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2223 ha->status));
2224 }
2225 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2226 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2227 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2228 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2229 reserve_list[i], reserve_list[i+1],
2230 reserve_list[i+2], reserve_list[i+3]));
2231 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2232 reserve_list[i+1], reserve_list[i+2] |
2233 (reserve_list[i+3] << 8))) {
2234 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2235 hanum, ha->status);
2236 }
2237 }
2238 }
2239
2240 /* Determine OEM string using IOCTL */
2241 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2242 oemstr->params.ctl_version = 0x01;
2243 oemstr->params.buffer_size = sizeof(oemstr->text);
2244 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2245 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2246 sizeof(gdth_oem_str_ioctl))) {
2247 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2248 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2249 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2250 /* Save the Host Drive inquiry data */
2251#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2252 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2253 sizeof(ha->oem_name));
2254#else
2255 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2256 ha->oem_name[7] = '\0';
2257#endif
2258 } else {
2259 /* Old method, based on PCI ID */
2260 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2261 printk("GDT-HA %d: Name: %s\n",
2262 hanum,ha->binfo.type_string);
2263#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2264 if (ha->oem_id == OEM_ID_INTEL)
2265 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2266 else
2267 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2268#else
2269 if (ha->oem_id == OEM_ID_INTEL)
2270 strcpy(ha->oem_name,"Intel ");
2271 else
2272 strcpy(ha->oem_name,"ICP ");
2273#endif
2274 }
2275
2276 /* scanning for host drives */
2277 for (i = 0; i < cdev_cnt; ++i)
2278 gdth_analyse_hdrive(hanum,i);
2279
2280 TRACE(("gdth_search_drives() OK\n"));
2281 return 1;
2282}
2283
2284static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2285{
2286 register gdth_ha_str *ha;
2287 ulong32 drv_cyls;
2288 int drv_hds, drv_secs;
2289
2290 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2291 if (hdrive >= MAX_HDRIVES)
2292 return 0;
2293 ha = HADATA(gdth_ctr_tab[hanum]);
2294
2295 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2296 return 0;
2297 ha->hdr[hdrive].present = TRUE;
2298 ha->hdr[hdrive].size = ha->info;
2299
2300 /* evaluate mapping (sectors per head, heads per cylinder) */
2301 ha->hdr[hdrive].size &= ~SECS32;
2302 if (ha->info2 == 0) {
2303 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2304 } else {
2305 drv_hds = ha->info2 & 0xff;
2306 drv_secs = (ha->info2 >> 8) & 0xff;
2307 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2308 }
2309 ha->hdr[hdrive].heads = (unchar)drv_hds;
2310 ha->hdr[hdrive].secs = (unchar)drv_secs;
2311 /* round size */
2312 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2313
2314 if (ha->cache_feat & GDT_64BIT) {
2315 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2316 && ha->info2 != 0) {
2317 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2318 }
2319 }
2320 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2321 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2322
2323 /* get informations about device */
2324 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2325 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2326 hdrive,ha->info));
2327 ha->hdr[hdrive].devtype = (ushort)ha->info;
2328 }
2329
2330 /* cluster info */
2331 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2332 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2333 hdrive,ha->info));
2334 if (!shared_access)
2335 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2336 }
2337
2338 /* R/W attributes */
2339 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2340 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2341 hdrive,ha->info));
2342 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2343 }
2344
2345 return 1;
2346}
2347
2348
2349/* command queueing/sending functions */
2350
2351static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2352{
2353 register gdth_ha_str *ha;
2354 register Scsi_Cmnd *pscp;
2355 register Scsi_Cmnd *nscp;
2356 ulong flags;
2357 unchar b, t;
2358
2359 TRACE(("gdth_putq() priority %d\n",priority));
2360 ha = HADATA(gdth_ctr_tab[hanum]);
2361 spin_lock_irqsave(&ha->smp_lock, flags);
2362
cbd5f69b
LA		 2363 if (scp->done != gdth_scsi_done) {
2364 scp->SCp.this_residual = (int)priority;
2365 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2366 t = scp->device->id;
2367 if (priority >= DEFAULT_PRI) {
2368 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2369 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2370 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2371 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2372 }
1da177e4
LT		 2373 }
2374 }
2375
2376 if (ha->req_first==NULL) {
2377 ha->req_first = scp; /* queue was empty */
2378 scp->SCp.ptr = NULL;
2379 } else { /* queue not empty */
2380 pscp = ha->req_first;
2381 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2382 /* priority: 0-highest,..,0xff-lowest */
2383 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2384 pscp = nscp;
2385 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2386 }
2387 pscp->SCp.ptr = (char *)scp;
2388 scp->SCp.ptr = (char *)nscp;
2389 }
2390 spin_unlock_irqrestore(&ha->smp_lock, flags);
2391
2392#ifdef GDTH_STATISTICS
2393 flags = 0;
2394 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2395 ++flags;
2396 if (max_rq < flags) {
2397 max_rq = flags;
2398 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2399 }
2400#endif
2401}
2402
2403static void gdth_next(int hanum)
2404{
2405 register gdth_ha_str *ha;
2406 register Scsi_Cmnd *pscp;
2407 register Scsi_Cmnd *nscp;
2408 unchar b, t, l, firsttime;
2409 unchar this_cmd, next_cmd;
2410 ulong flags = 0;
2411 int cmd_index;
2412
2413 TRACE(("gdth_next() hanum %d\n",hanum));
2414 ha = HADATA(gdth_ctr_tab[hanum]);
2415 if (!gdth_polling)
2416 spin_lock_irqsave(&ha->smp_lock, flags);
2417
2418 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2419 this_cmd = firsttime = TRUE;
2420 next_cmd = gdth_polling ? FALSE:TRUE;
2421 cmd_index = 0;
2422
2423 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2424 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2425 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
cbd5f69b
LA		 2426 if (nscp->done != gdth_scsi_done) {
2427 b = virt_ctr ?
2428 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2429 t = nscp->device->id;
2430 l = nscp->device->lun;
2431 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2432 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2433 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2434 continue;
2435 }
2436 } else
2437 b = t = l = 0;
1da177e4
LT		 2438
2439 if (firsttime) {
2440 if (gdth_test_busy(hanum)) { /* controller busy ? */
2441 TRACE(("gdth_next() controller %d busy !\n",hanum));
2442 if (!gdth_polling) {
2443 spin_unlock_irqrestore(&ha->smp_lock, flags);
2444 return;
2445 }
2446 while (gdth_test_busy(hanum))
2447 gdth_delay(1);
2448 }
2449 firsttime = FALSE;
2450 }
2451
cbd5f69b 2452 if (nscp->done != gdth_scsi_done) {
1da177e4
LT		 2453 if (nscp->SCp.phase == -1) {
2454 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2455 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2456 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2457 b, t, l));
2458 /* TEST_UNIT_READY -> set scan mode */
2459 if ((ha->scan_mode & 0x0f) == 0) {
2460 if (b == 0 && t == 0 && l == 0) {
2461 ha->scan_mode |= 1;
2462 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2463 }
2464 } else if ((ha->scan_mode & 0x0f) == 1) {
2465 if (b == 0 && ((t == 0 && l == 1) ||
2466 (t == 1 && l == 0))) {
2467 nscp->SCp.sent_command = GDT_SCAN_START;
2468 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2469 | SCSIRAWSERVICE;
2470 ha->scan_mode = 0x12;
2471 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2472 ha->scan_mode));
2473 } else {
2474 ha->scan_mode &= 0x10;
2475 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2476 }
2477 } else if (ha->scan_mode == 0x12) {
2478 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2479 nscp->SCp.phase = SCSIRAWSERVICE;
2480 nscp->SCp.sent_command = GDT_SCAN_END;
2481 ha->scan_mode &= 0x10;
2482 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2483 ha->scan_mode));
2484 }
2485 }
2486 }
2487 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2488 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2489 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2490 /* always GDT_CLUST_INFO! */
2491 nscp->SCp.sent_command = GDT_CLUST_INFO;
2492 }
2493 }
2494 }
2495
2496 if (nscp->SCp.sent_command != -1) {
2497 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2498 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2499 this_cmd = FALSE;
2500 next_cmd = FALSE;
2501 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2502 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2503 this_cmd = FALSE;
2504 next_cmd = FALSE;
2505 } else {
2506 memset((char*)nscp->sense_buffer,0,16);
2507 nscp->sense_buffer[0] = 0x70;
2508 nscp->sense_buffer[2] = NOT_READY;
2509 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2510 if (!nscp->SCp.have_data_in)
2511 nscp->SCp.have_data_in++;
2512 else
2513 nscp->scsi_done(nscp);
2514 }
cbd5f69b 2515 } else if (nscp->done == gdth_scsi_done) {
1da177e4
LT		 2516 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2517 this_cmd = FALSE;
2518 next_cmd = FALSE;
2519 } else if (b != ha->virt_bus) {
2520 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2521 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2522 this_cmd = FALSE;
2523 else
2524 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2525 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2526 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2527 nscp->cmnd[0], b, t, l));
2528 nscp->result = DID_BAD_TARGET << 16;
2529 if (!nscp->SCp.have_data_in)
2530 nscp->SCp.have_data_in++;
2531 else
2532 nscp->scsi_done(nscp);
2533 } else {
2534 switch (nscp->cmnd[0]) {
2535 case TEST_UNIT_READY:
2536 case INQUIRY:
2537 case REQUEST_SENSE:
2538 case READ_CAPACITY:
2539 case VERIFY:
2540 case START_STOP:
2541 case MODE_SENSE:
2542 case SERVICE_ACTION_IN:
2543 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2544 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2545 nscp->cmnd[4],nscp->cmnd[5]));
2546 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2547 /* return UNIT_ATTENTION */
2548 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2549 nscp->cmnd[0], t));
2550 ha->hdr[t].media_changed = FALSE;
2551 memset((char*)nscp->sense_buffer,0,16);
2552 nscp->sense_buffer[0] = 0x70;
2553 nscp->sense_buffer[2] = UNIT_ATTENTION;
2554 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2555 if (!nscp->SCp.have_data_in)
2556 nscp->SCp.have_data_in++;
2557 else
2558 nscp->scsi_done(nscp);
2559 } else if (gdth_internal_cache_cmd(hanum,nscp))
2560 nscp->scsi_done(nscp);
2561 break;
2562
2563 case ALLOW_MEDIUM_REMOVAL:
2564 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2565 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2566 nscp->cmnd[4],nscp->cmnd[5]));
2567 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2568 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2569 nscp->result = DID_OK << 16;
2570 nscp->sense_buffer[0] = 0;
2571 if (!nscp->SCp.have_data_in)
2572 nscp->SCp.have_data_in++;
2573 else
2574 nscp->scsi_done(nscp);
2575 } else {
2576 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2577 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2578 nscp->cmnd[4],nscp->cmnd[3]));
2579 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2580 this_cmd = FALSE;
2581 }
2582 break;
2583
2584 case RESERVE:
2585 case RELEASE:
2586 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2587 "RESERVE" : "RELEASE"));
2588 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2589 this_cmd = FALSE;
2590 break;
2591
2592 case READ_6:
2593 case WRITE_6:
2594 case READ_10:
2595 case WRITE_10:
2596 case READ_16:
2597 case WRITE_16:
2598 if (ha->hdr[t].media_changed) {
2599 /* return UNIT_ATTENTION */
2600 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2601 nscp->cmnd[0], t));
2602 ha->hdr[t].media_changed = FALSE;
2603 memset((char*)nscp->sense_buffer,0,16);
2604 nscp->sense_buffer[0] = 0x70;
2605 nscp->sense_buffer[2] = UNIT_ATTENTION;
2606 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2607 if (!nscp->SCp.have_data_in)
2608 nscp->SCp.have_data_in++;
2609 else
2610 nscp->scsi_done(nscp);
2611 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2612 this_cmd = FALSE;
2613 break;
2614
2615 default:
2616 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2617 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2618 nscp->cmnd[4],nscp->cmnd[5]));
2619 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2620 hanum, nscp->cmnd[0]);
2621 nscp->result = DID_ABORT << 16;
2622 if (!nscp->SCp.have_data_in)
2623 nscp->SCp.have_data_in++;
2624 else
2625 nscp->scsi_done(nscp);
2626 break;
2627 }
2628 }
2629
2630 if (!this_cmd)
2631 break;
2632 if (nscp == ha->req_first)
2633 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2634 else
2635 pscp->SCp.ptr = nscp->SCp.ptr;
2636 if (!next_cmd)
2637 break;
2638 }
2639
2640 if (ha->cmd_cnt > 0) {
2641 gdth_release_event(hanum);
2642 }
2643
2644 if (!gdth_polling)
2645 spin_unlock_irqrestore(&ha->smp_lock, flags);
2646
2647 if (gdth_polling && ha->cmd_cnt > 0) {
2648 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2649 printk("GDT-HA %d: Command %d timed out !\n",
2650 hanum,cmd_index);
2651 }
2652}
2653
2654static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2655 char *buffer,ushort count)
2656{
2657 ushort cpcount,i;
2658 ushort cpsum,cpnow;
2659 struct scatterlist *sl;
2660 gdth_ha_str *ha;
2661 char *address;
2662
5d5ff44f 2663 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
1da177e4
LT		 2664 ha = HADATA(gdth_ctr_tab[hanum]);
2665
2666 if (scp->use_sg) {
2667 sl = (struct scatterlist *)scp->request_buffer;
2668 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
cbd5f69b 2669 unsigned long flags;
1da177e4
LT		 2670 cpnow = (ushort)sl->length;
2671 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2672 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2673 if (cpsum+cpnow > cpcount)
2674 cpnow = cpcount - cpsum;
2675 cpsum += cpnow;
2676 if (!sl->page) {
2677 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2678 hanum);
2679 return;
2680 }
cbd5f69b
LA		 2681 local_irq_save(flags);
2682#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2683 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2684 memcpy(address,buffer,cpnow);
2685 flush_dcache_page(sl->page);
2686 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2687#else
2688 address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
1da177e4 2689 memcpy(address,buffer,cpnow);
cbd5f69b
LA		 2690 flush_dcache_page(sl->page);
2691 kunmap_atomic(address, KM_BH_IRQ);
2692#endif
2693 local_irq_restore(flags);
1da177e4
LT		 2694 if (cpsum == cpcount)
2695 break;
2696 buffer += cpnow;
2697 }
2698 } else {
2699 TRACE(("copy_internal() count %d\n",cpcount));
2700 memcpy((char*)scp->request_buffer,buffer,cpcount);
2701 }
2702}
2703
2704static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2705{
2706 register gdth_ha_str *ha;
2707 unchar t;
2708 gdth_inq_data inq;
2709 gdth_rdcap_data rdc;
2710 gdth_sense_data sd;
2711 gdth_modep_data mpd;
2712
2713 ha = HADATA(gdth_ctr_tab[hanum]);
2714 t = scp->device->id;
2715 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2716 scp->cmnd[0],t));
2717
2718 scp->result = DID_OK << 16;
2719 scp->sense_buffer[0] = 0;
2720
2721 switch (scp->cmnd[0]) {
2722 case TEST_UNIT_READY:
2723 case VERIFY:
2724 case START_STOP:
2725 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2726 break;
2727
2728 case INQUIRY:
2729 TRACE2(("Inquiry hdrive %d devtype %d\n",
2730 t,ha->hdr[t].devtype));
2731 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2732 /* you can here set all disks to removable, if you want to do
2733 a flush using the ALLOW_MEDIUM_REMOVAL command */
2734 inq.modif_rmb = 0x00;
2735 if ((ha->hdr[t].devtype & 1) ||
2736 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2737 inq.modif_rmb = 0x80;
2738 inq.version = 2;
2739 inq.resp_aenc = 2;
2740 inq.add_length= 32;
2741 strcpy(inq.vendor,ha->oem_name);
2742 sprintf(inq.product,"Host Drive #%02d",t);
2743 strcpy(inq.revision," ");
2744 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2745 break;
2746
2747 case REQUEST_SENSE:
2748 TRACE2(("Request sense hdrive %d\n",t));
2749 sd.errorcode = 0x70;
2750 sd.segno = 0x00;
2751 sd.key = NO_SENSE;
2752 sd.info = 0;
2753 sd.add_length= 0;
2754 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2755 break;
2756
2757 case MODE_SENSE:
2758 TRACE2(("Mode sense hdrive %d\n",t));
2759 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2760 mpd.hd.data_length = sizeof(gdth_modep_data);
2761 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2762 mpd.hd.bd_length = sizeof(mpd.bd);
2763 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2764 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2765 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2766 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2767 break;
2768
2769 case READ_CAPACITY:
2770 TRACE2(("Read capacity hdrive %d\n",t));
2771 if (ha->hdr[t].size > (ulong64)0xffffffff)
2772 rdc.last_block_no = 0xffffffff;
2773 else
2774 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2775 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2776 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2777 break;
2778
2779 case SERVICE_ACTION_IN:
2780 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2781 (ha->cache_feat & GDT_64BIT)) {
2782 gdth_rdcap16_data rdc16;
2783
2784 TRACE2(("Read capacity (16) hdrive %d\n",t));
2785 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2786 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2787 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2788 } else {
2789 scp->result = DID_ABORT << 16;
2790 }
2791 break;
2792
2793 default:
2794 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2795 break;
2796 }
2797
2798 if (!scp->SCp.have_data_in)
2799 scp->SCp.have_data_in++;
2800 else
2801 return 1;
2802
2803 return 0;
2804}
2805
2806static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2807{
2808 register gdth_ha_str *ha;
2809 register gdth_cmd_str *cmdp;
2810 struct scatterlist *sl;
2811 ulong32 cnt, blockcnt;
2812 ulong64 no, blockno;
2813 dma_addr_t phys_addr;
2814 int i, cmd_index, read_write, sgcnt, mode64;
2815 struct page *page;
2816 ulong offset;
2817
2818 ha = HADATA(gdth_ctr_tab[hanum]);
2819 cmdp = ha->pccb;
2820 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2821 scp->cmnd[0],scp->cmd_len,hdrive));
2822
2823 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2824 return 0;
2825
2826 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2827 /* test for READ_16, WRITE_16 if !mode64 ? ---
2828 not required, should not occur due to error return on
2829 READ_CAPACITY_16 */
2830
2831 cmdp->Service = CACHESERVICE;
2832 cmdp->RequestBuffer = scp;
2833 /* search free command index */
2834 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2835 TRACE(("GDT: No free command index found\n"));
2836 return 0;
2837 }
2838 /* if it's the first command, set command semaphore */
2839 if (ha->cmd_cnt == 0)
2840 gdth_set_sema0(hanum);
2841
2842 /* fill command */
2843 read_write = 0;
2844 if (scp->SCp.sent_command != -1)
2845 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2846 else if (scp->cmnd[0] == RESERVE)
2847 cmdp->OpCode = GDT_RESERVE_DRV;
2848 else if (scp->cmnd[0] == RELEASE)
2849 cmdp->OpCode = GDT_RELEASE_DRV;
2850 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2851 if (scp->cmnd[4] & 1) /* prevent ? */
2852 cmdp->OpCode = GDT_MOUNT;
2853 else if (scp->cmnd[3] & 1) /* removable drive ? */
2854 cmdp->OpCode = GDT_UNMOUNT;
2855 else
2856 cmdp->OpCode = GDT_FLUSH;
2857 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2858 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2859 ) {
2860 read_write = 1;
2861 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2862 (ha->cache_feat & GDT_WR_THROUGH)))
2863 cmdp->OpCode = GDT_WRITE_THR;
2864 else
2865 cmdp->OpCode = GDT_WRITE;
2866 } else {
2867 read_write = 2;
2868 cmdp->OpCode = GDT_READ;
2869 }
2870
2871 cmdp->BoardNode = LOCALBOARD;
2872 if (mode64) {
2873 cmdp->u.cache64.DeviceNo = hdrive;
2874 cmdp->u.cache64.BlockNo = 1;
2875 cmdp->u.cache64.sg_canz = 0;
2876 } else {
2877 cmdp->u.cache.DeviceNo = hdrive;
2878 cmdp->u.cache.BlockNo = 1;
2879 cmdp->u.cache.sg_canz = 0;
2880 }
2881
2882 if (read_write) {
2883 if (scp->cmd_len == 16) {
2884 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2885 blockno = be64_to_cpu(no);
2886 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2887 blockcnt = be32_to_cpu(cnt);
2888 } else if (scp->cmd_len == 10) {
2889 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2890 blockno = be32_to_cpu(no);
2891 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2892 blockcnt = be16_to_cpu(cnt);
2893 } else {
2894 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2895 blockno = be32_to_cpu(no) & 0x001fffffUL;
2896 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2897 }
2898 if (mode64) {
2899 cmdp->u.cache64.BlockNo = blockno;
2900 cmdp->u.cache64.BlockCnt = blockcnt;
2901 } else {
2902 cmdp->u.cache.BlockNo = (ulong32)blockno;
2903 cmdp->u.cache.BlockCnt = blockcnt;
2904 }
2905
2906 if (scp->use_sg) {
2907 sl = (struct scatterlist *)scp->request_buffer;
2908 sgcnt = scp->use_sg;
2909 scp->SCp.Status = GDTH_MAP_SG;
2910 scp->SCp.Message = (read_write == 1 ?
2911 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2912 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2913 if (mode64) {
2914 cmdp->u.cache64.DestAddr= (ulong64)-1;
2915 cmdp->u.cache64.sg_canz = sgcnt;
2916 for (i=0; i<sgcnt; ++i,++sl) {
2917 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2918#ifdef GDTH_DMA_STATISTICS
2919 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2920 ha->dma64_cnt++;
2921 else
2922 ha->dma32_cnt++;
2923#endif
2924 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2925 }
2926 } else {
2927 cmdp->u.cache.DestAddr= 0xffffffff;
2928 cmdp->u.cache.sg_canz = sgcnt;
2929 for (i=0; i<sgcnt; ++i,++sl) {
2930 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2931#ifdef GDTH_DMA_STATISTICS
2932 ha->dma32_cnt++;
2933#endif
2934 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2935 }
2936 }
2937
2938#ifdef GDTH_STATISTICS
2939 if (max_sg < (ulong32)sgcnt) {
2940 max_sg = (ulong32)sgcnt;
2941 TRACE3(("GDT: max_sg = %d\n",max_sg));
2942 }
2943#endif
2944
40cdc840 2945 } else if (scp->request_bufflen) {
1da177e4
LT		 2946 scp->SCp.Status = GDTH_MAP_SINGLE;
2947 scp->SCp.Message = (read_write == 1 ?
2948 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2949 page = virt_to_page(scp->request_buffer);
2950 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2951 phys_addr = pci_map_page(ha->pdev,page,offset,
2952 scp->request_bufflen,scp->SCp.Message);
2953 scp->SCp.dma_handle = phys_addr;
2954 if (mode64) {
2955 if (ha->cache_feat & SCATTER_GATHER) {
2956 cmdp->u.cache64.DestAddr = (ulong64)-1;
2957 cmdp->u.cache64.sg_canz = 1;
2958 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2959 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2960 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2961 } else {
2962 cmdp->u.cache64.DestAddr = phys_addr;
2963 cmdp->u.cache64.sg_canz= 0;
2964 }
2965 } else {
2966 if (ha->cache_feat & SCATTER_GATHER) {
2967 cmdp->u.cache.DestAddr = 0xffffffff;
2968 cmdp->u.cache.sg_canz = 1;
2969 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2970 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2971 cmdp->u.cache.sg_lst[1].sg_len = 0;
2972 } else {
2973 cmdp->u.cache.DestAddr = phys_addr;
2974 cmdp->u.cache.sg_canz= 0;
2975 }
2976 }
2977 }
2978 }
2979 /* evaluate command size, check space */
2980 if (mode64) {
2981 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2982 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2983 cmdp->u.cache64.sg_lst[0].sg_ptr,
2984 cmdp->u.cache64.sg_lst[0].sg_len));
2985 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2986 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2987 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2988 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2989 } else {
2990 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2991 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2992 cmdp->u.cache.sg_lst[0].sg_ptr,
2993 cmdp->u.cache.sg_lst[0].sg_len));
2994 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2995 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2996 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2997 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2998 }
2999 if (ha->cmd_len & 3)
3000 ha->cmd_len += (4 - (ha->cmd_len & 3));
3001
3002 if (ha->cmd_cnt > 0) {
3003 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3004 ha->ic_all_size) {
3005 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
3006 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3007 return 0;
3008 }
3009 }
3010
3011 /* copy command */
3012 gdth_copy_command(hanum);
3013 return cmd_index;
3014}
3015
3016static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
3017{
3018 register gdth_ha_str *ha;
3019 register gdth_cmd_str *cmdp;
3020 struct scatterlist *sl;
3021 ushort i;
3022 dma_addr_t phys_addr, sense_paddr;
3023 int cmd_index, sgcnt, mode64;
3024 unchar t,l;
3025 struct page *page;
3026 ulong offset;
3027
3028 ha = HADATA(gdth_ctr_tab[hanum]);
3029 t = scp->device->id;
3030 l = scp->device->lun;
3031 cmdp = ha->pccb;
3032 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
3033 scp->cmnd[0],b,t,l));
3034
3035 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3036 return 0;
3037
3038 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
3039
3040 cmdp->Service = SCSIRAWSERVICE;
3041 cmdp->RequestBuffer = scp;
3042 /* search free command index */
3043 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3044 TRACE(("GDT: No free command index found\n"));
3045 return 0;
3046 }
3047 /* if it's the first command, set command semaphore */
3048 if (ha->cmd_cnt == 0)
3049 gdth_set_sema0(hanum);
3050
3051 /* fill command */
3052 if (scp->SCp.sent_command != -1) {
3053 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
3054 cmdp->BoardNode = LOCALBOARD;
3055 if (mode64) {
3056 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
3057 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3058 cmdp->OpCode, cmdp->u.raw64.direction));
3059 /* evaluate command size */
3060 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
3061 } else {
3062 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
3063 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3064 cmdp->OpCode, cmdp->u.raw.direction));
3065 /* evaluate command size */
3066 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
3067 }
3068
3069 } else {
3070 page = virt_to_page(scp->sense_buffer);
3071 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
3072 sense_paddr = pci_map_page(ha->pdev,page,offset,
3073 16,PCI_DMA_FROMDEVICE);
cbd5f69b 3074 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
1da177e4 3075 /* high part, if 64bit */
cbd5f69b 3076 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
1da177e4
LT		 3077 cmdp->OpCode = GDT_WRITE; /* always */
3078 cmdp->BoardNode = LOCALBOARD;
3079 if (mode64) {
3080 cmdp->u.raw64.reserved = 0;
3081 cmdp->u.raw64.mdisc_time = 0;
3082 cmdp->u.raw64.mcon_time = 0;
3083 cmdp->u.raw64.clen = scp->cmd_len;
3084 cmdp->u.raw64.target = t;
3085 cmdp->u.raw64.lun = l;
3086 cmdp->u.raw64.bus = b;
3087 cmdp->u.raw64.priority = 0;
3088 cmdp->u.raw64.sdlen = scp->request_bufflen;
3089 cmdp->u.raw64.sense_len = 16;
3090 cmdp->u.raw64.sense_data = sense_paddr;
3091 cmdp->u.raw64.direction =
3092 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3093 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
3094 } else {
3095 cmdp->u.raw.reserved = 0;
3096 cmdp->u.raw.mdisc_time = 0;
3097 cmdp->u.raw.mcon_time = 0;
3098 cmdp->u.raw.clen = scp->cmd_len;
3099 cmdp->u.raw.target = t;
3100 cmdp->u.raw.lun = l;
3101 cmdp->u.raw.bus = b;
3102 cmdp->u.raw.priority = 0;
3103 cmdp->u.raw.link_p = 0;
3104 cmdp->u.raw.sdlen = scp->request_bufflen;
3105 cmdp->u.raw.sense_len = 16;
3106 cmdp->u.raw.sense_data = sense_paddr;
3107 cmdp->u.raw.direction =
3108 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3109 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
3110 }
3111
3112 if (scp->use_sg) {
3113 sl = (struct scatterlist *)scp->request_buffer;
3114 sgcnt = scp->use_sg;
3115 scp->SCp.Status = GDTH_MAP_SG;
3116 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3117 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
3118 if (mode64) {
3119 cmdp->u.raw64.sdata = (ulong64)-1;
3120 cmdp->u.raw64.sg_ranz = sgcnt;
3121 for (i=0; i<sgcnt; ++i,++sl) {
3122 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
3123#ifdef GDTH_DMA_STATISTICS
3124 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3125 ha->dma64_cnt++;
3126 else
3127 ha->dma32_cnt++;
3128#endif
3129 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3130 }
3131 } else {
3132 cmdp->u.raw.sdata = 0xffffffff;
3133 cmdp->u.raw.sg_ranz = sgcnt;
3134 for (i=0; i<sgcnt; ++i,++sl) {
3135 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3136#ifdef GDTH_DMA_STATISTICS
3137 ha->dma32_cnt++;
3138#endif
3139 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3140 }
3141 }
3142
3143#ifdef GDTH_STATISTICS
3144 if (max_sg < sgcnt) {
3145 max_sg = sgcnt;
3146 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3147 }
3148#endif
3149
cbd5f69b 3150 } else if (scp->request_bufflen) {
1da177e4
LT		 3151 scp->SCp.Status = GDTH_MAP_SINGLE;
3152 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3153 page = virt_to_page(scp->request_buffer);
3154 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3155 phys_addr = pci_map_page(ha->pdev,page,offset,
3156 scp->request_bufflen,scp->SCp.Message);
3157 scp->SCp.dma_handle = phys_addr;
3158
3159 if (mode64) {
3160 if (ha->raw_feat & SCATTER_GATHER) {
3161 cmdp->u.raw64.sdata = (ulong64)-1;
3162 cmdp->u.raw64.sg_ranz= 1;
3163 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3164 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3165 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3166 } else {
3167 cmdp->u.raw64.sdata = phys_addr;
3168 cmdp->u.raw64.sg_ranz= 0;
3169 }
3170 } else {
3171 if (ha->raw_feat & SCATTER_GATHER) {
3172 cmdp->u.raw.sdata = 0xffffffff;
3173 cmdp->u.raw.sg_ranz= 1;
3174 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3175 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3176 cmdp->u.raw.sg_lst[1].sg_len = 0;
3177 } else {
3178 cmdp->u.raw.sdata = phys_addr;
3179 cmdp->u.raw.sg_ranz= 0;
3180 }
3181 }
3182 }
3183 if (mode64) {
3184 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3185 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3186 cmdp->u.raw64.sg_lst[0].sg_ptr,
3187 cmdp->u.raw64.sg_lst[0].sg_len));
3188 /* evaluate command size */
3189 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3190 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3191 } else {
3192 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3193 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3194 cmdp->u.raw.sg_lst[0].sg_ptr,
3195 cmdp->u.raw.sg_lst[0].sg_len));
3196 /* evaluate command size */
3197 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3198 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3199 }
3200 }
3201 /* check space */
3202 if (ha->cmd_len & 3)
3203 ha->cmd_len += (4 - (ha->cmd_len & 3));
3204
3205 if (ha->cmd_cnt > 0) {
3206 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3207 ha->ic_all_size) {
3208 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3209 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3210 return 0;
3211 }
3212 }
3213
3214 /* copy command */
3215 gdth_copy_command(hanum);
3216 return cmd_index;
3217}
3218
3219static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3220{
3221 register gdth_ha_str *ha;
3222 register gdth_cmd_str *cmdp;
3223 int cmd_index;
3224
3225 ha = HADATA(gdth_ctr_tab[hanum]);
3226 cmdp= ha->pccb;
3227 TRACE2(("gdth_special_cmd(): "));
3228
3229 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3230 return 0;
3231
3232 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3233 cmdp->RequestBuffer = scp;
3234
3235 /* search free command index */
3236 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3237 TRACE(("GDT: No free command index found\n"));
3238 return 0;
3239 }
3240
3241 /* if it's the first command, set command semaphore */
3242 if (ha->cmd_cnt == 0)
3243 gdth_set_sema0(hanum);
3244
3245 /* evaluate command size, check space */
3246 if (cmdp->OpCode == GDT_IOCTL) {
3247 TRACE2(("IOCTL\n"));
3248 ha->cmd_len =
3249 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3250 } else if (cmdp->Service == CACHESERVICE) {
3251 TRACE2(("cache command %d\n",cmdp->OpCode));
3252 if (ha->cache_feat & GDT_64BIT)
3253 ha->cmd_len =
3254 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3255 else
3256 ha->cmd_len =
3257 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3258 } else if (cmdp->Service == SCSIRAWSERVICE) {
3259 TRACE2(("raw command %d\n",cmdp->OpCode));
3260 if (ha->raw_feat & GDT_64BIT)
3261 ha->cmd_len =
3262 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3263 else
3264 ha->cmd_len =
3265 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3266 }
3267
3268 if (ha->cmd_len & 3)
3269 ha->cmd_len += (4 - (ha->cmd_len & 3));
3270
3271 if (ha->cmd_cnt > 0) {
3272 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3273 ha->ic_all_size) {
3274 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3275 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3276 return 0;
3277 }
3278 }
3279
3280 /* copy command */
3281 gdth_copy_command(hanum);
3282 return cmd_index;
3283}
3284
3285
3286/* Controller event handling functions */
3287static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3288 ushort idx, gdth_evt_data *evt)
3289{
3290 gdth_evt_str *e;
3291 struct timeval tv;
3292
3293 /* no GDTH_LOCK_HA() ! */
3294 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3295 if (source == 0) /* no source -> no event */
3296 return NULL;
3297
3298 if (ebuffer[elastidx].event_source == source &&
3299 ebuffer[elastidx].event_idx == idx &&
3300 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3301 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3302 (char *)&evt->eu, evt->size)) ||
3303 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3304 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3305 (char *)&evt->event_string)))) {
3306 e = &ebuffer[elastidx];
3307 do_gettimeofday(&tv);
3308 e->last_stamp = tv.tv_sec;
3309 ++e->same_count;
3310 } else {
3311 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3312 ++elastidx;
3313 if (elastidx == MAX_EVENTS)
3314 elastidx = 0;
3315 if (elastidx == eoldidx) { /* reached mark ? */
3316 ++eoldidx;
3317 if (eoldidx == MAX_EVENTS)
3318 eoldidx = 0;
3319 }
3320 }
3321 e = &ebuffer[elastidx];
3322 e->event_source = source;
3323 e->event_idx = idx;
3324 do_gettimeofday(&tv);
3325 e->first_stamp = e->last_stamp = tv.tv_sec;
3326 e->same_count = 1;
3327 e->event_data = *evt;
3328 e->application = 0;
3329 }
3330 return e;
3331}
3332
3333static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3334{
3335 gdth_evt_str *e;
3336 int eindex;
3337 ulong flags;
3338
3339 TRACE2(("gdth_read_event() handle %d\n", handle));
3340 spin_lock_irqsave(&ha->smp_lock, flags);
3341 if (handle == -1)
3342 eindex = eoldidx;
3343 else
3344 eindex = handle;
3345 estr->event_source = 0;
3346
3347 if (eindex >= MAX_EVENTS) {
3348 spin_unlock_irqrestore(&ha->smp_lock, flags);
3349 return eindex;
3350 }
3351 e = &ebuffer[eindex];
3352 if (e->event_source != 0) {
3353 if (eindex != elastidx) {
3354 if (++eindex == MAX_EVENTS)
3355 eindex = 0;
3356 } else {
3357 eindex = -1;
3358 }
3359 memcpy(estr, e, sizeof(gdth_evt_str));
3360 }
3361 spin_unlock_irqrestore(&ha->smp_lock, flags);
3362 return eindex;
3363}
3364
3365static void gdth_readapp_event(gdth_ha_str *ha,
3366 unchar application, gdth_evt_str *estr)
3367{
3368 gdth_evt_str *e;
3369 int eindex;
3370 ulong flags;
3371 unchar found = FALSE;
3372
3373 TRACE2(("gdth_readapp_event() app. %d\n", application));
3374 spin_lock_irqsave(&ha->smp_lock, flags);
3375 eindex = eoldidx;
3376 for (;;) {
3377 e = &ebuffer[eindex];
3378 if (e->event_source == 0)
3379 break;
3380 if ((e->application & application) == 0) {
3381 e->application |= application;
3382 found = TRUE;
3383 break;
3384 }
3385 if (eindex == elastidx)
3386 break;
3387 if (++eindex == MAX_EVENTS)
3388 eindex = 0;
3389 }
3390 if (found)
3391 memcpy(estr, e, sizeof(gdth_evt_str));
3392 else
3393 estr->event_source = 0;
3394 spin_unlock_irqrestore(&ha->smp_lock, flags);
3395}
3396
3397static void gdth_clear_events(void)
3398{
3399 TRACE(("gdth_clear_events()"));
3400
3401 eoldidx = elastidx = 0;
3402 ebuffer[0].event_source = 0;
3403}
3404
3405
3406/* SCSI interface functions */
3407
7d12e780 3408static irqreturn_t gdth_interrupt(int irq,void *dev_id)
1da177e4
LT		 3409{
3410 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3411 register gdth_ha_str *ha;
3412 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3413 gdt6_dpram_str __iomem *dp6_ptr;
3414 gdt2_dpram_str __iomem *dp2_ptr;
3415 Scsi_Cmnd *scp;
3416 int hanum, rval, i;
3417 unchar IStatus;
3418 ushort Service;
3419 ulong flags = 0;
3420#ifdef INT_COAL
3421 int coalesced = FALSE;
3422 int next = FALSE;
3423 gdth_coal_status *pcs = NULL;
3424 int act_int_coal = 0;
3425#endif
3426
3427 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3428
3429 /* if polling and not from gdth_wait() -> return */
3430 if (gdth_polling) {
3431 if (!gdth_from_wait) {
3432 return IRQ_HANDLED;
3433 }
3434 }
3435
3436 if (!gdth_polling)
cbd5f69b 3437 spin_lock_irqsave(&ha2->smp_lock, flags);
1da177e4
LT		 3438 wait_index = 0;
3439
3440 /* search controller */
3441 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3442 /* spurious interrupt */
3443 if (!gdth_polling)
3444 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3445 return IRQ_HANDLED;
3446 }
3447 ha = HADATA(gdth_ctr_tab[hanum]);
3448
3449#ifdef GDTH_STATISTICS
3450 ++act_ints;
3451#endif
3452
3453#ifdef INT_COAL
3454 /* See if the fw is returning coalesced status */
3455 if (IStatus == COALINDEX) {
3456 /* Coalesced status. Setup the initial status
3457 buffer pointer and flags */
3458 pcs = ha->coal_stat;
3459 coalesced = TRUE;
3460 next = TRUE;
3461 }
3462
3463 do {
3464 if (coalesced) {
3465 /* For coalesced requests all status
3466 information is found in the status buffer */
3467 IStatus = (unchar)(pcs->status & 0xff);
3468 }
3469#endif
3470
3471 if (ha->type == GDT_EISA) {
3472 if (IStatus & 0x80) { /* error flag */
3473 IStatus &= ~0x80;
3474 ha->status = inw(ha->bmic + MAILBOXREG+8);
3475 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3476 } else /* no error */
3477 ha->status = S_OK;
3478 ha->info = inl(ha->bmic + MAILBOXREG+12);
3479 ha->service = inw(ha->bmic + MAILBOXREG+10);
3480 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3481
3482 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3483 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3484 } else if (ha->type == GDT_ISA) {
3485 dp2_ptr = ha->brd;
3486 if (IStatus & 0x80) { /* error flag */
3487 IStatus &= ~0x80;
3488 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3489 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3490 } else /* no error */
3491 ha->status = S_OK;
3492 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3493 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3494 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3495
3496 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3497 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3498 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3499 } else if (ha->type == GDT_PCI) {
3500 dp6_ptr = ha->brd;
3501 if (IStatus & 0x80) { /* error flag */
3502 IStatus &= ~0x80;
3503 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3504 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3505 } else /* no error */
3506 ha->status = S_OK;
3507 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3508 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3509 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3510
3511 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3512 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3513 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3514 } else if (ha->type == GDT_PCINEW) {
3515 if (IStatus & 0x80) { /* error flag */
3516 IStatus &= ~0x80;
3517 ha->status = inw(PTR2USHORT(&ha->plx->status));
3518 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3519 } else
3520 ha->status = S_OK;
3521 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3522 ha->service = inw(PTR2USHORT(&ha->plx->service));
3523 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3524
3525 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3526 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3527 } else if (ha->type == GDT_PCIMPR) {
3528 dp6m_ptr = ha->brd;
3529 if (IStatus & 0x80) { /* error flag */
3530 IStatus &= ~0x80;
3531#ifdef INT_COAL
3532 if (coalesced)
107e716b 3533 ha->status = pcs->ext_status & 0xffff;
1da177e4
LT		 3534 else
3535#endif
3536 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3537 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3538 } else /* no error */
3539 ha->status = S_OK;
3540#ifdef INT_COAL
3541 /* get information */
3542 if (coalesced) {
3543 ha->info = pcs->info0;
3544 ha->info2 = pcs->info1;
107e716b 3545 ha->service = (pcs->ext_status >> 16) & 0xffff;
1da177e4
LT		 3546 } else
3547#endif
3548 {
3549 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3550 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3551 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3552 }
3553 /* event string */
3554 if (IStatus == ASYNCINDEX) {
3555 if (ha->service != SCREENSERVICE &&
3556 (ha->fw_vers & 0xff) >= 0x1a) {
3557 ha->dvr.severity = gdth_readb
3558 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3559 for (i = 0; i < 256; ++i) {
3560 ha->dvr.event_string[i] = gdth_readb
3561 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3562 if (ha->dvr.event_string[i] == 0)
3563 break;
3564 }
3565 }
3566 }
3567#ifdef INT_COAL
3568 /* Make sure that non coalesced interrupts get cleared
3569 before being handled by gdth_async_event/gdth_sync_event */
3570 if (!coalesced)
3571#endif
3572 {
3573 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3574 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3575 }
3576 } else {
3577 TRACE2(("gdth_interrupt() unknown controller type\n"));
3578 if (!gdth_polling)
3579 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3580 return IRQ_HANDLED;
3581 }
3582
3583 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3584 IStatus,ha->status,ha->info));
3585
3586 if (gdth_from_wait) {
3587 wait_hanum = hanum;
3588 wait_index = (int)IStatus;
3589 }
3590
3591 if (IStatus == ASYNCINDEX) {
3592 TRACE2(("gdth_interrupt() async. event\n"));
3593 gdth_async_event(hanum);
3594 if (!gdth_polling)
3595 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3596 gdth_next(hanum);
3597 return IRQ_HANDLED;
3598 }
3599
3600 if (IStatus == SPEZINDEX) {
3601 TRACE2(("Service unknown or not initialized !\n"));
3602 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3603 ha->dvr.eu.driver.ionode = hanum;
3604 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3605 if (!gdth_polling)
3606 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3607 return IRQ_HANDLED;
3608 }
3609 scp = ha->cmd_tab[IStatus-2].cmnd;
3610 Service = ha->cmd_tab[IStatus-2].service;
3611 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3612 if (scp == UNUSED_CMND) {
3613 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3614 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3615 ha->dvr.eu.driver.ionode = hanum;
3616 ha->dvr.eu.driver.index = IStatus;
3617 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3618 if (!gdth_polling)
3619 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3620 return IRQ_HANDLED;
3621 }
3622 if (scp == INTERNAL_CMND) {
3623 TRACE(("gdth_interrupt() answer to internal command\n"));
3624 if (!gdth_polling)
3625 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3626 return IRQ_HANDLED;
3627 }
3628
3629 TRACE(("gdth_interrupt() sync. status\n"));
3630 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3631 if (!gdth_polling)
3632 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3633 if (rval == 2) {
3634 gdth_putq(hanum,scp,scp->SCp.this_residual);
3635 } else if (rval == 1) {
3636 scp->scsi_done(scp);
3637 }
3638
3639#ifdef INT_COAL
3640 if (coalesced) {
3641 /* go to the next status in the status buffer */
3642 ++pcs;
3643#ifdef GDTH_STATISTICS
3644 ++act_int_coal;
3645 if (act_int_coal > max_int_coal) {
3646 max_int_coal = act_int_coal;
3647 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3648 }
3649#endif
3650 /* see if there is another status */
3651 if (pcs->status == 0)
3652 /* Stop the coalesce loop */
3653 next = FALSE;
3654 }
3655 } while (next);
3656
3657 /* coalescing only for new GDT_PCIMPR controllers available */
3658 if (ha->type == GDT_PCIMPR && coalesced) {
3659 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3660 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3661 }
3662#endif
3663
3664 gdth_next(hanum);
3665 return IRQ_HANDLED;
3666}
3667
3668static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3669{
3670 register gdth_ha_str *ha;
3671 gdth_msg_str *msg;
3672 gdth_cmd_str *cmdp;
3673 unchar b, t;
3674
3675 ha = HADATA(gdth_ctr_tab[hanum]);
3676 cmdp = ha->pccb;
3677 TRACE(("gdth_sync_event() serv %d status %d\n",
3678 service,ha->status));
3679
3680 if (service == SCREENSERVICE) {
3681 msg = ha->pmsg;
3682 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3683 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3684 if (msg->msg_len > MSGLEN+1)
3685 msg->msg_len = MSGLEN+1;
3686 if (msg->msg_len)
3687 if (!(msg->msg_answer && msg->msg_ext)) {
3688 msg->msg_text[msg->msg_len] = '\0';
3689 printk("%s",msg->msg_text);
3690 }
3691
3692 if (msg->msg_ext && !msg->msg_answer) {
3693 while (gdth_test_busy(hanum))
3694 gdth_delay(0);
3695 cmdp->Service = SCREENSERVICE;
3696 cmdp->RequestBuffer = SCREEN_CMND;
3697 gdth_get_cmd_index(hanum);
3698 gdth_set_sema0(hanum);
3699 cmdp->OpCode = GDT_READ;
3700 cmdp->BoardNode = LOCALBOARD;
3701 cmdp->u.screen.reserved = 0;
3702 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3703 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3704 ha->cmd_offs_dpmem = 0;
3705 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3706 + sizeof(ulong64);
3707 ha->cmd_cnt = 0;
3708 gdth_copy_command(hanum);
3709 gdth_release_event(hanum);
3710 return 0;
3711 }
3712
3713 if (msg->msg_answer && msg->msg_alen) {
3714 /* default answers (getchar() not possible) */
3715 if (msg->msg_alen == 1) {
3716 msg->msg_alen = 0;
3717 msg->msg_len = 1;
3718 msg->msg_text[0] = 0;
3719 } else {
3720 msg->msg_alen -= 2;
3721 msg->msg_len = 2;
3722 msg->msg_text[0] = 1;
3723 msg->msg_text[1] = 0;
3724 }
3725 msg->msg_ext = 0;
3726 msg->msg_answer = 0;
3727 while (gdth_test_busy(hanum))
3728 gdth_delay(0);
3729 cmdp->Service = SCREENSERVICE;
3730 cmdp->RequestBuffer = SCREEN_CMND;
3731 gdth_get_cmd_index(hanum);
3732 gdth_set_sema0(hanum);
3733 cmdp->OpCode = GDT_WRITE;
3734 cmdp->BoardNode = LOCALBOARD;
3735 cmdp->u.screen.reserved = 0;
3736 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3737 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3738 ha->cmd_offs_dpmem = 0;
3739 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3740 + sizeof(ulong64);
3741 ha->cmd_cnt = 0;
3742 gdth_copy_command(hanum);
3743 gdth_release_event(hanum);
3744 return 0;
3745 }
3746 printk("\n");
3747
3748 } else {
3749 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3750 t = scp->device->id;
3751 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3752 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3753 }
3754 /* cache or raw service */
3755 if (ha->status == S_BSY) {
3756 TRACE2(("Controller busy -> retry !\n"));
3757 if (scp->SCp.sent_command == GDT_MOUNT)
3758 scp->SCp.sent_command = GDT_CLUST_INFO;
3759 /* retry */
3760 return 2;
3761 }
3762 if (scp->SCp.Status == GDTH_MAP_SG)
3763 pci_unmap_sg(ha->pdev,scp->request_buffer,
3764 scp->use_sg,scp->SCp.Message);
3765 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3766 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3767 scp->request_bufflen,scp->SCp.Message);
3768 if (scp->SCp.buffer) {
3769 dma_addr_t addr;
cbd5f69b 3770 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
1da177e4 3771 if (scp->host_scribble)
cbd5f69b
LA		 3772 addr += (dma_addr_t)
3773 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
1da177e4
LT		 3774 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3775 }
3776
3777 if (ha->status == S_OK) {
3778 scp->SCp.Status = S_OK;
3779 scp->SCp.Message = ha->info;
3780 if (scp->SCp.sent_command != -1) {
3781 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3782 scp->SCp.sent_command));
3783 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3784 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3785 ha->hdr[t].cluster_type = (unchar)ha->info;
3786 if (!(ha->hdr[t].cluster_type &
3787 CLUSTER_MOUNTED)) {
3788 /* NOT MOUNTED -> MOUNT */
3789 scp->SCp.sent_command = GDT_MOUNT;
3790 if (ha->hdr[t].cluster_type &
3791 CLUSTER_RESERVED) {
3792 /* cluster drive RESERVED (on the other node) */
3793 scp->SCp.phase = -2; /* reservation conflict */
3794 }
3795 } else {
3796 scp->SCp.sent_command = -1;
3797 }
3798 } else {
3799 if (scp->SCp.sent_command == GDT_MOUNT) {
3800 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3801 ha->hdr[t].media_changed = TRUE;
3802 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3803 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3804 ha->hdr[t].media_changed = TRUE;
3805 }
3806 scp->SCp.sent_command = -1;
3807 }
3808 /* retry */
3809 scp->SCp.this_residual = HIGH_PRI;
3810 return 2;
3811 } else {
3812 /* RESERVE/RELEASE ? */
3813 if (scp->cmnd[0] == RESERVE) {
3814 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3815 } else if (scp->cmnd[0] == RELEASE) {
3816 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3817 }
3818 scp->result = DID_OK << 16;
3819 scp->sense_buffer[0] = 0;
3820 }
3821 } else {
3822 scp->SCp.Status = ha->status;
3823 scp->SCp.Message = ha->info;
3824
3825 if (scp->SCp.sent_command != -1) {
3826 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3827 scp->SCp.sent_command, ha->status));
3828 if (scp->SCp.sent_command == GDT_SCAN_START ||
3829 scp->SCp.sent_command == GDT_SCAN_END) {
3830 scp->SCp.sent_command = -1;
3831 /* retry */
3832 scp->SCp.this_residual = HIGH_PRI;
3833 return 2;
3834 }
3835 memset((char*)scp->sense_buffer,0,16);
3836 scp->sense_buffer[0] = 0x70;
3837 scp->sense_buffer[2] = NOT_READY;
3838 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3839 } else if (service == CACHESERVICE) {
3840 if (ha->status == S_CACHE_UNKNOWN &&
3841 (ha->hdr[t].cluster_type &
3842 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3843 /* bus reset -> force GDT_CLUST_INFO */
3844 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3845 }
3846 memset((char*)scp->sense_buffer,0,16);
3847 if (ha->status == (ushort)S_CACHE_RESERV) {
3848 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3849 } else {
3850 scp->sense_buffer[0] = 0x70;
3851 scp->sense_buffer[2] = NOT_READY;
3852 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3853 }
3854 if (scp->done != gdth_scsi_done) {
3855 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3856 ha->dvr.eu.sync.ionode = hanum;
3857 ha->dvr.eu.sync.service = service;
3858 ha->dvr.eu.sync.status = ha->status;
3859 ha->dvr.eu.sync.info = ha->info;
3860 ha->dvr.eu.sync.hostdrive = t;
3861 if (ha->status >= 0x8000)
3862 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3863 else
3864 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3865 }
3866 } else {
3867 /* sense buffer filled from controller firmware (DMA) */
3868 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3869 scp->result = DID_BAD_TARGET << 16;
3870 } else {
3871 scp->result = (DID_OK << 16) | ha->info;
3872 }
3873 }
3874 }
3875 if (!scp->SCp.have_data_in)
3876 scp->SCp.have_data_in++;
3877 else
3878 return 1;
3879 }
3880
3881 return 0;
3882}
3883
3884static char *async_cache_tab[] = {
3885/* 0*/ "\011\000\002\002\002\004\002\006\004"
3886 "GDT HA %u, service %u, async. status %u/%lu unknown",
3887/* 1*/ "\011\000\002\002\002\004\002\006\004"
3888 "GDT HA %u, service %u, async. status %u/%lu unknown",
3889/* 2*/ "\005\000\002\006\004"
3890 "GDT HA %u, Host Drive %lu not ready",
3891/* 3*/ "\005\000\002\006\004"
3892 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3893/* 4*/ "\005\000\002\006\004"
3894 "GDT HA %u, mirror update on Host Drive %lu failed",
3895/* 5*/ "\005\000\002\006\004"
3896 "GDT HA %u, Mirror Drive %lu failed",
3897/* 6*/ "\005\000\002\006\004"
3898 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3899/* 7*/ "\005\000\002\006\004"
3900 "GDT HA %u, Host Drive %lu write protected",
3901/* 8*/ "\005\000\002\006\004"
3902 "GDT HA %u, media changed in Host Drive %lu",
3903/* 9*/ "\005\000\002\006\004"
3904 "GDT HA %u, Host Drive %lu is offline",
3905/*10*/ "\005\000\002\006\004"
3906 "GDT HA %u, media change of Mirror Drive %lu",
3907/*11*/ "\005\000\002\006\004"
3908 "GDT HA %u, Mirror Drive %lu is write protected",
3909/*12*/ "\005\000\002\006\004"
3910 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3911/*13*/ "\007\000\002\006\002\010\002"
3912 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3913/*14*/ "\005\000\002\006\002"
3914 "GDT HA %u, Array Drive %u: FAIL state entered",
3915/*15*/ "\005\000\002\006\002"
3916 "GDT HA %u, Array Drive %u: error",
3917/*16*/ "\007\000\002\006\002\010\002"
3918 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3919/*17*/ "\005\000\002\006\002"
3920 "GDT HA %u, Array Drive %u: parity build failed",
3921/*18*/ "\005\000\002\006\002"
3922 "GDT HA %u, Array Drive %u: drive rebuild failed",
3923/*19*/ "\005\000\002\010\002"
3924 "GDT HA %u, Test of Hot Fix %u failed",
3925/*20*/ "\005\000\002\006\002"
3926 "GDT HA %u, Array Drive %u: drive build finished successfully",
3927/*21*/ "\005\000\002\006\002"
3928 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3929/*22*/ "\007\000\002\006\002\010\002"
3930 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3931/*23*/ "\005\000\002\006\002"
3932 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3933/*24*/ "\005\000\002\010\002"
3934 "GDT HA %u, mirror update on Cache Drive %u completed",
3935/*25*/ "\005\000\002\010\002"
3936 "GDT HA %u, mirror update on Cache Drive %lu failed",
3937/*26*/ "\005\000\002\006\002"
3938 "GDT HA %u, Array Drive %u: drive rebuild started",
3939/*27*/ "\005\000\002\012\001"
3940 "GDT HA %u, Fault bus %u: SHELF OK detected",
3941/*28*/ "\005\000\002\012\001"
3942 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3943/*29*/ "\007\000\002\012\001\013\001"
3944 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3945/*30*/ "\007\000\002\012\001\013\001"
3946 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3947/*31*/ "\007\000\002\012\001\013\001"
3948 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3949/*32*/ "\007\000\002\012\001\013\001"
3950 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3951/*33*/ "\007\000\002\012\001\013\001"
3952 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3953/*34*/ "\011\000\002\012\001\013\001\006\004"
3954 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3955/*35*/ "\007\000\002\012\001\013\001"
3956 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3957/*36*/ "\007\000\002\012\001\013\001"
3958 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3959/*37*/ "\007\000\002\012\001\006\004"
3960 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3961/*38*/ "\007\000\002\012\001\013\001"
3962 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3963/*39*/ "\007\000\002\012\001\013\001"
3964 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3965/*40*/ "\007\000\002\012\001\013\001"
3966 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3967/*41*/ "\007\000\002\012\001\013\001"
3968 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3969/*42*/ "\005\000\002\006\002"
3970 "GDT HA %u, Array Drive %u: drive build started",
3971/*43*/ "\003\000\002"
3972 "GDT HA %u, DRAM parity error detected",
3973/*44*/ "\005\000\002\006\002"
3974 "GDT HA %u, Mirror Drive %u: update started",
3975/*45*/ "\007\000\002\006\002\010\002"
3976 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3977/*46*/ "\005\000\002\006\002"
3978 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3979/*47*/ "\005\000\002\006\002"
3980 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3981/*48*/ "\005\000\002\006\002"
3982 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3983/*49*/ "\005\000\002\006\002"
3984 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3985/*50*/ "\007\000\002\012\001\013\001"
3986 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3987/*51*/ "\005\000\002\006\002"
3988 "GDT HA %u, Array Drive %u: expand started",
3989/*52*/ "\005\000\002\006\002"
3990 "GDT HA %u, Array Drive %u: expand finished successfully",
3991/*53*/ "\005\000\002\006\002"
3992 "GDT HA %u, Array Drive %u: expand failed",
3993/*54*/ "\003\000\002"
3994 "GDT HA %u, CPU temperature critical",
3995/*55*/ "\003\000\002"
3996 "GDT HA %u, CPU temperature OK",
3997/*56*/ "\005\000\002\006\004"
3998 "GDT HA %u, Host drive %lu created",
3999/*57*/ "\005\000\002\006\002"
4000 "GDT HA %u, Array Drive %u: expand restarted",
4001/*58*/ "\005\000\002\006\002"
4002 "GDT HA %u, Array Drive %u: expand stopped",
4003/*59*/ "\005\000\002\010\002"
4004 "GDT HA %u, Mirror Drive %u: drive build quited",
4005/*60*/ "\005\000\002\006\002"
4006 "GDT HA %u, Array Drive %u: parity build quited",
4007/*61*/ "\005\000\002\006\002"
4008 "GDT HA %u, Array Drive %u: drive rebuild quited",
4009/*62*/ "\005\000\002\006\002"
4010 "GDT HA %u, Array Drive %u: parity verify started",
4011/*63*/ "\005\000\002\006\002"
4012 "GDT HA %u, Array Drive %u: parity verify done",
4013/*64*/ "\005\000\002\006\002"
4014 "GDT HA %u, Array Drive %u: parity verify failed",
4015/*65*/ "\005\000\002\006\002"
4016 "GDT HA %u, Array Drive %u: parity error detected",
4017/*66*/ "\005\000\002\006\002"
4018 "GDT HA %u, Array Drive %u: parity verify quited",
4019/*67*/ "\005\000\002\006\002"
4020 "GDT HA %u, Host Drive %u reserved",
4021/*68*/ "\005\000\002\006\002"
4022 "GDT HA %u, Host Drive %u mounted and released",
4023/*69*/ "\005\000\002\006\002"
4024 "GDT HA %u, Host Drive %u released",
4025/*70*/ "\003\000\002"
4026 "GDT HA %u, DRAM error detected and corrected with ECC",
4027/*71*/ "\003\000\002"
4028 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
4029/*72*/ "\011\000\002\012\001\013\001\014\001"
4030 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
4031/*73*/ "\005\000\002\006\002"
4032 "GDT HA %u, Host drive %u resetted locally",
4033/*74*/ "\005\000\002\006\002"
4034 "GDT HA %u, Host drive %u resetted remotely",
4035/*75*/ "\003\000\002"
4036 "GDT HA %u, async. status 75 unknown",
4037};
4038
4039
4040static int gdth_async_event(int hanum)
4041{
4042 gdth_ha_str *ha;
4043 gdth_cmd_str *cmdp;
4044 int cmd_index;
4045
4046 ha = HADATA(gdth_ctr_tab[hanum]);
4047 cmdp= ha->pccb;
4048 TRACE2(("gdth_async_event() ha %d serv %d\n",
4049 hanum,ha->service));
4050
4051 if (ha->service == SCREENSERVICE) {
4052 if (ha->status == MSG_REQUEST) {
4053 while (gdth_test_busy(hanum))
4054 gdth_delay(0);
4055 cmdp->Service = SCREENSERVICE;
4056 cmdp->RequestBuffer = SCREEN_CMND;
4057 cmd_index = gdth_get_cmd_index(hanum);
4058 gdth_set_sema0(hanum);
4059 cmdp->OpCode = GDT_READ;
4060 cmdp->BoardNode = LOCALBOARD;
4061 cmdp->u.screen.reserved = 0;
4062 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
4063 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
4064 ha->cmd_offs_dpmem = 0;
4065 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
4066 + sizeof(ulong64);
4067 ha->cmd_cnt = 0;
4068 gdth_copy_command(hanum);
4069 if (ha->type == GDT_EISA)
4070 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
4071 else if (ha->type == GDT_ISA)
4072 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
4073 else
4074 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
4075 (ushort)((ha->brd_phys>>3)&0x1f));
4076 gdth_release_event(hanum);
4077 }
4078
4079 } else {
4080 if (ha->type == GDT_PCIMPR &&
4081 (ha->fw_vers & 0xff) >= 0x1a) {
4082 ha->dvr.size = 0;
4083 ha->dvr.eu.async.ionode = hanum;
4084 ha->dvr.eu.async.status = ha->status;
4085 /* severity and event_string already set! */
4086 } else {
4087 ha->dvr.size = sizeof(ha->dvr.eu.async);
4088 ha->dvr.eu.async.ionode = hanum;
4089 ha->dvr.eu.async.service = ha->service;
4090 ha->dvr.eu.async.status = ha->status;
4091 ha->dvr.eu.async.info = ha->info;
4092 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
4093 }
4094 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
4095 gdth_log_event( &ha->dvr, NULL );
4096
4097 /* new host drive from expand? */
4098 if (ha->service == CACHESERVICE && ha->status == 56) {
4099 TRACE2(("gdth_async_event(): new host drive %d created\n",
4100 (ushort)ha->info));
4101 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
4102 }
4103 }
4104 return 1;
4105}
4106
4107static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
4108{
4109 gdth_stackframe stack;
4110 char *f = NULL;
4111 int i,j;
4112
4113 TRACE2(("gdth_log_event()\n"));
4114 if (dvr->size == 0) {
4115 if (buffer == NULL) {
4116 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
4117 } else {
4118 sprintf(buffer,"Adapter %d: %s\n",
4119 dvr->eu.async.ionode,dvr->event_string);
4120 }
4121 } else if (dvr->eu.async.service == CACHESERVICE &&
4122 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
4123 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
4124 dvr->eu.async.status));
4125
4126 f = async_cache_tab[dvr->eu.async.status];
4127
4128 /* i: parameter to push, j: stack element to fill */
4129 for (j=0,i=1; i < f[0]; i+=2) {
4130 switch (f[i+1]) {
4131 case 4:
4132 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4133 break;
4134 case 2:
4135 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4136 break;
4137 case 1:
4138 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4139 break;
4140 default:
4141 break;
4142 }
4143 }
4144
4145 if (buffer == NULL) {
4146 printk(&f[(int)f[0]],stack);
4147 printk("\n");
4148 } else {
4149 sprintf(buffer,&f[(int)f[0]],stack);
4150 }
4151
4152 } else {
4153 if (buffer == NULL) {
4154 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4155 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4156 } else {
4157 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4158 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4159 }
4160 }
4161}
4162
4163#ifdef GDTH_STATISTICS
8e879041 4164static void gdth_timeout(ulong data)
1da177e4
LT		 4165{
4166 ulong32 i;
4167 Scsi_Cmnd *nscp;
4168 gdth_ha_str *ha;
4169 ulong flags;
4170 int hanum = 0;
4171
4172 ha = HADATA(gdth_ctr_tab[hanum]);
4173 spin_lock_irqsave(&ha->smp_lock, flags);
4174
4175 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4176 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4177 ++act_stats;
4178
4179 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4180 ++act_rq;
4181
4182 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4183 act_ints, act_ios, act_stats, act_rq));
4184 act_ints = act_ios = 0;
4185
4186 gdth_timer.expires = jiffies + 30 * HZ;
4187 add_timer(&gdth_timer);
4188 spin_unlock_irqrestore(&ha->smp_lock, flags);
4189}
4190#endif
4191
8e879041 4192static void __init internal_setup(char *str,int *ints)
1da177e4
LT		 4193{
4194 int i, argc;
4195 char *cur_str, *argv;
4196
4197 TRACE2(("internal_setup() str %s ints[0] %d\n",
4198 str ? str:"NULL", ints ? ints[0]:0));
4199
4200 /* read irq[] from ints[] */
4201 if (ints) {
4202 argc = ints[0];
4203 if (argc > 0) {
4204 if (argc > MAXHA)
4205 argc = MAXHA;
4206 for (i = 0; i < argc; ++i)
4207 irq[i] = ints[i+1];
4208 }
4209 }
4210
4211 /* analyse string */
4212 argv = str;
4213 while (argv && (cur_str = strchr(argv, ':'))) {
4214 int val = 0, c = *++cur_str;
4215
4216 if (c == 'n' || c == 'N')
4217 val = 0;
4218 else if (c == 'y' || c == 'Y')
4219 val = 1;
4220 else
4221 val = (int)simple_strtoul(cur_str, NULL, 0);
4222
4223 if (!strncmp(argv, "disable:", 8))
4224 disable = val;
4225 else if (!strncmp(argv, "reserve_mode:", 13))
4226 reserve_mode = val;
4227 else if (!strncmp(argv, "reverse_scan:", 13))
4228 reverse_scan = val;
4229 else if (!strncmp(argv, "hdr_channel:", 12))
4230 hdr_channel = val;
4231 else if (!strncmp(argv, "max_ids:", 8))
4232 max_ids = val;
4233 else if (!strncmp(argv, "rescan:", 7))
4234 rescan = val;
4235 else if (!strncmp(argv, "virt_ctr:", 9))
4236 virt_ctr = val;
4237 else if (!strncmp(argv, "shared_access:", 14))
4238 shared_access = val;
4239 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4240 probe_eisa_isa = val;
4241 else if (!strncmp(argv, "reserve_list:", 13)) {
4242 reserve_list[0] = val;
4243 for (i = 1; i < MAX_RES_ARGS; i++) {
4244 cur_str = strchr(cur_str, ',');
4245 if (!cur_str)
4246 break;
4247 if (!isdigit((int)*++cur_str)) {
4248 --cur_str;
4249 break;
4250 }
4251 reserve_list[i] =
4252 (int)simple_strtoul(cur_str, NULL, 0);
4253 }
4254 if (!cur_str)
4255 break;
4256 argv = ++cur_str;
4257 continue;
4258 }
4259
4260 if ((argv = strchr(argv, ',')))
4261 ++argv;
4262 }
4263}
4264
4265int __init option_setup(char *str)
4266{
4267 int ints[MAXHA];
4268 char *cur = str;
4269 int i = 1;
4270
4271 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4272
4273 while (cur && isdigit(*cur) && i <= MAXHA) {
4274 ints[i++] = simple_strtoul(cur, NULL, 0);
4275 if ((cur = strchr(cur, ',')) != NULL) cur++;
4276 }
4277
4278 ints[0] = i - 1;
4279 internal_setup(cur, ints);
4280 return 1;
4281}
4282
cbd5f69b 4283#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
d0be4a7d 4284static int __init gdth_detect(struct scsi_host_template *shtp)
cbd5f69b
LA		 4285#else
4286static int __init gdth_detect(Scsi_Host_Template *shtp)
4287#endif
1da177e4
LT		 4288{
4289 struct Scsi_Host *shp;
4290 gdth_pci_str pcistr[MAXHA];
4291 gdth_ha_str *ha;
4292 ulong32 isa_bios;
4293 ushort eisa_slot;
4294 int i,hanum,cnt,ctr,err;
4295 unchar b;
4296
4297
4298#ifdef DEBUG_GDTH
4299 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4300 DebugState);
4301 printk(" Destination of debugging information: ");
4302#ifdef __SERIAL__
4303#ifdef __COM2__
4304 printk("Serial port COM2\n");
4305#else
4306 printk("Serial port COM1\n");
4307#endif
4308#else
4309 printk("Console\n");
4310#endif
4311 gdth_delay(3000);
4312#endif
4313
4314 TRACE(("gdth_detect()\n"));
4315
4316 if (disable) {
4317 printk("GDT-HA: Controller driver disabled from command line !\n");
4318 return 0;
4319 }
4320
cbd5f69b 4321 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
1da177e4
LT		 4322 /* initializations */
4323 gdth_polling = TRUE; b = 0;
4324 gdth_clear_events();
4325
4326 /* As default we do not probe for EISA or ISA controllers */
4327 if (probe_eisa_isa) {
4328 /* scanning for controllers, at first: ISA controller */
4329 for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
4330 dma_addr_t scratch_dma_handle;
4331 scratch_dma_handle = 0;
4332
4333 if (gdth_ctr_count >= MAXHA)
4334 break;
4335 if (gdth_search_isa(isa_bios)) { /* controller found */
4336 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4337 if (shp == NULL)
4338 continue;
4339
4340 ha = HADATA(shp);
4341 if (!gdth_init_isa(isa_bios,ha)) {
4342 scsi_unregister(shp);
4343 continue;
4344 }
4345#ifdef __ia64__
4346 break;
4347#else
4348 /* controller found and initialized */
4349 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4350 isa_bios,ha->irq,ha->drq);
4351
1d6f359a 4352 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
1da177e4
LT		 4353 printk("GDT-ISA: Unable to allocate IRQ\n");
4354 scsi_unregister(shp);
4355 continue;
4356 }
4357 if (request_dma(ha->drq,"gdth")) {
4358 printk("GDT-ISA: Unable to allocate DMA channel\n");
4359 free_irq(ha->irq,ha);
4360 scsi_unregister(shp);
4361 continue;
4362 }
4363 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4364 enable_dma(ha->drq);
4365 shp->unchecked_isa_dma = 1;
4366 shp->irq = ha->irq;
4367 shp->dma_channel = ha->drq;
4368 hanum = gdth_ctr_count;
4369 gdth_ctr_tab[gdth_ctr_count++] = shp;
4370 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4371
4372 NUMDATA(shp)->hanum = (ushort)hanum;
4373 NUMDATA(shp)->busnum= 0;
4374
4375 ha->pccb = CMDDATA(shp);
4376 ha->ccb_phys = 0L;
4377 ha->pdev = NULL;
4378 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4379 &scratch_dma_handle);
4380 ha->scratch_phys = scratch_dma_handle;
4381 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4382 &scratch_dma_handle);
4383 ha->msg_phys = scratch_dma_handle;
4384#ifdef INT_COAL
4385 ha->coal_stat = (gdth_coal_status *)
4386 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4387 MAXOFFSETS, &scratch_dma_handle);
4388 ha->coal_stat_phys = scratch_dma_handle;
4389#endif
4390
4391 ha->scratch_busy = FALSE;
4392 ha->req_first = NULL;
4393 ha->tid_cnt = MAX_HDRIVES;
4394 if (max_ids > 0 && max_ids < ha->tid_cnt)
4395 ha->tid_cnt = max_ids;
4396 for (i=0; i<GDTH_MAXCMDS; ++i)
4397 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4398 ha->scan_mode = rescan ? 0x10 : 0;
4399
4400 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4401 !gdth_search_drives(hanum)) {
4402 printk("GDT-ISA: Error during device scan\n");
4403 --gdth_ctr_count;
4404 --gdth_ctr_vcount;
4405
4406#ifdef INT_COAL
4407 if (ha->coal_stat)
4408 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4409 MAXOFFSETS, ha->coal_stat,
4410 ha->coal_stat_phys);
4411#endif
4412 if (ha->pscratch)
4413 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4414 ha->pscratch, ha->scratch_phys);
4415 if (ha->pmsg)
4416 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4417 ha->pmsg, ha->msg_phys);
4418
4419 free_irq(ha->irq,ha);
4420 scsi_unregister(shp);
4421 continue;
4422 }
4423 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4424 hdr_channel = ha->bus_cnt;
4425 ha->virt_bus = hdr_channel;
4426
4427#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4428 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4429 shp->highmem_io = 0;
4430#endif
4431 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4432 shp->max_cmd_len = 16;
4433
4434 shp->max_id = ha->tid_cnt;
4435 shp->max_lun = MAXLUN;
4436 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4437 if (virt_ctr) {
4438 virt_ctr = 1;
4439 /* register addit. SCSI channels as virtual controllers */
4440 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4441 shp = scsi_register(shtp,sizeof(gdth_num_str));
4442 shp->unchecked_isa_dma = 1;
4443 shp->irq = ha->irq;
4444 shp->dma_channel = ha->drq;
4445 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4446 NUMDATA(shp)->hanum = (ushort)hanum;
4447 NUMDATA(shp)->busnum = b;
4448 }
4449 }
4450
4451 spin_lock_init(&ha->smp_lock);
4452 gdth_enable_int(hanum);
4453#endif /* !__ia64__ */
4454 }
4455 }
4456
4457 /* scanning for EISA controllers */
4458 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4459 dma_addr_t scratch_dma_handle;
4460 scratch_dma_handle = 0;
4461
4462 if (gdth_ctr_count >= MAXHA)
4463 break;
4464 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4465 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4466 if (shp == NULL)
4467 continue;
4468
4469 ha = HADATA(shp);
4470 if (!gdth_init_eisa(eisa_slot,ha)) {
4471 scsi_unregister(shp);
4472 continue;
4473 }
4474 /* controller found and initialized */
4475 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4476 eisa_slot>>12,ha->irq);
4477
1d6f359a 4478 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
1da177e4
LT		 4479 printk("GDT-EISA: Unable to allocate IRQ\n");
4480 scsi_unregister(shp);
4481 continue;
4482 }
4483 shp->unchecked_isa_dma = 0;
4484 shp->irq = ha->irq;
4485 shp->dma_channel = 0xff;
4486 hanum = gdth_ctr_count;
4487 gdth_ctr_tab[gdth_ctr_count++] = shp;
4488 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4489
4490 NUMDATA(shp)->hanum = (ushort)hanum;
4491 NUMDATA(shp)->busnum= 0;
4492 TRACE2(("EISA detect Bus 0: hanum %d\n",
4493 NUMDATA(shp)->hanum));
4494
4495 ha->pccb = CMDDATA(shp);
4496 ha->ccb_phys = 0L;
4497
4498 ha->pdev = NULL;
4499 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4500 &scratch_dma_handle);
4501 ha->scratch_phys = scratch_dma_handle;
4502 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4503 &scratch_dma_handle);
4504 ha->msg_phys = scratch_dma_handle;
4505#ifdef INT_COAL
4506 ha->coal_stat = (gdth_coal_status *)
4507 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4508 MAXOFFSETS, &scratch_dma_handle);
4509 ha->coal_stat_phys = scratch_dma_handle;
4510#endif
4511 ha->ccb_phys =
4512 pci_map_single(ha->pdev,ha->pccb,
4513 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4514 ha->scratch_busy = FALSE;
4515 ha->req_first = NULL;
4516 ha->tid_cnt = MAX_HDRIVES;
4517 if (max_ids > 0 && max_ids < ha->tid_cnt)
4518 ha->tid_cnt = max_ids;
4519 for (i=0; i<GDTH_MAXCMDS; ++i)
4520 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4521 ha->scan_mode = rescan ? 0x10 : 0;
4522
4523 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4524 !gdth_search_drives(hanum)) {
4525 printk("GDT-EISA: Error during device scan\n");
4526 --gdth_ctr_count;
4527 --gdth_ctr_vcount;
4528#ifdef INT_COAL
4529 if (ha->coal_stat)
4530 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4531 MAXOFFSETS, ha->coal_stat,
4532 ha->coal_stat_phys);
4533#endif
4534 if (ha->pscratch)
4535 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4536 ha->pscratch, ha->scratch_phys);
4537 if (ha->pmsg)
4538 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4539 ha->pmsg, ha->msg_phys);
4540 if (ha->ccb_phys)
4541 pci_unmap_single(ha->pdev,ha->ccb_phys,
4542 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4543 free_irq(ha->irq,ha);
4544 scsi_unregister(shp);
4545 continue;
4546 }
4547 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4548 hdr_channel = ha->bus_cnt;
4549 ha->virt_bus = hdr_channel;
4550
4551#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4552 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4553 shp->highmem_io = 0;
4554#endif
4555 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4556 shp->max_cmd_len = 16;
4557
4558 shp->max_id = ha->tid_cnt;
4559 shp->max_lun = MAXLUN;
4560 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4561 if (virt_ctr) {
4562 virt_ctr = 1;
4563 /* register addit. SCSI channels as virtual controllers */
4564 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4565 shp = scsi_register(shtp,sizeof(gdth_num_str));
4566 shp->unchecked_isa_dma = 0;
4567 shp->irq = ha->irq;
4568 shp->dma_channel = 0xff;
4569 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4570 NUMDATA(shp)->hanum = (ushort)hanum;
4571 NUMDATA(shp)->busnum = b;
4572 }
4573 }
4574
4575 spin_lock_init(&ha->smp_lock);
4576 gdth_enable_int(hanum);
4577 }
4578 }
4579 }
4580
4581 /* scanning for PCI controllers */
4582 cnt = gdth_search_pci(pcistr);
4583 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4584 gdth_sort_pci(pcistr,cnt);
4585 for (ctr = 0; ctr < cnt; ++ctr) {
4586 dma_addr_t scratch_dma_handle;
4587 scratch_dma_handle = 0;
4588
4589 if (gdth_ctr_count >= MAXHA)
4590 break;
4591 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4592 if (shp == NULL)
4593 continue;
4594
4595 ha = HADATA(shp);
4596 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4597 scsi_unregister(shp);
4598 continue;
4599 }
4600 /* controller found and initialized */
4601 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4602 pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
4603
4604 if (request_irq(ha->irq, gdth_interrupt,
1d6f359a 4605 IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
1da177e4
LT		 4606 {
4607 printk("GDT-PCI: Unable to allocate IRQ\n");
4608 scsi_unregister(shp);
4609 continue;
4610 }
4611 shp->unchecked_isa_dma = 0;
4612 shp->irq = ha->irq;
4613 shp->dma_channel = 0xff;
4614 hanum = gdth_ctr_count;
4615 gdth_ctr_tab[gdth_ctr_count++] = shp;
4616 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4617
4618 NUMDATA(shp)->hanum = (ushort)hanum;
4619 NUMDATA(shp)->busnum= 0;
4620
4621 ha->pccb = CMDDATA(shp);
4622 ha->ccb_phys = 0L;
4623
4624 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4625 &scratch_dma_handle);
4626 ha->scratch_phys = scratch_dma_handle;
4627 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4628 &scratch_dma_handle);
4629 ha->msg_phys = scratch_dma_handle;
4630#ifdef INT_COAL
4631 ha->coal_stat = (gdth_coal_status *)
4632 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4633 MAXOFFSETS, &scratch_dma_handle);
4634 ha->coal_stat_phys = scratch_dma_handle;
4635#endif
4636 ha->scratch_busy = FALSE;
4637 ha->req_first = NULL;
4638 ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
4639 if (max_ids > 0 && max_ids < ha->tid_cnt)
4640 ha->tid_cnt = max_ids;
4641 for (i=0; i<GDTH_MAXCMDS; ++i)
4642 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4643 ha->scan_mode = rescan ? 0x10 : 0;
4644
4645 err = FALSE;
4646 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4647 !gdth_search_drives(hanum)) {
4648 err = TRUE;
4649 } else {
4650 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4651 hdr_channel = ha->bus_cnt;
4652 ha->virt_bus = hdr_channel;
4653
4654
12413197 4655#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
1da177e4
LT		 4656 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4657#endif
4658 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4659 /* 64-bit DMA only supported from FW >= x.43 */
4660 (!ha->dma64_support)) {
910638ae 4661 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 4662 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4663 err = TRUE;
4664 }
4665 } else {
4666 shp->max_cmd_len = 16;
910638ae 4667 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
1da177e4 4668 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
910638ae 4669 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 4670 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4671 err = TRUE;
4672 }
4673 }
4674 }
4675
4676 if (err) {
4677 printk("GDT-PCI %d: Error during device scan\n", hanum);
4678 --gdth_ctr_count;
4679 --gdth_ctr_vcount;
4680#ifdef INT_COAL
4681 if (ha->coal_stat)
4682 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4683 MAXOFFSETS, ha->coal_stat,
4684 ha->coal_stat_phys);
4685#endif
4686 if (ha->pscratch)
4687 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4688 ha->pscratch, ha->scratch_phys);
4689 if (ha->pmsg)
4690 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4691 ha->pmsg, ha->msg_phys);
4692 free_irq(ha->irq,ha);
4693 scsi_unregister(shp);
4694 continue;
4695 }
4696
4697 shp->max_id = ha->tid_cnt;
4698 shp->max_lun = MAXLUN;
4699 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4700 if (virt_ctr) {
4701 virt_ctr = 1;
4702 /* register addit. SCSI channels as virtual controllers */
4703 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4704 shp = scsi_register(shtp,sizeof(gdth_num_str));
4705 shp->unchecked_isa_dma = 0;
4706 shp->irq = ha->irq;
4707 shp->dma_channel = 0xff;
4708 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4709 NUMDATA(shp)->hanum = (ushort)hanum;
4710 NUMDATA(shp)->busnum = b;
4711 }
4712 }
4713
4714 spin_lock_init(&ha->smp_lock);
4715 gdth_enable_int(hanum);
4716 }
4717
4718 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4719 if (gdth_ctr_count > 0) {
4720#ifdef GDTH_STATISTICS
4721 TRACE2(("gdth_detect(): Initializing timer !\n"));
4722 init_timer(&gdth_timer);
4723 gdth_timer.expires = jiffies + HZ;
4724 gdth_timer.data = 0L;
4725 gdth_timer.function = gdth_timeout;
4726 add_timer(&gdth_timer);
4727#endif
4728 major = register_chrdev(0,"gdth",&gdth_fops);
e041c683 4729 notifier_disabled = 0;
1da177e4
LT		 4730 register_reboot_notifier(&gdth_notifier);
4731 }
4732 gdth_polling = FALSE;
4733 return gdth_ctr_vcount;
4734}
4735
8e879041 4736static int gdth_release(struct Scsi_Host *shp)
1da177e4
LT		 4737{
4738 int hanum;
4739 gdth_ha_str *ha;
4740
4741 TRACE2(("gdth_release()\n"));
4742 if (NUMDATA(shp)->busnum == 0) {
4743 hanum = NUMDATA(shp)->hanum;
4744 ha = HADATA(gdth_ctr_tab[hanum]);
4745 if (ha->sdev) {
4746 scsi_free_host_dev(ha->sdev);
4747 ha->sdev = NULL;
4748 }
4749 gdth_flush(hanum);
4750
4751 if (shp->irq) {
4752 free_irq(shp->irq,ha);
4753 }
4754#ifndef __ia64__
4755 if (shp->dma_channel != 0xff) {
4756 free_dma(shp->dma_channel);
4757 }
4758#endif
4759#ifdef INT_COAL
4760 if (ha->coal_stat)
4761 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4762 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4763#endif
4764 if (ha->pscratch)
4765 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4766 ha->pscratch, ha->scratch_phys);
4767 if (ha->pmsg)
4768 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4769 ha->pmsg, ha->msg_phys);
4770 if (ha->ccb_phys)
4771 pci_unmap_single(ha->pdev,ha->ccb_phys,
4772 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4773 gdth_ctr_released++;
4774 TRACE2(("gdth_release(): HA %d of %d\n",
4775 gdth_ctr_released, gdth_ctr_count));
4776
4777 if (gdth_ctr_released == gdth_ctr_count) {
4778#ifdef GDTH_STATISTICS
4779 del_timer(&gdth_timer);
4780#endif
4781 unregister_chrdev(major,"gdth");
4782 unregister_reboot_notifier(&gdth_notifier);
4783 }
4784 }
4785
4786 scsi_unregister(shp);
4787 return 0;
4788}
4789
4790
4791static const char *gdth_ctr_name(int hanum)
4792{
4793 gdth_ha_str *ha;
4794
4795 TRACE2(("gdth_ctr_name()\n"));
4796
4797 ha = HADATA(gdth_ctr_tab[hanum]);
4798
4799 if (ha->type == GDT_EISA) {
4800 switch (ha->stype) {
4801 case GDT3_ID:
4802 return("GDT3000/3020");
4803 case GDT3A_ID:
4804 return("GDT3000A/3020A/3050A");
4805 case GDT3B_ID:
4806 return("GDT3000B/3010A");
4807 }
4808 } else if (ha->type == GDT_ISA) {
4809 return("GDT2000/2020");
4810 } else if (ha->type == GDT_PCI) {
4811 switch (ha->stype) {
4812 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4813 return("GDT6000/6020/6050");
4814 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4815 return("GDT6000B/6010");
4816 }
4817 }
4818 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4819
4820 return("");
4821}
4822
8e879041 4823static const char *gdth_info(struct Scsi_Host *shp)
1da177e4
LT		 4824{
4825 int hanum;
4826 gdth_ha_str *ha;
4827
4828 TRACE2(("gdth_info()\n"));
4829 hanum = NUMDATA(shp)->hanum;
4830 ha = HADATA(gdth_ctr_tab[hanum]);
4831
4832 return ((const char *)ha->binfo.type_string);
4833}
4834
8e879041 4835static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
1da177e4
LT		 4836{
4837 int i, hanum;
4838 gdth_ha_str *ha;
4839 ulong flags;
4840 Scsi_Cmnd *cmnd;
4841 unchar b;
4842
4843 TRACE2(("gdth_eh_bus_reset()\n"));
4844
4845 hanum = NUMDATA(scp->device->host)->hanum;
4846 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4847 ha = HADATA(gdth_ctr_tab[hanum]);
4848
4849 /* clear command tab */
4850 spin_lock_irqsave(&ha->smp_lock, flags);
4851 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4852 cmnd = ha->cmd_tab[i].cmnd;
4853 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4854 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4855 }
4856 spin_unlock_irqrestore(&ha->smp_lock, flags);
4857
4858 if (b == ha->virt_bus) {
4859 /* host drives */
4860 for (i = 0; i < MAX_HDRIVES; ++i) {
4861 if (ha->hdr[i].present) {
4862 spin_lock_irqsave(&ha->smp_lock, flags);
4863 gdth_polling = TRUE;
4864 while (gdth_test_busy(hanum))
4865 gdth_delay(0);
4866 if (gdth_internal_cmd(hanum, CACHESERVICE,
4867 GDT_CLUST_RESET, i, 0, 0))
4868 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4869 gdth_polling = FALSE;
4870 spin_unlock_irqrestore(&ha->smp_lock, flags);
4871 }
4872 }
4873 } else {
4874 /* raw devices */
4875 spin_lock_irqsave(&ha->smp_lock, flags);
4876 for (i = 0; i < MAXID; ++i)
4877 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4878 gdth_polling = TRUE;
4879 while (gdth_test_busy(hanum))
4880 gdth_delay(0);
4881 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4882 BUS_L2P(ha,b), 0, 0);
4883 gdth_polling = FALSE;
cbd5f69b 4884 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 4885 }
4886 return SUCCESS;
4887}
4888
1da177e4 4889#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
8e879041 4890static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
1da177e4 4891#else
8e879041 4892static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
1da177e4
LT		 4893#endif
4894{
4895 unchar b, t;
4896 int hanum;
4897 gdth_ha_str *ha;
4898 struct scsi_device *sd;
4899 unsigned capacity;
4900
4901#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4902 sd = sdev;
4903 capacity = cap;
4904#else
4905 sd = disk->device;
4906 capacity = disk->capacity;
4907#endif
4908 hanum = NUMDATA(sd->host)->hanum;
4909 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4910 t = sd->id;
4911 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4912 ha = HADATA(gdth_ctr_tab[hanum]);
4913
4914 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4915 /* raw device or host drive without mapping information */
4916 TRACE2(("Evaluate mapping\n"));
4917 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4918 } else {
4919 ip[0] = ha->hdr[t].heads;
4920 ip[1] = ha->hdr[t].secs;
4921 ip[2] = capacity / ip[0] / ip[1];
4922 }
4923
4924 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4925 ip[0],ip[1],ip[2]));
4926 return 0;
4927}
4928
4929
8e879041 4930static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
1da177e4
LT		 4931{
4932 int hanum;
4933 int priority;
4934
4935 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4936
4937 scp->scsi_done = (void *)done;
4938 scp->SCp.have_data_in = 1;
4939 scp->SCp.phase = -1;
4940 scp->SCp.sent_command = -1;
4941 scp->SCp.Status = GDTH_MAP_NONE;
4942 scp->SCp.buffer = (struct scatterlist *)NULL;
4943
4944 hanum = NUMDATA(scp->device->host)->hanum;
4945#ifdef GDTH_STATISTICS
4946 ++act_ios;
4947#endif
4948
4949 priority = DEFAULT_PRI;
4950 if (scp->done == gdth_scsi_done)
4951 priority = scp->SCp.this_residual;
cbd5f69b
LA		 4952 else
4953 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4954
1da177e4
LT		 4955 gdth_putq( hanum, scp, priority );
4956 gdth_next( hanum );
4957 return 0;
4958}
4959
4960
4961static int gdth_open(struct inode *inode, struct file *filep)
4962{
4963 gdth_ha_str *ha;
4964 int i;
4965
4966 for (i = 0; i < gdth_ctr_count; i++) {
4967 ha = HADATA(gdth_ctr_tab[i]);
4968 if (!ha->sdev)
4969 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4970 }
4971
4972 TRACE(("gdth_open()\n"));
4973 return 0;
4974}
4975
4976static int gdth_close(struct inode *inode, struct file *filep)
4977{
4978 TRACE(("gdth_close()\n"));
4979 return 0;
4980}
4981
4982static int ioc_event(void __user *arg)
4983{
4984 gdth_ioctl_event evt;
4985 gdth_ha_str *ha;
4986 ulong flags;
4987
4988 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4989 evt.ionode >= gdth_ctr_count)
4990 return -EFAULT;
4991 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4992
4993 if (evt.erase == 0xff) {
4994 if (evt.event.event_source == ES_TEST)
4995 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4996 else if (evt.event.event_source == ES_DRIVER)
4997 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4998 else if (evt.event.event_source == ES_SYNC)
4999 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
5000 else
5001 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
5002 spin_lock_irqsave(&ha->smp_lock, flags);
5003 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
5004 &evt.event.event_data);
5005 spin_unlock_irqrestore(&ha->smp_lock, flags);
5006 } else if (evt.erase == 0xfe) {
5007 gdth_clear_events();
5008 } else if (evt.erase == 0) {
5009 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
5010 } else {
5011 gdth_readapp_event(ha, evt.erase, &evt.event);
5012 }
5013 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
5014 return -EFAULT;
5015 return 0;
5016}
5017
5018static int ioc_lockdrv(void __user *arg)
5019{
5020 gdth_ioctl_lockdrv ldrv;
5021 unchar i, j;
5022 ulong flags;
5023 gdth_ha_str *ha;
5024
5025 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
5026 ldrv.ionode >= gdth_ctr_count)
5027 return -EFAULT;
5028 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
5029
5030 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
5031 j = ldrv.drives[i];
5032 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
5033 continue;
5034 if (ldrv.lock) {
5035 spin_lock_irqsave(&ha->smp_lock, flags);
5036 ha->hdr[j].lock = 1;
5037 spin_unlock_irqrestore(&ha->smp_lock, flags);
5038 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
5039 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
5040 } else {
5041 spin_lock_irqsave(&ha->smp_lock, flags);
5042 ha->hdr[j].lock = 0;
5043 spin_unlock_irqrestore(&ha->smp_lock, flags);
5044 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
5045 gdth_next(ldrv.ionode);
5046 }
5047 }
5048 return 0;
5049}
5050
5051static int ioc_resetdrv(void __user *arg, char *cmnd)
5052{
5053 gdth_ioctl_reset res;
5054 gdth_cmd_str cmd;
5055 int hanum;
5056 gdth_ha_str *ha;
cbd5f69b 5057 int rval;
1da177e4
LT		 5058
5059 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
5060 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
5061 return -EFAULT;
5062 hanum = res.ionode;
5063 ha = HADATA(gdth_ctr_tab[hanum]);
5064
5065 if (!ha->hdr[res.number].present)
5066 return 0;
5067 memset(&cmd, 0, sizeof(gdth_cmd_str));
5068 cmd.Service = CACHESERVICE;
5069 cmd.OpCode = GDT_CLUST_RESET;
5070 if (ha->cache_feat & GDT_64BIT)
5071 cmd.u.cache64.DeviceNo = res.number;
5072 else
5073 cmd.u.cache.DeviceNo = res.number;
cbd5f69b
LA		 5074
5075 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
5076 if (rval < 0)
5077 return rval;
5078 res.status = rval;
1da177e4
LT		 5079
5080 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
5081 return -EFAULT;
5082 return 0;
5083}
5084
5085static int ioc_general(void __user *arg, char *cmnd)
5086{
5087 gdth_ioctl_general gen;
5088 char *buf = NULL;
5089 ulong64 paddr;
5090 int hanum;
cbd5f69b
LA		 5091 gdth_ha_str *ha;
5092 int rval;
1da177e4
LT		 5093
5094 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
5095 gen.ionode >= gdth_ctr_count)
5096 return -EFAULT;
5097 hanum = gen.ionode;
5098 ha = HADATA(gdth_ctr_tab[hanum]);
5099 if (gen.data_len + gen.sense_len != 0) {
5100 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
5101 FALSE, &paddr)))
5102 return -EFAULT;
5103 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
5104 gen.data_len + gen.sense_len)) {
5105 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5106 return -EFAULT;
5107 }
5108
5109 if (gen.command.OpCode == GDT_IOCTL) {
5110 gen.command.u.ioctl.p_param = paddr;
5111 } else if (gen.command.Service == CACHESERVICE) {
5112 if (ha->cache_feat & GDT_64BIT) {
5113 /* copy elements from 32-bit IOCTL structure */
5114 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5115 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5116 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5117 /* addresses */
5118 if (ha->cache_feat & SCATTER_GATHER) {
5119 gen.command.u.cache64.DestAddr = (ulong64)-1;
5120 gen.command.u.cache64.sg_canz = 1;
5121 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5122 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5123 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5124 } else {
5125 gen.command.u.cache64.DestAddr = paddr;
5126 gen.command.u.cache64.sg_canz = 0;
5127 }
5128 } else {
5129 if (ha->cache_feat & SCATTER_GATHER) {
5130 gen.command.u.cache.DestAddr = 0xffffffff;
5131 gen.command.u.cache.sg_canz = 1;
5132 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5133 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5134 gen.command.u.cache.sg_lst[1].sg_len = 0;
5135 } else {
5136 gen.command.u.cache.DestAddr = paddr;
5137 gen.command.u.cache.sg_canz = 0;
5138 }
5139 }
5140 } else if (gen.command.Service == SCSIRAWSERVICE) {
5141 if (ha->raw_feat & GDT_64BIT) {
5142 /* copy elements from 32-bit IOCTL structure */
5143 char cmd[16];
5144 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5145 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5146 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5147 gen.command.u.raw64.target = gen.command.u.raw.target;
5148 memcpy(cmd, gen.command.u.raw.cmd, 16);
5149 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5150 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5151 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5152 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5153 /* addresses */
5154 if (ha->raw_feat & SCATTER_GATHER) {
5155 gen.command.u.raw64.sdata = (ulong64)-1;
5156 gen.command.u.raw64.sg_ranz = 1;
5157 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5158 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5159 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5160 } else {
5161 gen.command.u.raw64.sdata = paddr;
5162 gen.command.u.raw64.sg_ranz = 0;
5163 }
5164 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5165 } else {
5166 if (ha->raw_feat & SCATTER_GATHER) {
5167 gen.command.u.raw.sdata = 0xffffffff;
5168 gen.command.u.raw.sg_ranz = 1;
5169 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5170 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5171 gen.command.u.raw.sg_lst[1].sg_len = 0;
5172 } else {
5173 gen.command.u.raw.sdata = paddr;
5174 gen.command.u.raw.sg_ranz = 0;
5175 }
5176 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5177 }
5178 } else {
5179 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5180 return -EFAULT;
5181 }
5182 }
5183
cbd5f69b
LA		 5184 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
5185 if (rval < 0)
5186 return rval;
5187 gen.status = rval;
1da177e4
LT		 5188
5189 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5190 gen.data_len + gen.sense_len)) {
5191 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5192 return -EFAULT;
5193 }
5194 if (copy_to_user(arg, &gen,
5195 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5196 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5197 return -EFAULT;
5198 }
5199 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5200 return 0;
5201}
5202
5203static int ioc_hdrlist(void __user *arg, char *cmnd)
5204{
5205 gdth_ioctl_rescan *rsc;
5206 gdth_cmd_str *cmd;
5207 gdth_ha_str *ha;
5208 unchar i;
5209 int hanum, rc = -ENOMEM;
cbd5f69b
LA		 5210 u32 cluster_type = 0;
5211
1da177e4
LT		 5212 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5213 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5214 if (!rsc || !cmd)
cbd5f69b 5215 goto free_fail;
1da177e4
LT		 5216
5217 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5218 rsc->ionode >= gdth_ctr_count) {
5219 rc = -EFAULT;
cbd5f69b 5220 goto free_fail;
1da177e4
LT		 5221 }
5222 hanum = rsc->ionode;
5223 ha = HADATA(gdth_ctr_tab[hanum]);
5224 memset(cmd, 0, sizeof(gdth_cmd_str));
5225
1da177e4
LT		 5226 for (i = 0; i < MAX_HDRIVES; ++i) {
5227 if (!ha->hdr[i].present) {
5228 rsc->hdr_list[i].bus = 0xff;
5229 continue;
5230 }
5231 rsc->hdr_list[i].bus = ha->virt_bus;
5232 rsc->hdr_list[i].target = i;
5233 rsc->hdr_list[i].lun = 0;
5234 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5235 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5236 cmd->Service = CACHESERVICE;
5237 cmd->OpCode = GDT_CLUST_INFO;
5238 if (ha->cache_feat & GDT_64BIT)
5239 cmd->u.cache64.DeviceNo = i;
5240 else
5241 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5242 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
5243 rsc->hdr_list[i].cluster_type = cluster_type;
1da177e4
LT		 5244 }
5245 }
cbd5f69b 5246
1da177e4
LT		 5247 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5248 rc = -EFAULT;
5249 else
cbd5f69b 5250 rc = 0;
1da177e4
LT		 5251
5252free_fail:
5253 kfree(rsc);
5254 kfree(cmd);
5255 return rc;
5256}
5257
5258static int ioc_rescan(void __user *arg, char *cmnd)
5259{
5260 gdth_ioctl_rescan *rsc;
5261 gdth_cmd_str *cmd;
5262 ushort i, status, hdr_cnt;
5263 ulong32 info;
5264 int hanum, cyls, hds, secs;
5265 int rc = -ENOMEM;
5266 ulong flags;
5267 gdth_ha_str *ha;
1da177e4
LT		 5268
5269 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5270 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5271 if (!cmd || !rsc)
cbd5f69b 5272 goto free_fail;
1da177e4
LT		 5273
5274 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5275 rsc->ionode >= gdth_ctr_count) {
cbd5f69b
LA		 5276 rc = -EFAULT;
5277 goto free_fail;
1da177e4
LT		 5278 }
5279 hanum = rsc->ionode;
5280 ha = HADATA(gdth_ctr_tab[hanum]);
5281 memset(cmd, 0, sizeof(gdth_cmd_str));
5282
1da177e4
LT		 5283 if (rsc->flag == 0) {
5284 /* old method: re-init. cache service */
5285 cmd->Service = CACHESERVICE;
5286 if (ha->cache_feat & GDT_64BIT) {
5287 cmd->OpCode = GDT_X_INIT_HOST;
5288 cmd->u.cache64.DeviceNo = LINUX_OS;
5289 } else {
5290 cmd->OpCode = GDT_INIT;
5291 cmd->u.cache.DeviceNo = LINUX_OS;
5292 }
cbd5f69b
LA		 5293
5294 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
1da177e4
LT		 5295 i = 0;
5296 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5297 } else {
5298 i = rsc->hdr_no;
5299 hdr_cnt = i + 1;
5300 }
5301
5302 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5303 cmd->Service = CACHESERVICE;
5304 cmd->OpCode = GDT_INFO;
5305 if (ha->cache_feat & GDT_64BIT)
5306 cmd->u.cache64.DeviceNo = i;
5307 else
5308 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5309
5310 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5311
1da177e4
LT		 5312 spin_lock_irqsave(&ha->smp_lock, flags);
5313 rsc->hdr_list[i].bus = ha->virt_bus;
5314 rsc->hdr_list[i].target = i;
5315 rsc->hdr_list[i].lun = 0;
5316 if (status != S_OK) {
5317 ha->hdr[i].present = FALSE;
5318 } else {
5319 ha->hdr[i].present = TRUE;
5320 ha->hdr[i].size = info;
5321 /* evaluate mapping */
5322 ha->hdr[i].size &= ~SECS32;
5323 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5324 ha->hdr[i].heads = hds;
5325 ha->hdr[i].secs = secs;
5326 /* round size */
5327 ha->hdr[i].size = cyls * hds * secs;
5328 }
5329 spin_unlock_irqrestore(&ha->smp_lock, flags);
5330 if (status != S_OK)
5331 continue;
5332
5333 /* extended info, if GDT_64BIT, for drives > 2 TB */
5334 /* but we need ha->info2, not yet stored in scp->SCp */
5335
5336 /* devtype, cluster info, R/W attribs */
5337 cmd->Service = CACHESERVICE;
5338 cmd->OpCode = GDT_DEVTYPE;
5339 if (ha->cache_feat & GDT_64BIT)
5340 cmd->u.cache64.DeviceNo = i;
5341 else
5342 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5343
5344 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5345
1da177e4
LT		 5346 spin_lock_irqsave(&ha->smp_lock, flags);
5347 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5348 spin_unlock_irqrestore(&ha->smp_lock, flags);
5349
5350 cmd->Service = CACHESERVICE;
5351 cmd->OpCode = GDT_CLUST_INFO;
5352 if (ha->cache_feat & GDT_64BIT)
5353 cmd->u.cache64.DeviceNo = i;
5354 else
5355 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5356
5357 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5358
1da177e4
LT		 5359 spin_lock_irqsave(&ha->smp_lock, flags);
5360 ha->hdr[i].cluster_type =
5361 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5362 spin_unlock_irqrestore(&ha->smp_lock, flags);
5363 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5364
5365 cmd->Service = CACHESERVICE;
5366 cmd->OpCode = GDT_RW_ATTRIBS;
5367 if (ha->cache_feat & GDT_64BIT)
5368 cmd->u.cache64.DeviceNo = i;
5369 else
5370 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 5371
5372 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5373
1da177e4
LT		 5374 spin_lock_irqsave(&ha->smp_lock, flags);
5375 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5376 spin_unlock_irqrestore(&ha->smp_lock, flags);
5377 }
1da177e4
LT		 5378
5379 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5380 rc = -EFAULT;
5381 else
cbd5f69b 5382 rc = 0;
1da177e4
LT		 5383
5384free_fail:
5385 kfree(rsc);
5386 kfree(cmd);
5387 return rc;
5388}
5389
5390static int gdth_ioctl(struct inode *inode, struct file *filep,
5391 unsigned int cmd, unsigned long arg)
5392{
5393 gdth_ha_str *ha;
5394 Scsi_Cmnd *scp;
5395 ulong flags;
5396 char cmnd[MAX_COMMAND_SIZE];
5397 void __user *argp = (void __user *)arg;
5398
5399 memset(cmnd, 0xff, 12);
5400
5401 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5402
5403 switch (cmd) {
5404 case GDTIOCTL_CTRCNT:
5405 {
5406 int cnt = gdth_ctr_count;
5407 if (put_user(cnt, (int __user *)argp))
5408 return -EFAULT;
5409 break;
5410 }
5411
5412 case GDTIOCTL_DRVERS:
5413 {
5414 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5415 if (put_user(ver, (int __user *)argp))
5416 return -EFAULT;
5417 break;
5418 }
5419
5420 case GDTIOCTL_OSVERS:
5421 {
5422 gdth_ioctl_osvers osv;
5423
5424 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5425 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5426 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5427 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5428 return -EFAULT;
5429 break;
5430 }
5431
5432 case GDTIOCTL_CTRTYPE:
5433 {
5434 gdth_ioctl_ctrtype ctrt;
5435
5436 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5437 ctrt.ionode >= gdth_ctr_count)
5438 return -EFAULT;
5439 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5440 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5441 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5442 } else {
5443 if (ha->type != GDT_PCIMPR) {
5444 ctrt.type = (unchar)((ha->stype<<4) + 6);
5445 } else {
5446 ctrt.type =
5447 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5448 if (ha->stype >= 0x300)
5449 ctrt.ext_type = 0x6000 | ha->subdevice_id;
5450 else
5451 ctrt.ext_type = 0x6000 | ha->stype;
5452 }
5453 ctrt.device_id = ha->stype;
5454 ctrt.sub_device_id = ha->subdevice_id;
5455 }
5456 ctrt.info = ha->brd_phys;
5457 ctrt.oem_id = ha->oem_id;
5458 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5459 return -EFAULT;
5460 break;
5461 }
5462
5463 case GDTIOCTL_GENERAL:
5464 return ioc_general(argp, cmnd);
5465
5466 case GDTIOCTL_EVENT:
5467 return ioc_event(argp);
5468
5469 case GDTIOCTL_LOCKDRV:
5470 return ioc_lockdrv(argp);
5471
5472 case GDTIOCTL_LOCKCHN:
5473 {
5474 gdth_ioctl_lockchn lchn;
5475 unchar i, j;
5476
5477 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5478 lchn.ionode >= gdth_ctr_count)
5479 return -EFAULT;
5480 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5481
5482 i = lchn.channel;
5483 if (i < ha->bus_cnt) {
5484 if (lchn.lock) {
5485 spin_lock_irqsave(&ha->smp_lock, flags);
5486 ha->raw[i].lock = 1;
5487 spin_unlock_irqrestore(&ha->smp_lock, flags);
5488 for (j = 0; j < ha->tid_cnt; ++j) {
5489 gdth_wait_completion(lchn.ionode, i, j);
5490 gdth_stop_timeout(lchn.ionode, i, j);
5491 }
5492 } else {
5493 spin_lock_irqsave(&ha->smp_lock, flags);
5494 ha->raw[i].lock = 0;
5495 spin_unlock_irqrestore(&ha->smp_lock, flags);
5496 for (j = 0; j < ha->tid_cnt; ++j) {
5497 gdth_start_timeout(lchn.ionode, i, j);
5498 gdth_next(lchn.ionode);
5499 }
5500 }
5501 }
5502 break;
5503 }
5504
5505 case GDTIOCTL_RESCAN:
5506 return ioc_rescan(argp, cmnd);
5507
5508 case GDTIOCTL_HDRLIST:
5509 return ioc_hdrlist(argp, cmnd);
5510
5511 case GDTIOCTL_RESET_BUS:
5512 {
5513 gdth_ioctl_reset res;
5514 int hanum, rval;
5515
5516 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5517 res.ionode >= gdth_ctr_count)
5518 return -EFAULT;
5519 hanum = res.ionode;
5520 ha = HADATA(gdth_ctr_tab[hanum]);
5521
1da177e4 5522#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
cbd5f69b 5523 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
1da177e4
LT		 5524 if (!scp)
5525 return -ENOMEM;
cbd5f69b
LA		 5526 memset(scp, 0, sizeof(*scp));
5527 scp->device = ha->sdev;
1da177e4
LT		 5528 scp->cmd_len = 12;
5529 scp->use_sg = 0;
5530 scp->device->channel = virt_ctr ? 0 : res.number;
5531 rval = gdth_eh_bus_reset(scp);
5532 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
cbd5f69b 5533 kfree(scp);
1da177e4
LT		 5534#else
5535 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5536 if (!scp)
5537 return -ENOMEM;
5538 scp->cmd_len = 12;
5539 scp->use_sg = 0;
5540 scp->channel = virt_ctr ? 0 : res.number;
5541 rval = gdth_eh_bus_reset(scp);
5542 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5543 scsi_release_command(scp);
5544#endif
5545 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5546 return -EFAULT;
5547 break;
5548 }
5549
5550 case GDTIOCTL_RESET_DRV:
5551 return ioc_resetdrv(argp, cmnd);
5552
5553 default:
5554 break;
5555 }
5556 return 0;
5557}
5558
5559
5560/* flush routine */
5561static void gdth_flush(int hanum)
5562{
5563 int i;
5564 gdth_ha_str *ha;
5565 gdth_cmd_str gdtcmd;
1da177e4
LT		 5566 char cmnd[MAX_COMMAND_SIZE];
5567 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5568
5569 TRACE2(("gdth_flush() hanum %d\n",hanum));
5570 ha = HADATA(gdth_ctr_tab[hanum]);
5571
1da177e4
LT		 5572 for (i = 0; i < MAX_HDRIVES; ++i) {
5573 if (ha->hdr[i].present) {
5574 gdtcmd.BoardNode = LOCALBOARD;
5575 gdtcmd.Service = CACHESERVICE;
5576 gdtcmd.OpCode = GDT_FLUSH;
5577 if (ha->cache_feat & GDT_64BIT) {
5578 gdtcmd.u.cache64.DeviceNo = i;
5579 gdtcmd.u.cache64.BlockNo = 1;
5580 gdtcmd.u.cache64.sg_canz = 0;
5581 } else {
5582 gdtcmd.u.cache.DeviceNo = i;
5583 gdtcmd.u.cache.BlockNo = 1;
5584 gdtcmd.u.cache.sg_canz = 0;
5585 }
5586 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
cbd5f69b
LA		 5587
5588 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
1da177e4
LT		 5589 }
5590 }
1da177e4
LT		 5591}
5592
5593/* shutdown routine */
5594static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5595{
5596 int hanum;
5597#ifndef __alpha__
5598 gdth_cmd_str gdtcmd;
1da177e4
LT		 5599 char cmnd[MAX_COMMAND_SIZE];
5600#endif
5601
e041c683 5602 if (notifier_disabled)
cbd5f69b 5603 return NOTIFY_OK;
e041c683 5604
1da177e4
LT		 5605 TRACE2(("gdth_halt() event %d\n",(int)event));
5606 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5607 return NOTIFY_DONE;
5608
e041c683 5609 notifier_disabled = 1;
1da177e4
LT		 5610 printk("GDT-HA: Flushing all host drives .. ");
5611 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5612 gdth_flush(hanum);
5613
5614#ifndef __alpha__
5615 /* controller reset */
5616 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5617 gdtcmd.BoardNode = LOCALBOARD;
5618 gdtcmd.Service = CACHESERVICE;
5619 gdtcmd.OpCode = GDT_RESET;
5620 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
cbd5f69b 5621 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
1da177e4
LT		 5622#endif
5623 }
5624 printk("Done.\n");
5625
5626#ifdef GDTH_STATISTICS
5627 del_timer(&gdth_timer);
5628#endif
1da177e4
LT		 5629 return NOTIFY_OK;
5630}
5631
cbd5f69b
LA		 5632#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5633/* configure lun */
5634static int gdth_slave_configure(struct scsi_device *sdev)
5635{
5636 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
5637 sdev->skip_ms_page_3f = 1;
5638 sdev->skip_ms_page_8 = 1;
5639 return 0;
5640}
5641#endif
5642
5643#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
d0be4a7d 5644static struct scsi_host_template driver_template = {
cbd5f69b
LA		 5645#else
5646static Scsi_Host_Template driver_template = {
5647#endif
1da177e4
LT		 5648 .proc_name = "gdth",
5649 .proc_info = gdth_proc_info,
5650 .name = "GDT SCSI Disk Array Controller",
5651 .detect = gdth_detect,
5652 .release = gdth_release,
5653 .info = gdth_info,
5654 .queuecommand = gdth_queuecommand,
1da177e4 5655 .eh_bus_reset_handler = gdth_eh_bus_reset,
1da177e4
LT		 5656 .bios_param = gdth_bios_param,
5657 .can_queue = GDTH_MAXCMDS,
cbd5f69b
LA		 5658#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5659 .slave_configure = gdth_slave_configure,
5660#endif
1da177e4
LT		 5661 .this_id = -1,
5662 .sg_tablesize = GDTH_MAXSG,
5663 .cmd_per_lun = GDTH_MAXC_P_L,
5664 .unchecked_isa_dma = 1,
5665 .use_clustering = ENABLE_CLUSTERING,
5666#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5667 .use_new_eh_code = 1,
5668#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5669 .highmem_io = 1,
5670#endif
5671#endif
5672};
5673
5674#include "scsi_module.c"
5675#ifndef MODULE
5676__setup("gdth=", option_setup);
5677#endif
Empty description
This page took 0.884805 seconds and 4 git commands to generate.