[linux.git] / drivers / edac / i82875p_edac.c

/*
 * Intel D82875P Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Contributors:
 *	Wang Zhenyu at intel.com
 *
 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
 */


#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>

#include <linux/pci.h>
#include <linux/pci_ids.h>

#include <linux/slab.h>

#include "edac_mc.h"


#define i82875p_printk(level, fmt, arg...) \
    edac_printk(level, "i82875p", fmt, ##arg)


#define i82875p_mc_printk(mci, level, fmt, arg...) \
    edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)


#ifndef PCI_DEVICE_ID_INTEL_82875_0
#define PCI_DEVICE_ID_INTEL_82875_0	0x2578
#endif				/* PCI_DEVICE_ID_INTEL_82875_0 */

#ifndef PCI_DEVICE_ID_INTEL_82875_6
#define PCI_DEVICE_ID_INTEL_82875_6	0x257e
#endif				/* PCI_DEVICE_ID_INTEL_82875_6 */


/* four csrows in dual channel, eight in single channel */
#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))


/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
#define I82875P_EAP		0x58	/* Error Address Pointer (32b)
					 *
					 * 31:12 block address
					 * 11:0  reserved
					 */

#define I82875P_DERRSYN		0x5c	/* DRAM Error Syndrome (8b)
					 *
					 *  7:0  DRAM ECC Syndrome
					 */

#define I82875P_DES		0x5d	/* DRAM Error Status (8b)
					 *
					 *  7:1  reserved
					 *  0    Error channel 0/1
					 */

#define I82875P_ERRSTS		0xc8	/* Error Status Register (16b)
					 *
					 * 15:10 reserved
					 *  9    non-DRAM lock error (ndlock)
					 *  8    Sftwr Generated SMI
					 *  7    ECC UE
					 *  6    reserved
					 *  5    MCH detects unimplemented cycle
					 *  4    AGP access outside GA
					 *  3    Invalid AGP access
					 *  2    Invalid GA translation table
					 *  1    Unsupported AGP command
					 *  0    ECC CE
					 */

#define I82875P_ERRCMD		0xca	/* Error Command (16b)
					 *
					 * 15:10 reserved
					 *  9    SERR on non-DRAM lock
					 *  8    SERR on ECC UE
					 *  7    SERR on ECC CE
					 *  6    target abort on high exception
					 *  5    detect unimplemented cyc
					 *  4    AGP access outside of GA
					 *  3    SERR on invalid AGP access
					 *  2    invalid translation table
					 *  1    SERR on unsupported AGP command
					 *  0    reserved
					 */


/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
#define I82875P_PCICMD6		0x04	/* PCI Command Register (16b)
					 *
					 * 15:10 reserved
					 *  9    fast back-to-back - ro 0
					 *  8    SERR enable - ro 0
					 *  7    addr/data stepping - ro 0
					 *  6    parity err enable - ro 0
					 *  5    VGA palette snoop - ro 0
					 *  4    mem wr & invalidate - ro 0
					 *  3    special cycle - ro 0
					 *  2    bus master - ro 0
					 *  1    mem access dev6 - 0(dis),1(en)
					 *  0    IO access dev3 - 0(dis),1(en)
					 */

#define I82875P_BAR6		0x10	/* Mem Delays Base ADDR Reg (32b)
					 *
					 * 31:12 mem base addr [31:12]
					 * 11:4  address mask - ro 0
					 *  3    prefetchable - ro 0(non),1(pre)
					 *  2:1  mem type - ro 0
					 *  0    mem space - ro 0
					 */

/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */

#define I82875P_DRB_SHIFT 26	/* 64MiB grain */
#define I82875P_DRB		0x00	/* DRAM Row Boundary (8b x 8)
					 *
					 *  7    reserved
					 *  6:0  64MiB row boundary addr
					 */

#define I82875P_DRA		0x10	/* DRAM Row Attribute (4b x 8)
					 *
					 *  7    reserved
					 *  6:4  row attr row 1
					 *  3    reserved
					 *  2:0  row attr row 0
					 *
					 * 000 =  4KiB
					 * 001 =  8KiB
					 * 010 = 16KiB
					 * 011 = 32KiB
					 */

#define I82875P_DRC		0x68	/* DRAM Controller Mode (32b)
					 *
					 * 31:30 reserved
					 * 29    init complete
					 * 28:23 reserved
					 * 22:21 nr chan 00=1,01=2
					 * 20    reserved
					 * 19:18 Data Integ Mode 00=none,01=ecc
					 * 17:11 reserved
					 * 10:8  refresh mode
					 *  7    reserved
					 *  6:4  mode select
					 *  3:2  reserved
					 *  1:0  DRAM type 01=DDR
					 */


enum i82875p_chips {
	I82875P = 0,
};


struct i82875p_pvt {
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window;
};


struct i82875p_dev_info {
	const char *ctl_name;
};


struct i82875p_error_info {
	u16 errsts;
	u32 eap;
	u8 des;
	u8 derrsyn;
	u16 errsts2;
};


static const struct i82875p_dev_info i82875p_devs[] = {
	[I82875P] = {
		     .ctl_name = "i82875p"},
};

static struct pci_dev *mci_pdev = NULL;	/* init dev: in case that AGP code
					   has already registered driver */
static int i82875p_registered = 1;

static void i82875p_get_error_info (struct mem_ctl_info *mci,
		struct i82875p_error_info *info)
{
	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
	pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
	pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
	pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
	pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);

	pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);

	/*
	 * If the error is the same then we can for both reads then
	 * the first set of reads is valid.  If there is a change then
	 * there is a CE no info and the second set of reads is valid
	 * and should be UE info.
	 */
	if (!(info->errsts2 & 0x0081))
		return;
	if ((info->errsts ^ info->errsts2) & 0x0081) {
		pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
		pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
		pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
		    &info->derrsyn);
	}
}

static int i82875p_process_error_info (struct mem_ctl_info *mci,
		struct i82875p_error_info *info, int handle_errors)
{
	int row, multi_chan;

	multi_chan = mci->csrows[0].nr_channels - 1;

	if (!(info->errsts2 & 0x0081))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0081) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0080)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
				       multi_chan ? (info->des & 0x1) : 0,
				       "i82875p CE");

	return 1;
}


static void i82875p_check(struct mem_ctl_info *mci)
{
	struct i82875p_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82875p_get_error_info(mci, &info);
	i82875p_process_error_info(mci, &info, 1);
}


#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *);
#endif

static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	int index;
	struct mem_ctl_info *mci = NULL;
	struct i82875p_pvt *pvt = NULL;
	unsigned long last_cumul_size;
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window = NULL;

	u32 drc;
	u32 drc_chan;		/* Number of channels 0=1chan,1=2chan */
	u32 nr_chans;
	u32 drc_ddim;		/* DRAM Data Integrity Mode 0=none,2=edac */

	debugf0("%s()\n", __func__);

	ovrfl_pdev = pci_find_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);

	if (!ovrfl_pdev) {
		/*
		 * Intel tells BIOS developers to hide device 6 which
		 * configures the overflow device access containing
		 * the DRBs - this is where we expose device 6.
		 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
		 */
		pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
		ovrfl_pdev =
		    pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
		if (!ovrfl_pdev)
			goto fail;
	}
#ifdef CONFIG_PROC_FS
	if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
		i82875p_printk(KERN_ERR,
			       "%s(): Failed to attach overflow device\n",
			       __func__);
		goto fail;
	}
#endif				/* CONFIG_PROC_FS */
	if (pci_enable_device(ovrfl_pdev)) {
		i82875p_printk(KERN_ERR,
			       "%s(): Failed to enable overflow device\n",
			       __func__);
		goto fail;
	}

	if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
#ifdef CORRECT_BIOS
		goto fail;
#endif
	}
	/* cache is irrelevant for PCI bus reads/writes */
	ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
				       pci_resource_len(ovrfl_pdev, 0));

	if (!ovrfl_window) {
		i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
			       __func__);
		goto fail;
	}

	/* need to find out the number of channels */
	drc = readl(ovrfl_window + I82875P_DRC);
	drc_chan = ((drc >> 21) & 0x1);
	nr_chans = drc_chan + 1;
	drc_ddim = (drc >> 18) & 0x1;

	mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
				 nr_chans);

	if (!mci) {
		rc = -ENOMEM;
		goto fail;
	}

	debugf3("%s(): init mci\n", __func__);

	mci->pdev = pdev;
	mci->mtype_cap = MEM_FLAG_DDR;

	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	/* adjust FLAGS */

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = "$Revision: 1.5.2.11 $";
	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
	mci->edac_check = i82875p_check;
	mci->ctl_page_to_phys = NULL;

	debugf3("%s(): init pvt\n", __func__);

	pvt = (struct i82875p_pvt *) mci->pvt_info;
	pvt->ovrfl_pdev = ovrfl_pdev;
	pvt->ovrfl_window = ovrfl_window;

	/*
	 * The dram row boundary (DRB) reg values are boundary address
	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
	 * contain the total memory contained in all eight rows.
	 */
	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
		u8 value;
		u32 cumul_size;
		struct csrow_info *csrow = &mci->csrows[index];

		value = readb(ovrfl_window + I82875P_DRB + index);
		cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;	/* I82875P_EAP has 4KiB reolution */
		csrow->mtype = MEM_DDR;
		csrow->dtype = DEV_UNKNOWN;
		csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
	}

	/* clear counters */
	pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);

	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* get this far and it's successful */
	debugf3("%s(): success\n", __func__);
	return 0;

      fail:
	if (mci)
		edac_mc_free(mci);

	if (ovrfl_window)
		iounmap(ovrfl_window);

	if (ovrfl_pdev) {
		pci_release_regions(ovrfl_pdev);
		pci_disable_device(ovrfl_pdev);
	}

	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	return rc;
}


/* returns count (>= 0), or negative on error */
static int __devinit i82875p_init_one(struct pci_dev *pdev,
				      const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);

	i82875p_printk(KERN_INFO, "i82875p init one\n");
	if(pci_enable_device(pdev) < 0)
		return -EIO;
	rc = i82875p_probe1(pdev, ent->driver_data);
	if (mci_pdev == NULL)
		mci_pdev = pci_dev_get(pdev);
	return rc;
}


static void __devexit i82875p_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct i82875p_pvt *pvt = NULL;

	debugf0("%s()\n", __func__);

	if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
		return;

	pvt = (struct i82875p_pvt *) mci->pvt_info;
	if (pvt->ovrfl_window)
		iounmap(pvt->ovrfl_window);

	if (pvt->ovrfl_pdev) {
#ifdef CORRECT_BIOS
		pci_release_regions(pvt->ovrfl_pdev);
#endif				/*CORRECT_BIOS */
		pci_disable_device(pvt->ovrfl_pdev);
		pci_dev_put(pvt->ovrfl_pdev);
	}

	if (edac_mc_del_mc(mci))
		return;

	edac_mc_free(mci);
}


static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
	{PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82875P},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);


static struct pci_driver i82875p_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82875p_init_one,
	.remove = __devexit_p(i82875p_remove_one),
	.id_table = i82875p_pci_tbl,
};


static int __init i82875p_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);
	pci_rc = pci_register_driver(&i82875p_driver);
	if (pci_rc < 0)
		return pci_rc;
	if (mci_pdev == NULL) {
		i82875p_registered = 0;
		mci_pdev =
		    pci_get_device(PCI_VENDOR_ID_INTEL,
				   PCI_DEVICE_ID_INTEL_82875_0, NULL);
		if (!mci_pdev) {
			debugf0("875p pci_get_device fail\n");
			return -ENODEV;
		}
		pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
		if (pci_rc < 0) {
			debugf0("875p init fail\n");
			pci_dev_put(mci_pdev);
			return -ENODEV;
		}
	}
	return 0;
}


static void __exit i82875p_exit(void)
{
	debugf3("%s()\n", __func__);

	pci_unregister_driver(&i82875p_driver);
	if (!i82875p_registered) {
		i82875p_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}


module_init(i82875p_init);
module_exit(i82875p_exit);


MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel D82875P Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Contributors:
	9	* Wang Zhenyu at intel.com
	10	*
	11	* $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	* Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
	14	*/
	15
	16
	17	#include <linux/config.h>
	18	#include <linux/module.h>
	19	#include <linux/init.h>
	20
	21	#include <linux/pci.h>
	22	#include <linux/pci_ids.h>
	23
	24	#include <linux/slab.h>
	25
	26	#include "edac_mc.h"
	27
	28
537fba28 DP	29	#define i82875p_printk(level, fmt, arg...) \
	30	edac_printk(level, "i82875p", fmt, ##arg)
	31
	32
	33	#define i82875p_mc_printk(mci, level, fmt, arg...) \
	34	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
	35
	36
0d88a10e AC	37	#ifndef PCI_DEVICE_ID_INTEL_82875_0
	38	#define PCI_DEVICE_ID_INTEL_82875_0 0x2578
	39	#endif /* PCI_DEVICE_ID_INTEL_82875_0 */
	40
	41	#ifndef PCI_DEVICE_ID_INTEL_82875_6
	42	#define PCI_DEVICE_ID_INTEL_82875_6 0x257e
	43	#endif /* PCI_DEVICE_ID_INTEL_82875_6 */
	44
	45
	46	/* four csrows in dual channel, eight in single channel */
	47	#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
	48
	49
	50	/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
	51	#define I82875P_EAP 0x58 /* Error Address Pointer (32b)
	52	*
	53	* 31:12 block address
	54	* 11:0 reserved
	55	*/
	56
	57	#define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
	58	*
	59	* 7:0 DRAM ECC Syndrome
	60	*/
	61
	62	#define I82875P_DES 0x5d /* DRAM Error Status (8b)
	63	*
	64	* 7:1 reserved
	65	* 0 Error channel 0/1
	66	*/
	67
	68	#define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
	69	*
	70	* 15:10 reserved
	71	* 9 non-DRAM lock error (ndlock)
	72	* 8 Sftwr Generated SMI
	73	* 7 ECC UE
	74	* 6 reserved
	75	* 5 MCH detects unimplemented cycle
	76	* 4 AGP access outside GA
	77	* 3 Invalid AGP access
	78	* 2 Invalid GA translation table
	79	* 1 Unsupported AGP command
	80	* 0 ECC CE
	81	*/
	82
	83	#define I82875P_ERRCMD 0xca /* Error Command (16b)
	84	*
	85	* 15:10 reserved
	86	* 9 SERR on non-DRAM lock
	87	* 8 SERR on ECC UE
	88	* 7 SERR on ECC CE
	89	* 6 target abort on high exception
	90	* 5 detect unimplemented cyc
	91	* 4 AGP access outside of GA
	92	* 3 SERR on invalid AGP access
	93	* 2 invalid translation table
	94	* 1 SERR on unsupported AGP command
	95	* 0 reserved
	96	*/
	97
	98
	99	/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
	100	#define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
101	*
102	* 15:10 reserved
103	* 9 fast back-to-back - ro 0
104	* 8 SERR enable - ro 0
105	* 7 addr/data stepping - ro 0
106	* 6 parity err enable - ro 0
107	* 5 VGA palette snoop - ro 0
108	* 4 mem wr & invalidate - ro 0
109	* 3 special cycle - ro 0
110	* 2 bus master - ro 0
111	* 1 mem access dev6 - 0(dis),1(en)
112	* 0 IO access dev3 - 0(dis),1(en)
113	*/
114
115	#define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
116	*
117	* 31:12 mem base addr [31:12]
118	* 11:4 address mask - ro 0
119	* 3 prefetchable - ro 0(non),1(pre)
120	* 2:1 mem type - ro 0
121	* 0 mem space - ro 0
122	*/
123
124	/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
125
126	#define I82875P_DRB_SHIFT 26 /* 64MiB grain */
127	#define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
128	*
129	* 7 reserved
130	* 6:0 64MiB row boundary addr
131	*/
132
133	#define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
134	*
135	* 7 reserved
136	* 6:4 row attr row 1
137	* 3 reserved
138	* 2:0 row attr row 0
139	*
140	* 000 = 4KiB
141	* 001 = 8KiB
142	* 010 = 16KiB
143	* 011 = 32KiB
144	*/
145
146	#define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
147	*
148	* 31:30 reserved
149	* 29 init complete
150	* 28:23 reserved
151	* 22:21 nr chan 00=1,01=2
152	* 20 reserved
153	* 19:18 Data Integ Mode 00=none,01=ecc
154	* 17:11 reserved
155	* 10:8 refresh mode
156	* 7 reserved
157	* 6:4 mode select
158	* 3:2 reserved
159	* 1:0 DRAM type 01=DDR
160	*/
161
162
163	enum i82875p_chips {
164	I82875P = 0,
165	};
166
167
168	struct i82875p_pvt {
169	struct pci_dev *ovrfl_pdev;
6d57348d	170	void __iomem *ovrfl_window;
0d88a10e AC	171	};
	172
	173
	174	struct i82875p_dev_info {
	175	const char *ctl_name;
	176	};
	177
	178
	179	struct i82875p_error_info {
	180	u16 errsts;
	181	u32 eap;
	182	u8 des;
	183	u8 derrsyn;
	184	u16 errsts2;
	185	};
	186
	187
	188	static const struct i82875p_dev_info i82875p_devs[] = {
	189	[I82875P] = {
	190	.ctl_name = "i82875p"},
	191	};
	192
	193	static struct pci_dev mci_pdev = NULL; / init dev: in case that AGP code
	194	has already registered driver */
	195	static int i82875p_registered = 1;
	196
	197	static void i82875p_get_error_info (struct mem_ctl_info *mci,
	198	struct i82875p_error_info *info)
	199	{
	200	/*
	201	* This is a mess because there is no atomic way to read all the
	202	* registers at once and the registers can transition from CE being
	203	* overwritten by UE.
	204	*/
	205	pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
	206	pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
	207	pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
	208	pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
	209	pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);
	210
	211	pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
	212
	213	/*
	214	* If the error is the same then we can for both reads then
	215	* the first set of reads is valid. If there is a change then
	216	* there is a CE no info and the second set of reads is valid
	217	* and should be UE info.
	218	*/
	219	if (!(info->errsts2 & 0x0081))
	220	return;
	221	if ((info->errsts ^ info->errsts2) & 0x0081) {
	222	pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
	223	pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
	224	pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
	225	&info->derrsyn);
	226	}
	227	}
	228
	229	static int i82875p_process_error_info (struct mem_ctl_info *mci,
	230	struct i82875p_error_info *info, int handle_errors)
	231	{
	232	int row, multi_chan;
	233
	234	multi_chan = mci->csrows[0].nr_channels - 1;
235
236	if (!(info->errsts2 & 0x0081))
237	return 0;
238
239	if (!handle_errors)
240	return 1;
241
242	if ((info->errsts ^ info->errsts2) & 0x0081) {
243	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
244	info->errsts = info->errsts2;
245	}
246
247	info->eap >>= PAGE_SHIFT;
248	row = edac_mc_find_csrow_by_page(mci, info->eap);
249
250	if (info->errsts & 0x0080)
251	edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
252	else
253	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
254	multi_chan ? (info->des & 0x1) : 0,
255	"i82875p CE");
256
257	return 1;
258	}
259
260
261	static void i82875p_check(struct mem_ctl_info *mci)
262	{
263	struct i82875p_error_info info;
264
537fba28	265	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	266	i82875p_get_error_info(mci, &info);
	267	i82875p_process_error_info(mci, &info, 1);
	268	}
	269
	270
	271	#ifdef CONFIG_PROC_FS
	272	extern int pci_proc_attach_device(struct pci_dev *);
	273	#endif
	274
	275	static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
	276	{
	277	int rc = -ENODEV;
	278	int index;
	279	struct mem_ctl_info *mci = NULL;
	280	struct i82875p_pvt *pvt = NULL;
	281	unsigned long last_cumul_size;
	282	struct pci_dev *ovrfl_pdev;
	283	void __iomem *ovrfl_window = NULL;
	284
	285	u32 drc;
	286	u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
	287	u32 nr_chans;
	288	u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
	289
537fba28	290	debugf0("%s()\n", __func__);
0d88a10e AC	291
	292	ovrfl_pdev = pci_find_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
	293
	294	if (!ovrfl_pdev) {
	295	/*
	296	* Intel tells BIOS developers to hide device 6 which
	297	* configures the overflow device access containing
	298	* the DRBs - this is where we expose device 6.
	299	* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
	300	*/
	301	pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
	302	ovrfl_pdev =
	303	pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
	304	if (!ovrfl_pdev)
	305	goto fail;
	306	}
	307	#ifdef CONFIG_PROC_FS
	308	if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
537fba28 DP	309	i82875p_printk(KERN_ERR,
	310	"%s(): Failed to attach overflow device\n",
	311	__func__);
0d88a10e AC	312	goto fail;
	313	}
	314	#endif /* CONFIG_PROC_FS */
	315	if (pci_enable_device(ovrfl_pdev)) {
537fba28 DP	316	i82875p_printk(KERN_ERR,
	317	"%s(): Failed to enable overflow device\n",
	318	__func__);
0d88a10e AC	319	goto fail;
	320	}
	321
	322	if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
	323	#ifdef CORRECT_BIOS
	324	goto fail;
	325	#endif
	326	}
	327	/* cache is irrelevant for PCI bus reads/writes */
	328	ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
	329	pci_resource_len(ovrfl_pdev, 0));
	330
	331	if (!ovrfl_window) {
537fba28 DP	332	i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
537fba28 DP	333	__func__);
0d88a10e AC	334	goto fail;
	335	}
	336
	337	/* need to find out the number of channels */
	338	drc = readl(ovrfl_window + I82875P_DRC);
	339	drc_chan = ((drc >> 21) & 0x1);
	340	nr_chans = drc_chan + 1;
	341	drc_ddim = (drc >> 18) & 0x1;
	342
	343	mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
	344	nr_chans);
	345
	346	if (!mci) {
	347	rc = -ENOMEM;
	348	goto fail;
	349	}
	350
537fba28	351	debugf3("%s(): init mci\n", __func__);
0d88a10e AC	352
	353	mci->pdev = pdev;
	354	mci->mtype_cap = MEM_FLAG_DDR;
	355
	356	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	357	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	358	/* adjust FLAGS */
	359
680cbbbb	360	mci->mod_name = EDAC_MOD_STR;
0d88a10e AC	361	mci->mod_ver = "$Revision: 1.5.2.11 $";
	362	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
	363	mci->edac_check = i82875p_check;
	364	mci->ctl_page_to_phys = NULL;
	365
537fba28	366	debugf3("%s(): init pvt\n", __func__);
0d88a10e AC	367
	368	pvt = (struct i82875p_pvt *) mci->pvt_info;
	369	pvt->ovrfl_pdev = ovrfl_pdev;
	370	pvt->ovrfl_window = ovrfl_window;
	371
	372	/*
	373	* The dram row boundary (DRB) reg values are boundary address
	374	* for each DRAM row with a granularity of 32 or 64MB (single/dual
	375	* channel operation). DRB regs are cumulative; therefore DRB7 will
	376	* contain the total memory contained in all eight rows.
	377	*/
	378	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
	379	u8 value;
	380	u32 cumul_size;
	381	struct csrow_info *csrow = &mci->csrows[index];
	382
	383	value = readb(ovrfl_window + I82875P_DRB + index);
	384	cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
537fba28 DP	385	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
537fba28 DP	386	cumul_size);
0d88a10e AC	387	if (cumul_size == last_cumul_size)
	388	continue; /* not populated */
	389
	390	csrow->first_page = last_cumul_size;
	391	csrow->last_page = cumul_size - 1;
	392	csrow->nr_pages = cumul_size - last_cumul_size;
	393	last_cumul_size = cumul_size;
	394	csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
	395	csrow->mtype = MEM_DDR;
	396	csrow->dtype = DEV_UNKNOWN;
	397	csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
	398	}
	399
	400	/* clear counters */
	401	pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
	402
	403	if (edac_mc_add_mc(mci)) {
537fba28	404	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
0d88a10e AC	405	goto fail;
	406	}
	407
	408	/* get this far and it's successful */
537fba28	409	debugf3("%s(): success\n", __func__);
0d88a10e AC	410	return 0;
	411
	412	fail:
	413	if (mci)
	414	edac_mc_free(mci);
	415
	416	if (ovrfl_window)
	417	iounmap(ovrfl_window);
	418
	419	if (ovrfl_pdev) {
	420	pci_release_regions(ovrfl_pdev);
	421	pci_disable_device(ovrfl_pdev);
	422	}
	423
	424	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	425	return rc;
	426	}
	427
	428
	429	/* returns count (>= 0), or negative on error */
	430	static int __devinit i82875p_init_one(struct pci_dev *pdev,
	431	const struct pci_device_id *ent)
	432	{
	433	int rc;
	434
537fba28	435	debugf0("%s()\n", __func__);
0d88a10e	436
537fba28	437	i82875p_printk(KERN_INFO, "i82875p init one\n");
0d88a10e AC	438	if(pci_enable_device(pdev) < 0)
	439	return -EIO;
	440	rc = i82875p_probe1(pdev, ent->driver_data);
	441	if (mci_pdev == NULL)
	442	mci_pdev = pci_dev_get(pdev);
	443	return rc;
	444	}
	445
	446
	447	static void __devexit i82875p_remove_one(struct pci_dev *pdev)
	448	{
	449	struct mem_ctl_info *mci;
	450	struct i82875p_pvt *pvt = NULL;
	451
537fba28	452	debugf0("%s()\n", __func__);
0d88a10e AC	453
	454	if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
	455	return;
	456
	457	pvt = (struct i82875p_pvt *) mci->pvt_info;
	458	if (pvt->ovrfl_window)
	459	iounmap(pvt->ovrfl_window);
	460
	461	if (pvt->ovrfl_pdev) {
	462	#ifdef CORRECT_BIOS
	463	pci_release_regions(pvt->ovrfl_pdev);
	464	#endif /CORRECT_BIOS /
	465	pci_disable_device(pvt->ovrfl_pdev);
	466	pci_dev_put(pvt->ovrfl_pdev);
	467	}
	468
	469	if (edac_mc_del_mc(mci))
	470	return;
	471
	472	edac_mc_free(mci);
	473	}
	474
	475
	476	static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
	477	{PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	478	I82875P},
	479	{0,} /* 0 terminated list. */
	480	};
	481
	482	MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
	483
	484
	485	static struct pci_driver i82875p_driver = {
680cbbbb	486	.name = EDAC_MOD_STR,
0d88a10e AC	487	.probe = i82875p_init_one,
	488	.remove = __devexit_p(i82875p_remove_one),
	489	.id_table = i82875p_pci_tbl,
	490	};
	491
	492
da9bb1d2	493	static int __init i82875p_init(void)
0d88a10e AC	494	{
	495	int pci_rc;
	496
537fba28	497	debugf3("%s()\n", __func__);
0d88a10e AC	498	pci_rc = pci_register_driver(&i82875p_driver);
	499	if (pci_rc < 0)
	500	return pci_rc;
	501	if (mci_pdev == NULL) {
	502	i82875p_registered = 0;
	503	mci_pdev =
	504	pci_get_device(PCI_VENDOR_ID_INTEL,
	505	PCI_DEVICE_ID_INTEL_82875_0, NULL);
	506	if (!mci_pdev) {
	507	debugf0("875p pci_get_device fail\n");
	508	return -ENODEV;
	509	}
	510	pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
	511	if (pci_rc < 0) {
	512	debugf0("875p init fail\n");
	513	pci_dev_put(mci_pdev);
	514	return -ENODEV;
	515	}
	516	}
	517	return 0;
	518	}
	519
	520
	521	static void __exit i82875p_exit(void)
	522	{
537fba28	523	debugf3("%s()\n", __func__);
0d88a10e AC	524
	525	pci_unregister_driver(&i82875p_driver);
	526	if (!i82875p_registered) {
	527	i82875p_remove_one(mci_pdev);
	528	pci_dev_put(mci_pdev);
	529	}
	530	}
	531
	532
	533	module_init(i82875p_init);
	534	module_exit(i82875p_exit);
	535
	536
	537	MODULE_LICENSE("GPL");
	538	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	539	MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");