[linux.git] / drivers / ata / pata_optidma.c

/*
 * pata_optidma.c 	- Opti DMA PATA for new ATA layer
 *			  (C) 2006 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *
 *	The Opti DMA controllers are related to the older PIO PCI controllers
 *	and indeed the VLB ones. The main differences are that the timing
 *	numbers are now based off PCI clocks not VLB and differ, and that
 *	MWDMA is supported.
 *
 *	This driver should support Viper-N+, FireStar, FireStar Plus.
 *
 *	These devices support virtual DMA for read (aka the CS5520). Later
 *	chips support UDMA33, but only if the rest of the board logic does,
 *	so you have to get this right. We don't support the virtual DMA
 *	but we do handle UDMA.
 *
 *	Bits that are worth knowing
 *		Most control registers are shadowed into I/O registers
 *		0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
 *		Virtual DMA registers *move* between rev 0x02 and rev 0x10
 *		UDMA requires a 66MHz FSB
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_optidma"
#define DRV_VERSION "0.3.2"

enum {
	READ_REG	= 0,	/* index of Read cycle timing register */
	WRITE_REG 	= 1,	/* index of Write cycle timing register */
	CNTRL_REG 	= 3,	/* index of Control register */
	STRAP_REG 	= 5,	/* index of Strap register */
	MISC_REG 	= 6	/* index of Miscellaneous register */
};

static int pci_clock;	/* 0 = 33 1 = 25 */

/**
 *	optidma_pre_reset		-	probe begin
 *	@ap: ATA port
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int optidma_pre_reset(struct ata_port *ap, unsigned long deadline)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits optidma_enable_bits = {
		0x40, 1, 0x08, 0x00
	};

	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
		return -ENOENT;

	return ata_std_prereset(ap, deadline);
}

/**
 *	optidma_probe_reset		-	probe reset
 *	@ap: ATA port
 *
 *	Perform the ATA probe and bus reset sequence plus specific handling
 *	for this hardware. The Opti needs little handling - we have no UDMA66
 *	capability that needs cable detection. All we must do is check the port
 *	is enabled.
 */

static void optidma_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	optidma_unlock		-	unlock control registers
 *	@ap: ATA port
 *
 *	Unlock the control register block for this adapter. Registers must not
 *	be unlocked in a situation where libata might look at them.
 */

static void optidma_unlock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* These 3 unlock the control register access */
	ioread16(regio + 1);
	ioread16(regio + 1);
	iowrite8(3, regio + 2);
}

/**
 *	optidma_lock		-	issue temporary relock
 *	@ap: ATA port
 *
 *	Re-lock the configuration register settings.
 */

static void optidma_lock(struct ata_port *ap)
{
	void __iomem *regio = ap->ioaddr.cmd_addr;

	/* Relock */
	iowrite8(0x83, regio + 2);
}

/**
 *	optidma_mode_setup	-	set mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: Mode to set
 *
 *	Called to do the DMA or PIO mode setup. Timing numbers are all
 *	pre computed to keep the code clean. There are two tables depending
 *	on the hardware clock speed.
 *
 *	WARNING: While we do this the IDE registers vanish. If we take an
 *	IRQ here we depend on the host set locking to avoid catastrophe.
 */

static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct ata_device *pair = ata_dev_pair(adev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int dma = adev->dma_mode - XFER_MW_DMA_0;
	void __iomem *regio = ap->ioaddr.cmd_addr;
	u8 addr;

	/* Address table precomputed with a DCLK of 2 */
	static const u8 addr_timing[2][5] = {
		{ 0x30, 0x20, 0x20, 0x10, 0x10 },
		{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	};
	static const u8 data_rec_timing[2][5] = {
		{ 0x59, 0x46, 0x30, 0x20, 0x20 },
		{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	};
	static const u8 dma_data_rec_timing[2][3] = {
		{ 0x76, 0x20, 0x20 },
		{ 0x54, 0x20, 0x10 }
	};

	/* Switch from IDE to control mode */
	optidma_unlock(ap);


	/*
 	 *	As with many controllers the address setup time is shared
 	 *	and must suit both devices if present. FIXME: Check if we
 	 *	need to look at slowest of PIO/DMA mode of either device
	 */

	if (mode >= XFER_MW_DMA_0)
		addr = 0;
	else
		addr = addr_timing[pci_clock][pio];

	if (pair) {
		u8 pair_addr;
		/* Hardware constraint */
		if (pair->dma_mode)
			pair_addr = 0;
		else
			pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
		if (pair_addr > addr)
			addr = pair_addr;
	}

	/* Commence primary programming sequence */
	/* First we load the device number into the timing select */
	iowrite8(adev->devno, regio + MISC_REG);
	/* Now we load the data timings into read data/write data */
	if (mode < XFER_MW_DMA_0) {
		iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
		iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
	} else if (mode < XFER_UDMA_0) {
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
		iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
	}
	/* Finally we load the address setup into the misc register */
	iowrite8(addr | adev->devno, regio + MISC_REG);

	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
	iowrite8(0x85, regio + CNTRL_REG);

	/* Switch back to IDE mode */
	optidma_lock(ap);

	/* Note: at this point our programming is incomplete. We are
	   not supposed to program PCI 0x43 "things we hacked onto the chip"
	   until we've done both sets of PIO/DMA timings */
}

/**
 *	optiplus_mode_setup	-	DMA setup for Firestar Plus
 *	@ap: ATA port
 *	@adev: device
 *	@mode: desired mode
 *
 *	The Firestar plus has additional UDMA functionality for UDMA0-2 and
 *	requires we do some additional work. Because the base work we must do
 *	is mostly shared we wrap the Firestar setup functionality in this
 *	one
 */

static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 udcfg;
	u8 udslave;
	int dev2 = 2 * adev->devno;
	int unit = 2 * ap->port_no + adev->devno;
	int udma = mode - XFER_UDMA_0;

	pci_read_config_byte(pdev, 0x44, &udcfg);
	if (mode <= XFER_UDMA_0) {
		udcfg &= ~(1 << unit);
		optidma_mode_setup(ap, adev, adev->dma_mode);
	} else {
		udcfg |=  (1 << unit);
		if (ap->port_no) {
			pci_read_config_byte(pdev, 0x45, &udslave);
			udslave &= ~(0x03 << dev2);
			udslave |= (udma << dev2);
			pci_write_config_byte(pdev, 0x45, udslave);
		} else {
			udcfg &= ~(0x30 << dev2);
			udcfg |= (udma << dev2);
		}
	}
	pci_write_config_byte(pdev, 0x44, udcfg);
}

/**
 *	optidma_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optidma_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optidma_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optiplus_set_pio_mode	-	PIO setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->pio_mode);
}

/**
 *	optiplus_set_dma_mode	-	DMA setup callback
 *	@ap: ATA port
 *	@adev: Device
 *
 *	The libata core provides separate functions for handling PIO and
 *	DMA programming. The architecture of the Firestar makes it easier
 *	for us to have a common function so we provide wrappers
 */

static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
{
	optiplus_mode_setup(ap, adev, adev->dma_mode);
}

/**
 *	optidma_make_bits	-	PCI setup helper
 *	@adev: ATA device
 *
 *	Turn the ATA device setup into PCI configuration bits
 *	for register 0x43 and return the two bits needed.
 */

static u8 optidma_make_bits43(struct ata_device *adev)
{
	static const u8 bits43[5] = {
		0, 0, 0, 1, 2
	};
	if (!ata_dev_enabled(adev))
		return 0;
	if (adev->dma_mode)
		return adev->dma_mode - XFER_MW_DMA_0;
	return bits43[adev->pio_mode - XFER_PIO_0];
}

/**
 *	optidma_set_mode	-	mode setup
 *	@ap: port to set up
 *
 *	Use the standard setup to tune the chipset and then finalise the
 *	configuration by writing the nibble of extra bits of data into
 *	the chip.
 */

static int optidma_set_mode(struct ata_port *ap, struct ata_device **r_failed)
{
	u8 r;
	int nybble = 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int rc  = ata_do_set_mode(ap, r_failed);
	if (rc == 0) {
		pci_read_config_byte(pdev, 0x43, &r);

		r &= (0x0F << nybble);
		r |= (optidma_make_bits43(&ap->device[0]) +
		     (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
		pci_write_config_byte(pdev, 0x43, r);
	}
	return rc;
}

static struct scsi_host_template optidma_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations optidma_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= optidma_set_pio_mode,
	.set_dmamode	= optidma_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations optiplus_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= optiplus_set_pio_mode,
	.set_dmamode	= optiplus_set_dma_mode,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.error_handler	= optidma_error_handler,
	.set_mode	= optidma_set_mode,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	optiplus_with_udma	-	Look for UDMA capable setup
 *	@pdev; ATA controller
 */

static int optiplus_with_udma(struct pci_dev *pdev)
{
	u8 r;
	int ret = 0;
	int ioport = 0x22;
	struct pci_dev *dev1;

	/* Find function 1 */
	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	if(dev1 == NULL)
		return 0;

	/* Rev must be >= 0x10 */
	pci_read_config_byte(dev1, 0x08, &r);
	if (r < 0x10)
		goto done_nomsg;
	/* Read the chipset system configuration to check our mode */
	pci_read_config_byte(dev1, 0x5F, &r);
	ioport |= (r << 8);
	outb(0x10, ioport);
	/* Must be 66Mhz sync */
	if ((inb(ioport + 2) & 1) == 0)
		goto done;

	/* Check the ATA arbitration/timing is suitable */
	pci_read_config_byte(pdev, 0x42, &r);
	if ((r & 0x36) != 0x36)
		goto done;
	pci_read_config_byte(dev1, 0x52, &r);
	if (r & 0x80)	/* IDEDIR disabled */
		ret = 1;
done:
	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
done_nomsg:		/* Wrong chip revision */
	pci_dev_put(dev1);
	return ret;
}

static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_82c700 = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &optidma_port_ops
	};
	static const struct ata_port_info info_82c700_udma = {
		.sht = &optidma_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
		.port_ops = &optiplus_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_82c700, NULL };
	static int printed_version;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	/* Fixed location chipset magic */
	inw(0x1F1);
	inw(0x1F1);
	pci_clock = inb(0x1F5) & 1;		/* 0 = 33Mhz, 1 = 25Mhz */

	if (optiplus_with_udma(dev))
		ppi[0] = &info_82c700_udma;

	return ata_pci_init_one(dev, ppi);
}

static const struct pci_device_id optidma[] = {
	{ PCI_VDEVICE(OPTI, 0xD568), },		/* Opti 82C700 */

	{ },
};

static struct pci_driver optidma_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= optidma,
	.probe 		= optidma_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init optidma_init(void)
{
	return pci_register_driver(&optidma_pci_driver);
}

static void __exit optidma_exit(void)
{
	pci_unregister_driver(&optidma_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, optidma);
MODULE_VERSION(DRV_VERSION);

module_init(optidma_init);
module_exit(optidma_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_optidma.c - Opti DMA PATA for new ATA layer
	3	* (C) 2006 Red Hat Inc
	4	* Alan Cox <[email protected]>
	5	*
	6	* The Opti DMA controllers are related to the older PIO PCI controllers
	7	* and indeed the VLB ones. The main differences are that the timing
	8	* numbers are now based off PCI clocks not VLB and differ, and that
	9	* MWDMA is supported.
	10	*
	11	* This driver should support Viper-N+, FireStar, FireStar Plus.
	12	*
	13	* These devices support virtual DMA for read (aka the CS5520). Later
	14	* chips support UDMA33, but only if the rest of the board logic does,
	15	* so you have to get this right. We don't support the virtual DMA
	16	* but we do handle UDMA.
	17	*
	18	* Bits that are worth knowing
	19	* Most control registers are shadowed into I/O registers
	20	* 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
	21	* Virtual DMA registers move between rev 0x02 and rev 0x10
	22	* UDMA requires a 66MHz FSB
	23	*
	24	*/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_optidma"
5c25bf0d	36	#define DRV_VERSION "0.3.2"
669a5db4 JG	37
	38	enum {
	39	READ_REG = 0, /* index of Read cycle timing register */
	40	WRITE_REG = 1, /* index of Write cycle timing register */
	41	CNTRL_REG = 3, /* index of Control register */
	42	STRAP_REG = 5, /* index of Strap register */
	43	MISC_REG = 6 /* index of Miscellaneous register */
	44	};
	45
	46	static int pci_clock; /* 0 = 33 1 = 25 */
	47
	48	/**
	49	* optidma_pre_reset - probe begin
	50	* @ap: ATA port
d4b2bab4	51	* @deadline: deadline jiffies for the operation
669a5db4 JG	52	*
	53	* Set up cable type and use generic probe init
	54	*/
85cd7251	55
d4b2bab4	56	static int optidma_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4 JG	57	{
669a5db4 JG	58	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	59	static const struct pci_bits optidma_enable_bits = {
669a5db4 JG	60	0x40, 1, 0x08, 0x00
	61	};
	62
c961922b AC	63	if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
	64	return -ENOENT;
	65
d4b2bab4	66	return ata_std_prereset(ap, deadline);
669a5db4 JG	67	}
	68
	69	/**
	70	* optidma_probe_reset - probe reset
	71	* @ap: ATA port
	72	*
	73	* Perform the ATA probe and bus reset sequence plus specific handling
	74	* for this hardware. The Opti needs little handling - we have no UDMA66
	75	* capability that needs cable detection. All we must do is check the port
	76	* is enabled.
	77	*/
	78
	79	static void optidma_error_handler(struct ata_port *ap)
	80	{
	81	ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	82	}
	83
	84	/**
	85	* optidma_unlock - unlock control registers
	86	* @ap: ATA port
	87	*
	88	* Unlock the control register block for this adapter. Registers must not
	89	* be unlocked in a situation where libata might look at them.
	90	*/
85cd7251	91
669a5db4 JG	92	static void optidma_unlock(struct ata_port *ap)
669a5db4 JG	93	{
0d5ff566	94	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	95
669a5db4	96	/* These 3 unlock the control register access */
0d5ff566 TH	97	ioread16(regio + 1);
	98	ioread16(regio + 1);
	99	iowrite8(3, regio + 2);
669a5db4 JG	100	}
	101
	102	/**
	103	* optidma_lock - issue temporary relock
	104	* @ap: ATA port
	105	*
	106	* Re-lock the configuration register settings.
	107	*/
85cd7251	108
669a5db4 JG	109	static void optidma_lock(struct ata_port *ap)
669a5db4 JG	110	{
0d5ff566	111	void __iomem *regio = ap->ioaddr.cmd_addr;
85cd7251	112
669a5db4	113	/* Relock */
0d5ff566	114	iowrite8(0x83, regio + 2);
669a5db4 JG	115	}
	116
	117	/**
5c25bf0d	118	* optidma_mode_setup - set mode data
669a5db4 JG	119	* @ap: ATA interface
	120	* @adev: ATA device
	121	* @mode: Mode to set
	122	*
	123	* Called to do the DMA or PIO mode setup. Timing numbers are all
	124	* pre computed to keep the code clean. There are two tables depending
	125	* on the hardware clock speed.
	126	*
	127	* WARNING: While we do this the IDE registers vanish. If we take an
	128	* IRQ here we depend on the host set locking to avoid catastrophe.
	129	*/
	130
5c25bf0d	131	static void optidma_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	132	{
	133	struct ata_device *pair = ata_dev_pair(adev);
	134	int pio = adev->pio_mode - XFER_PIO_0;
	135	int dma = adev->dma_mode - XFER_MW_DMA_0;
0d5ff566	136	void __iomem *regio = ap->ioaddr.cmd_addr;
669a5db4 JG	137	u8 addr;
	138
	139	/* Address table precomputed with a DCLK of 2 */
	140	static const u8 addr_timing[2][5] = {
	141	{ 0x30, 0x20, 0x20, 0x10, 0x10 },
	142	{ 0x20, 0x20, 0x10, 0x10, 0x10 }
	143	};
	144	static const u8 data_rec_timing[2][5] = {
	145	{ 0x59, 0x46, 0x30, 0x20, 0x20 },
	146	{ 0x46, 0x32, 0x20, 0x20, 0x10 }
	147	};
	148	static const u8 dma_data_rec_timing[2][3] = {
	149	{ 0x76, 0x20, 0x20 },
	150	{ 0x54, 0x20, 0x10 }
	151	};
	152
	153	/* Switch from IDE to control mode */
	154	optidma_unlock(ap);
85cd7251	155
669a5db4 JG	156
	157	/*
	158	* As with many controllers the address setup time is shared
	159	* and must suit both devices if present. FIXME: Check if we
	160	* need to look at slowest of PIO/DMA mode of either device
	161	*/
	162
	163	if (mode >= XFER_MW_DMA_0)
	164	addr = 0;
	165	else
	166	addr = addr_timing[pci_clock][pio];
85cd7251	167
669a5db4 JG	168	if (pair) {
	169	u8 pair_addr;
	170	/* Hardware constraint */
	171	if (pair->dma_mode)
	172	pair_addr = 0;
	173	else
	174	pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
	175	if (pair_addr > addr)
	176	addr = pair_addr;
	177	}
85cd7251	178
669a5db4 JG	179	/* Commence primary programming sequence */
669a5db4 JG	180	/* First we load the device number into the timing select */
0d5ff566	181	iowrite8(adev->devno, regio + MISC_REG);
669a5db4 JG	182	/* Now we load the data timings into read data/write data */
669a5db4 JG	183	if (mode < XFER_MW_DMA_0) {
0d5ff566 TH	184	iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
0d5ff566 TH	185	iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
669a5db4	186	} else if (mode < XFER_UDMA_0) {
0d5ff566 TH	187	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
0d5ff566 TH	188	iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
669a5db4 JG	189	}
669a5db4 JG	190	/* Finally we load the address setup into the misc register */
0d5ff566	191	iowrite8(addr \| adev->devno, regio + MISC_REG);
669a5db4 JG	192
669a5db4 JG	193	/* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
0d5ff566	194	iowrite8(0x85, regio + CNTRL_REG);
85cd7251	195
669a5db4 JG	196	/* Switch back to IDE mode */
669a5db4 JG	197	optidma_lock(ap);
85cd7251	198
669a5db4 JG	199	/* Note: at this point our programming is incomplete. We are
	200	not supposed to program PCI 0x43 "things we hacked onto the chip"
	201	until we've done both sets of PIO/DMA timings */
	202	}
	203
	204	/**
5c25bf0d	205	* optiplus_mode_setup - DMA setup for Firestar Plus
669a5db4 JG	206	* @ap: ATA port
	207	* @adev: device
	208	* @mode: desired mode
	209	*
	210	* The Firestar plus has additional UDMA functionality for UDMA0-2 and
	211	* requires we do some additional work. Because the base work we must do
	212	* is mostly shared we wrap the Firestar setup functionality in this
	213	* one
	214	*/
	215
5c25bf0d	216	static void optiplus_mode_setup(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	217	{
	218	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	219	u8 udcfg;
	220	u8 udslave;
	221	int dev2 = 2 * adev->devno;
	222	int unit = 2 * ap->port_no + adev->devno;
	223	int udma = mode - XFER_UDMA_0;
85cd7251	224
669a5db4 JG	225	pci_read_config_byte(pdev, 0x44, &udcfg);
	226	if (mode <= XFER_UDMA_0) {
	227	udcfg &= ~(1 << unit);
5c25bf0d	228	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	229	} else {
	230	udcfg \|= (1 << unit);
	231	if (ap->port_no) {
	232	pci_read_config_byte(pdev, 0x45, &udslave);
	233	udslave &= ~(0x03 << dev2);
	234	udslave \|= (udma << dev2);
	235	pci_write_config_byte(pdev, 0x45, udslave);
	236	} else {
	237	udcfg &= ~(0x30 << dev2);
	238	udcfg \|= (udma << dev2);
	239	}
	240	}
	241	pci_write_config_byte(pdev, 0x44, udcfg);
	242	}
	243
	244	/**
	245	* optidma_set_pio_mode - PIO setup callback
	246	* @ap: ATA port
	247	* @adev: Device
	248	*
	249	* The libata core provides separate functions for handling PIO and
	250	* DMA programming. The architecture of the Firestar makes it easier
	251	* for us to have a common function so we provide wrappers
	252	*/
85cd7251	253
669a5db4 JG	254	static void optidma_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	255	{
5c25bf0d	256	optidma_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	257	}
	258
	259	/**
	260	* optidma_set_dma_mode - DMA setup callback
	261	* @ap: ATA port
	262	* @adev: Device
	263	*
	264	* The libata core provides separate functions for handling PIO and
	265	* DMA programming. The architecture of the Firestar makes it easier
	266	* for us to have a common function so we provide wrappers
	267	*/
85cd7251	268
669a5db4 JG	269	static void optidma_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	270	{
5c25bf0d	271	optidma_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	272	}
	273
	274	/**
	275	* optiplus_set_pio_mode - PIO setup callback
	276	* @ap: ATA port
	277	* @adev: Device
	278	*
	279	* The libata core provides separate functions for handling PIO and
	280	* DMA programming. The architecture of the Firestar makes it easier
	281	* for us to have a common function so we provide wrappers
	282	*/
85cd7251	283
669a5db4 JG	284	static void optiplus_set_pio_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	285	{
5c25bf0d	286	optiplus_mode_setup(ap, adev, adev->pio_mode);
669a5db4 JG	287	}
	288
	289	/**
	290	* optiplus_set_dma_mode - DMA setup callback
	291	* @ap: ATA port
	292	* @adev: Device
	293	*
	294	* The libata core provides separate functions for handling PIO and
	295	* DMA programming. The architecture of the Firestar makes it easier
	296	* for us to have a common function so we provide wrappers
	297	*/
85cd7251	298
669a5db4 JG	299	static void optiplus_set_dma_mode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	300	{
5c25bf0d	301	optiplus_mode_setup(ap, adev, adev->dma_mode);
669a5db4 JG	302	}
	303
	304	/**
	305	* optidma_make_bits - PCI setup helper
	306	* @adev: ATA device
	307	*
	308	* Turn the ATA device setup into PCI configuration bits
	309	* for register 0x43 and return the two bits needed.
	310	*/
85cd7251	311
669a5db4 JG	312	static u8 optidma_make_bits43(struct ata_device *adev)
	313	{
	314	static const u8 bits43[5] = {
	315	0, 0, 0, 1, 2
	316	};
	317	if (!ata_dev_enabled(adev))
	318	return 0;
	319	if (adev->dma_mode)
	320	return adev->dma_mode - XFER_MW_DMA_0;
	321	return bits43[adev->pio_mode - XFER_PIO_0];
	322	}
	323
	324	/**
5c25bf0d	325	* optidma_set_mode - mode setup
669a5db4 JG	326	* @ap: port to set up
669a5db4 JG	327	*
5c25bf0d AC	328	* Use the standard setup to tune the chipset and then finalise the
	329	* configuration by writing the nibble of extra bits of data into
	330	* the chip.
669a5db4	331	*/
85cd7251	332
5c25bf0d	333	static int optidma_set_mode(struct ata_port ap, struct ata_device *r_failed)
669a5db4 JG	334	{
	335	u8 r;
	336	int nybble = 4 * ap->port_no;
	337	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
5c25bf0d AC	338	int rc = ata_do_set_mode(ap, r_failed);
	339	if (rc == 0) {
	340	pci_read_config_byte(pdev, 0x43, &r);
	341
	342	r &= (0x0F << nybble);
	343	r \|= (optidma_make_bits43(&ap->device[0]) +
	344	(optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
	345	pci_write_config_byte(pdev, 0x43, r);
	346	}
	347	return rc;
669a5db4 JG	348	}
	349
	350	static struct scsi_host_template optidma_sht = {
	351	.module = THIS_MODULE,
	352	.name = DRV_NAME,
	353	.ioctl = ata_scsi_ioctl,
	354	.queuecommand = ata_scsi_queuecmd,
	355	.can_queue = ATA_DEF_QUEUE,
	356	.this_id = ATA_SHT_THIS_ID,
	357	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	358	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	359	.emulated = ATA_SHT_EMULATED,
	360	.use_clustering = ATA_SHT_USE_CLUSTERING,
	361	.proc_name = DRV_NAME,
	362	.dma_boundary = ATA_DMA_BOUNDARY,
	363	.slave_configure = ata_scsi_slave_config,
afdfe899	364	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	365	.bios_param = ata_std_bios_param,
	366	};
	367
	368	static struct ata_port_operations optidma_port_ops = {
	369	.port_disable = ata_port_disable,
	370	.set_piomode = optidma_set_pio_mode,
	371	.set_dmamode = optidma_set_dma_mode,
	372
	373	.tf_load = ata_tf_load,
	374	.tf_read = ata_tf_read,
	375	.check_status = ata_check_status,
	376	.exec_command = ata_exec_command,
	377	.dev_select = ata_std_dev_select,
	378
	379	.freeze = ata_bmdma_freeze,
	380	.thaw = ata_bmdma_thaw,
	381	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	382	.error_handler = optidma_error_handler,
5c25bf0d AC	383	.set_mode = optidma_set_mode,
5c25bf0d AC	384	.cable_detect = ata_cable_40wire,
669a5db4 JG	385
	386	.bmdma_setup = ata_bmdma_setup,
	387	.bmdma_start = ata_bmdma_start,
	388	.bmdma_stop = ata_bmdma_stop,
	389	.bmdma_status = ata_bmdma_status,
	390
	391	.qc_prep = ata_qc_prep,
	392	.qc_issue = ata_qc_issue_prot,
bda30288	393
0d5ff566	394	.data_xfer = ata_data_xfer,
669a5db4 JG	395
	396	.irq_handler = ata_interrupt,
	397	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	398	.irq_on = ata_irq_on,
246ce3b6 AI	399	.irq_ack = ata_irq_ack,
669a5db4 JG	400
669a5db4 JG	401	.port_start = ata_port_start,
669a5db4 JG	402	};
	403
	404	static struct ata_port_operations optiplus_port_ops = {
	405	.port_disable = ata_port_disable,
	406	.set_piomode = optiplus_set_pio_mode,
	407	.set_dmamode = optiplus_set_dma_mode,
	408
	409	.tf_load = ata_tf_load,
	410	.tf_read = ata_tf_read,
	411	.check_status = ata_check_status,
	412	.exec_command = ata_exec_command,
	413	.dev_select = ata_std_dev_select,
	414
	415	.freeze = ata_bmdma_freeze,
	416	.thaw = ata_bmdma_thaw,
	417	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	418	.error_handler = optidma_error_handler,
5c25bf0d AC	419	.set_mode = optidma_set_mode,
5c25bf0d AC	420	.cable_detect = ata_cable_40wire,
669a5db4 JG	421
	422	.bmdma_setup = ata_bmdma_setup,
	423	.bmdma_start = ata_bmdma_start,
	424	.bmdma_stop = ata_bmdma_stop,
	425	.bmdma_status = ata_bmdma_status,
	426
	427	.qc_prep = ata_qc_prep,
	428	.qc_issue = ata_qc_issue_prot,
bda30288	429
0d5ff566	430	.data_xfer = ata_data_xfer,
669a5db4 JG	431
	432	.irq_handler = ata_interrupt,
	433	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	434	.irq_on = ata_irq_on,
246ce3b6 AI	435	.irq_ack = ata_irq_ack,
669a5db4 JG	436
669a5db4 JG	437	.port_start = ata_port_start,
669a5db4 JG	438	};
	439
	440	/**
	441	* optiplus_with_udma - Look for UDMA capable setup
	442	* @pdev; ATA controller
	443	*/
85cd7251	444
669a5db4 JG	445	static int optiplus_with_udma(struct pci_dev *pdev)
	446	{
	447	u8 r;
	448	int ret = 0;
	449	int ioport = 0x22;
	450	struct pci_dev *dev1;
85cd7251	451
669a5db4 JG	452	/* Find function 1 */
	453	dev1 = pci_get_device(0x1045, 0xC701, NULL);
	454	if(dev1 == NULL)
	455	return 0;
85cd7251	456
669a5db4 JG	457	/* Rev must be >= 0x10 */
	458	pci_read_config_byte(dev1, 0x08, &r);
	459	if (r < 0x10)
	460	goto done_nomsg;
	461	/* Read the chipset system configuration to check our mode */
	462	pci_read_config_byte(dev1, 0x5F, &r);
	463	ioport \|= (r << 8);
	464	outb(0x10, ioport);
	465	/* Must be 66Mhz sync */
	466	if ((inb(ioport + 2) & 1) == 0)
	467	goto done;
	468
	469	/* Check the ATA arbitration/timing is suitable */
	470	pci_read_config_byte(pdev, 0x42, &r);
	471	if ((r & 0x36) != 0x36)
	472	goto done;
	473	pci_read_config_byte(dev1, 0x52, &r);
	474	if (r & 0x80) /* IDEDIR disabled */
	475	ret = 1;
85cd7251	476	done:
669a5db4 JG	477	printk(KERN_WARNING "UDMA not supported in this configuration.\n");
	478	done_nomsg: /* Wrong chip revision */
	479	pci_dev_put(dev1);
	480	return ret;
	481	}
	482
	483	static int optidma_init_one(struct pci_dev dev, const struct pci_device_id id)
	484	{
1626aeb8	485	static const struct ata_port_info info_82c700 = {
669a5db4	486	.sht = &optidma_sht,
1d2808fd	487	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	488	.pio_mask = 0x1f,
	489	.mwdma_mask = 0x07,
	490	.port_ops = &optidma_port_ops
	491	};
1626aeb8	492	static const struct ata_port_info info_82c700_udma = {
669a5db4	493	.sht = &optidma_sht,
1d2808fd	494	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	495	.pio_mask = 0x1f,
	496	.mwdma_mask = 0x07,
	497	.udma_mask = 0x07,
	498	.port_ops = &optiplus_port_ops
	499	};
1626aeb8	500	const struct ata_port_info *ppi[] = { &info_82c700, NULL };
669a5db4 JG	501	static int printed_version;
	502
	503	if (!printed_version++)
	504	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	505
	506	/* Fixed location chipset magic */
	507	inw(0x1F1);
	508	inw(0x1F1);
	509	pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
85cd7251	510
669a5db4	511	if (optiplus_with_udma(dev))
1626aeb8	512	ppi[0] = &info_82c700_udma;
669a5db4	513
1626aeb8	514	return ata_pci_init_one(dev, ppi);
669a5db4 JG	515	}
	516
	517	static const struct pci_device_id optidma[] = {
2d2744fc JG	518	{ PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
	519
	520	{ },
669a5db4 JG	521	};
	522
	523	static struct pci_driver optidma_pci_driver = {
2d2744fc	524	.name = DRV_NAME,
669a5db4 JG	525	.id_table = optidma,
669a5db4 JG	526	.probe = optidma_init_one,
30ced0f0	527	.remove = ata_pci_remove_one,
438ac6d5	528	#ifdef CONFIG_PM
30ced0f0 AC	529	.suspend = ata_pci_device_suspend,
30ced0f0 AC	530	.resume = ata_pci_device_resume,
438ac6d5	531	#endif
669a5db4 JG	532	};
	533
	534	static int __init optidma_init(void)
	535	{
	536	return pci_register_driver(&optidma_pci_driver);
	537	}
	538
669a5db4 JG	539	static void __exit optidma_exit(void)
	540	{
	541	pci_unregister_driver(&optidma_pci_driver);
	542	}
	543
669a5db4 JG	544	MODULE_AUTHOR("Alan Cox");
	545	MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
	546	MODULE_LICENSE("GPL");
	547	MODULE_DEVICE_TABLE(pci, optidma);
	548	MODULE_VERSION(DRV_VERSION);
	549
	550	module_init(optidma_init);
	551	module_exit(optidma_exit);