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KVM: x86: IN instruction emulation should ignore REP-prefix
[linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <[email protected]>
13 * Yaniv Kamay <[email protected]>
4d5c5d0f
BAY		 14 * Amit Shah <[email protected]>
15 * Ben-Ami Yassour <[email protected]>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
97ec8c06
FW		 655 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
656 return 1;
657
afcbf13f 658 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 659 return 1;
660
a03490ed 661 if (is_long_mode(vcpu)) {
0f12244f
GN		 662 if (!(cr4 & X86_CR4_PAE))
663 return 1;
a2edf57f
AK		 664 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
665 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 666 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
667 kvm_read_cr3(vcpu)))
0f12244f
GN		 668 return 1;
669
ad756a16
MJ		 670 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
671 if (!guest_cpuid_has_pcid(vcpu))
672 return 1;
673
674 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
675 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
676 return 1;
677 }
678
5e1746d6 679 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 680 return 1;
a03490ed 681
ad756a16
MJ		 682 if (((cr4 ^ old_cr4) & pdptr_bits) ||
683 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 684 kvm_mmu_reset_context(vcpu);
0f12244f 685
97ec8c06
FW		 686 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
687 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
688
2acf923e 689 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 690 kvm_update_cpuid(vcpu);
2acf923e 691
0f12244f
GN		 692 return 0;
693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 695
2390218b 696int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 697{
9f8fe504 698 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 699 kvm_mmu_sync_roots(vcpu);
d835dfec 700 kvm_mmu_flush_tlb(vcpu);
0f12244f 701 return 0;
d835dfec
AK		 702 }
703
346874c9
NA		 704 if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS))
705 return 1;
706 if (is_pae(vcpu) && is_paging(vcpu) &&
707 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
708 return 1;
a03490ed 709
0f12244f 710 vcpu->arch.cr3 = cr3;
aff48baa 711 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 712 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 713 return 0;
714}
2d3ad1f4 715EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 716
eea1cff9 717int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 718{
0f12244f
GN		 719 if (cr8 & CR8_RESERVED_BITS)
720 return 1;
a03490ed
CO		 721 if (irqchip_in_kernel(vcpu->kvm))
722 kvm_lapic_set_tpr(vcpu, cr8);
723 else
ad312c7c 724 vcpu->arch.cr8 = cr8;
0f12244f
GN		 725 return 0;
726}
2d3ad1f4 727EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 728
2d3ad1f4 729unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 730{
731 if (irqchip_in_kernel(vcpu->kvm))
732 return kvm_lapic_get_cr8(vcpu);
733 else
ad312c7c 734 return vcpu->arch.cr8;
a03490ed 735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 737
73aaf249
JK		 738static void kvm_update_dr6(struct kvm_vcpu *vcpu)
739{
740 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
741 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
742}
743
c8639010
JK		 744static void kvm_update_dr7(struct kvm_vcpu *vcpu)
745{
746 unsigned long dr7;
747
748 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
749 dr7 = vcpu->arch.guest_debug_dr7;
750 else
751 dr7 = vcpu->arch.dr7;
752 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 753 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
754 if (dr7 & DR7_BP_EN_MASK)
755 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 756}
757
338dbc97 758static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 759{
760 switch (dr) {
761 case 0 ... 3:
762 vcpu->arch.db[dr] = val;
763 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
764 vcpu->arch.eff_db[dr] = val;
765 break;
766 case 4:
338dbc97
GN		 767 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
768 return 1; /* #UD */
020df079
GN		 769 /* fall through */
770 case 6:
338dbc97
GN		 771 if (val & 0xffffffff00000000ULL)
772 return -1; /* #GP */
020df079 773 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 774 kvm_update_dr6(vcpu);
020df079
GN		 775 break;
776 case 5:
338dbc97
GN		 777 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
778 return 1; /* #UD */
020df079
GN		 779 /* fall through */
780 default: /* 7 */
338dbc97
GN		 781 if (val & 0xffffffff00000000ULL)
782 return -1; /* #GP */
020df079 783 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 784 kvm_update_dr7(vcpu);
020df079
GN		 785 break;
786 }
787
788 return 0;
789}
338dbc97
GN		 790
791int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
792{
793 int res;
794
795 res = __kvm_set_dr(vcpu, dr, val);
796 if (res > 0)
797 kvm_queue_exception(vcpu, UD_VECTOR);
798 else if (res < 0)
799 kvm_inject_gp(vcpu, 0);
800
801 return res;
802}
020df079
GN		 803EXPORT_SYMBOL_GPL(kvm_set_dr);
804
338dbc97 805static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 806{
807 switch (dr) {
808 case 0 ... 3:
809 *val = vcpu->arch.db[dr];
810 break;
811 case 4:
338dbc97 812 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 813 return 1;
020df079
GN		 814 /* fall through */
815 case 6:
73aaf249
JK		 816 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
817 *val = vcpu->arch.dr6;
818 else
819 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 820 break;
821 case 5:
338dbc97 822 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 823 return 1;
020df079
GN		 824 /* fall through */
825 default: /* 7 */
826 *val = vcpu->arch.dr7;
827 break;
828 }
829
830 return 0;
831}
338dbc97
GN		 832
833int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
834{
835 if (_kvm_get_dr(vcpu, dr, val)) {
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 return 1;
838 }
839 return 0;
840}
020df079
GN		 841EXPORT_SYMBOL_GPL(kvm_get_dr);
842
022cd0e8
AK		 843bool kvm_rdpmc(struct kvm_vcpu *vcpu)
844{
845 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
846 u64 data;
847 int err;
848
849 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
850 if (err)
851 return err;
852 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
853 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
854 return err;
855}
856EXPORT_SYMBOL_GPL(kvm_rdpmc);
857
043405e1
CO		 858/*
859 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
860 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
861 *
862 * This list is modified at module load time to reflect the
e3267cbb
GC		 863 * capabilities of the host cpu. This capabilities test skips MSRs that are
864 * kvm-specific. Those are put in the beginning of the list.
043405e1 865 */
e3267cbb 866
e984097b 867#define KVM_SAVE_MSRS_BEGIN 12
043405e1 868static u32 msrs_to_save[] = {
e3267cbb 869 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 870 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 871 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 872 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 873 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 874 MSR_KVM_PV_EOI_EN,
043405e1 875 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 876 MSR_STAR,
043405e1
CO		 877#ifdef CONFIG_X86_64
878 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
879#endif
b3897a49 880 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 881 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 882};
883
884static unsigned num_msrs_to_save;
885
f1d24831 886static const u32 emulated_msrs[] = {
ba904635 887 MSR_IA32_TSC_ADJUST,
a3e06bbe 888 MSR_IA32_TSCDEADLINE,
043405e1 889 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 890 MSR_IA32_MCG_STATUS,
891 MSR_IA32_MCG_CTL,
043405e1
CO		 892};
893
384bb783 894bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 895{
b69e8cae 896 if (efer & efer_reserved_bits)
384bb783 897 return false;
15c4a640 898
1b2fd70c
AG		 899 if (efer & EFER_FFXSR) {
900 struct kvm_cpuid_entry2 *feat;
901
902 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 903 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 904 return false;
1b2fd70c
AG		 905 }
906
d8017474
AG		 907 if (efer & EFER_SVME) {
908 struct kvm_cpuid_entry2 *feat;
909
910 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 911 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 912 return false;
d8017474
AG		 913 }
914
384bb783
JK		 915 return true;
916}
917EXPORT_SYMBOL_GPL(kvm_valid_efer);
918
919static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
920{
921 u64 old_efer = vcpu->arch.efer;
922
923 if (!kvm_valid_efer(vcpu, efer))
924 return 1;
925
926 if (is_paging(vcpu)
927 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
928 return 1;
929
15c4a640 930 efer &= ~EFER_LMA;
f6801dff 931 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 932
a3d204e2
SY		 933 kvm_x86_ops->set_efer(vcpu, efer);
934
aad82703
SY		 935 /* Update reserved bits */
936 if ((efer ^ old_efer) & EFER_NX)
937 kvm_mmu_reset_context(vcpu);
938
b69e8cae 939 return 0;
15c4a640
CO		 940}
941
f2b4b7dd
JR		 942void kvm_enable_efer_bits(u64 mask)
943{
944 efer_reserved_bits &= ~mask;
945}
946EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
947
948
15c4a640
CO		 949/*
950 * Writes msr value into into the appropriate "register".
951 * Returns 0 on success, non-0 otherwise.
952 * Assumes vcpu_load() was already called.
953 */
8fe8ab46 954int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 955{
8fe8ab46 956 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 957}
958
313a3dc7
CO		 959/*
960 * Adapt set_msr() to msr_io()'s calling convention
961 */
962static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
963{
8fe8ab46
WA		 964 struct msr_data msr;
965
966 msr.data = *data;
967 msr.index = index;
968 msr.host_initiated = true;
969 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 970}
971
16e8d74d
MT		 972#ifdef CONFIG_X86_64
973struct pvclock_gtod_data {
974 seqcount_t seq;
975
976 struct { /* extract of a clocksource struct */
977 int vclock_mode;
978 cycle_t cycle_last;
979 cycle_t mask;
980 u32 mult;
981 u32 shift;
982 } clock;
983
984 /* open coded 'struct timespec' */
985 u64 monotonic_time_snsec;
986 time_t monotonic_time_sec;
987};
988
989static struct pvclock_gtod_data pvclock_gtod_data;
990
991static void update_pvclock_gtod(struct timekeeper *tk)
992{
993 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
994
995 write_seqcount_begin(&vdata->seq);
996
997 /* copy pvclock gtod data */
998 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
999 vdata->clock.cycle_last = tk->clock->cycle_last;
1000 vdata->clock.mask = tk->clock->mask;
1001 vdata->clock.mult = tk->mult;
1002 vdata->clock.shift = tk->shift;
1003
1004 vdata->monotonic_time_sec = tk->xtime_sec
1005 + tk->wall_to_monotonic.tv_sec;
1006 vdata->monotonic_time_snsec = tk->xtime_nsec
1007 + (tk->wall_to_monotonic.tv_nsec
1008 << tk->shift);
1009 while (vdata->monotonic_time_snsec >=
1010 (((u64)NSEC_PER_SEC) << tk->shift)) {
1011 vdata->monotonic_time_snsec -=
1012 ((u64)NSEC_PER_SEC) << tk->shift;
1013 vdata->monotonic_time_sec++;
1014 }
1015
1016 write_seqcount_end(&vdata->seq);
1017}
1018#endif
1019
1020
18068523
GOC		 1021static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1022{
9ed3c444
AK		 1023 int version;
1024 int r;
50d0a0f9 1025 struct pvclock_wall_clock wc;
923de3cf 1026 struct timespec boot;
18068523
GOC		 1027
1028 if (!wall_clock)
1029 return;
1030
9ed3c444
AK		 1031 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1032 if (r)
1033 return;
1034
1035 if (version & 1)
1036 ++version; /* first time write, random junk */
1037
1038 ++version;
18068523 1039
18068523
GOC		 1040 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1041
50d0a0f9
GH		 1042 /*
1043 * The guest calculates current wall clock time by adding
34c238a1 1044 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1045 * wall clock specified here. guest system time equals host
1046 * system time for us, thus we must fill in host boot time here.
1047 */
923de3cf 1048 getboottime(&boot);
50d0a0f9 1049
4b648665
BR		 1050 if (kvm->arch.kvmclock_offset) {
1051 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1052 boot = timespec_sub(boot, ts);
1053 }
50d0a0f9
GH		 1054 wc.sec = boot.tv_sec;
1055 wc.nsec = boot.tv_nsec;
1056 wc.version = version;
18068523
GOC		 1057
1058 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1059
1060 version++;
1061 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1062}
1063
50d0a0f9
GH		 1064static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1065{
1066 uint32_t quotient, remainder;
1067
1068 /* Don't try to replace with do_div(), this one calculates
1069 * "(dividend << 32) / divisor" */
1070 __asm__ ( "divl %4"
1071 : "=a" (quotient), "=d" (remainder)
1072 : "0" (0), "1" (dividend), "r" (divisor) );
1073 return quotient;
1074}
1075
5f4e3f88
ZA		 1076static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1077 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1078{
5f4e3f88 1079 uint64_t scaled64;
50d0a0f9
GH		 1080 int32_t shift = 0;
1081 uint64_t tps64;
1082 uint32_t tps32;
1083
5f4e3f88
ZA		 1084 tps64 = base_khz * 1000LL;
1085 scaled64 = scaled_khz * 1000LL;
50933623 1086 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1087 tps64 >>= 1;
1088 shift--;
1089 }
1090
1091 tps32 = (uint32_t)tps64;
50933623
JK		 1092 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1093 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1094 scaled64 >>= 1;
1095 else
1096 tps32 <<= 1;
50d0a0f9
GH		 1097 shift++;
1098 }
1099
5f4e3f88
ZA		 1100 *pshift = shift;
1101 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1102
5f4e3f88
ZA		 1103 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1104 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1105}
1106
759379dd
ZA		 1107static inline u64 get_kernel_ns(void)
1108{
1109 struct timespec ts;
1110
759379dd
ZA		 1111 ktime_get_ts(&ts);
1112 monotonic_to_bootbased(&ts);
1113 return timespec_to_ns(&ts);
50d0a0f9
GH		 1114}
1115
d828199e 1116#ifdef CONFIG_X86_64
16e8d74d 1117static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1118#endif
16e8d74d 1119
c8076604 1120static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1121unsigned long max_tsc_khz;
c8076604 1122
cc578287 1123static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1124{
cc578287
ZA		 1125 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1126 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1127}
1128
cc578287 1129static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1130{
cc578287
ZA		 1131 u64 v = (u64)khz * (1000000 + ppm);
1132 do_div(v, 1000000);
1133 return v;
1e993611
JR		 1134}
1135
cc578287 1136static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1137{
cc578287
ZA		 1138 u32 thresh_lo, thresh_hi;
1139 int use_scaling = 0;
217fc9cf 1140
03ba32ca
MT		 1141 /* tsc_khz can be zero if TSC calibration fails */
1142 if (this_tsc_khz == 0)
1143 return;
1144
c285545f
ZA		 1145 /* Compute a scale to convert nanoseconds in TSC cycles */
1146 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1147 &vcpu->arch.virtual_tsc_shift,
1148 &vcpu->arch.virtual_tsc_mult);
1149 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1150
1151 /*
1152 * Compute the variation in TSC rate which is acceptable
1153 * within the range of tolerance and decide if the
1154 * rate being applied is within that bounds of the hardware
1155 * rate. If so, no scaling or compensation need be done.
1156 */
1157 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1158 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1159 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1160 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1161 use_scaling = 1;
1162 }
1163 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1164}
1165
1166static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1167{
e26101b1 1168 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1169 vcpu->arch.virtual_tsc_mult,
1170 vcpu->arch.virtual_tsc_shift);
e26101b1 1171 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1172 return tsc;
1173}
1174
b48aa97e
MT		 1175void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1176{
1177#ifdef CONFIG_X86_64
1178 bool vcpus_matched;
1179 bool do_request = false;
1180 struct kvm_arch *ka = &vcpu->kvm->arch;
1181 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1182
1183 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1184 atomic_read(&vcpu->kvm->online_vcpus));
1185
1186 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1187 if (!ka->use_master_clock)
1188 do_request = 1;
1189
1190 if (!vcpus_matched && ka->use_master_clock)
1191 do_request = 1;
1192
1193 if (do_request)
1194 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1195
1196 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1197 atomic_read(&vcpu->kvm->online_vcpus),
1198 ka->use_master_clock, gtod->clock.vclock_mode);
1199#endif
1200}
1201
ba904635
WA		 1202static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1203{
1204 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1205 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1206}
1207
8fe8ab46 1208void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1209{
1210 struct kvm *kvm = vcpu->kvm;
f38e098f 1211 u64 offset, ns, elapsed;
99e3e30a 1212 unsigned long flags;
02626b6a 1213 s64 usdiff;
b48aa97e 1214 bool matched;
8fe8ab46 1215 u64 data = msr->data;
99e3e30a 1216
038f8c11 1217 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1218 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1219 ns = get_kernel_ns();
f38e098f 1220 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1221
03ba32ca 1222 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1223 int faulted = 0;
1224
03ba32ca
MT		 1225 /* n.b - signed multiplication and division required */
1226 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1227#ifdef CONFIG_X86_64
03ba32ca 1228 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1229#else
03ba32ca 1230 /* do_div() only does unsigned */
8915aa27
MT		 1231 asm("1: idivl %[divisor]\n"
1232 "2: xor %%edx, %%edx\n"
1233 " movl $0, %[faulted]\n"
1234 "3:\n"
1235 ".section .fixup,\"ax\"\n"
1236 "4: movl $1, %[faulted]\n"
1237 " jmp 3b\n"
1238 ".previous\n"
1239
1240 _ASM_EXTABLE(1b, 4b)
1241
1242 : "=A"(usdiff), [faulted] "=r" (faulted)
1243 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1244
5d3cb0f6 1245#endif
03ba32ca
MT		 1246 do_div(elapsed, 1000);
1247 usdiff -= elapsed;
1248 if (usdiff < 0)
1249 usdiff = -usdiff;
8915aa27
MT		 1250
1251 /* idivl overflow => difference is larger than USEC_PER_SEC */
1252 if (faulted)
1253 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1254 } else
1255 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1256
1257 /*
5d3cb0f6
ZA		 1258 * Special case: TSC write with a small delta (1 second) of virtual
1259 * cycle time against real time is interpreted as an attempt to
1260 * synchronize the CPU.
1261 *
1262 * For a reliable TSC, we can match TSC offsets, and for an unstable
1263 * TSC, we add elapsed time in this computation. We could let the
1264 * compensation code attempt to catch up if we fall behind, but
1265 * it's better to try to match offsets from the beginning.
1266 */
02626b6a 1267 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1268 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1269 if (!check_tsc_unstable()) {
e26101b1 1270 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1271 pr_debug("kvm: matched tsc offset for %llu\n", data);
1272 } else {
857e4099 1273 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1274 data += delta;
1275 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1276 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1277 }
b48aa97e 1278 matched = true;
e26101b1
ZA		 1279 } else {
1280 /*
1281 * We split periods of matched TSC writes into generations.
1282 * For each generation, we track the original measured
1283 * nanosecond time, offset, and write, so if TSCs are in
1284 * sync, we can match exact offset, and if not, we can match
4a969980 1285 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1286 *
1287 * These values are tracked in kvm->arch.cur_xxx variables.
1288 */
1289 kvm->arch.cur_tsc_generation++;
1290 kvm->arch.cur_tsc_nsec = ns;
1291 kvm->arch.cur_tsc_write = data;
1292 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1293 matched = false;
e26101b1
ZA		 1294 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1295 kvm->arch.cur_tsc_generation, data);
f38e098f 1296 }
e26101b1
ZA		 1297
1298 /*
1299 * We also track th most recent recorded KHZ, write and time to
1300 * allow the matching interval to be extended at each write.
1301 */
f38e098f
ZA		 1302 kvm->arch.last_tsc_nsec = ns;
1303 kvm->arch.last_tsc_write = data;
5d3cb0f6 1304 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1305
b183aa58 1306 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1307
1308 /* Keep track of which generation this VCPU has synchronized to */
1309 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1310 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1311 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1312
ba904635
WA		 1313 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1314 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1315 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1316 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1317
1318 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1319 if (matched)
1320 kvm->arch.nr_vcpus_matched_tsc++;
1321 else
1322 kvm->arch.nr_vcpus_matched_tsc = 0;
1323
1324 kvm_track_tsc_matching(vcpu);
1325 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1326}
e26101b1 1327
99e3e30a
ZA		 1328EXPORT_SYMBOL_GPL(kvm_write_tsc);
1329
d828199e
MT		 1330#ifdef CONFIG_X86_64
1331
1332static cycle_t read_tsc(void)
1333{
1334 cycle_t ret;
1335 u64 last;
1336
1337 /*
1338 * Empirically, a fence (of type that depends on the CPU)
1339 * before rdtsc is enough to ensure that rdtsc is ordered
1340 * with respect to loads. The various CPU manuals are unclear
1341 * as to whether rdtsc can be reordered with later loads,
1342 * but no one has ever seen it happen.
1343 */
1344 rdtsc_barrier();
1345 ret = (cycle_t)vget_cycles();
1346
1347 last = pvclock_gtod_data.clock.cycle_last;
1348
1349 if (likely(ret >= last))
1350 return ret;
1351
1352 /*
1353 * GCC likes to generate cmov here, but this branch is extremely
1354 * predictable (it's just a funciton of time and the likely is
1355 * very likely) and there's a data dependence, so force GCC
1356 * to generate a branch instead. I don't barrier() because
1357 * we don't actually need a barrier, and if this function
1358 * ever gets inlined it will generate worse code.
1359 */
1360 asm volatile ("");
1361 return last;
1362}
1363
1364static inline u64 vgettsc(cycle_t *cycle_now)
1365{
1366 long v;
1367 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1368
1369 *cycle_now = read_tsc();
1370
1371 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1372 return v * gtod->clock.mult;
1373}
1374
1375static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1376{
1377 unsigned long seq;
1378 u64 ns;
1379 int mode;
1380 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1381
1382 ts->tv_nsec = 0;
1383 do {
1384 seq = read_seqcount_begin(&gtod->seq);
1385 mode = gtod->clock.vclock_mode;
1386 ts->tv_sec = gtod->monotonic_time_sec;
1387 ns = gtod->monotonic_time_snsec;
1388 ns += vgettsc(cycle_now);
1389 ns >>= gtod->clock.shift;
1390 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1391 timespec_add_ns(ts, ns);
1392
1393 return mode;
1394}
1395
1396/* returns true if host is using tsc clocksource */
1397static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1398{
1399 struct timespec ts;
1400
1401 /* checked again under seqlock below */
1402 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1403 return false;
1404
1405 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1406 return false;
1407
1408 monotonic_to_bootbased(&ts);
1409 *kernel_ns = timespec_to_ns(&ts);
1410
1411 return true;
1412}
1413#endif
1414
1415/*
1416 *
b48aa97e
MT		 1417 * Assuming a stable TSC across physical CPUS, and a stable TSC
1418 * across virtual CPUs, the following condition is possible.
1419 * Each numbered line represents an event visible to both
d828199e
MT		 1420 * CPUs at the next numbered event.
1421 *
1422 * "timespecX" represents host monotonic time. "tscX" represents
1423 * RDTSC value.
1424 *
1425 * VCPU0 on CPU0 | VCPU1 on CPU1
1426 *
1427 * 1. read timespec0,tsc0
1428 * 2. | timespec1 = timespec0 + N
1429 * | tsc1 = tsc0 + M
1430 * 3. transition to guest | transition to guest
1431 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1432 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1433 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1434 *
1435 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1436 *
1437 * - ret0 < ret1
1438 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1439 * ...
1440 * - 0 < N - M => M < N
1441 *
1442 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1443 * always the case (the difference between two distinct xtime instances
1444 * might be smaller then the difference between corresponding TSC reads,
1445 * when updating guest vcpus pvclock areas).
1446 *
1447 * To avoid that problem, do not allow visibility of distinct
1448 * system_timestamp/tsc_timestamp values simultaneously: use a master
1449 * copy of host monotonic time values. Update that master copy
1450 * in lockstep.
1451 *
b48aa97e 1452 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1453 *
1454 */
1455
1456static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1457{
1458#ifdef CONFIG_X86_64
1459 struct kvm_arch *ka = &kvm->arch;
1460 int vclock_mode;
b48aa97e
MT		 1461 bool host_tsc_clocksource, vcpus_matched;
1462
1463 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1464 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1465
1466 /*
1467 * If the host uses TSC clock, then passthrough TSC as stable
1468 * to the guest.
1469 */
b48aa97e 1470 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1471 &ka->master_kernel_ns,
1472 &ka->master_cycle_now);
1473
b48aa97e
MT		 1474 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1475
d828199e
MT		 1476 if (ka->use_master_clock)
1477 atomic_set(&kvm_guest_has_master_clock, 1);
1478
1479 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1480 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1481 vcpus_matched);
d828199e
MT		 1482#endif
1483}
1484
2e762ff7
MT		 1485static void kvm_gen_update_masterclock(struct kvm *kvm)
1486{
1487#ifdef CONFIG_X86_64
1488 int i;
1489 struct kvm_vcpu *vcpu;
1490 struct kvm_arch *ka = &kvm->arch;
1491
1492 spin_lock(&ka->pvclock_gtod_sync_lock);
1493 kvm_make_mclock_inprogress_request(kvm);
1494 /* no guest entries from this point */
1495 pvclock_update_vm_gtod_copy(kvm);
1496
1497 kvm_for_each_vcpu(i, vcpu, kvm)
1498 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1499
1500 /* guest entries allowed */
1501 kvm_for_each_vcpu(i, vcpu, kvm)
1502 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1503
1504 spin_unlock(&ka->pvclock_gtod_sync_lock);
1505#endif
1506}
1507
34c238a1 1508static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1509{
d828199e 1510 unsigned long flags, this_tsc_khz;
18068523 1511 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1512 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1513 s64 kernel_ns;
d828199e 1514 u64 tsc_timestamp, host_tsc;
0b79459b 1515 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1516 u8 pvclock_flags;
d828199e
MT		 1517 bool use_master_clock;
1518
1519 kernel_ns = 0;
1520 host_tsc = 0;
18068523 1521
d828199e
MT		 1522 /*
1523 * If the host uses TSC clock, then passthrough TSC as stable
1524 * to the guest.
1525 */
1526 spin_lock(&ka->pvclock_gtod_sync_lock);
1527 use_master_clock = ka->use_master_clock;
1528 if (use_master_clock) {
1529 host_tsc = ka->master_cycle_now;
1530 kernel_ns = ka->master_kernel_ns;
1531 }
1532 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1533
1534 /* Keep irq disabled to prevent changes to the clock */
1535 local_irq_save(flags);
1536 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1537 if (unlikely(this_tsc_khz == 0)) {
1538 local_irq_restore(flags);
1539 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1540 return 1;
1541 }
d828199e
MT		 1542 if (!use_master_clock) {
1543 host_tsc = native_read_tsc();
1544 kernel_ns = get_kernel_ns();
1545 }
1546
1547 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1548
c285545f
ZA		 1549 /*
1550 * We may have to catch up the TSC to match elapsed wall clock
1551 * time for two reasons, even if kvmclock is used.
1552 * 1) CPU could have been running below the maximum TSC rate
1553 * 2) Broken TSC compensation resets the base at each VCPU
1554 * entry to avoid unknown leaps of TSC even when running
1555 * again on the same CPU. This may cause apparent elapsed
1556 * time to disappear, and the guest to stand still or run
1557 * very slowly.
1558 */
1559 if (vcpu->tsc_catchup) {
1560 u64 tsc = compute_guest_tsc(v, kernel_ns);
1561 if (tsc > tsc_timestamp) {
f1e2b260 1562 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1563 tsc_timestamp = tsc;
1564 }
50d0a0f9
GH		 1565 }
1566
18068523
GOC		 1567 local_irq_restore(flags);
1568
0b79459b 1569 if (!vcpu->pv_time_enabled)
c285545f 1570 return 0;
18068523 1571
e48672fa 1572 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1573 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1574 &vcpu->hv_clock.tsc_shift,
1575 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1576 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1577 }
1578
1579 /* With all the info we got, fill in the values */
1d5f066e 1580 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1581 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1582 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1583
18068523
GOC		 1584 /*
1585 * The interface expects us to write an even number signaling that the
1586 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1587 * state, we just increase by 2 at the end.
18068523 1588 */
50d0a0f9 1589 vcpu->hv_clock.version += 2;
18068523 1590
0b79459b
AH		 1591 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1592 &guest_hv_clock, sizeof(guest_hv_clock))))
1593 return 0;
78c0337a
MT		 1594
1595 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1596 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1597
1598 if (vcpu->pvclock_set_guest_stopped_request) {
1599 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1600 vcpu->pvclock_set_guest_stopped_request = false;
1601 }
1602
d828199e
MT		 1603 /* If the host uses TSC clocksource, then it is stable */
1604 if (use_master_clock)
1605 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1606
78c0337a
MT		 1607 vcpu->hv_clock.flags = pvclock_flags;
1608
0b79459b
AH		 1609 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1610 &vcpu->hv_clock,
1611 sizeof(vcpu->hv_clock));
8cfdc000 1612 return 0;
c8076604
GH		 1613}
1614
0061d53d
MT		 1615/*
1616 * kvmclock updates which are isolated to a given vcpu, such as
1617 * vcpu->cpu migration, should not allow system_timestamp from
1618 * the rest of the vcpus to remain static. Otherwise ntp frequency
1619 * correction applies to one vcpu's system_timestamp but not
1620 * the others.
1621 *
1622 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1623 * We need to rate-limit these requests though, as they can
1624 * considerably slow guests that have a large number of vcpus.
1625 * The time for a remote vcpu to update its kvmclock is bound
1626 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1627 */
1628
7e44e449
AJ		 1629#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1630
1631static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1632{
1633 int i;
7e44e449
AJ		 1634 struct delayed_work *dwork = to_delayed_work(work);
1635 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1636 kvmclock_update_work);
1637 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1638 struct kvm_vcpu *vcpu;
1639
1640 kvm_for_each_vcpu(i, vcpu, kvm) {
1641 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1642 kvm_vcpu_kick(vcpu);
1643 }
1644}
1645
7e44e449
AJ		 1646static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1647{
1648 struct kvm *kvm = v->kvm;
1649
1650 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1651 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1652 KVMCLOCK_UPDATE_DELAY);
1653}
1654
332967a3
AJ		 1655#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1656
1657static void kvmclock_sync_fn(struct work_struct *work)
1658{
1659 struct delayed_work *dwork = to_delayed_work(work);
1660 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1661 kvmclock_sync_work);
1662 struct kvm *kvm = container_of(ka, struct kvm, arch);
1663
1664 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1665 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1666 KVMCLOCK_SYNC_PERIOD);
1667}
1668
9ba075a6
AK		 1669static bool msr_mtrr_valid(unsigned msr)
1670{
1671 switch (msr) {
1672 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1673 case MSR_MTRRfix64K_00000:
1674 case MSR_MTRRfix16K_80000:
1675 case MSR_MTRRfix16K_A0000:
1676 case MSR_MTRRfix4K_C0000:
1677 case MSR_MTRRfix4K_C8000:
1678 case MSR_MTRRfix4K_D0000:
1679 case MSR_MTRRfix4K_D8000:
1680 case MSR_MTRRfix4K_E0000:
1681 case MSR_MTRRfix4K_E8000:
1682 case MSR_MTRRfix4K_F0000:
1683 case MSR_MTRRfix4K_F8000:
1684 case MSR_MTRRdefType:
1685 case MSR_IA32_CR_PAT:
1686 return true;
1687 case 0x2f8:
1688 return true;
1689 }
1690 return false;
1691}
1692
d6289b93
MT		 1693static bool valid_pat_type(unsigned t)
1694{
1695 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1696}
1697
1698static bool valid_mtrr_type(unsigned t)
1699{
1700 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1701}
1702
1703static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1704{
1705 int i;
1706
1707 if (!msr_mtrr_valid(msr))
1708 return false;
1709
1710 if (msr == MSR_IA32_CR_PAT) {
1711 for (i = 0; i < 8; i++)
1712 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1713 return false;
1714 return true;
1715 } else if (msr == MSR_MTRRdefType) {
1716 if (data & ~0xcff)
1717 return false;
1718 return valid_mtrr_type(data & 0xff);
1719 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1720 for (i = 0; i < 8 ; i++)
1721 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1722 return false;
1723 return true;
1724 }
1725
1726 /* variable MTRRs */
1727 return valid_mtrr_type(data & 0xff);
1728}
1729
9ba075a6
AK		 1730static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1731{
0bed3b56
SY		 1732 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1733
d6289b93 1734 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1735 return 1;
1736
0bed3b56
SY		 1737 if (msr == MSR_MTRRdefType) {
1738 vcpu->arch.mtrr_state.def_type = data;
1739 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1740 } else if (msr == MSR_MTRRfix64K_00000)
1741 p[0] = data;
1742 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1743 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1744 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1745 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1746 else if (msr == MSR_IA32_CR_PAT)
1747 vcpu->arch.pat = data;
1748 else { /* Variable MTRRs */
1749 int idx, is_mtrr_mask;
1750 u64 *pt;
1751
1752 idx = (msr - 0x200) / 2;
1753 is_mtrr_mask = msr - 0x200 - 2 * idx;
1754 if (!is_mtrr_mask)
1755 pt =
1756 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1757 else
1758 pt =
1759 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1760 *pt = data;
1761 }
1762
1763 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1764 return 0;
1765}
15c4a640 1766
890ca9ae 1767static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1768{
890ca9ae
YH		 1769 u64 mcg_cap = vcpu->arch.mcg_cap;
1770 unsigned bank_num = mcg_cap & 0xff;
1771
15c4a640 1772 switch (msr) {
15c4a640 1773 case MSR_IA32_MCG_STATUS:
890ca9ae 1774 vcpu->arch.mcg_status = data;
15c4a640 1775 break;
c7ac679c 1776 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 1777 if (!(mcg_cap & MCG_CTL_P))
1778 return 1;
1779 if (data != 0 && data != ~(u64)0)
1780 return -1;
1781 vcpu->arch.mcg_ctl = data;
1782 break;
1783 default:
1784 if (msr >= MSR_IA32_MC0_CTL &&
1785 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1786 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1787 /* only 0 or all 1s can be written to IA32_MCi_CTL
1788 * some Linux kernels though clear bit 10 in bank 4 to
1789 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1790 * this to avoid an uncatched #GP in the guest
1791 */
890ca9ae 1792 if ((offset & 0x3) == 0 &&
114be429 1793 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
YH		 1794 return -1;
1795 vcpu->arch.mce_banks[offset] = data;
1796 break;
1797 }
1798 return 1;
1799 }
1800 return 0;
1801}
1802
ffde22ac
ES		 1803static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1804{
1805 struct kvm *kvm = vcpu->kvm;
1806 int lm = is_long_mode(vcpu);
1807 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1808 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1809 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1810 : kvm->arch.xen_hvm_config.blob_size_32;
1811 u32 page_num = data & ~PAGE_MASK;
1812 u64 page_addr = data & PAGE_MASK;
1813 u8 *page;
1814 int r;
1815
1816 r = -E2BIG;
1817 if (page_num >= blob_size)
1818 goto out;
1819 r = -ENOMEM;
ff5c2c03
SL		 1820 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1821 if (IS_ERR(page)) {
1822 r = PTR_ERR(page);
ffde22ac 1823 goto out;
ff5c2c03 1824 }
ffde22ac
ES		 1825 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1826 goto out_free;
1827 r = 0;
1828out_free:
1829 kfree(page);
1830out:
1831 return r;
1832}
1833
55cd8e5a
GN		 1834static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1835{
1836 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1837}
1838
1839static bool kvm_hv_msr_partition_wide(u32 msr)
1840{
1841 bool r = false;
1842 switch (msr) {
1843 case HV_X64_MSR_GUEST_OS_ID:
1844 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1845 case HV_X64_MSR_REFERENCE_TSC:
1846 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1847 r = true;
1848 break;
1849 }
1850
1851 return r;
1852}
1853
1854static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1855{
1856 struct kvm *kvm = vcpu->kvm;
1857
1858 switch (msr) {
1859 case HV_X64_MSR_GUEST_OS_ID:
1860 kvm->arch.hv_guest_os_id = data;
1861 /* setting guest os id to zero disables hypercall page */
1862 if (!kvm->arch.hv_guest_os_id)
1863 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1864 break;
1865 case HV_X64_MSR_HYPERCALL: {
1866 u64 gfn;
1867 unsigned long addr;
1868 u8 instructions[4];
1869
1870 /* if guest os id is not set hypercall should remain disabled */
1871 if (!kvm->arch.hv_guest_os_id)
1872 break;
1873 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1874 kvm->arch.hv_hypercall = data;
1875 break;
1876 }
1877 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1878 addr = gfn_to_hva(kvm, gfn);
1879 if (kvm_is_error_hva(addr))
1880 return 1;
1881 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1882 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1883 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1884 return 1;
1885 kvm->arch.hv_hypercall = data;
b94b64c9 1886 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1887 break;
1888 }
e984097b
VR		 1889 case HV_X64_MSR_REFERENCE_TSC: {
1890 u64 gfn;
1891 HV_REFERENCE_TSC_PAGE tsc_ref;
1892 memset(&tsc_ref, 0, sizeof(tsc_ref));
1893 kvm->arch.hv_tsc_page = data;
1894 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1895 break;
1896 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1897 if (kvm_write_guest(kvm, data,
1898 &tsc_ref, sizeof(tsc_ref)))
1899 return 1;
1900 mark_page_dirty(kvm, gfn);
1901 break;
1902 }
55cd8e5a 1903 default:
a737f256
CD		 1904 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1905 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1906 return 1;
1907 }
1908 return 0;
1909}
1910
1911static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1912{
10388a07
GN		 1913 switch (msr) {
1914 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1915 u64 gfn;
10388a07 1916 unsigned long addr;
55cd8e5a 1917
10388a07
GN		 1918 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1919 vcpu->arch.hv_vapic = data;
1920 break;
1921 }
b3af1e88
VR		 1922 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1923 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1924 if (kvm_is_error_hva(addr))
1925 return 1;
8b0cedff 1926 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1927 return 1;
1928 vcpu->arch.hv_vapic = data;
b3af1e88 1929 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1930 break;
1931 }
1932 case HV_X64_MSR_EOI:
1933 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1934 case HV_X64_MSR_ICR:
1935 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1936 case HV_X64_MSR_TPR:
1937 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1938 default:
a737f256
CD		 1939 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1940 "data 0x%llx\n", msr, data);
10388a07
GN		 1941 return 1;
1942 }
1943
1944 return 0;
55cd8e5a
GN		 1945}
1946
344d9588
GN		 1947static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1948{
1949 gpa_t gpa = data & ~0x3f;
1950
4a969980 1951 /* Bits 2:5 are reserved, Should be zero */
6adba527 1952 if (data & 0x3c)
344d9588
GN		 1953 return 1;
1954
1955 vcpu->arch.apf.msr_val = data;
1956
1957 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1958 kvm_clear_async_pf_completion_queue(vcpu);
1959 kvm_async_pf_hash_reset(vcpu);
1960 return 0;
1961 }
1962
8f964525
AH		 1963 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1964 sizeof(u32)))
344d9588
GN		 1965 return 1;
1966
6adba527 1967 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1968 kvm_async_pf_wakeup_all(vcpu);
1969 return 0;
1970}
1971
12f9a48f
GC		 1972static void kvmclock_reset(struct kvm_vcpu *vcpu)
1973{
0b79459b 1974 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1975}
1976
c9aaa895
GC		 1977static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1978{
1979 u64 delta;
1980
1981 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1982 return;
1983
1984 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1985 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1986 vcpu->arch.st.accum_steal = delta;
1987}
1988
1989static void record_steal_time(struct kvm_vcpu *vcpu)
1990{
1991 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1992 return;
1993
1994 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1995 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1996 return;
1997
1998 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1999 vcpu->arch.st.steal.version += 2;
2000 vcpu->arch.st.accum_steal = 0;
2001
2002 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2003 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2004}
2005
8fe8ab46 2006int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2007{
5753785f 2008 bool pr = false;
8fe8ab46
WA		 2009 u32 msr = msr_info->index;
2010 u64 data = msr_info->data;
5753785f 2011
15c4a640 2012 switch (msr) {
2e32b719
BP		 2013 case MSR_AMD64_NB_CFG:
2014 case MSR_IA32_UCODE_REV:
2015 case MSR_IA32_UCODE_WRITE:
2016 case MSR_VM_HSAVE_PA:
2017 case MSR_AMD64_PATCH_LOADER:
2018 case MSR_AMD64_BU_CFG2:
2019 break;
2020
15c4a640 2021 case MSR_EFER:
b69e8cae 2022 return set_efer(vcpu, data);
8f1589d9
AP		 2023 case MSR_K7_HWCR:
2024 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2025 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2026 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2027 if (data != 0) {
a737f256
CD		 2028 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2029 data);
8f1589d9
AP		 2030 return 1;
2031 }
15c4a640 2032 break;
f7c6d140
AP		 2033 case MSR_FAM10H_MMIO_CONF_BASE:
2034 if (data != 0) {
a737f256
CD		 2035 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2036 "0x%llx\n", data);
f7c6d140
AP		 2037 return 1;
2038 }
15c4a640 2039 break;
b5e2fec0
AG		 2040 case MSR_IA32_DEBUGCTLMSR:
2041 if (!data) {
2042 /* We support the non-activated case already */
2043 break;
2044 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2045 /* Values other than LBR and BTF are vendor-specific,
2046 thus reserved and should throw a #GP */
2047 return 1;
2048 }
a737f256
CD		 2049 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2050 __func__, data);
b5e2fec0 2051 break;
9ba075a6
AK		 2052 case 0x200 ... 0x2ff:
2053 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2054 case MSR_IA32_APICBASE:
58cb628d 2055 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2056 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2057 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2058 case MSR_IA32_TSCDEADLINE:
2059 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2060 break;
ba904635
WA		 2061 case MSR_IA32_TSC_ADJUST:
2062 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2063 if (!msr_info->host_initiated) {
2064 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2065 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2066 }
2067 vcpu->arch.ia32_tsc_adjust_msr = data;
2068 }
2069 break;
15c4a640 2070 case MSR_IA32_MISC_ENABLE:
ad312c7c 2071 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2072 break;
11c6bffa 2073 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2074 case MSR_KVM_WALL_CLOCK:
2075 vcpu->kvm->arch.wall_clock = data;
2076 kvm_write_wall_clock(vcpu->kvm, data);
2077 break;
11c6bffa 2078 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2079 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2080 u64 gpa_offset;
12f9a48f 2081 kvmclock_reset(vcpu);
18068523
GOC		 2082
2083 vcpu->arch.time = data;
0061d53d 2084 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2085
2086 /* we verify if the enable bit is set... */
2087 if (!(data & 1))
2088 break;
2089
0b79459b 2090 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2091
0b79459b 2092 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2093 &vcpu->arch.pv_time, data & ~1ULL,
2094 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2095 vcpu->arch.pv_time_enabled = false;
2096 else
2097 vcpu->arch.pv_time_enabled = true;
32cad84f 2098
18068523
GOC		 2099 break;
2100 }
344d9588
GN		 2101 case MSR_KVM_ASYNC_PF_EN:
2102 if (kvm_pv_enable_async_pf(vcpu, data))
2103 return 1;
2104 break;
c9aaa895
GC		 2105 case MSR_KVM_STEAL_TIME:
2106
2107 if (unlikely(!sched_info_on()))
2108 return 1;
2109
2110 if (data & KVM_STEAL_RESERVED_MASK)
2111 return 1;
2112
2113 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2114 data & KVM_STEAL_VALID_BITS,
2115 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2116 return 1;
2117
2118 vcpu->arch.st.msr_val = data;
2119
2120 if (!(data & KVM_MSR_ENABLED))
2121 break;
2122
2123 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2124
2125 preempt_disable();
2126 accumulate_steal_time(vcpu);
2127 preempt_enable();
2128
2129 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2130
2131 break;
ae7a2a3f
MT		 2132 case MSR_KVM_PV_EOI_EN:
2133 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2134 return 1;
2135 break;
c9aaa895 2136
890ca9ae
YH		 2137 case MSR_IA32_MCG_CTL:
2138 case MSR_IA32_MCG_STATUS:
2139 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2140 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2141
2142 /* Performance counters are not protected by a CPUID bit,
2143 * so we should check all of them in the generic path for the sake of
2144 * cross vendor migration.
2145 * Writing a zero into the event select MSRs disables them,
2146 * which we perfectly emulate ;-). Any other value should be at least
2147 * reported, some guests depend on them.
2148 */
71db6023
AP		 2149 case MSR_K7_EVNTSEL0:
2150 case MSR_K7_EVNTSEL1:
2151 case MSR_K7_EVNTSEL2:
2152 case MSR_K7_EVNTSEL3:
2153 if (data != 0)
a737f256
CD		 2154 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2155 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2156 break;
2157 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2158 * so we ignore writes to make it happy.
2159 */
71db6023
AP		 2160 case MSR_K7_PERFCTR0:
2161 case MSR_K7_PERFCTR1:
2162 case MSR_K7_PERFCTR2:
2163 case MSR_K7_PERFCTR3:
a737f256
CD		 2164 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2165 "0x%x data 0x%llx\n", msr, data);
71db6023 2166 break;
5753785f
GN		 2167 case MSR_P6_PERFCTR0:
2168 case MSR_P6_PERFCTR1:
2169 pr = true;
2170 case MSR_P6_EVNTSEL0:
2171 case MSR_P6_EVNTSEL1:
2172 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2173 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2174
2175 if (pr || data != 0)
a737f256
CD		 2176 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2177 "0x%x data 0x%llx\n", msr, data);
5753785f 2178 break;
84e0cefa
JS		 2179 case MSR_K7_CLK_CTL:
2180 /*
2181 * Ignore all writes to this no longer documented MSR.
2182 * Writes are only relevant for old K7 processors,
2183 * all pre-dating SVM, but a recommended workaround from
4a969980 2184 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2185 * affected processor models on the command line, hence
2186 * the need to ignore the workaround.
2187 */
2188 break;
55cd8e5a
GN		 2189 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2190 if (kvm_hv_msr_partition_wide(msr)) {
2191 int r;
2192 mutex_lock(&vcpu->kvm->lock);
2193 r = set_msr_hyperv_pw(vcpu, msr, data);
2194 mutex_unlock(&vcpu->kvm->lock);
2195 return r;
2196 } else
2197 return set_msr_hyperv(vcpu, msr, data);
2198 break;
91c9c3ed 2199 case MSR_IA32_BBL_CR_CTL3:
2200 /* Drop writes to this legacy MSR -- see rdmsr
2201 * counterpart for further detail.
2202 */
a737f256 2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2204 break;
2b036c6b
BO		 2205 case MSR_AMD64_OSVW_ID_LENGTH:
2206 if (!guest_cpuid_has_osvw(vcpu))
2207 return 1;
2208 vcpu->arch.osvw.length = data;
2209 break;
2210 case MSR_AMD64_OSVW_STATUS:
2211 if (!guest_cpuid_has_osvw(vcpu))
2212 return 1;
2213 vcpu->arch.osvw.status = data;
2214 break;
15c4a640 2215 default:
ffde22ac
ES		 2216 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2217 return xen_hvm_config(vcpu, data);
f5132b01 2218 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2219 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2220 if (!ignore_msrs) {
a737f256
CD		 2221 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2222 msr, data);
ed85c068
AP		 2223 return 1;
2224 } else {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2226 msr, data);
ed85c068
AP		 2227 break;
2228 }
15c4a640
CO		 2229 }
2230 return 0;
2231}
2232EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2233
2234
2235/*
2236 * Reads an msr value (of 'msr_index') into 'pdata'.
2237 * Returns 0 on success, non-0 otherwise.
2238 * Assumes vcpu_load() was already called.
2239 */
2240int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2241{
2242 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2243}
2244
9ba075a6
AK		 2245static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2246{
0bed3b56
SY		 2247 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2248
9ba075a6
AK		 2249 if (!msr_mtrr_valid(msr))
2250 return 1;
2251
0bed3b56
SY		 2252 if (msr == MSR_MTRRdefType)
2253 *pdata = vcpu->arch.mtrr_state.def_type +
2254 (vcpu->arch.mtrr_state.enabled << 10);
2255 else if (msr == MSR_MTRRfix64K_00000)
2256 *pdata = p[0];
2257 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2258 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2259 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2260 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2261 else if (msr == MSR_IA32_CR_PAT)
2262 *pdata = vcpu->arch.pat;
2263 else { /* Variable MTRRs */
2264 int idx, is_mtrr_mask;
2265 u64 *pt;
2266
2267 idx = (msr - 0x200) / 2;
2268 is_mtrr_mask = msr - 0x200 - 2 * idx;
2269 if (!is_mtrr_mask)
2270 pt =
2271 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2272 else
2273 pt =
2274 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2275 *pdata = *pt;
2276 }
2277
9ba075a6
AK		 2278 return 0;
2279}
2280
890ca9ae 2281static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2282{
2283 u64 data;
890ca9ae
YH		 2284 u64 mcg_cap = vcpu->arch.mcg_cap;
2285 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2286
2287 switch (msr) {
15c4a640
CO		 2288 case MSR_IA32_P5_MC_ADDR:
2289 case MSR_IA32_P5_MC_TYPE:
890ca9ae
YH		 2290 data = 0;
2291 break;
15c4a640 2292 case MSR_IA32_MCG_CAP:
890ca9ae
YH		 2293 data = vcpu->arch.mcg_cap;
2294 break;
c7ac679c 2295 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 2296 if (!(mcg_cap & MCG_CTL_P))
2297 return 1;
2298 data = vcpu->arch.mcg_ctl;
2299 break;
2300 case MSR_IA32_MCG_STATUS:
2301 data = vcpu->arch.mcg_status;
2302 break;
2303 default:
2304 if (msr >= MSR_IA32_MC0_CTL &&
2305 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2306 u32 offset = msr - MSR_IA32_MC0_CTL;
2307 data = vcpu->arch.mce_banks[offset];
2308 break;
2309 }
2310 return 1;
2311 }
2312 *pdata = data;
2313 return 0;
2314}
2315
55cd8e5a
GN		 2316static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2317{
2318 u64 data = 0;
2319 struct kvm *kvm = vcpu->kvm;
2320
2321 switch (msr) {
2322 case HV_X64_MSR_GUEST_OS_ID:
2323 data = kvm->arch.hv_guest_os_id;
2324 break;
2325 case HV_X64_MSR_HYPERCALL:
2326 data = kvm->arch.hv_hypercall;
2327 break;
e984097b
VR		 2328 case HV_X64_MSR_TIME_REF_COUNT: {
2329 data =
2330 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2331 break;
2332 }
2333 case HV_X64_MSR_REFERENCE_TSC:
2334 data = kvm->arch.hv_tsc_page;
2335 break;
55cd8e5a 2336 default:
a737f256 2337 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2338 return 1;
2339 }
2340
2341 *pdata = data;
2342 return 0;
2343}
2344
2345static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2346{
2347 u64 data = 0;
2348
2349 switch (msr) {
2350 case HV_X64_MSR_VP_INDEX: {
2351 int r;
2352 struct kvm_vcpu *v;
684851a1
TY		 2353 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2354 if (v == vcpu) {
55cd8e5a 2355 data = r;
684851a1
TY		 2356 break;
2357 }
2358 }
55cd8e5a
GN		 2359 break;
2360 }
10388a07
GN		 2361 case HV_X64_MSR_EOI:
2362 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2363 case HV_X64_MSR_ICR:
2364 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2365 case HV_X64_MSR_TPR:
2366 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2367 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2368 data = vcpu->arch.hv_vapic;
2369 break;
55cd8e5a 2370 default:
a737f256 2371 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2372 return 1;
2373 }
2374 *pdata = data;
2375 return 0;
2376}
2377
890ca9ae
YH		 2378int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2379{
2380 u64 data;
2381
2382 switch (msr) {
890ca9ae 2383 case MSR_IA32_PLATFORM_ID:
15c4a640 2384 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2385 case MSR_IA32_DEBUGCTLMSR:
2386 case MSR_IA32_LASTBRANCHFROMIP:
2387 case MSR_IA32_LASTBRANCHTOIP:
2388 case MSR_IA32_LASTINTFROMIP:
2389 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2390 case MSR_K8_SYSCFG:
2391 case MSR_K7_HWCR:
61a6bd67 2392 case MSR_VM_HSAVE_PA:
9e699624 2393 case MSR_K7_EVNTSEL0:
1f3ee616 2394 case MSR_K7_PERFCTR0:
1fdbd48c 2395 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2396 case MSR_AMD64_NB_CFG:
f7c6d140 2397 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2398 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2399 data = 0;
2400 break;
5753785f
GN		 2401 case MSR_P6_PERFCTR0:
2402 case MSR_P6_PERFCTR1:
2403 case MSR_P6_EVNTSEL0:
2404 case MSR_P6_EVNTSEL1:
2405 if (kvm_pmu_msr(vcpu, msr))
2406 return kvm_pmu_get_msr(vcpu, msr, pdata);
2407 data = 0;
2408 break;
742bc670
MT		 2409 case MSR_IA32_UCODE_REV:
2410 data = 0x100000000ULL;
2411 break;
9ba075a6
AK		 2412 case MSR_MTRRcap:
2413 data = 0x500 | KVM_NR_VAR_MTRR;
2414 break;
2415 case 0x200 ... 0x2ff:
2416 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2417 case 0xcd: /* fsb frequency */
2418 data = 3;
2419 break;
7b914098
JS		 2420 /*
2421 * MSR_EBC_FREQUENCY_ID
2422 * Conservative value valid for even the basic CPU models.
2423 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2424 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2425 * and 266MHz for model 3, or 4. Set Core Clock
2426 * Frequency to System Bus Frequency Ratio to 1 (bits
2427 * 31:24) even though these are only valid for CPU
2428 * models > 2, however guests may end up dividing or
2429 * multiplying by zero otherwise.
2430 */
2431 case MSR_EBC_FREQUENCY_ID:
2432 data = 1 << 24;
2433 break;
15c4a640
CO		 2434 case MSR_IA32_APICBASE:
2435 data = kvm_get_apic_base(vcpu);
2436 break;
0105d1a5
GN		 2437 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2438 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2439 break;
a3e06bbe
LJ		 2440 case MSR_IA32_TSCDEADLINE:
2441 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2442 break;
ba904635
WA		 2443 case MSR_IA32_TSC_ADJUST:
2444 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2445 break;
15c4a640 2446 case MSR_IA32_MISC_ENABLE:
ad312c7c 2447 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2448 break;
847f0ad8
AG		 2449 case MSR_IA32_PERF_STATUS:
2450 /* TSC increment by tick */
2451 data = 1000ULL;
2452 /* CPU multiplier */
2453 data |= (((uint64_t)4ULL) << 40);
2454 break;
15c4a640 2455 case MSR_EFER:
f6801dff 2456 data = vcpu->arch.efer;
15c4a640 2457 break;
18068523 2458 case MSR_KVM_WALL_CLOCK:
11c6bffa 2459 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2460 data = vcpu->kvm->arch.wall_clock;
2461 break;
2462 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2463 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2464 data = vcpu->arch.time;
2465 break;
344d9588
GN		 2466 case MSR_KVM_ASYNC_PF_EN:
2467 data = vcpu->arch.apf.msr_val;
2468 break;
c9aaa895
GC		 2469 case MSR_KVM_STEAL_TIME:
2470 data = vcpu->arch.st.msr_val;
2471 break;
1d92128f
MT		 2472 case MSR_KVM_PV_EOI_EN:
2473 data = vcpu->arch.pv_eoi.msr_val;
2474 break;
890ca9ae
YH		 2475 case MSR_IA32_P5_MC_ADDR:
2476 case MSR_IA32_P5_MC_TYPE:
2477 case MSR_IA32_MCG_CAP:
2478 case MSR_IA32_MCG_CTL:
2479 case MSR_IA32_MCG_STATUS:
2480 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2481 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2482 case MSR_K7_CLK_CTL:
2483 /*
2484 * Provide expected ramp-up count for K7. All other
2485 * are set to zero, indicating minimum divisors for
2486 * every field.
2487 *
2488 * This prevents guest kernels on AMD host with CPU
2489 * type 6, model 8 and higher from exploding due to
2490 * the rdmsr failing.
2491 */
2492 data = 0x20000000;
2493 break;
55cd8e5a
GN		 2494 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2495 if (kvm_hv_msr_partition_wide(msr)) {
2496 int r;
2497 mutex_lock(&vcpu->kvm->lock);
2498 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2499 mutex_unlock(&vcpu->kvm->lock);
2500 return r;
2501 } else
2502 return get_msr_hyperv(vcpu, msr, pdata);
2503 break;
91c9c3ed 2504 case MSR_IA32_BBL_CR_CTL3:
2505 /* This legacy MSR exists but isn't fully documented in current
2506 * silicon. It is however accessed by winxp in very narrow
2507 * scenarios where it sets bit #19, itself documented as
2508 * a "reserved" bit. Best effort attempt to source coherent
2509 * read data here should the balance of the register be
2510 * interpreted by the guest:
2511 *
2512 * L2 cache control register 3: 64GB range, 256KB size,
2513 * enabled, latency 0x1, configured
2514 */
2515 data = 0xbe702111;
2516 break;
2b036c6b
BO		 2517 case MSR_AMD64_OSVW_ID_LENGTH:
2518 if (!guest_cpuid_has_osvw(vcpu))
2519 return 1;
2520 data = vcpu->arch.osvw.length;
2521 break;
2522 case MSR_AMD64_OSVW_STATUS:
2523 if (!guest_cpuid_has_osvw(vcpu))
2524 return 1;
2525 data = vcpu->arch.osvw.status;
2526 break;
15c4a640 2527 default:
f5132b01
GN		 2528 if (kvm_pmu_msr(vcpu, msr))
2529 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2530 if (!ignore_msrs) {
a737f256 2531 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2532 return 1;
2533 } else {
a737f256 2534 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2535 data = 0;
2536 }
2537 break;
15c4a640
CO		 2538 }
2539 *pdata = data;
2540 return 0;
2541}
2542EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2543
313a3dc7
CO		 2544/*
2545 * Read or write a bunch of msrs. All parameters are kernel addresses.
2546 *
2547 * @return number of msrs set successfully.
2548 */
2549static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2550 struct kvm_msr_entry *entries,
2551 int (*do_msr)(struct kvm_vcpu *vcpu,
2552 unsigned index, u64 *data))
2553{
f656ce01 2554 int i, idx;
313a3dc7 2555
f656ce01 2556 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2557 for (i = 0; i < msrs->nmsrs; ++i)
2558 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2559 break;
f656ce01 2560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2561
313a3dc7
CO		 2562 return i;
2563}
2564
2565/*
2566 * Read or write a bunch of msrs. Parameters are user addresses.
2567 *
2568 * @return number of msrs set successfully.
2569 */
2570static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2571 int (*do_msr)(struct kvm_vcpu *vcpu,
2572 unsigned index, u64 *data),
2573 int writeback)
2574{
2575 struct kvm_msrs msrs;
2576 struct kvm_msr_entry *entries;
2577 int r, n;
2578 unsigned size;
2579
2580 r = -EFAULT;
2581 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2582 goto out;
2583
2584 r = -E2BIG;
2585 if (msrs.nmsrs >= MAX_IO_MSRS)
2586 goto out;
2587
313a3dc7 2588 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2589 entries = memdup_user(user_msrs->entries, size);
2590 if (IS_ERR(entries)) {
2591 r = PTR_ERR(entries);
313a3dc7 2592 goto out;
ff5c2c03 2593 }
313a3dc7
CO		 2594
2595 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2596 if (r < 0)
2597 goto out_free;
2598
2599 r = -EFAULT;
2600 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2601 goto out_free;
2602
2603 r = n;
2604
2605out_free:
7a73c028 2606 kfree(entries);
313a3dc7
CO		 2607out:
2608 return r;
2609}
2610
018d00d2
ZX		 2611int kvm_dev_ioctl_check_extension(long ext)
2612{
2613 int r;
2614
2615 switch (ext) {
2616 case KVM_CAP_IRQCHIP:
2617 case KVM_CAP_HLT:
2618 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2619 case KVM_CAP_SET_TSS_ADDR:
07716717 2620 case KVM_CAP_EXT_CPUID:
9c15bb1d 2621 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2622 case KVM_CAP_CLOCKSOURCE:
7837699f 2623 case KVM_CAP_PIT:
a28e4f5a 2624 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2625 case KVM_CAP_MP_STATE:
ed848624 2626 case KVM_CAP_SYNC_MMU:
a355c85c 2627 case KVM_CAP_USER_NMI:
52d939a0 2628 case KVM_CAP_REINJECT_CONTROL:
4925663a 2629 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2630 case KVM_CAP_IRQFD:
d34e6b17 2631 case KVM_CAP_IOEVENTFD:
f848a5a8 2632 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2633 case KVM_CAP_PIT2:
e9f42757 2634 case KVM_CAP_PIT_STATE2:
b927a3ce 2635 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2636 case KVM_CAP_XEN_HVM:
afbcf7ab 2637 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2638 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2639 case KVM_CAP_HYPERV:
10388a07 2640 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2641 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2642 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2643 case KVM_CAP_DEBUGREGS:
d2be1651 2644 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2645 case KVM_CAP_XSAVE:
344d9588 2646 case KVM_CAP_ASYNC_PF:
92a1f12d 2647 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2648 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2649 case KVM_CAP_READONLY_MEM:
5f66b620 2650 case KVM_CAP_HYPERV_TIME:
100943c5 2651 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2652#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2653 case KVM_CAP_ASSIGN_DEV_IRQ:
2654 case KVM_CAP_PCI_2_3:
2655#endif
018d00d2
ZX		 2656 r = 1;
2657 break;
542472b5
LV		 2658 case KVM_CAP_COALESCED_MMIO:
2659 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2660 break;
774ead3a
AK		 2661 case KVM_CAP_VAPIC:
2662 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2663 break;
f725230a 2664 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2665 r = KVM_SOFT_MAX_VCPUS;
2666 break;
2667 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2668 r = KVM_MAX_VCPUS;
2669 break;
a988b910 2670 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2671 r = KVM_USER_MEM_SLOTS;
a988b910 2672 break;
a68a6a72
MT		 2673 case KVM_CAP_PV_MMU: /* obsolete */
2674 r = 0;
2f333bcb 2675 break;
4cee4b72 2676#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2677 case KVM_CAP_IOMMU:
a1b60c1c 2678 r = iommu_present(&pci_bus_type);
62c476c7 2679 break;
4cee4b72 2680#endif
890ca9ae
YH		 2681 case KVM_CAP_MCE:
2682 r = KVM_MAX_MCE_BANKS;
2683 break;
2d5b5a66
SY		 2684 case KVM_CAP_XCRS:
2685 r = cpu_has_xsave;
2686 break;
92a1f12d
JR		 2687 case KVM_CAP_TSC_CONTROL:
2688 r = kvm_has_tsc_control;
2689 break;
4d25a066
JK		 2690 case KVM_CAP_TSC_DEADLINE_TIMER:
2691 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2692 break;
018d00d2
ZX		 2693 default:
2694 r = 0;
2695 break;
2696 }
2697 return r;
2698
2699}
2700
043405e1
CO		 2701long kvm_arch_dev_ioctl(struct file *filp,
2702 unsigned int ioctl, unsigned long arg)
2703{
2704 void __user *argp = (void __user *)arg;
2705 long r;
2706
2707 switch (ioctl) {
2708 case KVM_GET_MSR_INDEX_LIST: {
2709 struct kvm_msr_list __user *user_msr_list = argp;
2710 struct kvm_msr_list msr_list;
2711 unsigned n;
2712
2713 r = -EFAULT;
2714 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2715 goto out;
2716 n = msr_list.nmsrs;
2717 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2718 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2719 goto out;
2720 r = -E2BIG;
e125e7b6 2721 if (n < msr_list.nmsrs)
043405e1
CO		 2722 goto out;
2723 r = -EFAULT;
2724 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2725 num_msrs_to_save * sizeof(u32)))
2726 goto out;
e125e7b6 2727 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2728 &emulated_msrs,
2729 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2730 goto out;
2731 r = 0;
2732 break;
2733 }
9c15bb1d
BP		 2734 case KVM_GET_SUPPORTED_CPUID:
2735 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
9c15bb1d
BP		 2742
2743 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2744 ioctl);
674eea0f
AK		 2745 if (r)
2746 goto out;
2747
2748 r = -EFAULT;
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750 goto out;
2751 r = 0;
2752 break;
2753 }
890ca9ae
YH		 2754 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2755 u64 mce_cap;
2756
2757 mce_cap = KVM_MCE_CAP_SUPPORTED;
2758 r = -EFAULT;
2759 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2760 goto out;
2761 r = 0;
2762 break;
2763 }
043405e1
CO		 2764 default:
2765 r = -EINVAL;
2766 }
2767out:
2768 return r;
2769}
2770
f5f48ee1
SY		 2771static void wbinvd_ipi(void *garbage)
2772{
2773 wbinvd();
2774}
2775
2776static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2777{
e0f0bbc5 2778 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2779}
2780
313a3dc7
CO		 2781void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2782{
f5f48ee1
SY		 2783 /* Address WBINVD may be executed by guest */
2784 if (need_emulate_wbinvd(vcpu)) {
2785 if (kvm_x86_ops->has_wbinvd_exit())
2786 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2787 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2788 smp_call_function_single(vcpu->cpu,
2789 wbinvd_ipi, NULL, 1);
2790 }
2791
313a3dc7 2792 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2793
0dd6a6ed
ZA		 2794 /* Apply any externally detected TSC adjustments (due to suspend) */
2795 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2796 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2797 vcpu->arch.tsc_offset_adjustment = 0;
2798 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2799 }
8f6055cb 2800
48434c20 2801 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2802 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2803 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2804 if (tsc_delta < 0)
2805 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2806 if (check_tsc_unstable()) {
b183aa58
ZA		 2807 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2808 vcpu->arch.last_guest_tsc);
2809 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2810 vcpu->arch.tsc_catchup = 1;
c285545f 2811 }
d98d07ca
MT		 2812 /*
2813 * On a host with synchronized TSC, there is no need to update
2814 * kvmclock on vcpu->cpu migration
2815 */
2816 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2817 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2818 if (vcpu->cpu != cpu)
2819 kvm_migrate_timers(vcpu);
e48672fa 2820 vcpu->cpu = cpu;
6b7d7e76 2821 }
c9aaa895
GC		 2822
2823 accumulate_steal_time(vcpu);
2824 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2825}
2826
2827void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2828{
02daab21 2829 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2830 kvm_put_guest_fpu(vcpu);
6f526ec5 2831 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2832}
2833
313a3dc7
CO		 2834static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2835 struct kvm_lapic_state *s)
2836{
5a71785d 2837 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2838 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2839
2840 return 0;
2841}
2842
2843static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2844 struct kvm_lapic_state *s)
2845{
64eb0620 2846 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2847 update_cr8_intercept(vcpu);
313a3dc7
CO		 2848
2849 return 0;
2850}
2851
f77bc6a4
ZX		 2852static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2853 struct kvm_interrupt *irq)
2854{
02cdb50f 2855 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2856 return -EINVAL;
2857 if (irqchip_in_kernel(vcpu->kvm))
2858 return -ENXIO;
f77bc6a4 2859
66fd3f7f 2860 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2861 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2862
f77bc6a4
ZX		 2863 return 0;
2864}
2865
c4abb7c9
JK		 2866static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2867{
c4abb7c9 2868 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2869
2870 return 0;
2871}
2872
b209749f
AK		 2873static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2874 struct kvm_tpr_access_ctl *tac)
2875{
2876 if (tac->flags)
2877 return -EINVAL;
2878 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2879 return 0;
2880}
2881
890ca9ae
YH		 2882static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2883 u64 mcg_cap)
2884{
2885 int r;
2886 unsigned bank_num = mcg_cap & 0xff, bank;
2887
2888 r = -EINVAL;
a9e38c3e 2889 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
YH		 2890 goto out;
2891 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2892 goto out;
2893 r = 0;
2894 vcpu->arch.mcg_cap = mcg_cap;
2895 /* Init IA32_MCG_CTL to all 1s */
2896 if (mcg_cap & MCG_CTL_P)
2897 vcpu->arch.mcg_ctl = ~(u64)0;
2898 /* Init IA32_MCi_CTL to all 1s */
2899 for (bank = 0; bank < bank_num; bank++)
2900 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2901out:
2902 return r;
2903}
2904
2905static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2906 struct kvm_x86_mce *mce)
2907{
2908 u64 mcg_cap = vcpu->arch.mcg_cap;
2909 unsigned bank_num = mcg_cap & 0xff;
2910 u64 *banks = vcpu->arch.mce_banks;
2911
2912 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2913 return -EINVAL;
2914 /*
2915 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2916 * reporting is disabled
2917 */
2918 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2919 vcpu->arch.mcg_ctl != ~(u64)0)
2920 return 0;
2921 banks += 4 * mce->bank;
2922 /*
2923 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2924 * reporting is disabled for the bank
2925 */
2926 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2927 return 0;
2928 if (mce->status & MCI_STATUS_UC) {
2929 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2930 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2931 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
YH		 2932 return 0;
2933 }
2934 if (banks[1] & MCI_STATUS_VAL)
2935 mce->status |= MCI_STATUS_OVER;
2936 banks[2] = mce->addr;
2937 banks[3] = mce->misc;
2938 vcpu->arch.mcg_status = mce->mcg_status;
2939 banks[1] = mce->status;
2940 kvm_queue_exception(vcpu, MC_VECTOR);
2941 } else if (!(banks[1] & MCI_STATUS_VAL)
2942 || !(banks[1] & MCI_STATUS_UC)) {
2943 if (banks[1] & MCI_STATUS_VAL)
2944 mce->status |= MCI_STATUS_OVER;
2945 banks[2] = mce->addr;
2946 banks[3] = mce->misc;
2947 banks[1] = mce->status;
2948 } else
2949 banks[1] |= MCI_STATUS_OVER;
2950 return 0;
2951}
2952
3cfc3092
JK		 2953static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2954 struct kvm_vcpu_events *events)
2955{
7460fb4a 2956 process_nmi(vcpu);
03b82a30
JK		 2957 events->exception.injected =
2958 vcpu->arch.exception.pending &&
2959 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2960 events->exception.nr = vcpu->arch.exception.nr;
2961 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2962 events->exception.pad = 0;
3cfc3092
JK		 2963 events->exception.error_code = vcpu->arch.exception.error_code;
2964
03b82a30
JK		 2965 events->interrupt.injected =
2966 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2967 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2968 events->interrupt.soft = 0;
48005f64
JK		 2969 events->interrupt.shadow =
2970 kvm_x86_ops->get_interrupt_shadow(vcpu,
2971 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2972
2973 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2974 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2975 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2976 events->nmi.pad = 0;
3cfc3092 2977
66450a21 2978 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2979
dab4b911 2980 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2981 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2982 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2983}
2984
2985static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2986 struct kvm_vcpu_events *events)
2987{
dab4b911 2988 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2989 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2990 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2991 return -EINVAL;
2992
7460fb4a 2993 process_nmi(vcpu);
3cfc3092
JK		 2994 vcpu->arch.exception.pending = events->exception.injected;
2995 vcpu->arch.exception.nr = events->exception.nr;
2996 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2997 vcpu->arch.exception.error_code = events->exception.error_code;
2998
2999 vcpu->arch.interrupt.pending = events->interrupt.injected;
3000 vcpu->arch.interrupt.nr = events->interrupt.nr;
3001 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3002 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3003 kvm_x86_ops->set_interrupt_shadow(vcpu,
3004 events->interrupt.shadow);
3cfc3092
JK		 3005
3006 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3007 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3008 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3009 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3010
66450a21
JK		 3011 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3012 kvm_vcpu_has_lapic(vcpu))
3013 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3014
3842d135
AK		 3015 kvm_make_request(KVM_REQ_EVENT, vcpu);
3016
3cfc3092
JK		 3017 return 0;
3018}
3019
a1efbe77
JK		 3020static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3021 struct kvm_debugregs *dbgregs)
3022{
73aaf249
JK		 3023 unsigned long val;
3024
a1efbe77 3025 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3026 _kvm_get_dr(vcpu, 6, &val);
3027 dbgregs->dr6 = val;
a1efbe77
JK		 3028 dbgregs->dr7 = vcpu->arch.dr7;
3029 dbgregs->flags = 0;
97e69aa6 3030 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3031}
3032
3033static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3034 struct kvm_debugregs *dbgregs)
3035{
3036 if (dbgregs->flags)
3037 return -EINVAL;
3038
a1efbe77
JK		 3039 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3040 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3041 kvm_update_dr6(vcpu);
a1efbe77 3042 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3043 kvm_update_dr7(vcpu);
a1efbe77 3044
a1efbe77
JK		 3045 return 0;
3046}
3047
2d5b5a66
SY		 3048static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3049 struct kvm_xsave *guest_xsave)
3050{
4344ee98 3051 if (cpu_has_xsave) {
2d5b5a66
SY		 3052 memcpy(guest_xsave->region,
3053 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3054 vcpu->arch.guest_xstate_size);
3055 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3056 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3057 } else {
2d5b5a66
SY		 3058 memcpy(guest_xsave->region,
3059 &vcpu->arch.guest_fpu.state->fxsave,
3060 sizeof(struct i387_fxsave_struct));
3061 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3062 XSTATE_FPSSE;
3063 }
3064}
3065
3066static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3067 struct kvm_xsave *guest_xsave)
3068{
3069 u64 xstate_bv =
3070 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3071
d7876f1b
PB		 3072 if (cpu_has_xsave) {
3073 /*
3074 * Here we allow setting states that are not present in
3075 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3076 * with old userspace.
3077 */
4ff41732 3078 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3079 return -EINVAL;
2d5b5a66 3080 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3081 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3082 } else {
2d5b5a66
SY		 3083 if (xstate_bv & ~XSTATE_FPSSE)
3084 return -EINVAL;
3085 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3086 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3087 }
3088 return 0;
3089}
3090
3091static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3092 struct kvm_xcrs *guest_xcrs)
3093{
3094 if (!cpu_has_xsave) {
3095 guest_xcrs->nr_xcrs = 0;
3096 return;
3097 }
3098
3099 guest_xcrs->nr_xcrs = 1;
3100 guest_xcrs->flags = 0;
3101 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3102 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3103}
3104
3105static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3106 struct kvm_xcrs *guest_xcrs)
3107{
3108 int i, r = 0;
3109
3110 if (!cpu_has_xsave)
3111 return -EINVAL;
3112
3113 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3114 return -EINVAL;
3115
3116 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3117 /* Only support XCR0 currently */
c67a04cb 3118 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3119 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3120 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3121 break;
3122 }
3123 if (r)
3124 r = -EINVAL;
3125 return r;
3126}
3127
1c0b28c2
EM		 3128/*
3129 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3130 * stopped by the hypervisor. This function will be called from the host only.
3131 * EINVAL is returned when the host attempts to set the flag for a guest that
3132 * does not support pv clocks.
3133 */
3134static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3135{
0b79459b 3136 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3137 return -EINVAL;
51d59c6b 3138 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3139 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3140 return 0;
3141}
3142
313a3dc7
CO		 3143long kvm_arch_vcpu_ioctl(struct file *filp,
3144 unsigned int ioctl, unsigned long arg)
3145{
3146 struct kvm_vcpu *vcpu = filp->private_data;
3147 void __user *argp = (void __user *)arg;
3148 int r;
d1ac91d8
AK		 3149 union {
3150 struct kvm_lapic_state *lapic;
3151 struct kvm_xsave *xsave;
3152 struct kvm_xcrs *xcrs;
3153 void *buffer;
3154 } u;
3155
3156 u.buffer = NULL;
313a3dc7
CO		 3157 switch (ioctl) {
3158 case KVM_GET_LAPIC: {
2204ae3c
MT		 3159 r = -EINVAL;
3160 if (!vcpu->arch.apic)
3161 goto out;
d1ac91d8 3162 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3163
b772ff36 3164 r = -ENOMEM;
d1ac91d8 3165 if (!u.lapic)
b772ff36 3166 goto out;
d1ac91d8 3167 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3168 if (r)
3169 goto out;
3170 r = -EFAULT;
d1ac91d8 3171 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3172 goto out;
3173 r = 0;
3174 break;
3175 }
3176 case KVM_SET_LAPIC: {
2204ae3c
MT		 3177 r = -EINVAL;
3178 if (!vcpu->arch.apic)
3179 goto out;
ff5c2c03 3180 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3181 if (IS_ERR(u.lapic))
3182 return PTR_ERR(u.lapic);
ff5c2c03 3183
d1ac91d8 3184 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3185 break;
3186 }
f77bc6a4
ZX		 3187 case KVM_INTERRUPT: {
3188 struct kvm_interrupt irq;
3189
3190 r = -EFAULT;
3191 if (copy_from_user(&irq, argp, sizeof irq))
3192 goto out;
3193 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3194 break;
3195 }
c4abb7c9
JK		 3196 case KVM_NMI: {
3197 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3198 break;
3199 }
313a3dc7
CO		 3200 case KVM_SET_CPUID: {
3201 struct kvm_cpuid __user *cpuid_arg = argp;
3202 struct kvm_cpuid cpuid;
3203
3204 r = -EFAULT;
3205 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3206 goto out;
3207 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3208 break;
3209 }
07716717
DK		 3210 case KVM_SET_CPUID2: {
3211 struct kvm_cpuid2 __user *cpuid_arg = argp;
3212 struct kvm_cpuid2 cpuid;
3213
3214 r = -EFAULT;
3215 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3216 goto out;
3217 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3218 cpuid_arg->entries);
07716717
DK		 3219 break;
3220 }
3221 case KVM_GET_CPUID2: {
3222 struct kvm_cpuid2 __user *cpuid_arg = argp;
3223 struct kvm_cpuid2 cpuid;
3224
3225 r = -EFAULT;
3226 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3227 goto out;
3228 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3229 cpuid_arg->entries);
07716717
DK		 3230 if (r)
3231 goto out;
3232 r = -EFAULT;
3233 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3234 goto out;
3235 r = 0;
3236 break;
3237 }
313a3dc7
CO		 3238 case KVM_GET_MSRS:
3239 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3240 break;
3241 case KVM_SET_MSRS:
3242 r = msr_io(vcpu, argp, do_set_msr, 0);
3243 break;
b209749f
AK		 3244 case KVM_TPR_ACCESS_REPORTING: {
3245 struct kvm_tpr_access_ctl tac;
3246
3247 r = -EFAULT;
3248 if (copy_from_user(&tac, argp, sizeof tac))
3249 goto out;
3250 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3251 if (r)
3252 goto out;
3253 r = -EFAULT;
3254 if (copy_to_user(argp, &tac, sizeof tac))
3255 goto out;
3256 r = 0;
3257 break;
3258 };
b93463aa
AK		 3259 case KVM_SET_VAPIC_ADDR: {
3260 struct kvm_vapic_addr va;
3261
3262 r = -EINVAL;
3263 if (!irqchip_in_kernel(vcpu->kvm))
3264 goto out;
3265 r = -EFAULT;
3266 if (copy_from_user(&va, argp, sizeof va))
3267 goto out;
fda4e2e8 3268 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3269 break;
3270 }
890ca9ae
YH		 3271 case KVM_X86_SETUP_MCE: {
3272 u64 mcg_cap;
3273
3274 r = -EFAULT;
3275 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3276 goto out;
3277 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3278 break;
3279 }
3280 case KVM_X86_SET_MCE: {
3281 struct kvm_x86_mce mce;
3282
3283 r = -EFAULT;
3284 if (copy_from_user(&mce, argp, sizeof mce))
3285 goto out;
3286 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3287 break;
3288 }
3cfc3092
JK		 3289 case KVM_GET_VCPU_EVENTS: {
3290 struct kvm_vcpu_events events;
3291
3292 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3293
3294 r = -EFAULT;
3295 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3296 break;
3297 r = 0;
3298 break;
3299 }
3300 case KVM_SET_VCPU_EVENTS: {
3301 struct kvm_vcpu_events events;
3302
3303 r = -EFAULT;
3304 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3305 break;
3306
3307 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3308 break;
3309 }
a1efbe77
JK		 3310 case KVM_GET_DEBUGREGS: {
3311 struct kvm_debugregs dbgregs;
3312
3313 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3314
3315 r = -EFAULT;
3316 if (copy_to_user(argp, &dbgregs,
3317 sizeof(struct kvm_debugregs)))
3318 break;
3319 r = 0;
3320 break;
3321 }
3322 case KVM_SET_DEBUGREGS: {
3323 struct kvm_debugregs dbgregs;
3324
3325 r = -EFAULT;
3326 if (copy_from_user(&dbgregs, argp,
3327 sizeof(struct kvm_debugregs)))
3328 break;
3329
3330 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3331 break;
3332 }
2d5b5a66 3333 case KVM_GET_XSAVE: {
d1ac91d8 3334 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3335 r = -ENOMEM;
d1ac91d8 3336 if (!u.xsave)
2d5b5a66
SY		 3337 break;
3338
d1ac91d8 3339 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3340
3341 r = -EFAULT;
d1ac91d8 3342 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3343 break;
3344 r = 0;
3345 break;
3346 }
3347 case KVM_SET_XSAVE: {
ff5c2c03 3348 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3349 if (IS_ERR(u.xsave))
3350 return PTR_ERR(u.xsave);
2d5b5a66 3351
d1ac91d8 3352 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3353 break;
3354 }
3355 case KVM_GET_XCRS: {
d1ac91d8 3356 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3357 r = -ENOMEM;
d1ac91d8 3358 if (!u.xcrs)
2d5b5a66
SY		 3359 break;
3360
d1ac91d8 3361 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3362
3363 r = -EFAULT;
d1ac91d8 3364 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3365 sizeof(struct kvm_xcrs)))
3366 break;
3367 r = 0;
3368 break;
3369 }
3370 case KVM_SET_XCRS: {
ff5c2c03 3371 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3372 if (IS_ERR(u.xcrs))
3373 return PTR_ERR(u.xcrs);
2d5b5a66 3374
d1ac91d8 3375 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3376 break;
3377 }
92a1f12d
JR		 3378 case KVM_SET_TSC_KHZ: {
3379 u32 user_tsc_khz;
3380
3381 r = -EINVAL;
92a1f12d
JR		 3382 user_tsc_khz = (u32)arg;
3383
3384 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3385 goto out;
3386
cc578287
ZA		 3387 if (user_tsc_khz == 0)
3388 user_tsc_khz = tsc_khz;
3389
3390 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3391
3392 r = 0;
3393 goto out;
3394 }
3395 case KVM_GET_TSC_KHZ: {
cc578287 3396 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3397 goto out;
3398 }
1c0b28c2
EM		 3399 case KVM_KVMCLOCK_CTRL: {
3400 r = kvm_set_guest_paused(vcpu);
3401 goto out;
3402 }
313a3dc7
CO		 3403 default:
3404 r = -EINVAL;
3405 }
3406out:
d1ac91d8 3407 kfree(u.buffer);
313a3dc7
CO		 3408 return r;
3409}
3410
5b1c1493
CO		 3411int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3412{
3413 return VM_FAULT_SIGBUS;
3414}
3415
1fe779f8
CO		 3416static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3417{
3418 int ret;
3419
3420 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3421 return -EINVAL;
1fe779f8
CO		 3422 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3423 return ret;
3424}
3425
b927a3ce
SY		 3426static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3427 u64 ident_addr)
3428{
3429 kvm->arch.ept_identity_map_addr = ident_addr;
3430 return 0;
3431}
3432
1fe779f8
CO		 3433static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3434 u32 kvm_nr_mmu_pages)
3435{
3436 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3437 return -EINVAL;
3438
79fac95e 3439 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3440
3441 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3442 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3443
79fac95e 3444 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3445 return 0;
3446}
3447
3448static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3449{
39de71ec 3450 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3451}
3452
1fe779f8
CO		 3453static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3454{
3455 int r;
3456
3457 r = 0;
3458 switch (chip->chip_id) {
3459 case KVM_IRQCHIP_PIC_MASTER:
3460 memcpy(&chip->chip.pic,
3461 &pic_irqchip(kvm)->pics[0],
3462 sizeof(struct kvm_pic_state));
3463 break;
3464 case KVM_IRQCHIP_PIC_SLAVE:
3465 memcpy(&chip->chip.pic,
3466 &pic_irqchip(kvm)->pics[1],
3467 sizeof(struct kvm_pic_state));
3468 break;
3469 case KVM_IRQCHIP_IOAPIC:
eba0226b 3470 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3471 break;
3472 default:
3473 r = -EINVAL;
3474 break;
3475 }
3476 return r;
3477}
3478
3479static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3480{
3481 int r;
3482
3483 r = 0;
3484 switch (chip->chip_id) {
3485 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3486 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3487 memcpy(&pic_irqchip(kvm)->pics[0],
3488 &chip->chip.pic,
3489 sizeof(struct kvm_pic_state));
f4f51050 3490 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3491 break;
3492 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3493 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3494 memcpy(&pic_irqchip(kvm)->pics[1],
3495 &chip->chip.pic,
3496 sizeof(struct kvm_pic_state));
f4f51050 3497 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3498 break;
3499 case KVM_IRQCHIP_IOAPIC:
eba0226b 3500 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3501 break;
3502 default:
3503 r = -EINVAL;
3504 break;
3505 }
3506 kvm_pic_update_irq(pic_irqchip(kvm));
3507 return r;
3508}
3509
e0f63cb9
SY		 3510static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3511{
3512 int r = 0;
3513
894a9c55 3514 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3515 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3516 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3517 return r;
3518}
3519
3520static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3521{
3522 int r = 0;
3523
894a9c55 3524 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3525 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3526 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3527 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3528 return r;
3529}
3530
3531static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3532{
3533 int r = 0;
3534
3535 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3536 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3537 sizeof(ps->channels));
3538 ps->flags = kvm->arch.vpit->pit_state.flags;
3539 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3540 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3541 return r;
3542}
3543
3544static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3545{
3546 int r = 0, start = 0;
3547 u32 prev_legacy, cur_legacy;
3548 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3549 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3550 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3551 if (!prev_legacy && cur_legacy)
3552 start = 1;
3553 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3554 sizeof(kvm->arch.vpit->pit_state.channels));
3555 kvm->arch.vpit->pit_state.flags = ps->flags;
3556 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3557 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3558 return r;
3559}
3560
52d939a0
MT		 3561static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3562 struct kvm_reinject_control *control)
3563{
3564 if (!kvm->arch.vpit)
3565 return -ENXIO;
894a9c55 3566 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3567 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3568 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3569 return 0;
3570}
3571
95d4c16c 3572/**
60c34612
TY		 3573 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3574 * @kvm: kvm instance
3575 * @log: slot id and address to which we copy the log
95d4c16c 3576 *
60c34612
TY		 3577 * We need to keep it in mind that VCPU threads can write to the bitmap
3578 * concurrently. So, to avoid losing data, we keep the following order for
3579 * each bit:
95d4c16c 3580 *
60c34612
TY		 3581 * 1. Take a snapshot of the bit and clear it if needed.
3582 * 2. Write protect the corresponding page.
3583 * 3. Flush TLB's if needed.
3584 * 4. Copy the snapshot to the userspace.
95d4c16c 3585 *
60c34612
TY		 3586 * Between 2 and 3, the guest may write to the page using the remaining TLB
3587 * entry. This is not a problem because the page will be reported dirty at
3588 * step 4 using the snapshot taken before and step 3 ensures that successive
3589 * writes will be logged for the next call.
5bb064dc 3590 */
60c34612 3591int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3592{
7850ac54 3593 int r;
5bb064dc 3594 struct kvm_memory_slot *memslot;
60c34612
TY		 3595 unsigned long n, i;
3596 unsigned long *dirty_bitmap;
3597 unsigned long *dirty_bitmap_buffer;
3598 bool is_dirty = false;
5bb064dc 3599
79fac95e 3600 mutex_lock(&kvm->slots_lock);
5bb064dc 3601
b050b015 3602 r = -EINVAL;
bbacc0c1 3603 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3604 goto out;
3605
28a37544 3606 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3607
3608 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3609 r = -ENOENT;
60c34612 3610 if (!dirty_bitmap)
b050b015
MT		 3611 goto out;
3612
87bf6e7d 3613 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3614
60c34612
TY		 3615 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3616 memset(dirty_bitmap_buffer, 0, n);
b050b015 3617
60c34612 3618 spin_lock(&kvm->mmu_lock);
b050b015 3619
60c34612
TY		 3620 for (i = 0; i < n / sizeof(long); i++) {
3621 unsigned long mask;
3622 gfn_t offset;
cdfca7b3 3623
60c34612
TY		 3624 if (!dirty_bitmap[i])
3625 continue;
b050b015 3626
60c34612 3627 is_dirty = true;
914ebccd 3628
60c34612
TY		 3629 mask = xchg(&dirty_bitmap[i], 0);
3630 dirty_bitmap_buffer[i] = mask;
edde99ce 3631
60c34612
TY		 3632 offset = i * BITS_PER_LONG;
3633 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3634 }
60c34612
TY		 3635 if (is_dirty)
3636 kvm_flush_remote_tlbs(kvm);
3637
3638 spin_unlock(&kvm->mmu_lock);
3639
3640 r = -EFAULT;
3641 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3642 goto out;
b050b015 3643
5bb064dc
ZX		 3644 r = 0;
3645out:
79fac95e 3646 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3647 return r;
3648}
3649
aa2fbe6d
YZ		 3650int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3651 bool line_status)
23d43cf9
CD		 3652{
3653 if (!irqchip_in_kernel(kvm))
3654 return -ENXIO;
3655
3656 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3657 irq_event->irq, irq_event->level,
3658 line_status);
23d43cf9
CD		 3659 return 0;
3660}
3661
1fe779f8
CO		 3662long kvm_arch_vm_ioctl(struct file *filp,
3663 unsigned int ioctl, unsigned long arg)
3664{
3665 struct kvm *kvm = filp->private_data;
3666 void __user *argp = (void __user *)arg;
367e1319 3667 int r = -ENOTTY;
f0d66275
DH		 3668 /*
3669 * This union makes it completely explicit to gcc-3.x
3670 * that these two variables' stack usage should be
3671 * combined, not added together.
3672 */
3673 union {
3674 struct kvm_pit_state ps;
e9f42757 3675 struct kvm_pit_state2 ps2;
c5ff41ce 3676 struct kvm_pit_config pit_config;
f0d66275 3677 } u;
1fe779f8
CO		 3678
3679 switch (ioctl) {
3680 case KVM_SET_TSS_ADDR:
3681 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3682 break;
b927a3ce
SY		 3683 case KVM_SET_IDENTITY_MAP_ADDR: {
3684 u64 ident_addr;
3685
3686 r = -EFAULT;
3687 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3688 goto out;
3689 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3690 break;
3691 }
1fe779f8
CO		 3692 case KVM_SET_NR_MMU_PAGES:
3693 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3694 break;
3695 case KVM_GET_NR_MMU_PAGES:
3696 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3697 break;
3ddea128
MT		 3698 case KVM_CREATE_IRQCHIP: {
3699 struct kvm_pic *vpic;
3700
3701 mutex_lock(&kvm->lock);
3702 r = -EEXIST;
3703 if (kvm->arch.vpic)
3704 goto create_irqchip_unlock;
3e515705
AK		 3705 r = -EINVAL;
3706 if (atomic_read(&kvm->online_vcpus))
3707 goto create_irqchip_unlock;
1fe779f8 3708 r = -ENOMEM;
3ddea128
MT		 3709 vpic = kvm_create_pic(kvm);
3710 if (vpic) {
1fe779f8
CO		 3711 r = kvm_ioapic_init(kvm);
3712 if (r) {
175504cd 3713 mutex_lock(&kvm->slots_lock);
72bb2fcd 3714 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3715 &vpic->dev_master);
3716 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3717 &vpic->dev_slave);
3718 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3719 &vpic->dev_eclr);
175504cd 3720 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3721 kfree(vpic);
3722 goto create_irqchip_unlock;
1fe779f8
CO		 3723 }
3724 } else
3ddea128
MT		 3725 goto create_irqchip_unlock;
3726 smp_wmb();
3727 kvm->arch.vpic = vpic;
3728 smp_wmb();
399ec807
AK		 3729 r = kvm_setup_default_irq_routing(kvm);
3730 if (r) {
175504cd 3731 mutex_lock(&kvm->slots_lock);
3ddea128 3732 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3733 kvm_ioapic_destroy(kvm);
3734 kvm_destroy_pic(kvm);
3ddea128 3735 mutex_unlock(&kvm->irq_lock);
175504cd 3736 mutex_unlock(&kvm->slots_lock);
399ec807 3737 }
3ddea128
MT		 3738 create_irqchip_unlock:
3739 mutex_unlock(&kvm->lock);
1fe779f8 3740 break;
3ddea128 3741 }
7837699f 3742 case KVM_CREATE_PIT:
c5ff41ce
JK		 3743 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3744 goto create_pit;
3745 case KVM_CREATE_PIT2:
3746 r = -EFAULT;
3747 if (copy_from_user(&u.pit_config, argp,
3748 sizeof(struct kvm_pit_config)))
3749 goto out;
3750 create_pit:
79fac95e 3751 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3752 r = -EEXIST;
3753 if (kvm->arch.vpit)
3754 goto create_pit_unlock;
7837699f 3755 r = -ENOMEM;
c5ff41ce 3756 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3757 if (kvm->arch.vpit)
3758 r = 0;
269e05e4 3759 create_pit_unlock:
79fac95e 3760 mutex_unlock(&kvm->slots_lock);
7837699f 3761 break;
1fe779f8
CO		 3762 case KVM_GET_IRQCHIP: {
3763 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3764 struct kvm_irqchip *chip;
1fe779f8 3765
ff5c2c03
SL		 3766 chip = memdup_user(argp, sizeof(*chip));
3767 if (IS_ERR(chip)) {
3768 r = PTR_ERR(chip);
1fe779f8 3769 goto out;
ff5c2c03
SL		 3770 }
3771
1fe779f8
CO		 3772 r = -ENXIO;
3773 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3774 goto get_irqchip_out;
3775 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3776 if (r)
f0d66275 3777 goto get_irqchip_out;
1fe779f8 3778 r = -EFAULT;
f0d66275
DH		 3779 if (copy_to_user(argp, chip, sizeof *chip))
3780 goto get_irqchip_out;
1fe779f8 3781 r = 0;
f0d66275
DH		 3782 get_irqchip_out:
3783 kfree(chip);
1fe779f8
CO		 3784 break;
3785 }
3786 case KVM_SET_IRQCHIP: {
3787 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3788 struct kvm_irqchip *chip;
1fe779f8 3789
ff5c2c03
SL		 3790 chip = memdup_user(argp, sizeof(*chip));
3791 if (IS_ERR(chip)) {
3792 r = PTR_ERR(chip);
1fe779f8 3793 goto out;
ff5c2c03
SL		 3794 }
3795
1fe779f8
CO		 3796 r = -ENXIO;
3797 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3798 goto set_irqchip_out;
3799 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3800 if (r)
f0d66275 3801 goto set_irqchip_out;
1fe779f8 3802 r = 0;
f0d66275
DH		 3803 set_irqchip_out:
3804 kfree(chip);
1fe779f8
CO		 3805 break;
3806 }
e0f63cb9 3807 case KVM_GET_PIT: {
e0f63cb9 3808 r = -EFAULT;
f0d66275 3809 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3810 goto out;
3811 r = -ENXIO;
3812 if (!kvm->arch.vpit)
3813 goto out;
f0d66275 3814 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3815 if (r)
3816 goto out;
3817 r = -EFAULT;
f0d66275 3818 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3819 goto out;
3820 r = 0;
3821 break;
3822 }
3823 case KVM_SET_PIT: {
e0f63cb9 3824 r = -EFAULT;
f0d66275 3825 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3826 goto out;
3827 r = -ENXIO;
3828 if (!kvm->arch.vpit)
3829 goto out;
f0d66275 3830 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3831 break;
3832 }
e9f42757
BK		 3833 case KVM_GET_PIT2: {
3834 r = -ENXIO;
3835 if (!kvm->arch.vpit)
3836 goto out;
3837 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3838 if (r)
3839 goto out;
3840 r = -EFAULT;
3841 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3842 goto out;
3843 r = 0;
3844 break;
3845 }
3846 case KVM_SET_PIT2: {
3847 r = -EFAULT;
3848 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3849 goto out;
3850 r = -ENXIO;
3851 if (!kvm->arch.vpit)
3852 goto out;
3853 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3854 break;
3855 }
52d939a0
MT		 3856 case KVM_REINJECT_CONTROL: {
3857 struct kvm_reinject_control control;
3858 r = -EFAULT;
3859 if (copy_from_user(&control, argp, sizeof(control)))
3860 goto out;
3861 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3862 break;
3863 }
ffde22ac
ES		 3864 case KVM_XEN_HVM_CONFIG: {
3865 r = -EFAULT;
3866 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3867 sizeof(struct kvm_xen_hvm_config)))
3868 goto out;
3869 r = -EINVAL;
3870 if (kvm->arch.xen_hvm_config.flags)
3871 goto out;
3872 r = 0;
3873 break;
3874 }
afbcf7ab 3875 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3876 struct kvm_clock_data user_ns;
3877 u64 now_ns;
3878 s64 delta;
3879
3880 r = -EFAULT;
3881 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3882 goto out;
3883
3884 r = -EINVAL;
3885 if (user_ns.flags)
3886 goto out;
3887
3888 r = 0;
395c6b0a 3889 local_irq_disable();
759379dd 3890 now_ns = get_kernel_ns();
afbcf7ab 3891 delta = user_ns.clock - now_ns;
395c6b0a 3892 local_irq_enable();
afbcf7ab 3893 kvm->arch.kvmclock_offset = delta;
2e762ff7 3894 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3895 break;
3896 }
3897 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3898 struct kvm_clock_data user_ns;
3899 u64 now_ns;
3900
395c6b0a 3901 local_irq_disable();
759379dd 3902 now_ns = get_kernel_ns();
afbcf7ab 3903 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3904 local_irq_enable();
afbcf7ab 3905 user_ns.flags = 0;
97e69aa6 3906 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3907
3908 r = -EFAULT;
3909 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3910 goto out;
3911 r = 0;
3912 break;
3913 }
3914
1fe779f8
CO		 3915 default:
3916 ;
3917 }
3918out:
3919 return r;
3920}
3921
a16b043c 3922static void kvm_init_msr_list(void)
043405e1
CO		 3923{
3924 u32 dummy[2];
3925 unsigned i, j;
3926
e3267cbb
GC		 3927 /* skip the first msrs in the list. KVM-specific */
3928 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3929 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3930 continue;
93c4adc7
PB		 3931
3932 /*
3933 * Even MSRs that are valid in the host may not be exposed
3934 * to the guests in some cases. We could work around this
3935 * in VMX with the generic MSR save/load machinery, but it
3936 * is not really worthwhile since it will really only
3937 * happen with nested virtualization.
3938 */
3939 switch (msrs_to_save[i]) {
3940 case MSR_IA32_BNDCFGS:
3941 if (!kvm_x86_ops->mpx_supported())
3942 continue;
3943 break;
3944 default:
3945 break;
3946 }
3947
043405e1
CO		 3948 if (j < i)
3949 msrs_to_save[j] = msrs_to_save[i];
3950 j++;
3951 }
3952 num_msrs_to_save = j;
3953}
3954
bda9020e
MT		 3955static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3956 const void *v)
bbd9b64e 3957{
70252a10
AK		 3958 int handled = 0;
3959 int n;
3960
3961 do {
3962 n = min(len, 8);
3963 if (!(vcpu->arch.apic &&
3964 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3965 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3966 break;
3967 handled += n;
3968 addr += n;
3969 len -= n;
3970 v += n;
3971 } while (len);
bbd9b64e 3972
70252a10 3973 return handled;
bbd9b64e
CO		 3974}
3975
bda9020e 3976static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3977{
70252a10
AK		 3978 int handled = 0;
3979 int n;
3980
3981 do {
3982 n = min(len, 8);
3983 if (!(vcpu->arch.apic &&
3984 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3985 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3986 break;
3987 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3988 handled += n;
3989 addr += n;
3990 len -= n;
3991 v += n;
3992 } while (len);
bbd9b64e 3993
70252a10 3994 return handled;
bbd9b64e
CO		 3995}
3996
2dafc6c2
GN		 3997static void kvm_set_segment(struct kvm_vcpu *vcpu,
3998 struct kvm_segment *var, int seg)
3999{
4000 kvm_x86_ops->set_segment(vcpu, var, seg);
4001}
4002
4003void kvm_get_segment(struct kvm_vcpu *vcpu,
4004 struct kvm_segment *var, int seg)
4005{
4006 kvm_x86_ops->get_segment(vcpu, var, seg);
4007}
4008
e459e322 4009gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4010{
4011 gpa_t t_gpa;
ab9ae313 4012 struct x86_exception exception;
02f59dc9
JR		 4013
4014 BUG_ON(!mmu_is_nested(vcpu));
4015
4016 /* NPT walks are always user-walks */
4017 access |= PFERR_USER_MASK;
ab9ae313 4018 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4019
4020 return t_gpa;
4021}
4022
ab9ae313
AK		 4023gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4024 struct x86_exception *exception)
1871c602
GN		 4025{
4026 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4027 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4028}
4029
ab9ae313
AK		 4030 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4031 struct x86_exception *exception)
1871c602
GN		 4032{
4033 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4034 access |= PFERR_FETCH_MASK;
ab9ae313 4035 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4036}
4037
ab9ae313
AK		 4038gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4039 struct x86_exception *exception)
1871c602
GN		 4040{
4041 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4042 access |= PFERR_WRITE_MASK;
ab9ae313 4043 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4044}
4045
4046/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4047gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4048 struct x86_exception *exception)
1871c602 4049{
ab9ae313 4050 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4051}
4052
4053static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4054 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4055 struct x86_exception *exception)
bbd9b64e
CO		 4056{
4057 void *data = val;
10589a46 4058 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4059
4060 while (bytes) {
14dfe855 4061 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4062 exception);
bbd9b64e 4063 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4064 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4065 int ret;
4066
bcc55cba 4067 if (gpa == UNMAPPED_GVA)
ab9ae313 4068 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4069 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4070 if (ret < 0) {
c3cd7ffa 4071 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4072 goto out;
4073 }
bbd9b64e 4074
77c2002e
IE		 4075 bytes -= toread;
4076 data += toread;
4077 addr += toread;
bbd9b64e 4078 }
10589a46 4079out:
10589a46 4080 return r;
bbd9b64e 4081}
77c2002e 4082
1871c602 4083/* used for instruction fetching */
0f65dd70
AK		 4084static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4085 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4086 struct x86_exception *exception)
1871c602 4087{
0f65dd70 4088 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4089 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4090
1871c602 4091 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4092 access | PFERR_FETCH_MASK,
4093 exception);
1871c602
GN		 4094}
4095
064aea77 4096int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4097 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4098 struct x86_exception *exception)
1871c602 4099{
0f65dd70 4100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4101 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4102
1871c602 4103 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4104 exception);
1871c602 4105}
064aea77 4106EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4107
0f65dd70
AK		 4108static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4109 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4110 struct x86_exception *exception)
1871c602 4111{
0f65dd70 4112 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4113 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4114}
4115
6a4d7550 4116int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4117 gva_t addr, void *val,
2dafc6c2 4118 unsigned int bytes,
bcc55cba 4119 struct x86_exception *exception)
77c2002e 4120{
0f65dd70 4121 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4122 void *data = val;
4123 int r = X86EMUL_CONTINUE;
4124
4125 while (bytes) {
14dfe855
JR		 4126 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4127 PFERR_WRITE_MASK,
ab9ae313 4128 exception);
77c2002e
IE		 4129 unsigned offset = addr & (PAGE_SIZE-1);
4130 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4131 int ret;
4132
bcc55cba 4133 if (gpa == UNMAPPED_GVA)
ab9ae313 4134 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4135 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4136 if (ret < 0) {
c3cd7ffa 4137 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4138 goto out;
4139 }
4140
4141 bytes -= towrite;
4142 data += towrite;
4143 addr += towrite;
4144 }
4145out:
4146 return r;
4147}
6a4d7550 4148EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4149
af7cc7d1
XG		 4150static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4151 gpa_t *gpa, struct x86_exception *exception,
4152 bool write)
4153{
97d64b78
AK		 4154 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4155 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4156
97d64b78 4157 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4158 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4159 vcpu->arch.access, access)) {
bebb106a
XG		 4160 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4161 (gva & (PAGE_SIZE - 1));
4f022648 4162 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4163 return 1;
4164 }
4165
af7cc7d1
XG		 4166 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4167
4168 if (*gpa == UNMAPPED_GVA)
4169 return -1;
4170
4171 /* For APIC access vmexit */
4172 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4173 return 1;
4174
4f022648
XG		 4175 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4176 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4177 return 1;
4f022648 4178 }
bebb106a 4179
af7cc7d1
XG		 4180 return 0;
4181}
4182
3200f405 4183int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4184 const void *val, int bytes)
bbd9b64e
CO		 4185{
4186 int ret;
4187
4188 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4189 if (ret < 0)
bbd9b64e 4190 return 0;
f57f2ef5 4191 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4192 return 1;
4193}
4194
77d197b2
XG		 4195struct read_write_emulator_ops {
4196 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4197 int bytes);
4198 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4199 void *val, int bytes);
4200 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4201 int bytes, void *val);
4202 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4203 void *val, int bytes);
4204 bool write;
4205};
4206
4207static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4208{
4209 if (vcpu->mmio_read_completed) {
77d197b2 4210 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4211 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4212 vcpu->mmio_read_completed = 0;
4213 return 1;
4214 }
4215
4216 return 0;
4217}
4218
4219static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4220 void *val, int bytes)
4221{
4222 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4223}
4224
4225static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4226 void *val, int bytes)
4227{
4228 return emulator_write_phys(vcpu, gpa, val, bytes);
4229}
4230
4231static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4232{
4233 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4234 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4235}
4236
4237static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4238 void *val, int bytes)
4239{
4240 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4241 return X86EMUL_IO_NEEDED;
4242}
4243
4244static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4245 void *val, int bytes)
4246{
f78146b0
AK		 4247 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4248
87da7e66 4249 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4250 return X86EMUL_CONTINUE;
4251}
4252
0fbe9b0b 4253static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4254 .read_write_prepare = read_prepare,
4255 .read_write_emulate = read_emulate,
4256 .read_write_mmio = vcpu_mmio_read,
4257 .read_write_exit_mmio = read_exit_mmio,
4258};
4259
0fbe9b0b 4260static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4261 .read_write_emulate = write_emulate,
4262 .read_write_mmio = write_mmio,
4263 .read_write_exit_mmio = write_exit_mmio,
4264 .write = true,
4265};
4266
22388a3c
XG		 4267static int emulator_read_write_onepage(unsigned long addr, void *val,
4268 unsigned int bytes,
4269 struct x86_exception *exception,
4270 struct kvm_vcpu *vcpu,
0fbe9b0b 4271 const struct read_write_emulator_ops *ops)
bbd9b64e 4272{
af7cc7d1
XG		 4273 gpa_t gpa;
4274 int handled, ret;
22388a3c 4275 bool write = ops->write;
f78146b0 4276 struct kvm_mmio_fragment *frag;
10589a46 4277
22388a3c 4278 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4279
af7cc7d1 4280 if (ret < 0)
bbd9b64e 4281 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4282
4283 /* For APIC access vmexit */
af7cc7d1 4284 if (ret)
bbd9b64e
CO		 4285 goto mmio;
4286
22388a3c 4287 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4288 return X86EMUL_CONTINUE;
4289
4290mmio:
4291 /*
4292 * Is this MMIO handled locally?
4293 */
22388a3c 4294 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4295 if (handled == bytes)
bbd9b64e 4296 return X86EMUL_CONTINUE;
bbd9b64e 4297
70252a10
AK		 4298 gpa += handled;
4299 bytes -= handled;
4300 val += handled;
4301
87da7e66
XG		 4302 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4303 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4304 frag->gpa = gpa;
4305 frag->data = val;
4306 frag->len = bytes;
f78146b0 4307 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4308}
4309
22388a3c
XG		 4310int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4311 void *val, unsigned int bytes,
4312 struct x86_exception *exception,
0fbe9b0b 4313 const struct read_write_emulator_ops *ops)
bbd9b64e 4314{
0f65dd70 4315 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4316 gpa_t gpa;
4317 int rc;
4318
4319 if (ops->read_write_prepare &&
4320 ops->read_write_prepare(vcpu, val, bytes))
4321 return X86EMUL_CONTINUE;
4322
4323 vcpu->mmio_nr_fragments = 0;
0f65dd70 4324
bbd9b64e
CO		 4325 /* Crossing a page boundary? */
4326 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4327 int now;
bbd9b64e
CO		 4328
4329 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4330 rc = emulator_read_write_onepage(addr, val, now, exception,
4331 vcpu, ops);
4332
bbd9b64e
CO		 4333 if (rc != X86EMUL_CONTINUE)
4334 return rc;
4335 addr += now;
4336 val += now;
4337 bytes -= now;
4338 }
22388a3c 4339
f78146b0
AK		 4340 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4341 vcpu, ops);
4342 if (rc != X86EMUL_CONTINUE)
4343 return rc;
4344
4345 if (!vcpu->mmio_nr_fragments)
4346 return rc;
4347
4348 gpa = vcpu->mmio_fragments[0].gpa;
4349
4350 vcpu->mmio_needed = 1;
4351 vcpu->mmio_cur_fragment = 0;
4352
87da7e66 4353 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4354 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4355 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4356 vcpu->run->mmio.phys_addr = gpa;
4357
4358 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4359}
4360
4361static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4362 unsigned long addr,
4363 void *val,
4364 unsigned int bytes,
4365 struct x86_exception *exception)
4366{
4367 return emulator_read_write(ctxt, addr, val, bytes,
4368 exception, &read_emultor);
4369}
4370
4371int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4372 unsigned long addr,
4373 const void *val,
4374 unsigned int bytes,
4375 struct x86_exception *exception)
4376{
4377 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4378 exception, &write_emultor);
bbd9b64e 4379}
bbd9b64e 4380
daea3e73
AK		 4381#define CMPXCHG_TYPE(t, ptr, old, new) \
4382 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4383
4384#ifdef CONFIG_X86_64
4385# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4386#else
4387# define CMPXCHG64(ptr, old, new) \
9749a6c0 4388 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4389#endif
4390
0f65dd70
AK		 4391static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4392 unsigned long addr,
bbd9b64e
CO		 4393 const void *old,
4394 const void *new,
4395 unsigned int bytes,
0f65dd70 4396 struct x86_exception *exception)
bbd9b64e 4397{
0f65dd70 4398 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4399 gpa_t gpa;
4400 struct page *page;
4401 char *kaddr;
4402 bool exchanged;
2bacc55c 4403
daea3e73
AK		 4404 /* guests cmpxchg8b have to be emulated atomically */
4405 if (bytes > 8 || (bytes & (bytes - 1)))
4406 goto emul_write;
10589a46 4407
daea3e73 4408 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4409
daea3e73
AK		 4410 if (gpa == UNMAPPED_GVA ||
4411 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4412 goto emul_write;
2bacc55c 4413
daea3e73
AK		 4414 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4415 goto emul_write;
72dc67a6 4416
daea3e73 4417 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4418 if (is_error_page(page))
c19b8bd6 4419 goto emul_write;
72dc67a6 4420
8fd75e12 4421 kaddr = kmap_atomic(page);
daea3e73
AK		 4422 kaddr += offset_in_page(gpa);
4423 switch (bytes) {
4424 case 1:
4425 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4426 break;
4427 case 2:
4428 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4429 break;
4430 case 4:
4431 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4432 break;
4433 case 8:
4434 exchanged = CMPXCHG64(kaddr, old, new);
4435 break;
4436 default:
4437 BUG();
2bacc55c 4438 }
8fd75e12 4439 kunmap_atomic(kaddr);
daea3e73
AK		 4440 kvm_release_page_dirty(page);
4441
4442 if (!exchanged)
4443 return X86EMUL_CMPXCHG_FAILED;
4444
d3714010 4445 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4446 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4447
4448 return X86EMUL_CONTINUE;
4a5f48f6 4449
3200f405 4450emul_write:
daea3e73 4451 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4452
0f65dd70 4453 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4454}
4455
cf8f70bf
GN		 4456static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4457{
4458 /* TODO: String I/O for in kernel device */
4459 int r;
4460
4461 if (vcpu->arch.pio.in)
4462 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4463 vcpu->arch.pio.size, pd);
4464 else
4465 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4466 vcpu->arch.pio.port, vcpu->arch.pio.size,
4467 pd);
4468 return r;
4469}
4470
6f6fbe98
XG		 4471static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4472 unsigned short port, void *val,
4473 unsigned int count, bool in)
cf8f70bf 4474{
6f6fbe98 4475 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4476
4477 vcpu->arch.pio.port = port;
6f6fbe98 4478 vcpu->arch.pio.in = in;
7972995b 4479 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4480 vcpu->arch.pio.size = size;
4481
4482 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4483 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4484 return 1;
4485 }
4486
4487 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4488 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4489 vcpu->run->io.size = size;
4490 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4491 vcpu->run->io.count = count;
4492 vcpu->run->io.port = port;
4493
4494 return 0;
4495}
4496
6f6fbe98
XG		 4497static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4498 int size, unsigned short port, void *val,
4499 unsigned int count)
cf8f70bf 4500{
ca1d4a9e 4501 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4502 int ret;
ca1d4a9e 4503
6f6fbe98
XG		 4504 if (vcpu->arch.pio.count)
4505 goto data_avail;
cf8f70bf 4506
6f6fbe98
XG		 4507 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4508 if (ret) {
4509data_avail:
4510 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4511 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4512 return 1;
4513 }
4514
cf8f70bf
GN		 4515 return 0;
4516}
4517
6f6fbe98
XG		 4518static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4519 int size, unsigned short port,
4520 const void *val, unsigned int count)
4521{
4522 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4523
4524 memcpy(vcpu->arch.pio_data, val, size * count);
4525 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4526}
4527
bbd9b64e
CO		 4528static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4529{
4530 return kvm_x86_ops->get_segment_base(vcpu, seg);
4531}
4532
3cb16fe7 4533static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4534{
3cb16fe7 4535 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4536}
4537
f5f48ee1
SY		 4538int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4539{
4540 if (!need_emulate_wbinvd(vcpu))
4541 return X86EMUL_CONTINUE;
4542
4543 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4544 int cpu = get_cpu();
4545
4546 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4547 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4548 wbinvd_ipi, NULL, 1);
2eec7343 4549 put_cpu();
f5f48ee1 4550 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4551 } else
4552 wbinvd();
f5f48ee1
SY		 4553 return X86EMUL_CONTINUE;
4554}
4555EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4556
bcaf5cc5
AK		 4557static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4558{
4559 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4560}
4561
717746e3 4562int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4563{
717746e3 4564 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4565}
4566
717746e3 4567int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4568{
338dbc97 4569
717746e3 4570 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4571}
4572
52a46617 4573static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4574{
52a46617 4575 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4576}
4577
717746e3 4578static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4579{
717746e3 4580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4581 unsigned long value;
4582
4583 switch (cr) {
4584 case 0:
4585 value = kvm_read_cr0(vcpu);
4586 break;
4587 case 2:
4588 value = vcpu->arch.cr2;
4589 break;
4590 case 3:
9f8fe504 4591 value = kvm_read_cr3(vcpu);
52a46617
GN		 4592 break;
4593 case 4:
4594 value = kvm_read_cr4(vcpu);
4595 break;
4596 case 8:
4597 value = kvm_get_cr8(vcpu);
4598 break;
4599 default:
a737f256 4600 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4601 return 0;
4602 }
4603
4604 return value;
4605}
4606
717746e3 4607static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4608{
717746e3 4609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4610 int res = 0;
4611
52a46617
GN		 4612 switch (cr) {
4613 case 0:
49a9b07e 4614 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4615 break;
4616 case 2:
4617 vcpu->arch.cr2 = val;
4618 break;
4619 case 3:
2390218b 4620 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4621 break;
4622 case 4:
a83b29c6 4623 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4624 break;
4625 case 8:
eea1cff9 4626 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4627 break;
4628 default:
a737f256 4629 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4630 res = -1;
52a46617 4631 }
0f12244f
GN		 4632
4633 return res;
52a46617
GN		 4634}
4635
4cee4798
KW		 4636static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4637{
4638 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4639}
4640
717746e3 4641static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4642{
717746e3 4643 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4644}
4645
4bff1e86 4646static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4647{
4bff1e86 4648 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4649}
4650
4bff1e86 4651static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4652{
4bff1e86 4653 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4654}
4655
1ac9d0cf
AK		 4656static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4657{
4658 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4659}
4660
4661static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4662{
4663 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4664}
4665
4bff1e86
AK		 4666static unsigned long emulator_get_cached_segment_base(
4667 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4668{
4bff1e86 4669 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4670}
4671
1aa36616
AK		 4672static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4673 struct desc_struct *desc, u32 *base3,
4674 int seg)
2dafc6c2
GN		 4675{
4676 struct kvm_segment var;
4677
4bff1e86 4678 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4679 *selector = var.selector;
2dafc6c2 4680
378a8b09
GN		 4681 if (var.unusable) {
4682 memset(desc, 0, sizeof(*desc));
2dafc6c2 4683 return false;
378a8b09 4684 }
2dafc6c2
GN		 4685
4686 if (var.g)
4687 var.limit >>= 12;
4688 set_desc_limit(desc, var.limit);
4689 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4690#ifdef CONFIG_X86_64
4691 if (base3)
4692 *base3 = var.base >> 32;
4693#endif
2dafc6c2
GN		 4694 desc->type = var.type;
4695 desc->s = var.s;
4696 desc->dpl = var.dpl;
4697 desc->p = var.present;
4698 desc->avl = var.avl;
4699 desc->l = var.l;
4700 desc->d = var.db;
4701 desc->g = var.g;
4702
4703 return true;
4704}
4705
1aa36616
AK		 4706static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4707 struct desc_struct *desc, u32 base3,
4708 int seg)
2dafc6c2 4709{
4bff1e86 4710 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4711 struct kvm_segment var;
4712
1aa36616 4713 var.selector = selector;
2dafc6c2 4714 var.base = get_desc_base(desc);
5601d05b
GN		 4715#ifdef CONFIG_X86_64
4716 var.base |= ((u64)base3) << 32;
4717#endif
2dafc6c2
GN		 4718 var.limit = get_desc_limit(desc);
4719 if (desc->g)
4720 var.limit = (var.limit << 12) | 0xfff;
4721 var.type = desc->type;
4722 var.present = desc->p;
4723 var.dpl = desc->dpl;
4724 var.db = desc->d;
4725 var.s = desc->s;
4726 var.l = desc->l;
4727 var.g = desc->g;
4728 var.avl = desc->avl;
4729 var.present = desc->p;
4730 var.unusable = !var.present;
4731 var.padding = 0;
4732
4733 kvm_set_segment(vcpu, &var, seg);
4734 return;
4735}
4736
717746e3
AK		 4737static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4738 u32 msr_index, u64 *pdata)
4739{
4740 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4741}
4742
4743static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4744 u32 msr_index, u64 data)
4745{
8fe8ab46
WA		 4746 struct msr_data msr;
4747
4748 msr.data = data;
4749 msr.index = msr_index;
4750 msr.host_initiated = false;
4751 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4752}
4753
222d21aa
AK		 4754static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4755 u32 pmc, u64 *pdata)
4756{
4757 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4758}
4759
6c3287f7
AK		 4760static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4761{
4762 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4763}
4764
5037f6f3
AK		 4765static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4766{
4767 preempt_disable();
5197b808 4768 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4769 /*
4770 * CR0.TS may reference the host fpu state, not the guest fpu state,
4771 * so it may be clear at this point.
4772 */
4773 clts();
4774}
4775
4776static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4777{
4778 preempt_enable();
4779}
4780
2953538e 4781static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4782 struct x86_instruction_info *info,
c4f035c6
AK		 4783 enum x86_intercept_stage stage)
4784{
2953538e 4785 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4786}
4787
0017f93a 4788static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4789 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4790{
0017f93a 4791 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4792}
4793
dd856efa
AK		 4794static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4795{
4796 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4797}
4798
4799static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4800{
4801 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4802}
4803
0225fb50 4804static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4805 .read_gpr = emulator_read_gpr,
4806 .write_gpr = emulator_write_gpr,
1871c602 4807 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4808 .write_std = kvm_write_guest_virt_system,
1871c602 4809 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4810 .read_emulated = emulator_read_emulated,
4811 .write_emulated = emulator_write_emulated,
4812 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4813 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4814 .pio_in_emulated = emulator_pio_in_emulated,
4815 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4816 .get_segment = emulator_get_segment,
4817 .set_segment = emulator_set_segment,
5951c442 4818 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4819 .get_gdt = emulator_get_gdt,
160ce1f1 4820 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4821 .set_gdt = emulator_set_gdt,
4822 .set_idt = emulator_set_idt,
52a46617
GN		 4823 .get_cr = emulator_get_cr,
4824 .set_cr = emulator_set_cr,
4cee4798 4825 .set_rflags = emulator_set_rflags,
9c537244 4826 .cpl = emulator_get_cpl,
35aa5375
GN		 4827 .get_dr = emulator_get_dr,
4828 .set_dr = emulator_set_dr,
717746e3
AK		 4829 .set_msr = emulator_set_msr,
4830 .get_msr = emulator_get_msr,
222d21aa 4831 .read_pmc = emulator_read_pmc,
6c3287f7 4832 .halt = emulator_halt,
bcaf5cc5 4833 .wbinvd = emulator_wbinvd,
d6aa1000 4834 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4835 .get_fpu = emulator_get_fpu,
4836 .put_fpu = emulator_put_fpu,
c4f035c6 4837 .intercept = emulator_intercept,
bdb42f5a 4838 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4839};
4840
95cb2295
GN		 4841static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4842{
4843 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4844 /*
4845 * an sti; sti; sequence only disable interrupts for the first
4846 * instruction. So, if the last instruction, be it emulated or
4847 * not, left the system with the INT_STI flag enabled, it
4848 * means that the last instruction is an sti. We should not
4849 * leave the flag on in this case. The same goes for mov ss
4850 */
4851 if (!(int_shadow & mask))
4852 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4853}
4854
54b8486f
GN		 4855static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4856{
4857 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4858 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4859 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4860 else if (ctxt->exception.error_code_valid)
4861 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4862 ctxt->exception.error_code);
54b8486f 4863 else
da9cb575 4864 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4865}
4866
dd856efa 4867static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4868{
1ce19dc1
BP		 4869 memset(&ctxt->opcode_len, 0,
4870 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4871
9dac77fa
AK		 4872 ctxt->fetch.start = 0;
4873 ctxt->fetch.end = 0;
4874 ctxt->io_read.pos = 0;
4875 ctxt->io_read.end = 0;
4876 ctxt->mem_read.pos = 0;
4877 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4878}
4879
8ec4722d
MG		 4880static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4881{
adf52235 4882 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4883 int cs_db, cs_l;
4884
8ec4722d
MG		 4885 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4886
adf52235
TY		 4887 ctxt->eflags = kvm_get_rflags(vcpu);
4888 ctxt->eip = kvm_rip_read(vcpu);
4889 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4890 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4891 cs_l ? X86EMUL_MODE_PROT64 :
4892 cs_db ? X86EMUL_MODE_PROT32 :
4893 X86EMUL_MODE_PROT16;
4894 ctxt->guest_mode = is_guest_mode(vcpu);
4895
dd856efa 4896 init_decode_cache(ctxt);
7ae441ea 4897 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4898}
4899
71f9833b 4900int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4901{
9d74191a 4902 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4903 int ret;
4904
4905 init_emulate_ctxt(vcpu);
4906
9dac77fa
AK		 4907 ctxt->op_bytes = 2;
4908 ctxt->ad_bytes = 2;
4909 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4910 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4911
4912 if (ret != X86EMUL_CONTINUE)
4913 return EMULATE_FAIL;
4914
9dac77fa 4915 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4916 kvm_rip_write(vcpu, ctxt->eip);
4917 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4918
4919 if (irq == NMI_VECTOR)
7460fb4a 4920 vcpu->arch.nmi_pending = 0;
63995653
MG		 4921 else
4922 vcpu->arch.interrupt.pending = false;
4923
4924 return EMULATE_DONE;
4925}
4926EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4927
6d77dbfc
GN		 4928static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4929{
fc3a9157
JR		 4930 int r = EMULATE_DONE;
4931
6d77dbfc
GN		 4932 ++vcpu->stat.insn_emulation_fail;
4933 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4934 if (!is_guest_mode(vcpu)) {
4935 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4936 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4937 vcpu->run->internal.ndata = 0;
4938 r = EMULATE_FAIL;
4939 }
6d77dbfc 4940 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4941
4942 return r;
6d77dbfc
GN		 4943}
4944
93c05d3e 4945static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4946 bool write_fault_to_shadow_pgtable,
4947 int emulation_type)
a6f177ef 4948{
95b3cf69 4949 gpa_t gpa = cr2;
8e3d9d06 4950 pfn_t pfn;
a6f177ef 4951
991eebf9
GN		 4952 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4953 return false;
4954
95b3cf69
XG		 4955 if (!vcpu->arch.mmu.direct_map) {
4956 /*
4957 * Write permission should be allowed since only
4958 * write access need to be emulated.
4959 */
4960 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4961
95b3cf69
XG		 4962 /*
4963 * If the mapping is invalid in guest, let cpu retry
4964 * it to generate fault.
4965 */
4966 if (gpa == UNMAPPED_GVA)
4967 return true;
4968 }
a6f177ef 4969
8e3d9d06
XG		 4970 /*
4971 * Do not retry the unhandleable instruction if it faults on the
4972 * readonly host memory, otherwise it will goto a infinite loop:
4973 * retry instruction -> write #PF -> emulation fail -> retry
4974 * instruction -> ...
4975 */
4976 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4977
4978 /*
4979 * If the instruction failed on the error pfn, it can not be fixed,
4980 * report the error to userspace.
4981 */
4982 if (is_error_noslot_pfn(pfn))
4983 return false;
4984
4985 kvm_release_pfn_clean(pfn);
4986
4987 /* The instructions are well-emulated on direct mmu. */
4988 if (vcpu->arch.mmu.direct_map) {
4989 unsigned int indirect_shadow_pages;
4990
4991 spin_lock(&vcpu->kvm->mmu_lock);
4992 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4993 spin_unlock(&vcpu->kvm->mmu_lock);
4994
4995 if (indirect_shadow_pages)
4996 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4997
a6f177ef 4998 return true;
8e3d9d06 4999 }
a6f177ef 5000
95b3cf69
XG		 5001 /*
5002 * if emulation was due to access to shadowed page table
5003 * and it failed try to unshadow page and re-enter the
5004 * guest to let CPU execute the instruction.
5005 */
5006 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5007
5008 /*
5009 * If the access faults on its page table, it can not
5010 * be fixed by unprotecting shadow page and it should
5011 * be reported to userspace.
5012 */
5013 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5014}
5015
1cb3f3ae
XG		 5016static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5017 unsigned long cr2, int emulation_type)
5018{
5019 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5020 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5021
5022 last_retry_eip = vcpu->arch.last_retry_eip;
5023 last_retry_addr = vcpu->arch.last_retry_addr;
5024
5025 /*
5026 * If the emulation is caused by #PF and it is non-page_table
5027 * writing instruction, it means the VM-EXIT is caused by shadow
5028 * page protected, we can zap the shadow page and retry this
5029 * instruction directly.
5030 *
5031 * Note: if the guest uses a non-page-table modifying instruction
5032 * on the PDE that points to the instruction, then we will unmap
5033 * the instruction and go to an infinite loop. So, we cache the
5034 * last retried eip and the last fault address, if we meet the eip
5035 * and the address again, we can break out of the potential infinite
5036 * loop.
5037 */
5038 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5039
5040 if (!(emulation_type & EMULTYPE_RETRY))
5041 return false;
5042
5043 if (x86_page_table_writing_insn(ctxt))
5044 return false;
5045
5046 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5047 return false;
5048
5049 vcpu->arch.last_retry_eip = ctxt->eip;
5050 vcpu->arch.last_retry_addr = cr2;
5051
5052 if (!vcpu->arch.mmu.direct_map)
5053 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5054
22368028 5055 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5056
5057 return true;
5058}
5059
716d51ab
GN		 5060static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5061static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5062
4a1e10d5
PB		 5063static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5064 unsigned long *db)
5065{
5066 u32 dr6 = 0;
5067 int i;
5068 u32 enable, rwlen;
5069
5070 enable = dr7;
5071 rwlen = dr7 >> 16;
5072 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5073 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5074 dr6 |= (1 << i);
5075 return dr6;
5076}
5077
663f4c61
PB		 5078static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5079{
5080 struct kvm_run *kvm_run = vcpu->run;
5081
5082 /*
5083 * Use the "raw" value to see if TF was passed to the processor.
5084 * Note that the new value of the flags has not been saved yet.
5085 *
5086 * This is correct even for TF set by the guest, because "the
5087 * processor will not generate this exception after the instruction
5088 * that sets the TF flag".
5089 */
5090 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5091
5092 if (unlikely(rflags & X86_EFLAGS_TF)) {
5093 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5094 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5095 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5096 kvm_run->debug.arch.exception = DB_VECTOR;
5097 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5098 *r = EMULATE_USER_EXIT;
5099 } else {
5100 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5101 /*
5102 * "Certain debug exceptions may clear bit 0-3. The
5103 * remaining contents of the DR6 register are never
5104 * cleared by the processor".
5105 */
5106 vcpu->arch.dr6 &= ~15;
5107 vcpu->arch.dr6 |= DR6_BS;
5108 kvm_queue_exception(vcpu, DB_VECTOR);
5109 }
5110 }
5111}
5112
4a1e10d5
PB		 5113static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5114{
5115 struct kvm_run *kvm_run = vcpu->run;
5116 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5117 u32 dr6 = 0;
5118
5119 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5120 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5121 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5122 vcpu->arch.guest_debug_dr7,
5123 vcpu->arch.eff_db);
5124
5125 if (dr6 != 0) {
5126 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5127 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5128 get_segment_base(vcpu, VCPU_SREG_CS);
5129
5130 kvm_run->debug.arch.exception = DB_VECTOR;
5131 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5132 *r = EMULATE_USER_EXIT;
5133 return true;
5134 }
5135 }
5136
5137 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5138 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5139 vcpu->arch.dr7,
5140 vcpu->arch.db);
5141
5142 if (dr6 != 0) {
5143 vcpu->arch.dr6 &= ~15;
5144 vcpu->arch.dr6 |= dr6;
5145 kvm_queue_exception(vcpu, DB_VECTOR);
5146 *r = EMULATE_DONE;
5147 return true;
5148 }
5149 }
5150
5151 return false;
5152}
5153
51d8b661
AP		 5154int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5155 unsigned long cr2,
dc25e89e
AP		 5156 int emulation_type,
5157 void *insn,
5158 int insn_len)
bbd9b64e 5159{
95cb2295 5160 int r;
9d74191a 5161 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5162 bool writeback = true;
93c05d3e 5163 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5164
93c05d3e
XG		 5165 /*
5166 * Clear write_fault_to_shadow_pgtable here to ensure it is
5167 * never reused.
5168 */
5169 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5170 kvm_clear_exception_queue(vcpu);
8d7d8102 5171
571008da 5172 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5173 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5174
5175 /*
5176 * We will reenter on the same instruction since
5177 * we do not set complete_userspace_io. This does not
5178 * handle watchpoints yet, those would be handled in
5179 * the emulate_ops.
5180 */
5181 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5182 return r;
5183
9d74191a
TY		 5184 ctxt->interruptibility = 0;
5185 ctxt->have_exception = false;
5186 ctxt->perm_ok = false;
bbd9b64e 5187
b51e974f 5188 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5189
9d74191a 5190 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5191
e46479f8 5192 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5193 ++vcpu->stat.insn_emulation;
1d2887e2 5194 if (r != EMULATION_OK) {
4005996e
AK		 5195 if (emulation_type & EMULTYPE_TRAP_UD)
5196 return EMULATE_FAIL;
991eebf9
GN		 5197 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5198 emulation_type))
bbd9b64e 5199 return EMULATE_DONE;
6d77dbfc
GN		 5200 if (emulation_type & EMULTYPE_SKIP)
5201 return EMULATE_FAIL;
5202 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5203 }
5204 }
5205
ba8afb6b 5206 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5207 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5208 return EMULATE_DONE;
5209 }
5210
1cb3f3ae
XG		 5211 if (retry_instruction(ctxt, cr2, emulation_type))
5212 return EMULATE_DONE;
5213
7ae441ea 5214 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5215 changes registers values during IO operation */
7ae441ea
GN		 5216 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5217 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5218 emulator_invalidate_register_cache(ctxt);
7ae441ea 5219 }
4d2179e1 5220
5cd21917 5221restart:
9d74191a 5222 r = x86_emulate_insn(ctxt);
bbd9b64e 5223
775fde86
JR		 5224 if (r == EMULATION_INTERCEPTED)
5225 return EMULATE_DONE;
5226
d2ddd1c4 5227 if (r == EMULATION_FAILED) {
991eebf9
GN		 5228 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5229 emulation_type))
c3cd7ffa
GN		 5230 return EMULATE_DONE;
5231
6d77dbfc 5232 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5233 }
5234
9d74191a 5235 if (ctxt->have_exception) {
54b8486f 5236 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5237 r = EMULATE_DONE;
5238 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5239 if (!vcpu->arch.pio.in) {
5240 /* FIXME: return into emulator if single-stepping. */
3457e419 5241 vcpu->arch.pio.count = 0;
0912c977 5242 } else {
7ae441ea 5243 writeback = false;
716d51ab
GN		 5244 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5245 }
ac0a48c3 5246 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5247 } else if (vcpu->mmio_needed) {
5248 if (!vcpu->mmio_is_write)
5249 writeback = false;
ac0a48c3 5250 r = EMULATE_USER_EXIT;
716d51ab 5251 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5252 } else if (r == EMULATION_RESTART)
5cd21917 5253 goto restart;
d2ddd1c4
GN		 5254 else
5255 r = EMULATE_DONE;
f850e2e6 5256
7ae441ea 5257 if (writeback) {
9d74191a 5258 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5259 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5260 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5261 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5262 if (r == EMULATE_DONE)
5263 kvm_vcpu_check_singlestep(vcpu, &r);
5264 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5265 } else
5266 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5267
5268 return r;
de7d789a 5269}
51d8b661 5270EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5271
cf8f70bf 5272int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5273{
cf8f70bf 5274 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5275 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5276 size, port, &val, 1);
cf8f70bf 5277 /* do not return to emulator after return from userspace */
7972995b 5278 vcpu->arch.pio.count = 0;
de7d789a
CO		 5279 return ret;
5280}
cf8f70bf 5281EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5282
8cfdc000
ZA		 5283static void tsc_bad(void *info)
5284{
0a3aee0d 5285 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5286}
5287
5288static void tsc_khz_changed(void *data)
c8076604 5289{
8cfdc000
ZA		 5290 struct cpufreq_freqs *freq = data;
5291 unsigned long khz = 0;
5292
5293 if (data)
5294 khz = freq->new;
5295 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5296 khz = cpufreq_quick_get(raw_smp_processor_id());
5297 if (!khz)
5298 khz = tsc_khz;
0a3aee0d 5299 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5300}
5301
c8076604
GH		 5302static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5303 void *data)
5304{
5305 struct cpufreq_freqs *freq = data;
5306 struct kvm *kvm;
5307 struct kvm_vcpu *vcpu;
5308 int i, send_ipi = 0;
5309
8cfdc000
ZA		 5310 /*
5311 * We allow guests to temporarily run on slowing clocks,
5312 * provided we notify them after, or to run on accelerating
5313 * clocks, provided we notify them before. Thus time never
5314 * goes backwards.
5315 *
5316 * However, we have a problem. We can't atomically update
5317 * the frequency of a given CPU from this function; it is
5318 * merely a notifier, which can be called from any CPU.
5319 * Changing the TSC frequency at arbitrary points in time
5320 * requires a recomputation of local variables related to
5321 * the TSC for each VCPU. We must flag these local variables
5322 * to be updated and be sure the update takes place with the
5323 * new frequency before any guests proceed.
5324 *
5325 * Unfortunately, the combination of hotplug CPU and frequency
5326 * change creates an intractable locking scenario; the order
5327 * of when these callouts happen is undefined with respect to
5328 * CPU hotplug, and they can race with each other. As such,
5329 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5330 * undefined; you can actually have a CPU frequency change take
5331 * place in between the computation of X and the setting of the
5332 * variable. To protect against this problem, all updates of
5333 * the per_cpu tsc_khz variable are done in an interrupt
5334 * protected IPI, and all callers wishing to update the value
5335 * must wait for a synchronous IPI to complete (which is trivial
5336 * if the caller is on the CPU already). This establishes the
5337 * necessary total order on variable updates.
5338 *
5339 * Note that because a guest time update may take place
5340 * anytime after the setting of the VCPU's request bit, the
5341 * correct TSC value must be set before the request. However,
5342 * to ensure the update actually makes it to any guest which
5343 * starts running in hardware virtualization between the set
5344 * and the acquisition of the spinlock, we must also ping the
5345 * CPU after setting the request bit.
5346 *
5347 */
5348
c8076604
GH		 5349 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5350 return 0;
5351 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5352 return 0;
8cfdc000
ZA		 5353
5354 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5355
2f303b74 5356 spin_lock(&kvm_lock);
c8076604 5357 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5358 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5359 if (vcpu->cpu != freq->cpu)
5360 continue;
c285545f 5361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5362 if (vcpu->cpu != smp_processor_id())
8cfdc000 5363 send_ipi = 1;
c8076604
GH		 5364 }
5365 }
2f303b74 5366 spin_unlock(&kvm_lock);
c8076604
GH		 5367
5368 if (freq->old < freq->new && send_ipi) {
5369 /*
5370 * We upscale the frequency. Must make the guest
5371 * doesn't see old kvmclock values while running with
5372 * the new frequency, otherwise we risk the guest sees
5373 * time go backwards.
5374 *
5375 * In case we update the frequency for another cpu
5376 * (which might be in guest context) send an interrupt
5377 * to kick the cpu out of guest context. Next time
5378 * guest context is entered kvmclock will be updated,
5379 * so the guest will not see stale values.
5380 */
8cfdc000 5381 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5382 }
5383 return 0;
5384}
5385
5386static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5387 .notifier_call = kvmclock_cpufreq_notifier
5388};
5389
5390static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5391 unsigned long action, void *hcpu)
5392{
5393 unsigned int cpu = (unsigned long)hcpu;
5394
5395 switch (action) {
5396 case CPU_ONLINE:
5397 case CPU_DOWN_FAILED:
5398 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5399 break;
5400 case CPU_DOWN_PREPARE:
5401 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5402 break;
5403 }
5404 return NOTIFY_OK;
5405}
5406
5407static struct notifier_block kvmclock_cpu_notifier_block = {
5408 .notifier_call = kvmclock_cpu_notifier,
5409 .priority = -INT_MAX
c8076604
GH		 5410};
5411
b820cc0c
ZA		 5412static void kvm_timer_init(void)
5413{
5414 int cpu;
5415
c285545f 5416 max_tsc_khz = tsc_khz;
460dd42e
SB		 5417
5418 cpu_notifier_register_begin();
b820cc0c 5419 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5420#ifdef CONFIG_CPU_FREQ
5421 struct cpufreq_policy policy;
5422 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5423 cpu = get_cpu();
5424 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5425 if (policy.cpuinfo.max_freq)
5426 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5427 put_cpu();
c285545f 5428#endif
b820cc0c
ZA		 5429 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5430 CPUFREQ_TRANSITION_NOTIFIER);
5431 }
c285545f 5432 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5433 for_each_online_cpu(cpu)
5434 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5435
5436 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5437 cpu_notifier_register_done();
5438
b820cc0c
ZA		 5439}
5440
ff9d07a0
ZY		 5441static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5442
f5132b01 5443int kvm_is_in_guest(void)
ff9d07a0 5444{
086c9855 5445 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5446}
5447
5448static int kvm_is_user_mode(void)
5449{
5450 int user_mode = 3;
dcf46b94 5451
086c9855
AS		 5452 if (__this_cpu_read(current_vcpu))
5453 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5454
ff9d07a0
ZY		 5455 return user_mode != 0;
5456}
5457
5458static unsigned long kvm_get_guest_ip(void)
5459{
5460 unsigned long ip = 0;
dcf46b94 5461
086c9855
AS		 5462 if (__this_cpu_read(current_vcpu))
5463 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5464
ff9d07a0
ZY		 5465 return ip;
5466}
5467
5468static struct perf_guest_info_callbacks kvm_guest_cbs = {
5469 .is_in_guest = kvm_is_in_guest,
5470 .is_user_mode = kvm_is_user_mode,
5471 .get_guest_ip = kvm_get_guest_ip,
5472};
5473
5474void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5475{
086c9855 5476 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5477}
5478EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5479
5480void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5481{
086c9855 5482 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5483}
5484EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5485
ce88decf
XG		 5486static void kvm_set_mmio_spte_mask(void)
5487{
5488 u64 mask;
5489 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5490
5491 /*
5492 * Set the reserved bits and the present bit of an paging-structure
5493 * entry to generate page fault with PFER.RSV = 1.
5494 */
885032b9
XG		 5495 /* Mask the reserved physical address bits. */
5496 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5497
5498 /* Bit 62 is always reserved for 32bit host. */
5499 mask |= 0x3ull << 62;
5500
5501 /* Set the present bit. */
ce88decf
XG		 5502 mask |= 1ull;
5503
5504#ifdef CONFIG_X86_64
5505 /*
5506 * If reserved bit is not supported, clear the present bit to disable
5507 * mmio page fault.
5508 */
5509 if (maxphyaddr == 52)
5510 mask &= ~1ull;
5511#endif
5512
5513 kvm_mmu_set_mmio_spte_mask(mask);
5514}
5515
16e8d74d
MT		 5516#ifdef CONFIG_X86_64
5517static void pvclock_gtod_update_fn(struct work_struct *work)
5518{
d828199e
MT		 5519 struct kvm *kvm;
5520
5521 struct kvm_vcpu *vcpu;
5522 int i;
5523
2f303b74 5524 spin_lock(&kvm_lock);
d828199e
MT		 5525 list_for_each_entry(kvm, &vm_list, vm_list)
5526 kvm_for_each_vcpu(i, vcpu, kvm)
5527 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5528 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5529 spin_unlock(&kvm_lock);
16e8d74d
MT		 5530}
5531
5532static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5533
5534/*
5535 * Notification about pvclock gtod data update.
5536 */
5537static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5538 void *priv)
5539{
5540 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5541 struct timekeeper *tk = priv;
5542
5543 update_pvclock_gtod(tk);
5544
5545 /* disable master clock if host does not trust, or does not
5546 * use, TSC clocksource
5547 */
5548 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5549 atomic_read(&kvm_guest_has_master_clock) != 0)
5550 queue_work(system_long_wq, &pvclock_gtod_work);
5551
5552 return 0;
5553}
5554
5555static struct notifier_block pvclock_gtod_notifier = {
5556 .notifier_call = pvclock_gtod_notify,
5557};
5558#endif
5559
f8c16bba 5560int kvm_arch_init(void *opaque)
043405e1 5561{
b820cc0c 5562 int r;
6b61edf7 5563 struct kvm_x86_ops *ops = opaque;
f8c16bba 5564
f8c16bba
ZX		 5565 if (kvm_x86_ops) {
5566 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5567 r = -EEXIST;
5568 goto out;
f8c16bba
ZX		 5569 }
5570
5571 if (!ops->cpu_has_kvm_support()) {
5572 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5573 r = -EOPNOTSUPP;
5574 goto out;
f8c16bba
ZX		 5575 }
5576 if (ops->disabled_by_bios()) {
5577 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5578 r = -EOPNOTSUPP;
5579 goto out;
f8c16bba
ZX		 5580 }
5581
013f6a5d
MT		 5582 r = -ENOMEM;
5583 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5584 if (!shared_msrs) {
5585 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5586 goto out;
5587 }
5588
97db56ce
AK		 5589 r = kvm_mmu_module_init();
5590 if (r)
013f6a5d 5591 goto out_free_percpu;
97db56ce 5592
ce88decf 5593 kvm_set_mmio_spte_mask();
97db56ce 5594
f8c16bba 5595 kvm_x86_ops = ops;
920c8377
PB		 5596 kvm_init_msr_list();
5597
7b52345e 5598 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5599 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5600
b820cc0c 5601 kvm_timer_init();
c8076604 5602
ff9d07a0
ZY		 5603 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5604
2acf923e
DC		 5605 if (cpu_has_xsave)
5606 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5607
c5cc421b 5608 kvm_lapic_init();
16e8d74d
MT		 5609#ifdef CONFIG_X86_64
5610 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5611#endif
5612
f8c16bba 5613 return 0;
56c6d28a 5614
013f6a5d
MT		 5615out_free_percpu:
5616 free_percpu(shared_msrs);
56c6d28a 5617out:
56c6d28a 5618 return r;
043405e1 5619}
8776e519 5620
f8c16bba
ZX		 5621void kvm_arch_exit(void)
5622{
ff9d07a0
ZY		 5623 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5624
888d256e
JK		 5625 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5626 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5627 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5628 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5629#ifdef CONFIG_X86_64
5630 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5631#endif
f8c16bba 5632 kvm_x86_ops = NULL;
56c6d28a 5633 kvm_mmu_module_exit();
013f6a5d 5634 free_percpu(shared_msrs);
56c6d28a 5635}
f8c16bba 5636
8776e519
HB		 5637int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5638{
5639 ++vcpu->stat.halt_exits;
5640 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5641 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5642 return 1;
5643 } else {
5644 vcpu->run->exit_reason = KVM_EXIT_HLT;
5645 return 0;
5646 }
5647}
5648EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5649
55cd8e5a
GN		 5650int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5651{
5652 u64 param, ingpa, outgpa, ret;
5653 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5654 bool fast, longmode;
5655 int cs_db, cs_l;
5656
5657 /*
5658 * hypercall generates UD from non zero cpl and real mode
5659 * per HYPER-V spec
5660 */
3eeb3288 5661 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5662 kvm_queue_exception(vcpu, UD_VECTOR);
5663 return 0;
5664 }
5665
5666 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5667 longmode = is_long_mode(vcpu) && cs_l == 1;
5668
5669 if (!longmode) {
ccd46936
GN		 5670 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5671 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5672 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5673 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5674 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5675 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5676 }
5677#ifdef CONFIG_X86_64
5678 else {
5679 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5680 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5681 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5682 }
5683#endif
5684
5685 code = param & 0xffff;
5686 fast = (param >> 16) & 0x1;
5687 rep_cnt = (param >> 32) & 0xfff;
5688 rep_idx = (param >> 48) & 0xfff;
5689
5690 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5691
c25bc163
GN		 5692 switch (code) {
5693 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5694 kvm_vcpu_on_spin(vcpu);
5695 break;
5696 default:
5697 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5698 break;
5699 }
55cd8e5a
GN		 5700
5701 ret = res | (((u64)rep_done & 0xfff) << 32);
5702 if (longmode) {
5703 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5704 } else {
5705 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5706 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5707 }
5708
5709 return 1;
5710}
5711
6aef266c
SV		 5712/*
5713 * kvm_pv_kick_cpu_op: Kick a vcpu.
5714 *
5715 * @apicid - apicid of vcpu to be kicked.
5716 */
5717static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5718{
24d2166b 5719 struct kvm_lapic_irq lapic_irq;
6aef266c 5720
24d2166b
R		 5721 lapic_irq.shorthand = 0;
5722 lapic_irq.dest_mode = 0;
5723 lapic_irq.dest_id = apicid;
6aef266c 5724
24d2166b
R		 5725 lapic_irq.delivery_mode = APIC_DM_REMRD;
5726 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5727}
5728
8776e519
HB		 5729int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5730{
5731 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5732 int r = 1;
8776e519 5733
55cd8e5a
GN		 5734 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5735 return kvm_hv_hypercall(vcpu);
5736
5fdbf976
MT		 5737 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5738 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5739 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5740 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5741 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5742
229456fc 5743 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5744
8776e519
HB		 5745 if (!is_long_mode(vcpu)) {
5746 nr &= 0xFFFFFFFF;
5747 a0 &= 0xFFFFFFFF;
5748 a1 &= 0xFFFFFFFF;
5749 a2 &= 0xFFFFFFFF;
5750 a3 &= 0xFFFFFFFF;
5751 }
5752
07708c4a
JK		 5753 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5754 ret = -KVM_EPERM;
5755 goto out;
5756 }
5757
8776e519 5758 switch (nr) {
b93463aa
AK		 5759 case KVM_HC_VAPIC_POLL_IRQ:
5760 ret = 0;
5761 break;
6aef266c
SV		 5762 case KVM_HC_KICK_CPU:
5763 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5764 ret = 0;
5765 break;
8776e519
HB		 5766 default:
5767 ret = -KVM_ENOSYS;
5768 break;
5769 }
07708c4a 5770out:
5fdbf976 5771 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5772 ++vcpu->stat.hypercalls;
2f333bcb 5773 return r;
8776e519
HB		 5774}
5775EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5776
b6785def 5777static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5778{
d6aa1000 5779 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5780 char instruction[3];
5fdbf976 5781 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5782
8776e519 5783 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5784
9d74191a 5785 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5786}
5787
b6c7a5dc
HB		 5788/*
5789 * Check if userspace requested an interrupt window, and that the
5790 * interrupt window is open.
5791 *
5792 * No need to exit to userspace if we already have an interrupt queued.
5793 */
851ba692 5794static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5795{
8061823a 5796 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5797 vcpu->run->request_interrupt_window &&
5df56646 5798 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5799}
5800
851ba692 5801static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5802{
851ba692
AK		 5803 struct kvm_run *kvm_run = vcpu->run;
5804
91586a3b 5805 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5806 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5807 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5808 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5809 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5810 else
b6c7a5dc 5811 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5812 kvm_arch_interrupt_allowed(vcpu) &&
5813 !kvm_cpu_has_interrupt(vcpu) &&
5814 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5815}
5816
95ba8273
GN		 5817static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5818{
5819 int max_irr, tpr;
5820
5821 if (!kvm_x86_ops->update_cr8_intercept)
5822 return;
5823
88c808fd
AK		 5824 if (!vcpu->arch.apic)
5825 return;
5826
8db3baa2
GN		 5827 if (!vcpu->arch.apic->vapic_addr)
5828 max_irr = kvm_lapic_find_highest_irr(vcpu);
5829 else
5830 max_irr = -1;
95ba8273
GN		 5831
5832 if (max_irr != -1)
5833 max_irr >>= 4;
5834
5835 tpr = kvm_lapic_get_cr8(vcpu);
5836
5837 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5838}
5839
b6b8a145 5840static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5841{
b6b8a145
JK		 5842 int r;
5843
95ba8273 5844 /* try to reinject previous events if any */
b59bb7bd 5845 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5846 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5847 vcpu->arch.exception.has_error_code,
5848 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5849 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5850 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5851 vcpu->arch.exception.error_code,
5852 vcpu->arch.exception.reinject);
b6b8a145 5853 return 0;
b59bb7bd
GN		 5854 }
5855
95ba8273
GN		 5856 if (vcpu->arch.nmi_injected) {
5857 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5858 return 0;
95ba8273
GN		 5859 }
5860
5861 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5862 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5863 return 0;
5864 }
5865
5866 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5867 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5868 if (r != 0)
5869 return r;
95ba8273
GN		 5870 }
5871
5872 /* try to inject new event if pending */
5873 if (vcpu->arch.nmi_pending) {
5874 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5875 --vcpu->arch.nmi_pending;
95ba8273
GN		 5876 vcpu->arch.nmi_injected = true;
5877 kvm_x86_ops->set_nmi(vcpu);
5878 }
c7c9c56c 5879 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5880 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5881 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5882 false);
5883 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5884 }
5885 }
b6b8a145 5886 return 0;
95ba8273
GN		 5887}
5888
7460fb4a
AK		 5889static void process_nmi(struct kvm_vcpu *vcpu)
5890{
5891 unsigned limit = 2;
5892
5893 /*
5894 * x86 is limited to one NMI running, and one NMI pending after it.
5895 * If an NMI is already in progress, limit further NMIs to just one.
5896 * Otherwise, allow two (and we'll inject the first one immediately).
5897 */
5898 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5899 limit = 1;
5900
5901 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5902 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5903 kvm_make_request(KVM_REQ_EVENT, vcpu);
5904}
5905
3d81bc7e 5906static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5907{
5908 u64 eoi_exit_bitmap[4];
cf9e65b7 5909 u32 tmr[8];
c7c9c56c 5910
3d81bc7e
YZ		 5911 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5912 return;
c7c9c56c
YZ		 5913
5914 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5915 memset(tmr, 0, 32);
c7c9c56c 5916
cf9e65b7 5917 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5918 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5919 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5920}
5921
9357d939
TY		 5922/*
5923 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5924 * exiting to the userspace. Otherwise, the value will be returned to the
5925 * userspace.
5926 */
851ba692 5927static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5928{
5929 int r;
6a8b1d13 5930 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5931 vcpu->run->request_interrupt_window;
730dca42 5932 bool req_immediate_exit = false;
b6c7a5dc 5933
3e007509 5934 if (vcpu->requests) {
a8eeb04a 5935 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5936 kvm_mmu_unload(vcpu);
a8eeb04a 5937 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5938 __kvm_migrate_timers(vcpu);
d828199e
MT		 5939 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5940 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5941 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5942 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5943 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5944 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5945 if (unlikely(r))
5946 goto out;
5947 }
a8eeb04a 5948 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5949 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5950 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5951 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5952 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5953 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5954 r = 0;
5955 goto out;
5956 }
a8eeb04a 5957 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5958 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5959 r = 0;
5960 goto out;
5961 }
a8eeb04a 5962 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5963 vcpu->fpu_active = 0;
5964 kvm_x86_ops->fpu_deactivate(vcpu);
5965 }
af585b92
GN		 5966 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5967 /* Page is swapped out. Do synthetic halt */
5968 vcpu->arch.apf.halted = true;
5969 r = 1;
5970 goto out;
5971 }
c9aaa895
GC		 5972 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5973 record_steal_time(vcpu);
7460fb4a
AK		 5974 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5975 process_nmi(vcpu);
f5132b01
GN		 5976 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5977 kvm_handle_pmu_event(vcpu);
5978 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5979 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5980 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5981 vcpu_scan_ioapic(vcpu);
2f52d58c 5982 }
b93463aa 5983
b463a6f7 5984 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5985 kvm_apic_accept_events(vcpu);
5986 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5987 r = 1;
5988 goto out;
5989 }
5990
b6b8a145
JK		 5991 if (inject_pending_event(vcpu, req_int_win) != 0)
5992 req_immediate_exit = true;
b463a6f7 5993 /* enable NMI/IRQ window open exits if needed */
b6b8a145 5994 else if (vcpu->arch.nmi_pending)
c9a7953f 5995 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5996 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 5997 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 5998
5999 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6000 /*
6001 * Update architecture specific hints for APIC
6002 * virtual interrupt delivery.
6003 */
6004 if (kvm_x86_ops->hwapic_irr_update)
6005 kvm_x86_ops->hwapic_irr_update(vcpu,
6006 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6007 update_cr8_intercept(vcpu);
6008 kvm_lapic_sync_to_vapic(vcpu);
6009 }
6010 }
6011
d8368af8
AK		 6012 r = kvm_mmu_reload(vcpu);
6013 if (unlikely(r)) {
d905c069 6014 goto cancel_injection;
d8368af8
AK		 6015 }
6016
b6c7a5dc
HB		 6017 preempt_disable();
6018
6019 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6020 if (vcpu->fpu_active)
6021 kvm_load_guest_fpu(vcpu);
2acf923e 6022 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6023
6b7e2d09
XG		 6024 vcpu->mode = IN_GUEST_MODE;
6025
01b71917
MT		 6026 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6027
6b7e2d09
XG		 6028 /* We should set ->mode before check ->requests,
6029 * see the comment in make_all_cpus_request.
6030 */
01b71917 6031 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6032
d94e1dc9 6033 local_irq_disable();
32f88400 6034
6b7e2d09 6035 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6036 || need_resched() || signal_pending(current)) {
6b7e2d09 6037 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6038 smp_wmb();
6c142801
AK		 6039 local_irq_enable();
6040 preempt_enable();
01b71917 6041 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6042 r = 1;
d905c069 6043 goto cancel_injection;
6c142801
AK		 6044 }
6045
d6185f20
NHE		 6046 if (req_immediate_exit)
6047 smp_send_reschedule(vcpu->cpu);
6048
b6c7a5dc
HB		 6049 kvm_guest_enter();
6050
42dbaa5a 6051 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6052 set_debugreg(0, 7);
6053 set_debugreg(vcpu->arch.eff_db[0], 0);
6054 set_debugreg(vcpu->arch.eff_db[1], 1);
6055 set_debugreg(vcpu->arch.eff_db[2], 2);
6056 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6057 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6058 }
b6c7a5dc 6059
229456fc 6060 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6061 kvm_x86_ops->run(vcpu);
b6c7a5dc 6062
c77fb5fe
PB		 6063 /*
6064 * Do this here before restoring debug registers on the host. And
6065 * since we do this before handling the vmexit, a DR access vmexit
6066 * can (a) read the correct value of the debug registers, (b) set
6067 * KVM_DEBUGREG_WONT_EXIT again.
6068 */
6069 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6070 int i;
6071
6072 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6073 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6074 for (i = 0; i < KVM_NR_DB_REGS; i++)
6075 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6076 }
6077
24f1e32c
FW		 6078 /*
6079 * If the guest has used debug registers, at least dr7
6080 * will be disabled while returning to the host.
6081 * If we don't have active breakpoints in the host, we don't
6082 * care about the messed up debug address registers. But if
6083 * we have some of them active, restore the old state.
6084 */
59d8eb53 6085 if (hw_breakpoint_active())
24f1e32c 6086 hw_breakpoint_restore();
42dbaa5a 6087
886b470c
MT		 6088 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6089 native_read_tsc());
1d5f066e 6090
6b7e2d09 6091 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6092 smp_wmb();
a547c6db
YZ		 6093
6094 /* Interrupt is enabled by handle_external_intr() */
6095 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6096
6097 ++vcpu->stat.exits;
6098
6099 /*
6100 * We must have an instruction between local_irq_enable() and
6101 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6102 * the interrupt shadow. The stat.exits increment will do nicely.
6103 * But we need to prevent reordering, hence this barrier():
6104 */
6105 barrier();
6106
6107 kvm_guest_exit();
6108
6109 preempt_enable();
6110
f656ce01 6111 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6112
b6c7a5dc
HB		 6113 /*
6114 * Profile KVM exit RIPs:
6115 */
6116 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6117 unsigned long rip = kvm_rip_read(vcpu);
6118 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6119 }
6120
cc578287
ZA		 6121 if (unlikely(vcpu->arch.tsc_always_catchup))
6122 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6123
5cfb1d5a
MT		 6124 if (vcpu->arch.apic_attention)
6125 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6126
851ba692 6127 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6128 return r;
6129
6130cancel_injection:
6131 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6132 if (unlikely(vcpu->arch.apic_attention))
6133 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6134out:
6135 return r;
6136}
b6c7a5dc 6137
09cec754 6138
851ba692 6139static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6140{
6141 int r;
f656ce01 6142 struct kvm *kvm = vcpu->kvm;
d7690175 6143
f656ce01 6144 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6145
6146 r = 1;
6147 while (r > 0) {
af585b92
GN		 6148 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6149 !vcpu->arch.apf.halted)
851ba692 6150 r = vcpu_enter_guest(vcpu);
d7690175 6151 else {
f656ce01 6152 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6153 kvm_vcpu_block(vcpu);
f656ce01 6154 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6155 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6156 kvm_apic_accept_events(vcpu);
09cec754
GN		 6157 switch(vcpu->arch.mp_state) {
6158 case KVM_MP_STATE_HALTED:
6aef266c 6159 vcpu->arch.pv.pv_unhalted = false;
d7690175 6160 vcpu->arch.mp_state =
09cec754
GN		 6161 KVM_MP_STATE_RUNNABLE;
6162 case KVM_MP_STATE_RUNNABLE:
af585b92 6163 vcpu->arch.apf.halted = false;
09cec754 6164 break;
66450a21
JK		 6165 case KVM_MP_STATE_INIT_RECEIVED:
6166 break;
09cec754
GN		 6167 default:
6168 r = -EINTR;
6169 break;
6170 }
6171 }
d7690175
MT		 6172 }
6173
09cec754
GN		 6174 if (r <= 0)
6175 break;
6176
6177 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6178 if (kvm_cpu_has_pending_timer(vcpu))
6179 kvm_inject_pending_timer_irqs(vcpu);
6180
851ba692 6181 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6182 r = -EINTR;
851ba692 6183 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6184 ++vcpu->stat.request_irq_exits;
6185 }
af585b92
GN		 6186
6187 kvm_check_async_pf_completion(vcpu);
6188
09cec754
GN		 6189 if (signal_pending(current)) {
6190 r = -EINTR;
851ba692 6191 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6192 ++vcpu->stat.signal_exits;
6193 }
6194 if (need_resched()) {
f656ce01 6195 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6196 cond_resched();
f656ce01 6197 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6198 }
b6c7a5dc
HB		 6199 }
6200
f656ce01 6201 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6202
6203 return r;
6204}
6205
716d51ab
GN		 6206static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6207{
6208 int r;
6209 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6210 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6211 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6212 if (r != EMULATE_DONE)
6213 return 0;
6214 return 1;
6215}
6216
6217static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6218{
6219 BUG_ON(!vcpu->arch.pio.count);
6220
6221 return complete_emulated_io(vcpu);
6222}
6223
f78146b0
AK		 6224/*
6225 * Implements the following, as a state machine:
6226 *
6227 * read:
6228 * for each fragment
87da7e66
XG		 6229 * for each mmio piece in the fragment
6230 * write gpa, len
6231 * exit
6232 * copy data
f78146b0
AK		 6233 * execute insn
6234 *
6235 * write:
6236 * for each fragment
87da7e66
XG		 6237 * for each mmio piece in the fragment
6238 * write gpa, len
6239 * copy data
6240 * exit
f78146b0 6241 */
716d51ab 6242static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6243{
6244 struct kvm_run *run = vcpu->run;
f78146b0 6245 struct kvm_mmio_fragment *frag;
87da7e66 6246 unsigned len;
5287f194 6247
716d51ab 6248 BUG_ON(!vcpu->mmio_needed);
5287f194 6249
716d51ab 6250 /* Complete previous fragment */
87da7e66
XG		 6251 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6252 len = min(8u, frag->len);
716d51ab 6253 if (!vcpu->mmio_is_write)
87da7e66
XG		 6254 memcpy(frag->data, run->mmio.data, len);
6255
6256 if (frag->len <= 8) {
6257 /* Switch to the next fragment. */
6258 frag++;
6259 vcpu->mmio_cur_fragment++;
6260 } else {
6261 /* Go forward to the next mmio piece. */
6262 frag->data += len;
6263 frag->gpa += len;
6264 frag->len -= len;
6265 }
6266
a08d3b3b 6267 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6268 vcpu->mmio_needed = 0;
0912c977
PB		 6269
6270 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6271 if (vcpu->mmio_is_write)
716d51ab
GN		 6272 return 1;
6273 vcpu->mmio_read_completed = 1;
6274 return complete_emulated_io(vcpu);
6275 }
87da7e66 6276
716d51ab
GN		 6277 run->exit_reason = KVM_EXIT_MMIO;
6278 run->mmio.phys_addr = frag->gpa;
6279 if (vcpu->mmio_is_write)
87da7e66
XG		 6280 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6281 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6282 run->mmio.is_write = vcpu->mmio_is_write;
6283 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6284 return 0;
5287f194
AK		 6285}
6286
716d51ab 6287
b6c7a5dc
HB		 6288int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6289{
6290 int r;
6291 sigset_t sigsaved;
6292
e5c30142
AK		 6293 if (!tsk_used_math(current) && init_fpu(current))
6294 return -ENOMEM;
6295
ac9f6dc0
AK		 6296 if (vcpu->sigset_active)
6297 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6298
a4535290 6299 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6300 kvm_vcpu_block(vcpu);
66450a21 6301 kvm_apic_accept_events(vcpu);
d7690175 6302 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6303 r = -EAGAIN;
6304 goto out;
b6c7a5dc
HB		 6305 }
6306
b6c7a5dc 6307 /* re-sync apic's tpr */
eea1cff9
AP		 6308 if (!irqchip_in_kernel(vcpu->kvm)) {
6309 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6310 r = -EINVAL;
6311 goto out;
6312 }
6313 }
b6c7a5dc 6314
716d51ab
GN		 6315 if (unlikely(vcpu->arch.complete_userspace_io)) {
6316 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6317 vcpu->arch.complete_userspace_io = NULL;
6318 r = cui(vcpu);
6319 if (r <= 0)
6320 goto out;
6321 } else
6322 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6323
851ba692 6324 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6325
6326out:
f1d86e46 6327 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6328 if (vcpu->sigset_active)
6329 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6330
b6c7a5dc
HB		 6331 return r;
6332}
6333
6334int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6335{
7ae441ea
GN		 6336 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6337 /*
6338 * We are here if userspace calls get_regs() in the middle of
6339 * instruction emulation. Registers state needs to be copied
4a969980 6340 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6341 * that usually, but some bad designed PV devices (vmware
6342 * backdoor interface) need this to work
6343 */
dd856efa 6344 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6345 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6346 }
5fdbf976
MT		 6347 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6348 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6349 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6350 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6351 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6352 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6353 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6354 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6355#ifdef CONFIG_X86_64
5fdbf976
MT		 6356 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6357 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6358 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6359 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6360 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6361 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6362 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6363 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6364#endif
6365
5fdbf976 6366 regs->rip = kvm_rip_read(vcpu);
91586a3b 6367 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6368
b6c7a5dc
HB		 6369 return 0;
6370}
6371
6372int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6373{
7ae441ea
GN		 6374 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6375 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6376
5fdbf976
MT		 6377 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6378 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6379 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6380 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6381 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6382 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6383 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6384 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6385#ifdef CONFIG_X86_64
5fdbf976
MT		 6386 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6387 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6388 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6389 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6390 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6391 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6392 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6393 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6394#endif
6395
5fdbf976 6396 kvm_rip_write(vcpu, regs->rip);
91586a3b 6397 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6398
b4f14abd
JK		 6399 vcpu->arch.exception.pending = false;
6400
3842d135
AK		 6401 kvm_make_request(KVM_REQ_EVENT, vcpu);
6402
b6c7a5dc
HB		 6403 return 0;
6404}
6405
b6c7a5dc
HB		 6406void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6407{
6408 struct kvm_segment cs;
6409
3e6e0aab 6410 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6411 *db = cs.db;
6412 *l = cs.l;
6413}
6414EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6415
6416int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6417 struct kvm_sregs *sregs)
6418{
89a27f4d 6419 struct desc_ptr dt;
b6c7a5dc 6420
3e6e0aab
GT		 6421 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6422 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6423 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6424 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6425 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6426 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6427
3e6e0aab
GT		 6428 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6429 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6430
6431 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6432 sregs->idt.limit = dt.size;
6433 sregs->idt.base = dt.address;
b6c7a5dc 6434 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6435 sregs->gdt.limit = dt.size;
6436 sregs->gdt.base = dt.address;
b6c7a5dc 6437
4d4ec087 6438 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6439 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6440 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6441 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6442 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6443 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6444 sregs->apic_base = kvm_get_apic_base(vcpu);
6445
923c61bb 6446 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6447
36752c9b 6448 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6449 set_bit(vcpu->arch.interrupt.nr,
6450 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6451
b6c7a5dc
HB		 6452 return 0;
6453}
6454
62d9f0db
MT		 6455int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6456 struct kvm_mp_state *mp_state)
6457{
66450a21 6458 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6459 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6460 vcpu->arch.pv.pv_unhalted)
6461 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6462 else
6463 mp_state->mp_state = vcpu->arch.mp_state;
6464
62d9f0db
MT		 6465 return 0;
6466}
6467
6468int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6469 struct kvm_mp_state *mp_state)
6470{
66450a21
JK		 6471 if (!kvm_vcpu_has_lapic(vcpu) &&
6472 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6473 return -EINVAL;
6474
6475 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6476 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6477 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6478 } else
6479 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6480 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6481 return 0;
6482}
6483
7f3d35fd
KW		 6484int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6485 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6486{
9d74191a 6487 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6488 int ret;
e01c2426 6489
8ec4722d 6490 init_emulate_ctxt(vcpu);
c697518a 6491
7f3d35fd 6492 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6493 has_error_code, error_code);
c697518a 6494
c697518a 6495 if (ret)
19d04437 6496 return EMULATE_FAIL;
37817f29 6497
9d74191a
TY		 6498 kvm_rip_write(vcpu, ctxt->eip);
6499 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6500 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6501 return EMULATE_DONE;
37817f29
IE		 6502}
6503EXPORT_SYMBOL_GPL(kvm_task_switch);
6504
b6c7a5dc
HB		 6505int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6506 struct kvm_sregs *sregs)
6507{
58cb628d 6508 struct msr_data apic_base_msr;
b6c7a5dc 6509 int mmu_reset_needed = 0;
63f42e02 6510 int pending_vec, max_bits, idx;
89a27f4d 6511 struct desc_ptr dt;
b6c7a5dc 6512
6d1068b3
PM		 6513 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6514 return -EINVAL;
6515
89a27f4d
GN		 6516 dt.size = sregs->idt.limit;
6517 dt.address = sregs->idt.base;
b6c7a5dc 6518 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6519 dt.size = sregs->gdt.limit;
6520 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6521 kvm_x86_ops->set_gdt(vcpu, &dt);
6522
ad312c7c 6523 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6524 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6525 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6526 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6527
2d3ad1f4 6528 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6529
f6801dff 6530 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6531 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6532 apic_base_msr.data = sregs->apic_base;
6533 apic_base_msr.host_initiated = true;
6534 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6535
4d4ec087 6536 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6537 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6538 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6539
fc78f519 6540 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6541 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6542 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6543 kvm_update_cpuid(vcpu);
63f42e02
XG		 6544
6545 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6546 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6547 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6548 mmu_reset_needed = 1;
6549 }
63f42e02 6550 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6551
6552 if (mmu_reset_needed)
6553 kvm_mmu_reset_context(vcpu);
6554
a50abc3b 6555 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6556 pending_vec = find_first_bit(
6557 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6558 if (pending_vec < max_bits) {
66fd3f7f 6559 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6560 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6561 }
6562
3e6e0aab
GT		 6563 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6564 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6565 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6566 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6567 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6568 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6569
3e6e0aab
GT		 6570 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6571 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6572
5f0269f5
ME		 6573 update_cr8_intercept(vcpu);
6574
9c3e4aab 6575 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6576 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6577 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6578 !is_protmode(vcpu))
9c3e4aab
MT		 6579 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6580
3842d135
AK		 6581 kvm_make_request(KVM_REQ_EVENT, vcpu);
6582
b6c7a5dc
HB		 6583 return 0;
6584}
6585
d0bfb940
JK		 6586int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6587 struct kvm_guest_debug *dbg)
b6c7a5dc 6588{
355be0b9 6589 unsigned long rflags;
ae675ef0 6590 int i, r;
b6c7a5dc 6591
4f926bf2
JK		 6592 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6593 r = -EBUSY;
6594 if (vcpu->arch.exception.pending)
2122ff5e 6595 goto out;
4f926bf2
JK		 6596 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6597 kvm_queue_exception(vcpu, DB_VECTOR);
6598 else
6599 kvm_queue_exception(vcpu, BP_VECTOR);
6600 }
6601
91586a3b
JK		 6602 /*
6603 * Read rflags as long as potentially injected trace flags are still
6604 * filtered out.
6605 */
6606 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6607
6608 vcpu->guest_debug = dbg->control;
6609 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6610 vcpu->guest_debug = 0;
6611
6612 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6613 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6614 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6615 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6616 } else {
6617 for (i = 0; i < KVM_NR_DB_REGS; i++)
6618 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6619 }
c8639010 6620 kvm_update_dr7(vcpu);
ae675ef0 6621
f92653ee
JK		 6622 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6623 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6624 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6625
91586a3b
JK		 6626 /*
6627 * Trigger an rflags update that will inject or remove the trace
6628 * flags.
6629 */
6630 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6631
c8639010 6632 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6633
4f926bf2 6634 r = 0;
d0bfb940 6635
2122ff5e 6636out:
b6c7a5dc
HB		 6637
6638 return r;
6639}
6640
8b006791
ZX		 6641/*
6642 * Translate a guest virtual address to a guest physical address.
6643 */
6644int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6645 struct kvm_translation *tr)
6646{
6647 unsigned long vaddr = tr->linear_address;
6648 gpa_t gpa;
f656ce01 6649 int idx;
8b006791 6650
f656ce01 6651 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6652 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6653 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6654 tr->physical_address = gpa;
6655 tr->valid = gpa != UNMAPPED_GVA;
6656 tr->writeable = 1;
6657 tr->usermode = 0;
8b006791
ZX		 6658
6659 return 0;
6660}
6661
d0752060
HB		 6662int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6663{
98918833
SY		 6664 struct i387_fxsave_struct *fxsave =
6665 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6666
d0752060
HB		 6667 memcpy(fpu->fpr, fxsave->st_space, 128);
6668 fpu->fcw = fxsave->cwd;
6669 fpu->fsw = fxsave->swd;
6670 fpu->ftwx = fxsave->twd;
6671 fpu->last_opcode = fxsave->fop;
6672 fpu->last_ip = fxsave->rip;
6673 fpu->last_dp = fxsave->rdp;
6674 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6675
d0752060
HB		 6676 return 0;
6677}
6678
6679int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6680{
98918833
SY		 6681 struct i387_fxsave_struct *fxsave =
6682 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6683
d0752060
HB		 6684 memcpy(fxsave->st_space, fpu->fpr, 128);
6685 fxsave->cwd = fpu->fcw;
6686 fxsave->swd = fpu->fsw;
6687 fxsave->twd = fpu->ftwx;
6688 fxsave->fop = fpu->last_opcode;
6689 fxsave->rip = fpu->last_ip;
6690 fxsave->rdp = fpu->last_dp;
6691 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6692
d0752060
HB		 6693 return 0;
6694}
6695
10ab25cd 6696int fx_init(struct kvm_vcpu *vcpu)
d0752060 6697{
10ab25cd
JK		 6698 int err;
6699
6700 err = fpu_alloc(&vcpu->arch.guest_fpu);
6701 if (err)
6702 return err;
6703
98918833 6704 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6705
2acf923e
DC		 6706 /*
6707 * Ensure guest xcr0 is valid for loading
6708 */
6709 vcpu->arch.xcr0 = XSTATE_FP;
6710
ad312c7c 6711 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6712
6713 return 0;
d0752060
HB		 6714}
6715EXPORT_SYMBOL_GPL(fx_init);
6716
98918833
SY		 6717static void fx_free(struct kvm_vcpu *vcpu)
6718{
6719 fpu_free(&vcpu->arch.guest_fpu);
6720}
6721
d0752060
HB		 6722void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6723{
2608d7a1 6724 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6725 return;
6726
2acf923e
DC		 6727 /*
6728 * Restore all possible states in the guest,
6729 * and assume host would use all available bits.
6730 * Guest xcr0 would be loaded later.
6731 */
6732 kvm_put_guest_xcr0(vcpu);
d0752060 6733 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6734 __kernel_fpu_begin();
98918833 6735 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6736 trace_kvm_fpu(1);
d0752060 6737}
d0752060
HB		 6738
6739void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6740{
2acf923e
DC		 6741 kvm_put_guest_xcr0(vcpu);
6742
d0752060
HB		 6743 if (!vcpu->guest_fpu_loaded)
6744 return;
6745
6746 vcpu->guest_fpu_loaded = 0;
98918833 6747 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6748 __kernel_fpu_end();
f096ed85 6749 ++vcpu->stat.fpu_reload;
a8eeb04a 6750 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6751 trace_kvm_fpu(0);
d0752060 6752}
e9b11c17
ZX		 6753
6754void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6755{
12f9a48f 6756 kvmclock_reset(vcpu);
7f1ea208 6757
f5f48ee1 6758 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6759 fx_free(vcpu);
e9b11c17
ZX		 6760 kvm_x86_ops->vcpu_free(vcpu);
6761}
6762
6763struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6764 unsigned int id)
6765{
6755bae8
ZA		 6766 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6767 printk_once(KERN_WARNING
6768 "kvm: SMP vm created on host with unstable TSC; "
6769 "guest TSC will not be reliable\n");
26e5215f
AK		 6770 return kvm_x86_ops->vcpu_create(kvm, id);
6771}
e9b11c17 6772
26e5215f
AK		 6773int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6774{
6775 int r;
e9b11c17 6776
0bed3b56 6777 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6778 r = vcpu_load(vcpu);
6779 if (r)
6780 return r;
57f252f2 6781 kvm_vcpu_reset(vcpu);
8a3c1a33 6782 kvm_mmu_setup(vcpu);
e9b11c17 6783 vcpu_put(vcpu);
e9b11c17 6784
26e5215f 6785 return r;
e9b11c17
ZX		 6786}
6787
42897d86
MT		 6788int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6789{
6790 int r;
8fe8ab46 6791 struct msr_data msr;
332967a3 6792 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6793
6794 r = vcpu_load(vcpu);
6795 if (r)
6796 return r;
8fe8ab46
WA		 6797 msr.data = 0x0;
6798 msr.index = MSR_IA32_TSC;
6799 msr.host_initiated = true;
6800 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6801 vcpu_put(vcpu);
6802
332967a3
AJ		 6803 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6804 KVMCLOCK_SYNC_PERIOD);
6805
42897d86
MT		 6806 return r;
6807}
6808
d40ccc62 6809void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6810{
9fc77441 6811 int r;
344d9588
GN		 6812 vcpu->arch.apf.msr_val = 0;
6813
9fc77441
MT		 6814 r = vcpu_load(vcpu);
6815 BUG_ON(r);
e9b11c17
ZX		 6816 kvm_mmu_unload(vcpu);
6817 vcpu_put(vcpu);
6818
98918833 6819 fx_free(vcpu);
e9b11c17
ZX		 6820 kvm_x86_ops->vcpu_free(vcpu);
6821}
6822
66450a21 6823void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6824{
7460fb4a
AK		 6825 atomic_set(&vcpu->arch.nmi_queued, 0);
6826 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6827 vcpu->arch.nmi_injected = false;
6828
42dbaa5a
JK		 6829 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6830 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6831 kvm_update_dr6(vcpu);
42dbaa5a 6832 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6833 kvm_update_dr7(vcpu);
42dbaa5a 6834
3842d135 6835 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6836 vcpu->arch.apf.msr_val = 0;
c9aaa895 6837 vcpu->arch.st.msr_val = 0;
3842d135 6838
12f9a48f
GC		 6839 kvmclock_reset(vcpu);
6840
af585b92
GN		 6841 kvm_clear_async_pf_completion_queue(vcpu);
6842 kvm_async_pf_hash_reset(vcpu);
6843 vcpu->arch.apf.halted = false;
3842d135 6844
f5132b01
GN		 6845 kvm_pmu_reset(vcpu);
6846
66f7b72e
JS		 6847 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6848 vcpu->arch.regs_avail = ~0;
6849 vcpu->arch.regs_dirty = ~0;
6850
57f252f2 6851 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6852}
6853
66450a21
JK		 6854void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6855{
6856 struct kvm_segment cs;
6857
6858 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6859 cs.selector = vector << 8;
6860 cs.base = vector << 12;
6861 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6862 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6863}
6864
10474ae8 6865int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6866{
ca84d1a2
ZA		 6867 struct kvm *kvm;
6868 struct kvm_vcpu *vcpu;
6869 int i;
0dd6a6ed
ZA		 6870 int ret;
6871 u64 local_tsc;
6872 u64 max_tsc = 0;
6873 bool stable, backwards_tsc = false;
18863bdd
AK		 6874
6875 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6876 ret = kvm_x86_ops->hardware_enable(garbage);
6877 if (ret != 0)
6878 return ret;
6879
6880 local_tsc = native_read_tsc();
6881 stable = !check_tsc_unstable();
6882 list_for_each_entry(kvm, &vm_list, vm_list) {
6883 kvm_for_each_vcpu(i, vcpu, kvm) {
6884 if (!stable && vcpu->cpu == smp_processor_id())
6885 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6886 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6887 backwards_tsc = true;
6888 if (vcpu->arch.last_host_tsc > max_tsc)
6889 max_tsc = vcpu->arch.last_host_tsc;
6890 }
6891 }
6892 }
6893
6894 /*
6895 * Sometimes, even reliable TSCs go backwards. This happens on
6896 * platforms that reset TSC during suspend or hibernate actions, but
6897 * maintain synchronization. We must compensate. Fortunately, we can
6898 * detect that condition here, which happens early in CPU bringup,
6899 * before any KVM threads can be running. Unfortunately, we can't
6900 * bring the TSCs fully up to date with real time, as we aren't yet far
6901 * enough into CPU bringup that we know how much real time has actually
6902 * elapsed; our helper function, get_kernel_ns() will be using boot
6903 * variables that haven't been updated yet.
6904 *
6905 * So we simply find the maximum observed TSC above, then record the
6906 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6907 * the adjustment will be applied. Note that we accumulate
6908 * adjustments, in case multiple suspend cycles happen before some VCPU
6909 * gets a chance to run again. In the event that no KVM threads get a
6910 * chance to run, we will miss the entire elapsed period, as we'll have
6911 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6912 * loose cycle time. This isn't too big a deal, since the loss will be
6913 * uniform across all VCPUs (not to mention the scenario is extremely
6914 * unlikely). It is possible that a second hibernate recovery happens
6915 * much faster than a first, causing the observed TSC here to be
6916 * smaller; this would require additional padding adjustment, which is
6917 * why we set last_host_tsc to the local tsc observed here.
6918 *
6919 * N.B. - this code below runs only on platforms with reliable TSC,
6920 * as that is the only way backwards_tsc is set above. Also note
6921 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6922 * have the same delta_cyc adjustment applied if backwards_tsc
6923 * is detected. Note further, this adjustment is only done once,
6924 * as we reset last_host_tsc on all VCPUs to stop this from being
6925 * called multiple times (one for each physical CPU bringup).
6926 *
4a969980 6927 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6928 * will be compensated by the logic in vcpu_load, which sets the TSC to
6929 * catchup mode. This will catchup all VCPUs to real time, but cannot
6930 * guarantee that they stay in perfect synchronization.
6931 */
6932 if (backwards_tsc) {
6933 u64 delta_cyc = max_tsc - local_tsc;
6934 list_for_each_entry(kvm, &vm_list, vm_list) {
6935 kvm_for_each_vcpu(i, vcpu, kvm) {
6936 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6937 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6938 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6939 &vcpu->requests);
0dd6a6ed
ZA		 6940 }
6941
6942 /*
6943 * We have to disable TSC offset matching.. if you were
6944 * booting a VM while issuing an S4 host suspend....
6945 * you may have some problem. Solving this issue is
6946 * left as an exercise to the reader.
6947 */
6948 kvm->arch.last_tsc_nsec = 0;
6949 kvm->arch.last_tsc_write = 0;
6950 }
6951
6952 }
6953 return 0;
e9b11c17
ZX		 6954}
6955
6956void kvm_arch_hardware_disable(void *garbage)
6957{
6958 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6959 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6960}
6961
6962int kvm_arch_hardware_setup(void)
6963{
6964 return kvm_x86_ops->hardware_setup();
6965}
6966
6967void kvm_arch_hardware_unsetup(void)
6968{
6969 kvm_x86_ops->hardware_unsetup();
6970}
6971
6972void kvm_arch_check_processor_compat(void *rtn)
6973{
6974 kvm_x86_ops->check_processor_compatibility(rtn);
6975}
6976
3e515705
AK		 6977bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6978{
6979 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6980}
6981
54e9818f
GN		 6982struct static_key kvm_no_apic_vcpu __read_mostly;
6983
e9b11c17
ZX		 6984int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6985{
6986 struct page *page;
6987 struct kvm *kvm;
6988 int r;
6989
6990 BUG_ON(vcpu->kvm == NULL);
6991 kvm = vcpu->kvm;
6992
6aef266c 6993 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6994 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6995 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6997 else
a4535290 6998 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6999
7000 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7001 if (!page) {
7002 r = -ENOMEM;
7003 goto fail;
7004 }
ad312c7c 7005 vcpu->arch.pio_data = page_address(page);
e9b11c17 7006
cc578287 7007 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7008
e9b11c17
ZX		 7009 r = kvm_mmu_create(vcpu);
7010 if (r < 0)
7011 goto fail_free_pio_data;
7012
7013 if (irqchip_in_kernel(kvm)) {
7014 r = kvm_create_lapic(vcpu);
7015 if (r < 0)
7016 goto fail_mmu_destroy;
54e9818f
GN		 7017 } else
7018 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7019
890ca9ae
YH		 7020 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7021 GFP_KERNEL);
7022 if (!vcpu->arch.mce_banks) {
7023 r = -ENOMEM;
443c39bc 7024 goto fail_free_lapic;
890ca9ae
YH		 7025 }
7026 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7027
f1797359
WY		 7028 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7029 r = -ENOMEM;
f5f48ee1 7030 goto fail_free_mce_banks;
f1797359 7031 }
f5f48ee1 7032
66f7b72e
JS		 7033 r = fx_init(vcpu);
7034 if (r)
7035 goto fail_free_wbinvd_dirty_mask;
7036
ba904635 7037 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7038 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7039
7040 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7041 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7042
af585b92 7043 kvm_async_pf_hash_reset(vcpu);
f5132b01 7044 kvm_pmu_init(vcpu);
af585b92 7045
e9b11c17 7046 return 0;
66f7b72e
JS		 7047fail_free_wbinvd_dirty_mask:
7048 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7049fail_free_mce_banks:
7050 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7051fail_free_lapic:
7052 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7053fail_mmu_destroy:
7054 kvm_mmu_destroy(vcpu);
7055fail_free_pio_data:
ad312c7c 7056 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7057fail:
7058 return r;
7059}
7060
7061void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7062{
f656ce01
MT		 7063 int idx;
7064
f5132b01 7065 kvm_pmu_destroy(vcpu);
36cb93fd 7066 kfree(vcpu->arch.mce_banks);
e9b11c17 7067 kvm_free_lapic(vcpu);
f656ce01 7068 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7069 kvm_mmu_destroy(vcpu);
f656ce01 7070 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7071 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7072 if (!irqchip_in_kernel(vcpu->kvm))
7073 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7074}
d19a9cd2 7075
e08b9637 7076int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7077{
e08b9637
CO		 7078 if (type)
7079 return -EINVAL;
7080
f05e70ac 7081 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7082 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7083 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7084 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7085
5550af4d
SY		 7086 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7087 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7088 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7089 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7090 &kvm->arch.irq_sources_bitmap);
5550af4d 7091
038f8c11 7092 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7093 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7094 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7095
7096 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7097
7e44e449 7098 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7099 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7100
d89f5eff 7101 return 0;
d19a9cd2
ZX		 7102}
7103
7104static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7105{
9fc77441
MT		 7106 int r;
7107 r = vcpu_load(vcpu);
7108 BUG_ON(r);
d19a9cd2
ZX		 7109 kvm_mmu_unload(vcpu);
7110 vcpu_put(vcpu);
7111}
7112
7113static void kvm_free_vcpus(struct kvm *kvm)
7114{
7115 unsigned int i;
988a2cae 7116 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7117
7118 /*
7119 * Unpin any mmu pages first.
7120 */
af585b92
GN		 7121 kvm_for_each_vcpu(i, vcpu, kvm) {
7122 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7123 kvm_unload_vcpu_mmu(vcpu);
af585b92 7124 }
988a2cae
GN		 7125 kvm_for_each_vcpu(i, vcpu, kvm)
7126 kvm_arch_vcpu_free(vcpu);
7127
7128 mutex_lock(&kvm->lock);
7129 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7130 kvm->vcpus[i] = NULL;
d19a9cd2 7131
988a2cae
GN		 7132 atomic_set(&kvm->online_vcpus, 0);
7133 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7134}
7135
ad8ba2cd
SY		 7136void kvm_arch_sync_events(struct kvm *kvm)
7137{
332967a3 7138 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7139 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7140 kvm_free_all_assigned_devices(kvm);
aea924f6 7141 kvm_free_pit(kvm);
ad8ba2cd
SY		 7142}
7143
d19a9cd2
ZX		 7144void kvm_arch_destroy_vm(struct kvm *kvm)
7145{
27469d29
AH		 7146 if (current->mm == kvm->mm) {
7147 /*
7148 * Free memory regions allocated on behalf of userspace,
7149 * unless the the memory map has changed due to process exit
7150 * or fd copying.
7151 */
7152 struct kvm_userspace_memory_region mem;
7153 memset(&mem, 0, sizeof(mem));
7154 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7155 kvm_set_memory_region(kvm, &mem);
7156
7157 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7158 kvm_set_memory_region(kvm, &mem);
7159
7160 mem.slot = TSS_PRIVATE_MEMSLOT;
7161 kvm_set_memory_region(kvm, &mem);
7162 }
6eb55818 7163 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7164 kfree(kvm->arch.vpic);
7165 kfree(kvm->arch.vioapic);
d19a9cd2 7166 kvm_free_vcpus(kvm);
3d45830c
AK		 7167 if (kvm->arch.apic_access_page)
7168 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7169 if (kvm->arch.ept_identity_pagetable)
7170 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7171 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7172}
0de10343 7173
5587027c 7174void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7175 struct kvm_memory_slot *dont)
7176{
7177 int i;
7178
d89cc617
TY		 7179 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7180 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7181 kvm_kvfree(free->arch.rmap[i]);
7182 free->arch.rmap[i] = NULL;
77d11309 7183 }
d89cc617
TY		 7184 if (i == 0)
7185 continue;
7186
7187 if (!dont || free->arch.lpage_info[i - 1] !=
7188 dont->arch.lpage_info[i - 1]) {
7189 kvm_kvfree(free->arch.lpage_info[i - 1]);
7190 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7191 }
7192 }
7193}
7194
5587027c
AK		 7195int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7196 unsigned long npages)
db3fe4eb
TY		 7197{
7198 int i;
7199
d89cc617 7200 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7201 unsigned long ugfn;
7202 int lpages;
d89cc617 7203 int level = i + 1;
db3fe4eb
TY		 7204
7205 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7206 slot->base_gfn, level) + 1;
7207
d89cc617
TY		 7208 slot->arch.rmap[i] =
7209 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7210 if (!slot->arch.rmap[i])
77d11309 7211 goto out_free;
d89cc617
TY		 7212 if (i == 0)
7213 continue;
77d11309 7214
d89cc617
TY		 7215 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7216 sizeof(*slot->arch.lpage_info[i - 1]));
7217 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7218 goto out_free;
7219
7220 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7221 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7222 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7223 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7224 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7225 /*
7226 * If the gfn and userspace address are not aligned wrt each
7227 * other, or if explicitly asked to, disable large page
7228 * support for this slot
7229 */
7230 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7231 !kvm_largepages_enabled()) {
7232 unsigned long j;
7233
7234 for (j = 0; j < lpages; ++j)
d89cc617 7235 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7236 }
7237 }
7238
7239 return 0;
7240
7241out_free:
d89cc617
TY		 7242 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7243 kvm_kvfree(slot->arch.rmap[i]);
7244 slot->arch.rmap[i] = NULL;
7245 if (i == 0)
7246 continue;
7247
7248 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7249 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7250 }
7251 return -ENOMEM;
7252}
7253
e59dbe09
TY		 7254void kvm_arch_memslots_updated(struct kvm *kvm)
7255{
e6dff7d1
TY		 7256 /*
7257 * memslots->generation has been incremented.
7258 * mmio generation may have reached its maximum value.
7259 */
7260 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7261}
7262
f7784b8e
MT		 7263int kvm_arch_prepare_memory_region(struct kvm *kvm,
7264 struct kvm_memory_slot *memslot,
f7784b8e 7265 struct kvm_userspace_memory_region *mem,
7b6195a9 7266 enum kvm_mr_change change)
0de10343 7267{
7a905b14
TY		 7268 /*
7269 * Only private memory slots need to be mapped here since
7270 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7271 */
7b6195a9 7272 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7273 unsigned long userspace_addr;
604b38ac 7274
7a905b14
TY		 7275 /*
7276 * MAP_SHARED to prevent internal slot pages from being moved
7277 * by fork()/COW.
7278 */
7b6195a9 7279 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7280 PROT_READ | PROT_WRITE,
7281 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7282
7a905b14
TY		 7283 if (IS_ERR((void *)userspace_addr))
7284 return PTR_ERR((void *)userspace_addr);
604b38ac 7285
7a905b14 7286 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7287 }
7288
f7784b8e
MT		 7289 return 0;
7290}
7291
7292void kvm_arch_commit_memory_region(struct kvm *kvm,
7293 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7294 const struct kvm_memory_slot *old,
7295 enum kvm_mr_change change)
f7784b8e
MT		 7296{
7297
8482644a 7298 int nr_mmu_pages = 0;
f7784b8e 7299
8482644a 7300 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7301 int ret;
7302
8482644a
TY		 7303 ret = vm_munmap(old->userspace_addr,
7304 old->npages * PAGE_SIZE);
f7784b8e
MT		 7305 if (ret < 0)
7306 printk(KERN_WARNING
7307 "kvm_vm_ioctl_set_memory_region: "
7308 "failed to munmap memory\n");
7309 }
7310
48c0e4e9
XG		 7311 if (!kvm->arch.n_requested_mmu_pages)
7312 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7313
48c0e4e9 7314 if (nr_mmu_pages)
0de10343 7315 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7316 /*
7317 * Write protect all pages for dirty logging.
7318 * Existing largepage mappings are destroyed here and new ones will
7319 * not be created until the end of the logging.
7320 */
8482644a 7321 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7322 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7323}
1d737c8a 7324
2df72e9b 7325void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7326{
6ca18b69 7327 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7328}
7329
2df72e9b
MT		 7330void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7331 struct kvm_memory_slot *slot)
7332{
6ca18b69 7333 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7334}
7335
1d737c8a
ZX		 7336int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7337{
b6b8a145
JK		 7338 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7339 kvm_x86_ops->check_nested_events(vcpu, false);
7340
af585b92
GN		 7341 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7342 !vcpu->arch.apf.halted)
7343 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7344 || kvm_apic_has_events(vcpu)
6aef266c 7345 || vcpu->arch.pv.pv_unhalted
7460fb4a 7346 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7347 (kvm_arch_interrupt_allowed(vcpu) &&
7348 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7349}
5736199a 7350
b6d33834 7351int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7352{
b6d33834 7353 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7354}
78646121
GN		 7355
7356int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7357{
7358 return kvm_x86_ops->interrupt_allowed(vcpu);
7359}
229456fc 7360
f92653ee
JK		 7361bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7362{
7363 unsigned long current_rip = kvm_rip_read(vcpu) +
7364 get_segment_base(vcpu, VCPU_SREG_CS);
7365
7366 return current_rip == linear_rip;
7367}
7368EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7369
94fe45da
JK		 7370unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7371{
7372 unsigned long rflags;
7373
7374 rflags = kvm_x86_ops->get_rflags(vcpu);
7375 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7376 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7377 return rflags;
7378}
7379EXPORT_SYMBOL_GPL(kvm_get_rflags);
7380
7381void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7382{
7383 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7384 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7385 rflags |= X86_EFLAGS_TF;
94fe45da 7386 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7387 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7388}
7389EXPORT_SYMBOL_GPL(kvm_set_rflags);
7390
56028d08
GN		 7391void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7392{
7393 int r;
7394
fb67e14f 7395 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7396 work->wakeup_all)
56028d08
GN		 7397 return;
7398
7399 r = kvm_mmu_reload(vcpu);
7400 if (unlikely(r))
7401 return;
7402
fb67e14f
XG		 7403 if (!vcpu->arch.mmu.direct_map &&
7404 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7405 return;
7406
56028d08
GN		 7407 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7408}
7409
af585b92
GN		 7410static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7411{
7412 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7413}
7414
7415static inline u32 kvm_async_pf_next_probe(u32 key)
7416{
7417 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7418}
7419
7420static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7421{
7422 u32 key = kvm_async_pf_hash_fn(gfn);
7423
7424 while (vcpu->arch.apf.gfns[key] != ~0)
7425 key = kvm_async_pf_next_probe(key);
7426
7427 vcpu->arch.apf.gfns[key] = gfn;
7428}
7429
7430static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7431{
7432 int i;
7433 u32 key = kvm_async_pf_hash_fn(gfn);
7434
7435 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7436 (vcpu->arch.apf.gfns[key] != gfn &&
7437 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7438 key = kvm_async_pf_next_probe(key);
7439
7440 return key;
7441}
7442
7443bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7444{
7445 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7446}
7447
7448static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7449{
7450 u32 i, j, k;
7451
7452 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7453 while (true) {
7454 vcpu->arch.apf.gfns[i] = ~0;
7455 do {
7456 j = kvm_async_pf_next_probe(j);
7457 if (vcpu->arch.apf.gfns[j] == ~0)
7458 return;
7459 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7460 /*
7461 * k lies cyclically in ]i,j]
7462 * | i.k.j |
7463 * |....j i.k.| or |.k..j i...|
7464 */
7465 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7466 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7467 i = j;
7468 }
7469}
7470
7c90705b
GN		 7471static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7472{
7473
7474 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7475 sizeof(val));
7476}
7477
af585b92
GN		 7478void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7479 struct kvm_async_pf *work)
7480{
6389ee94
AK		 7481 struct x86_exception fault;
7482
7c90705b 7483 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7484 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7485
7486 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7487 (vcpu->arch.apf.send_user_only &&
7488 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7489 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7490 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7491 fault.vector = PF_VECTOR;
7492 fault.error_code_valid = true;
7493 fault.error_code = 0;
7494 fault.nested_page_fault = false;
7495 fault.address = work->arch.token;
7496 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7497 }
af585b92
GN		 7498}
7499
7500void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7501 struct kvm_async_pf *work)
7502{
6389ee94
AK		 7503 struct x86_exception fault;
7504
7c90705b 7505 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7506 if (work->wakeup_all)
7c90705b
GN		 7507 work->arch.token = ~0; /* broadcast wakeup */
7508 else
7509 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7510
7511 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7512 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7513 fault.vector = PF_VECTOR;
7514 fault.error_code_valid = true;
7515 fault.error_code = 0;
7516 fault.nested_page_fault = false;
7517 fault.address = work->arch.token;
7518 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7519 }
e6d53e3b 7520 vcpu->arch.apf.halted = false;
a4fa1635 7521 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7522}
7523
7524bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7525{
7526 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7527 return true;
7528 else
7529 return !kvm_event_needs_reinjection(vcpu) &&
7530 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7531}
7532
e0f0bbc5
AW		 7533void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7534{
7535 atomic_inc(&kvm->arch.noncoherent_dma_count);
7536}
7537EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7538
7539void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7540{
7541 atomic_dec(&kvm->arch.noncoherent_dma_count);
7542}
7543EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7544
7545bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7546{
7547 return atomic_read(&kvm->arch.noncoherent_dma_count);
7548}
7549EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7550
229456fc
MT		 7551EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7552EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7553EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7554EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7555EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7556EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7557EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7558EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7559EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7560EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7561EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7562EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7563EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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