[linux.git] / arch / ppc / platforms / fads.h

/*
 * A collection of structures, addresses, and values associated with
 * the Motorola 860T FADS board.  Copied from the MBX stuff.
 *
 * Copyright (c) 1998 Dan Malek ([email protected])
 *
 * Added MPC86XADS support.
 * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
 * for SW point of view". This is 99% correct.
 *
 * Author: MontaVista Software, Inc.
 *         [email protected]
 * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
 * terms of the GNU General Public License version 2.  This program is licensed
 * "as is" without any warranty of any kind, whether express or implied.
 */

#ifdef __KERNEL__
#ifndef __ASM_FADS_H__
#define __ASM_FADS_H__

#include <linux/config.h>

#include <asm/ppcboot.h>

#if defined(CONFIG_MPC86XADS)

/* U-Boot maps BCSR to 0xff080000 */
#define BCSR_ADDR		((uint)0xff080000)

/* MPC86XADS has one more CPLD and an additional BCSR.
 */
#define CFG_PHYDEV_ADDR		((uint)0xff0a0000)
#define BCSR5			((uint)(CFG_PHYDEV_ADDR + 0x300))

#define BCSR5_T1_RST		0x10
#define BCSR5_ATM155_RST	0x08
#define BCSR5_ATM25_RST		0x04
#define BCSR5_MII1_EN		0x02
#define BCSR5_MII1_RST		0x01

/* There is no PHY link change interrupt */
#define PHY_INTERRUPT	(-1)

#else /* FADS */

/* Memory map is configured by the PROM startup.
 * I tried to follow the FADS manual, although the startup PROM
 * dictates this and we simply have to move some of the physical
 * addresses for Linux.
 */
#define BCSR_ADDR		((uint)0xff010000)

/* PHY link change interrupt */
#define PHY_INTERRUPT	SIU_IRQ2

#endif /* CONFIG_MPC86XADS */

#define BCSR_SIZE		((uint)(64 * 1024))
#define BCSR0			((uint)(BCSR_ADDR + 0x00))
#define BCSR1			((uint)(BCSR_ADDR + 0x04))
#define BCSR2			((uint)(BCSR_ADDR + 0x08))
#define BCSR3			((uint)(BCSR_ADDR + 0x0c))
#define BCSR4			((uint)(BCSR_ADDR + 0x10))

#define IMAP_ADDR		((uint)0xff000000)
#define IMAP_SIZE		((uint)(64 * 1024))

#define PCMCIA_MEM_ADDR		((uint)0xff020000)
#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))

/* Bits of interest in the BCSRs.
 */
#define BCSR1_ETHEN		((uint)0x20000000)
#define BCSR1_IRDAEN		((uint)0x10000000)
#define BCSR1_RS232EN_1		((uint)0x01000000)
#define BCSR1_PCCEN		((uint)0x00800000)
#define BCSR1_PCCVCC0		((uint)0x00400000)
#define BCSR1_PCCVPP0		((uint)0x00200000)
#define BCSR1_PCCVPP1		((uint)0x00100000)
#define BCSR1_PCCVPP_MASK	(BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
#define BCSR1_RS232EN_2		((uint)0x00040000)
#define BCSR1_PCCVCC1		((uint)0x00010000)
#define BCSR1_PCCVCC_MASK	(BCSR1_PCCVCC0 | BCSR1_PCCVCC1)

#define BCSR4_ETHLOOP		((uint)0x80000000)	/* EEST Loopback */
#define BCSR4_EEFDX		((uint)0x40000000)	/* EEST FDX enable */
#define BCSR4_FETH_EN		((uint)0x08000000)	/* PHY enable */
#define BCSR4_FETHCFG0		((uint)0x04000000)	/* PHY autoneg mode */
#define BCSR4_FETHCFG1		((uint)0x00400000)	/* PHY autoneg mode */
#define BCSR4_FETHFDE		((uint)0x02000000)	/* PHY FDX advertise */
#define BCSR4_FETHRST		((uint)0x00200000)	/* PHY Reset */

/* IO_BASE definition for pcmcia.
 */
#define _IO_BASE	0x80000000
#define _IO_BASE_SIZE	0x1000

#ifdef CONFIG_IDE
#define MAX_HWIFS 1
#endif

/* Interrupt level assignments.
 */
#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */

/* We don't use the 8259.
 */
#define NR_8259_INTS	0

/* CPM Ethernet through SCC1 or SCC2 */

#ifdef CONFIG_SCC1_ENET		/* Probably 860 variant */
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 * TCLK - CLK1, RCLK - CLK2.
 */
#define PA_ENET_RXD	((ushort)0x0001)
#define PA_ENET_TXD	((ushort)0x0002)
#define PA_ENET_TCLK	((ushort)0x0100)
#define PA_ENET_RCLK	((ushort)0x0200)
#define PB_ENET_TENA	((uint)0x00001000)
#define PC_ENET_CLSN	((ushort)0x0010)
#define PC_ENET_RENA	((ushort)0x0020)

/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x0000002c)
#endif /* CONFIG_SCC1_ENET */

#ifdef CONFIG_SCC2_ENET		/* Probably 823/850 variant */
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 * TCLK - CLK1, RCLK - CLK2.
 */
#define PA_ENET_RXD	((ushort)0x0004)
#define PA_ENET_TXD	((ushort)0x0008)
#define PA_ENET_TCLK	((ushort)0x0400)
#define PA_ENET_RCLK	((ushort)0x0200)
#define PB_ENET_TENA	((uint)0x00002000)
#define PC_ENET_CLSN	((ushort)0x0040)
#define PC_ENET_RENA	((ushort)0x0080)

/* Control bits in the SICR to route TCLK and RCLK to
 * SCC2.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002e00)
#endif /* CONFIG_SCC2_ENET */

#endif /* __ASM_FADS_H__ */
#endif /* __KERNEL__ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* A collection of structures, addresses, and values associated with
	3	* the Motorola 860T FADS board. Copied from the MBX stuff.
	4	*
	5	* Copyright (c) 1998 Dan Malek ([email protected])
e6b6239f AK	6	*
	7	* Added MPC86XADS support.
	8	* The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
	9	* for SW point of view". This is 99% correct.
	10	*
	11	* Author: MontaVista Software, Inc.
	12	* [email protected]
	13	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	14	* terms of the GNU General Public License version 2. This program is licensed
	15	* "as is" without any warranty of any kind, whether express or implied.
1da177e4	16	*/
e6b6239f	17
1da177e4 LT	18	#ifdef __KERNEL__
	19	#ifndef __ASM_FADS_H__
	20	#define __ASM_FADS_H__
	21
	22	#include <linux/config.h>
	23
	24	#include <asm/ppcboot.h>
	25
e6b6239f AK	26	#if defined(CONFIG_MPC86XADS)
	27
	28	/* U-Boot maps BCSR to 0xff080000 */
	29	#define BCSR_ADDR ((uint)0xff080000)
	30
	31	/* MPC86XADS has one more CPLD and an additional BCSR.
	32	*/
	33	#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
	34	#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
	35
	36	#define BCSR5_T1_RST 0x10
	37	#define BCSR5_ATM155_RST 0x08
	38	#define BCSR5_ATM25_RST 0x04
	39	#define BCSR5_MII1_EN 0x02
	40	#define BCSR5_MII1_RST 0x01
	41
	42	/* There is no PHY link change interrupt */
	43	#define PHY_INTERRUPT (-1)
	44
	45	#else /* FADS */
	46
1da177e4 LT	47	/* Memory map is configured by the PROM startup.
	48	* I tried to follow the FADS manual, although the startup PROM
	49	* dictates this and we simply have to move some of the physical
	50	* addresses for Linux.
	51	*/
	52	#define BCSR_ADDR ((uint)0xff010000)
e6b6239f AK	53
	54	/* PHY link change interrupt */
	55	#define PHY_INTERRUPT SIU_IRQ2
	56
	57	#endif /* CONFIG_MPC86XADS */
	58
1da177e4	59	#define BCSR_SIZE ((uint)(64 * 1024))
e6b6239f AK	60	#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
	61	#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
	62	#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
	63	#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
	64	#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
1da177e4 LT	65
	66	#define IMAP_ADDR ((uint)0xff000000)
	67	#define IMAP_SIZE ((uint)(64 * 1024))
	68
	69	#define PCMCIA_MEM_ADDR ((uint)0xff020000)
	70	#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
	71
	72	/* Bits of interest in the BCSRs.
	73	*/
	74	#define BCSR1_ETHEN ((uint)0x20000000)
e6b6239f	75	#define BCSR1_IRDAEN ((uint)0x10000000)
1da177e4	76	#define BCSR1_RS232EN_1 ((uint)0x01000000)
e6b6239f AK	77	#define BCSR1_PCCEN ((uint)0x00800000)
	78	#define BCSR1_PCCVCC0 ((uint)0x00400000)
	79	#define BCSR1_PCCVPP0 ((uint)0x00200000)
	80	#define BCSR1_PCCVPP1 ((uint)0x00100000)
	81	#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 \| BCSR1_PCCVPP1)
1da177e4	82	#define BCSR1_RS232EN_2 ((uint)0x00040000)
e6b6239f AK	83	#define BCSR1_PCCVCC1 ((uint)0x00010000)
	84	#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 \| BCSR1_PCCVCC1)
	85
1da177e4 LT	86	#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */
	87	#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */
	88	#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */
	89	#define BCSR4_FETHCFG0 ((uint)0x04000000) /* PHY autoneg mode */
	90	#define BCSR4_FETHCFG1 ((uint)0x00400000) /* PHY autoneg mode */
	91	#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */
	92	#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */
	93
e6b6239f AK	94	/* IO_BASE definition for pcmcia.
	95	*/
	96	#define _IO_BASE 0x80000000
	97	#define _IO_BASE_SIZE 0x1000
	98
	99	#ifdef CONFIG_IDE
	100	#define MAX_HWIFS 1
	101	#endif
	102
1da177e4 LT	103	/* Interrupt level assignments.
	104	*/
	105	#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
1da177e4 LT	106
	107	/* We don't use the 8259.
	108	*/
	109	#define NR_8259_INTS 0
	110
e6b6239f AK	111	/* CPM Ethernet through SCC1 or SCC2 */
	112
	113	#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */
	114	/* Bits in parallel I/O port registers that have to be set/cleared
	115	* to configure the pins for SCC1 use.
	116	* TCLK - CLK1, RCLK - CLK2.
	117	*/
	118	#define PA_ENET_RXD ((ushort)0x0001)
	119	#define PA_ENET_TXD ((ushort)0x0002)
	120	#define PA_ENET_TCLK ((ushort)0x0100)
	121	#define PA_ENET_RCLK ((ushort)0x0200)
	122	#define PB_ENET_TENA ((uint)0x00001000)
	123	#define PC_ENET_CLSN ((ushort)0x0010)
	124	#define PC_ENET_RENA ((ushort)0x0020)
	125
	126	/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
	127	* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
	128	*/
	129	#define SICR_ENET_MASK ((uint)0x000000ff)
	130	#define SICR_ENET_CLKRT ((uint)0x0000002c)
	131	#endif /* CONFIG_SCC1_ENET */
	132
	133	#ifdef CONFIG_SCC2_ENET /* Probably 823/850 variant */
	134	/* Bits in parallel I/O port registers that have to be set/cleared
	135	* to configure the pins for SCC1 use.
	136	* TCLK - CLK1, RCLK - CLK2.
	137	*/
	138	#define PA_ENET_RXD ((ushort)0x0004)
	139	#define PA_ENET_TXD ((ushort)0x0008)
	140	#define PA_ENET_TCLK ((ushort)0x0400)
	141	#define PA_ENET_RCLK ((ushort)0x0200)
	142	#define PB_ENET_TENA ((uint)0x00002000)
	143	#define PC_ENET_CLSN ((ushort)0x0040)
	144	#define PC_ENET_RENA ((ushort)0x0080)
	145
	146	/* Control bits in the SICR to route TCLK and RCLK to
	147	* SCC2. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
	148	*/
	149	#define SICR_ENET_MASK ((uint)0x0000ff00)
	150	#define SICR_ENET_CLKRT ((uint)0x00002e00)
	151	#endif /* CONFIG_SCC2_ENET */
	152
1da177e4 LT	153	#endif /* __ASM_FADS_H__ */
1da177e4 LT	154	#endif /* __KERNEL__ */