[linux.git] / drivers / clk / clk-moxart.c

/*
 * MOXA ART SoCs clock driver.
 *
 * Copyright (C) 2013 Jonas Jensen
 *
 * Jonas Jensen <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/clkdev.h>

static void __init moxart_of_pll_clk_init(struct device_node *node)
{
	void __iomem *base;
	struct clk_hw *hw;
	struct clk *ref_clk;
	unsigned int mul;
	const char *name = node->name;
	const char *parent_name;

	of_property_read_string(node, "clock-output-names", &name);
	parent_name = of_clk_get_parent_name(node, 0);

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("%pOF: of_iomap failed\n", node);
		return;
	}

	mul = readl(base + 0x30) >> 3 & 0x3f;
	iounmap(base);

	ref_clk = of_clk_get(node, 0);
	if (IS_ERR(ref_clk)) {
		pr_err("%pOF: of_clk_get failed\n", node);
		return;
	}

	hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
	if (IS_ERR(hw)) {
		pr_err("%pOF: failed to register clock\n", node);
		return;
	}

	clk_hw_register_clkdev(hw, NULL, name);
	of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
	       moxart_of_pll_clk_init);

static void __init moxart_of_apb_clk_init(struct device_node *node)
{
	void __iomem *base;
	struct clk_hw *hw;
	struct clk *pll_clk;
	unsigned int div, val;
	unsigned int div_idx[] = { 2, 3, 4, 6, 8};
	const char *name = node->name;
	const char *parent_name;

	of_property_read_string(node, "clock-output-names", &name);
	parent_name = of_clk_get_parent_name(node, 0);

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("%pOF: of_iomap failed\n", node);
		return;
	}

	val = readl(base + 0xc) >> 4 & 0x7;
	iounmap(base);

	if (val > 4)
		val = 0;
	div = div_idx[val] * 2;

	pll_clk = of_clk_get(node, 0);
	if (IS_ERR(pll_clk)) {
		pr_err("%pOF: of_clk_get failed\n", node);
		return;
	}

	hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
	if (IS_ERR(hw)) {
		pr_err("%pOF: failed to register clock\n", node);
		return;
	}

	clk_hw_register_clkdev(hw, NULL, name);
	of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
}
CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock",
	       moxart_of_apb_clk_init);
Commit	Line	Data
c7bb4fc1 JJ	1	/*
	2	* MOXA ART SoCs clock driver.
	3	*
	4	* Copyright (C) 2013 Jonas Jensen
	5	*
	6	* Jonas Jensen <[email protected]>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
67bb5408	13	#include <linux/clk.h>
c7bb4fc1 JJ	14	#include <linux/clk-provider.h>
	15	#include <linux/io.h>
	16	#include <linux/of_address.h>
	17	#include <linux/clkdev.h>
	18
61ad23a1	19	static void __init moxart_of_pll_clk_init(struct device_node *node)
c7bb4fc1	20	{
c8108cf2	21	void __iomem *base;
5a962d2e SB	22	struct clk_hw *hw;
5a962d2e SB	23	struct clk *ref_clk;
c7bb4fc1 JJ	24	unsigned int mul;
	25	const char *name = node->name;
	26	const char *parent_name;
	27
	28	of_property_read_string(node, "clock-output-names", &name);
	29	parent_name = of_clk_get_parent_name(node, 0);
	30
	31	base = of_iomap(node, 0);
	32	if (!base) {
16673931	33	pr_err("%pOF: of_iomap failed\n", node);
c7bb4fc1 JJ	34	return;
	35	}
	36
	37	mul = readl(base + 0x30) >> 3 & 0x3f;
	38	iounmap(base);
	39
	40	ref_clk = of_clk_get(node, 0);
	41	if (IS_ERR(ref_clk)) {
16673931	42	pr_err("%pOF: of_clk_get failed\n", node);
c7bb4fc1 JJ	43	return;
	44	}
	45
5a962d2e SB	46	hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
5a962d2e SB	47	if (IS_ERR(hw)) {
16673931	48	pr_err("%pOF: failed to register clock\n", node);
c7bb4fc1 JJ	49	return;
	50	}
	51
5a962d2e SB	52	clk_hw_register_clkdev(hw, NULL, name);
5a962d2e SB	53	of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
c7bb4fc1 JJ	54	}
	55	CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
	56	moxart_of_pll_clk_init);
	57
61ad23a1	58	static void __init moxart_of_apb_clk_init(struct device_node *node)
c7bb4fc1	59	{
c8108cf2	60	void __iomem *base;
5a962d2e SB	61	struct clk_hw *hw;
5a962d2e SB	62	struct clk *pll_clk;
c7bb4fc1 JJ	63	unsigned int div, val;
	64	unsigned int div_idx[] = { 2, 3, 4, 6, 8};
	65	const char *name = node->name;
	66	const char *parent_name;
	67
	68	of_property_read_string(node, "clock-output-names", &name);
	69	parent_name = of_clk_get_parent_name(node, 0);
	70
	71	base = of_iomap(node, 0);
	72	if (!base) {
16673931	73	pr_err("%pOF: of_iomap failed\n", node);
c7bb4fc1 JJ	74	return;
	75	}
	76
	77	val = readl(base + 0xc) >> 4 & 0x7;
	78	iounmap(base);
	79
	80	if (val > 4)
	81	val = 0;
	82	div = div_idx[val] * 2;
	83
	84	pll_clk = of_clk_get(node, 0);
	85	if (IS_ERR(pll_clk)) {
16673931	86	pr_err("%pOF: of_clk_get failed\n", node);
c7bb4fc1 JJ	87	return;
	88	}
	89
5a962d2e SB	90	hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
5a962d2e SB	91	if (IS_ERR(hw)) {
16673931	92	pr_err("%pOF: failed to register clock\n", node);
c7bb4fc1 JJ	93	return;
	94	}
	95
5a962d2e SB	96	clk_hw_register_clkdev(hw, NULL, name);
5a962d2e SB	97	of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
c7bb4fc1 JJ	98	}
	99	CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock",
	100	moxart_of_apb_clk_init);