[linux.git] / drivers / pwm / pwm-lpss.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Intel Low Power Subsystem PWM controller driver
 *
 * Copyright (C) 2014, Intel Corporation
 * Author: Mika Westerberg <[email protected]>
 * Author: Chew Kean Ho <[email protected]>
 * Author: Chang Rebecca Swee Fun <[email protected]>
 * Author: Chew Chiau Ee <[email protected]>
 * Author: Alan Cox <[email protected]>
 */

#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/time.h>

#define DEFAULT_SYMBOL_NAMESPACE PWM_LPSS

#include "pwm-lpss.h"

#define PWM				0x00000000
#define PWM_ENABLE			BIT(31)
#define PWM_SW_UPDATE			BIT(30)
#define PWM_BASE_UNIT_SHIFT		8
#define PWM_ON_TIME_DIV_MASK		GENMASK(7, 0)

/* Size of each PWM register space if multiple */
#define PWM_SIZE			0x400

/* BayTrail */
const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
	.clk_rate = 25000000,
	.npwm = 1,
	.base_unit_bits = 16,
};
EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);

/* Braswell */
const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
	.clk_rate = 19200000,
	.npwm = 1,
	.base_unit_bits = 16,
	.other_devices_aml_touches_pwm_regs = true,
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);

/* Broxton */
const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
	.clk_rate = 19200000,
	.npwm = 4,
	.base_unit_bits = 22,
	.bypass = true,
};
EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);

/* Tangier */
const struct pwm_lpss_boardinfo pwm_lpss_tng_info = {
	.clk_rate = 19200000,
	.npwm = 4,
	.base_unit_bits = 22,
};
EXPORT_SYMBOL_GPL(pwm_lpss_tng_info);

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_lpss_chip, chip);
}

static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
	const unsigned int ms = 500 * USEC_PER_MSEC;
	u32 val;
	int err;

	/*
	 * PWM Configuration register has SW_UPDATE bit that is set when a new
	 * configuration is written to the register. The bit is automatically
	 * cleared at the start of the next output cycle by the IP block.
	 *
	 * If one writes a new configuration to the register while it still has
	 * the bit enabled, PWM may freeze. That is, while one can still write
	 * to the register, it won't have an effect. Thus, we try to sleep long
	 * enough that the bit gets cleared and make sure the bit is not
	 * enabled while we update the configuration.
	 */
	err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
	if (err)
		dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");

	return err;
}

static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
{
	if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {
		dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n");
		return -EBUSY;
	}

	return 0;
}

static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
			     int duty_ns, int period_ns)
{
	unsigned long long on_time_div;
	unsigned long c = lpwm->info->clk_rate, base_unit_range;
	unsigned long long base_unit, freq = NSEC_PER_SEC;
	u32 ctrl;

	do_div(freq, period_ns);

	/*
	 * The equation is:
	 * base_unit = round(base_unit_range * freq / c)
	 */
	base_unit_range = BIT(lpwm->info->base_unit_bits);
	freq *= base_unit_range;

	base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
	/* base_unit must not be 0 and we also want to avoid overflowing it */
	base_unit = clamp_val(base_unit, 1, base_unit_range - 1);

	on_time_div = 255ULL * duty_ns;
	do_div(on_time_div, period_ns);
	on_time_div = 255ULL - on_time_div;

	ctrl = pwm_lpss_read(pwm);
	ctrl &= ~PWM_ON_TIME_DIV_MASK;
	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
	ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
	ctrl |= on_time_div;

	pwm_lpss_write(pwm, ctrl);
	pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
}

static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
{
	if (cond)
		pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
}

static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
				   struct pwm_device *pwm,
				   const struct pwm_state *state)
{
	int ret;

	ret = pwm_lpss_is_updating(pwm);
	if (ret)
		return ret;

	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
	ret = pwm_lpss_wait_for_update(pwm);
	if (ret)
		return ret;

	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
	return 0;
}

static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			  const struct pwm_state *state)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	int ret = 0;

	if (state->enabled) {
		if (!pwm_is_enabled(pwm)) {
			pm_runtime_get_sync(chip->dev);
			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
			if (ret)
				pm_runtime_put(chip->dev);
		} else {
			ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
		}
	} else if (pwm_is_enabled(pwm)) {
		pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
		pm_runtime_put(chip->dev);
	}

	return ret;
}

static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
			       struct pwm_state *state)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	unsigned long base_unit_range;
	unsigned long long base_unit, freq, on_time_div;
	u32 ctrl;

	pm_runtime_get_sync(chip->dev);

	base_unit_range = BIT(lpwm->info->base_unit_bits);

	ctrl = pwm_lpss_read(pwm);
	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);

	freq = base_unit * lpwm->info->clk_rate;
	do_div(freq, base_unit_range);
	if (freq == 0)
		state->period = NSEC_PER_SEC;
	else
		state->period = NSEC_PER_SEC / (unsigned long)freq;

	on_time_div *= state->period;
	do_div(on_time_div, 255);
	state->duty_cycle = on_time_div;

	state->polarity = PWM_POLARITY_NORMAL;
	state->enabled = !!(ctrl & PWM_ENABLE);

	pm_runtime_put(chip->dev);
}

static const struct pwm_ops pwm_lpss_ops = {
	.apply = pwm_lpss_apply,
	.get_state = pwm_lpss_get_state,
	.owner = THIS_MODULE,
};

struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base,
				     const struct pwm_lpss_boardinfo *info)
{
	struct pwm_lpss_chip *lpwm;
	unsigned long c;
	int i, ret;
	u32 ctrl;

	if (WARN_ON(info->npwm > MAX_PWMS))
		return ERR_PTR(-ENODEV);

	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
	if (!lpwm)
		return ERR_PTR(-ENOMEM);

	lpwm->regs = base;
	lpwm->info = info;

	c = lpwm->info->clk_rate;
	if (!c)
		return ERR_PTR(-EINVAL);

	lpwm->chip.dev = dev;
	lpwm->chip.ops = &pwm_lpss_ops;
	lpwm->chip.npwm = info->npwm;

	ret = devm_pwmchip_add(dev, &lpwm->chip);
	if (ret) {
		dev_err(dev, "failed to add PWM chip: %d\n", ret);
		return ERR_PTR(ret);
	}

	for (i = 0; i < lpwm->info->npwm; i++) {
		ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
		if (ctrl & PWM_ENABLE)
			pm_runtime_get(dev);
	}

	return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);

MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <[email protected]>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
d16a5aa9 MW	2	/*
	3	* Intel Low Power Subsystem PWM controller driver
	4	*
	5	* Copyright (C) 2014, Intel Corporation
	6	* Author: Mika Westerberg <[email protected]>
	7	* Author: Chew Kean Ho <[email protected]>
	8	* Author: Chang Rebecca Swee Fun <[email protected]>
	9	* Author: Chew Chiau Ee <[email protected]>
093e00bb	10	* Author: Alan Cox <[email protected]>
d16a5aa9 MW	11	*/
d16a5aa9 MW	12
4fdb3281	13	#include <linux/bits.h>
37670676	14	#include <linux/delay.h>
e0c86a3b	15	#include <linux/io.h>
10d56a4c	16	#include <linux/iopoll.h>
d16a5aa9 MW	17	#include <linux/kernel.h>
d16a5aa9 MW	18	#include <linux/module.h>
f080be27	19	#include <linux/pm_runtime.h>
883e4d07	20	#include <linux/time.h>
093e00bb	21
a3682d2f AS	22	#define DEFAULT_SYMBOL_NAMESPACE PWM_LPSS
a3682d2f AS	23
c558e39e	24	#include "pwm-lpss.h"
d16a5aa9 MW	25
	26	#define PWM 0x00000000
	27	#define PWM_ENABLE BIT(31)
	28	#define PWM_SW_UPDATE BIT(30)
	29	#define PWM_BASE_UNIT_SHIFT 8
4fdb3281	30	#define PWM_ON_TIME_DIV_MASK GENMASK(7, 0)
d16a5aa9	31
4e11f5ac MW	32	/* Size of each PWM register space if multiple */
	33	#define PWM_SIZE 0x400
	34
090e78d0 UKK	35	/* BayTrail */
	36	const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
	37	.clk_rate = 25000000,
	38	.npwm = 1,
	39	.base_unit_bits = 16,
	40	};
	41	EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
	42
	43	/* Braswell */
	44	const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
	45	.clk_rate = 19200000,
	46	.npwm = 1,
	47	.base_unit_bits = 16,
	48	.other_devices_aml_touches_pwm_regs = true,
	49	};
	50	EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
	51
	52	/* Broxton */
	53	const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
	54	.clk_rate = 19200000,
	55	.npwm = 4,
	56	.base_unit_bits = 22,
	57	.bypass = true,
	58	};
	59	EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
	60
	61	/* Tangier */
	62	const struct pwm_lpss_boardinfo pwm_lpss_tng_info = {
	63	.clk_rate = 19200000,
	64	.npwm = 4,
	65	.base_unit_bits = 22,
	66	};
	67	EXPORT_SYMBOL_GPL(pwm_lpss_tng_info);
	68
d16a5aa9 MW	69	static inline struct pwm_lpss_chip to_lpwm(struct pwm_chip chip)
	70	{
	71	return container_of(chip, struct pwm_lpss_chip, chip);
	72	}
	73
4e11f5ac MW	74	static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
	75	{
	76	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	77
	78	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	79	}
	80
	81	static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
	82	{
	83	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	84
	85	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	86	}
	87
b997e3ed	88	static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
37670676	89	{
10d56a4c IK	90	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	91	const void __iomem addr = lpwm->regs + pwm->hwpwm PWM_SIZE + PWM;
	92	const unsigned int ms = 500 * USEC_PER_MSEC;
	93	u32 val;
	94	int err;
	95
b14e8cef	96	/*
10d56a4c IK	97	* PWM Configuration register has SW_UPDATE bit that is set when a new
	98	* configuration is written to the register. The bit is automatically
	99	* cleared at the start of the next output cycle by the IP block.
	100	*
	101	* If one writes a new configuration to the register while it still has
	102	* the bit enabled, PWM may freeze. That is, while one can still write
	103	* to the register, it won't have an effect. Thus, we try to sleep long
	104	* enough that the bit gets cleared and make sure the bit is not
	105	* enabled while we update the configuration.
b14e8cef	106	*/
10d56a4c IK	107	err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
	108	if (err)
	109	dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
b14e8cef	110
10d56a4c IK	111	return err;
	112	}
	113
	114	static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
	115	{
d58560e6 HG	116	if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {
	117	dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n");
	118	return -EBUSY;
	119	}
	120
	121	return 0;
37670676 MW	122	}
37670676 MW	123
b14e8cef AS	124	static void pwm_lpss_prepare(struct pwm_lpss_chip lpwm, struct pwm_device pwm,
b14e8cef AS	125	int duty_ns, int period_ns)
d16a5aa9	126	{
ab248b60	127	unsigned long long on_time_div;
d9cd4a73	128	unsigned long c = lpwm->info->clk_rate, base_unit_range;
883e4d07	129	unsigned long long base_unit, freq = NSEC_PER_SEC;
d6d54bac	130	u32 ctrl;
d16a5aa9 MW	131
	132	do_div(freq, period_ns);
	133
883e4d07	134	/*
883e4d07	135	* The equation is:
e5ca4245	136	* base_unit = round(base_unit_range * freq / c)
883e4d07	137	*/
181f4d2f	138	base_unit_range = BIT(lpwm->info->base_unit_bits);
e5ca4245	139	freq *= base_unit_range;
d16a5aa9	140
e5ca4245	141	base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
ef9f60da HG	142	/* base_unit must not be 0 and we also want to avoid overflowing it */
ef9f60da HG	143	base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
d16a5aa9	144
ab248b60 MW	145	on_time_div = 255ULL * duty_ns;
	146	do_div(on_time_div, period_ns);
	147	on_time_div = 255ULL - on_time_div;
d16a5aa9	148
d6d54bac	149	ctrl = pwm_lpss_read(pwm);
883e4d07	150	ctrl &= ~PWM_ON_TIME_DIV_MASK;
181f4d2f	151	ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
883e4d07	152	ctrl \|= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
d16a5aa9	153	ctrl \|= on_time_div;
2153bbc1	154
d6d54bac HG	155	pwm_lpss_write(pwm, ctrl);
d6d54bac HG	156	pwm_lpss_write(pwm, ctrl \| PWM_SW_UPDATE);
d16a5aa9 MW	157	}
d16a5aa9 MW	158
b997e3ed HG	159	static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
	160	{
	161	if (cond)
	162	pwm_lpss_write(pwm, pwm_lpss_read(pwm) \| PWM_ENABLE);
	163	}
	164
092d83e3 HG	165	static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
092d83e3 HG	166	struct pwm_device *pwm,
d6d54bac	167	const struct pwm_state *state)
092d83e3 HG	168	{
	169	int ret;
	170
	171	ret = pwm_lpss_is_updating(pwm);
	172	if (ret)
	173	return ret;
	174
	175	pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
d6d54bac	176	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
092d83e3 HG	177	ret = pwm_lpss_wait_for_update(pwm);
	178	if (ret)
	179	return ret;
	180
d6d54bac	181	pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
092d83e3 HG	182	return 0;
	183	}
	184
b14e8cef	185	static int pwm_lpss_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	186	const struct pwm_state *state)
d16a5aa9	187	{
b14e8cef	188	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
092d83e3	189	int ret = 0;
37670676	190
b14e8cef AS	191	if (state->enabled) {
	192	if (!pwm_is_enabled(pwm)) {
	193	pm_runtime_get_sync(chip->dev);
d6d54bac	194	ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
092d83e3	195	if (ret)
10d56a4c	196	pm_runtime_put(chip->dev);
b14e8cef	197	} else {
d6d54bac	198	ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
b14e8cef AS	199	}
	200	} else if (pwm_is_enabled(pwm)) {
	201	pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
	202	pm_runtime_put(chip->dev);
	203	}
d16a5aa9	204
092d83e3	205	return ret;
d16a5aa9 MW	206	}
d16a5aa9 MW	207
280fec4c HG	208	static void pwm_lpss_get_state(struct pwm_chip chip, struct pwm_device pwm,
	209	struct pwm_state *state)
	210	{
	211	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	212	unsigned long base_unit_range;
	213	unsigned long long base_unit, freq, on_time_div;
	214	u32 ctrl;
	215
01aa905d HG	216	pm_runtime_get_sync(chip->dev);
01aa905d HG	217
280fec4c HG	218	base_unit_range = BIT(lpwm->info->base_unit_bits);
	219
	220	ctrl = pwm_lpss_read(pwm);
	221	on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
	222	base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
	223
	224	freq = base_unit * lpwm->info->clk_rate;
	225	do_div(freq, base_unit_range);
	226	if (freq == 0)
	227	state->period = NSEC_PER_SEC;
	228	else
	229	state->period = NSEC_PER_SEC / (unsigned long)freq;
	230
	231	on_time_div *= state->period;
	232	do_div(on_time_div, 255);
	233	state->duty_cycle = on_time_div;
	234
	235	state->polarity = PWM_POLARITY_NORMAL;
	236	state->enabled = !!(ctrl & PWM_ENABLE);
	237
01aa905d	238	pm_runtime_put(chip->dev);
280fec4c HG	239	}
280fec4c HG	240
d16a5aa9	241	static const struct pwm_ops pwm_lpss_ops = {
b14e8cef	242	.apply = pwm_lpss_apply,
280fec4c	243	.get_state = pwm_lpss_get_state,
d16a5aa9 MW	244	.owner = THIS_MODULE,
	245	};
	246
68af6fb0	247	struct pwm_lpss_chip pwm_lpss_probe(struct device dev, void __iomem *base,
c558e39e	248	const struct pwm_lpss_boardinfo *info)
d16a5aa9 MW	249	{
d16a5aa9 MW	250	struct pwm_lpss_chip *lpwm;
d9cd4a73	251	unsigned long c;
01aa905d HG	252	int i, ret;
01aa905d HG	253	u32 ctrl;
d16a5aa9	254
1d375b58 HG	255	if (WARN_ON(info->npwm > MAX_PWMS))
	256	return ERR_PTR(-ENODEV);
	257
093e00bb	258	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9	259	if (!lpwm)
093e00bb	260	return ERR_PTR(-ENOMEM);
d16a5aa9	261
68af6fb0	262	lpwm->regs = base;
883e4d07	263	lpwm->info = info;
d9cd4a73 AS	264
	265	c = lpwm->info->clk_rate;
	266	if (!c)
	267	return ERR_PTR(-EINVAL);
	268
093e00bb	269	lpwm->chip.dev = dev;
d16a5aa9	270	lpwm->chip.ops = &pwm_lpss_ops;
4e11f5ac	271	lpwm->chip.npwm = info->npwm;
d16a5aa9	272
d1e487b7	273	ret = devm_pwmchip_add(dev, &lpwm->chip);
d16a5aa9	274	if (ret) {
093e00bb AC	275	dev_err(dev, "failed to add PWM chip: %d\n", ret);
093e00bb AC	276	return ERR_PTR(ret);
d16a5aa9 MW	277	}
d16a5aa9 MW	278
01aa905d HG	279	for (i = 0; i < lpwm->info->npwm; i++) {
	280	ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
	281	if (ctrl & PWM_ENABLE)
	282	pm_runtime_get(dev);
	283	}
	284
093e00bb	285	return lpwm;
d16a5aa9	286	}
c558e39e	287	EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9	288
d16a5aa9 MW	289	MODULE_DESCRIPTION("PWM driver for Intel LPSS");
	290	MODULE_AUTHOR("Mika Westerberg <[email protected]>");
	291	MODULE_LICENSE("GPL v2");