[linux.git] / drivers / ata / pata_imx.c

/*
 * Freescale iMX PATA driver
 *
 * Copyright (C) 2011 Arnaud Patard <[email protected]>
 *
 * Based on pata_platform - Copyright (C) 2006 - 2007  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * TODO:
 * - dmaengine support
 */

#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#define DRV_NAME "pata_imx"

#define PATA_IMX_ATA_TIME_OFF		0x00
#define PATA_IMX_ATA_TIME_ON		0x01
#define PATA_IMX_ATA_TIME_1		0x02
#define PATA_IMX_ATA_TIME_2W		0x03
#define PATA_IMX_ATA_TIME_2R		0x04
#define PATA_IMX_ATA_TIME_AX		0x05
#define PATA_IMX_ATA_TIME_PIO_RDX	0x06
#define PATA_IMX_ATA_TIME_4		0x07
#define PATA_IMX_ATA_TIME_9		0x08

#define PATA_IMX_ATA_CONTROL		0x24
#define PATA_IMX_ATA_CTRL_FIFO_RST_B	(1<<7)
#define PATA_IMX_ATA_CTRL_ATA_RST_B	(1<<6)
#define PATA_IMX_ATA_CTRL_IORDY_EN	(1<<0)
#define PATA_IMX_ATA_INT_EN		0x2C
#define PATA_IMX_ATA_INTR_ATA_INTRQ2	(1<<3)
#define PATA_IMX_DRIVE_DATA		0xA0
#define PATA_IMX_DRIVE_CONTROL		0xD8

static u32 pio_t4[] = { 30,  20,  15,  10,  10 };
static u32 pio_t9[] = { 20,  15,  10,  10,  10 };
static u32 pio_tA[] = { 35,  35,  35,  35,  35 };

struct pata_imx_priv {
	struct clk *clk;
	/* timings/interrupt/control regs */
	void __iomem *host_regs;
	u32 ata_ctl;
};

static void pata_imx_set_timing(struct ata_device *adev,
				struct pata_imx_priv *priv)
{
	struct ata_timing timing;
	unsigned long clkrate;
	u32 T, mode;

	clkrate = clk_get_rate(priv->clk);

	if (adev->pio_mode < XFER_PIO_0 || adev->pio_mode > XFER_PIO_4 ||
	    !clkrate)
		return;

	T = 1000000000 / clkrate;
	ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);

	mode = adev->pio_mode - XFER_PIO_0;

	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
	writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
	writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);

	writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
	writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
	writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX);
}

static void pata_imx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pata_imx_priv *priv = ap->host->private_data;
	u32 val;

	pata_imx_set_timing(adev, priv);

	val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
	if (ata_pio_need_iordy(adev))
		val |= PATA_IMX_ATA_CTRL_IORDY_EN;
	else
		val &= ~PATA_IMX_ATA_CTRL_IORDY_EN;
	__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
}

static struct scsi_host_template pata_imx_sht = {
	ATA_PIO_SHT(DRV_NAME),
};

static struct ata_port_operations pata_imx_port_ops = {
	.inherits		= &ata_sff_port_ops,
	.sff_data_xfer		= ata_sff_data_xfer_noirq,
	.cable_detect		= ata_cable_unknown,
	.set_piomode		= pata_imx_set_piomode,
};

static void pata_imx_setup_port(struct ata_ioports *ioaddr)
{
	/* Fixup the port shift for platforms that need it */
	ioaddr->data_addr	= ioaddr->cmd_addr + (ATA_REG_DATA    << 2);
	ioaddr->error_addr	= ioaddr->cmd_addr + (ATA_REG_ERR     << 2);
	ioaddr->feature_addr	= ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
	ioaddr->nsect_addr	= ioaddr->cmd_addr + (ATA_REG_NSECT   << 2);
	ioaddr->lbal_addr	= ioaddr->cmd_addr + (ATA_REG_LBAL    << 2);
	ioaddr->lbam_addr	= ioaddr->cmd_addr + (ATA_REG_LBAM    << 2);
	ioaddr->lbah_addr	= ioaddr->cmd_addr + (ATA_REG_LBAH    << 2);
	ioaddr->device_addr	= ioaddr->cmd_addr + (ATA_REG_DEVICE  << 2);
	ioaddr->status_addr	= ioaddr->cmd_addr + (ATA_REG_STATUS  << 2);
	ioaddr->command_addr	= ioaddr->cmd_addr + (ATA_REG_CMD     << 2);
}

static int pata_imx_probe(struct platform_device *pdev)
{
	struct ata_host *host;
	struct ata_port *ap;
	struct pata_imx_priv *priv;
	int irq = 0;
	struct resource *io_res;
	int ret;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	priv = devm_kzalloc(&pdev->dev,
				sizeof(struct pata_imx_priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(priv->clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return PTR_ERR(priv->clk);
	}

	ret = clk_prepare_enable(priv->clk);
	if (ret)
		return ret;

	host = ata_host_alloc(&pdev->dev, 1);
	if (!host) {
		ret = -ENOMEM;
		goto err;
	}

	host->private_data = priv;
	ap = host->ports[0];

	ap->ops = &pata_imx_port_ops;
	ap->pio_mask = ATA_PIO4;
	ap->flags |= ATA_FLAG_SLAVE_POSS;

	io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->host_regs = devm_ioremap_resource(&pdev->dev, io_res);
	if (IS_ERR(priv->host_regs)) {
		ret = PTR_ERR(priv->host_regs);
		goto err;
	}

	ap->ioaddr.cmd_addr = priv->host_regs + PATA_IMX_DRIVE_DATA;
	ap->ioaddr.ctl_addr = priv->host_regs + PATA_IMX_DRIVE_CONTROL;

	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;

	pata_imx_setup_port(&ap->ioaddr);

	ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
		(unsigned long long)io_res->start + PATA_IMX_DRIVE_DATA,
		(unsigned long long)io_res->start + PATA_IMX_DRIVE_CONTROL);

	/* deassert resets */
	__raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B |
			PATA_IMX_ATA_CTRL_ATA_RST_B,
			priv->host_regs + PATA_IMX_ATA_CONTROL);
	/* enable interrupts */
	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
			priv->host_regs + PATA_IMX_ATA_INT_EN);

	/* activate */
	ret = ata_host_activate(host, irq, ata_sff_interrupt, 0,
				&pata_imx_sht);

	if (ret)
		goto err;

	return 0;
err:
	clk_disable_unprepare(priv->clk);

	return ret;
}

static int pata_imx_remove(struct platform_device *pdev)
{
	struct ata_host *host = platform_get_drvdata(pdev);
	struct pata_imx_priv *priv = host->private_data;

	ata_host_detach(host);

	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);

	clk_disable_unprepare(priv->clk);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int pata_imx_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct pata_imx_priv *priv = host->private_data;
	int ret;

	ret = ata_host_suspend(host, PMSG_SUSPEND);
	if (!ret) {
		__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
		priv->ata_ctl =
			__raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
		clk_disable_unprepare(priv->clk);
	}

	return ret;
}

static int pata_imx_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct pata_imx_priv *priv = host->private_data;

	int ret = clk_prepare_enable(priv->clk);
	if (ret)
		return ret;

	__raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL);

	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
			priv->host_regs + PATA_IMX_ATA_INT_EN);

	ata_host_resume(host);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(pata_imx_pm_ops, pata_imx_suspend, pata_imx_resume);

static const struct of_device_id imx_pata_dt_ids[] = {
	{
		.compatible = "fsl,imx27-pata",
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(of, imx_pata_dt_ids);

static struct platform_driver pata_imx_driver = {
	.probe		= pata_imx_probe,
	.remove		= pata_imx_remove,
	.driver = {
		.name		= DRV_NAME,
		.of_match_table	= imx_pata_dt_ids,
		.pm		= &pata_imx_pm_ops,
	},
};

module_platform_driver(pata_imx_driver);

MODULE_AUTHOR("Arnaud Patard <[email protected]>");
MODULE_DESCRIPTION("low-level driver for iMX PATA");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
e39c75cf AP	1	/*
	2	* Freescale iMX PATA driver
	3	*
	4	* Copyright (C) 2011 Arnaud Patard <[email protected]>
	5	*
	6	* Based on pata_platform - Copyright (C) 2006 - 2007 Paul Mundt
	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*
	12	* TODO:
	13	* - dmaengine support
e39c75cf	14	*/
07b9733f	15
e39c75cf	16	#include <linux/ata.h>
07b9733f	17	#include <linux/clk.h>
e39c75cf	18	#include <linux/libata.h>
07b9733f	19	#include <linux/module.h>
e39c75cf	20	#include <linux/platform_device.h>
e39c75cf AP	21
	22	#define DRV_NAME "pata_imx"
	23
fab43e14 VZ	24	#define PATA_IMX_ATA_TIME_OFF 0x00
	25	#define PATA_IMX_ATA_TIME_ON 0x01
	26	#define PATA_IMX_ATA_TIME_1 0x02
	27	#define PATA_IMX_ATA_TIME_2W 0x03
	28	#define PATA_IMX_ATA_TIME_2R 0x04
	29	#define PATA_IMX_ATA_TIME_AX 0x05
	30	#define PATA_IMX_ATA_TIME_PIO_RDX 0x06
	31	#define PATA_IMX_ATA_TIME_4 0x07
	32	#define PATA_IMX_ATA_TIME_9 0x08
	33
e39c75cf AP	34	#define PATA_IMX_ATA_CONTROL 0x24
	35	#define PATA_IMX_ATA_CTRL_FIFO_RST_B (1<<7)
	36	#define PATA_IMX_ATA_CTRL_ATA_RST_B (1<<6)
	37	#define PATA_IMX_ATA_CTRL_IORDY_EN (1<<0)
	38	#define PATA_IMX_ATA_INT_EN 0x2C
	39	#define PATA_IMX_ATA_INTR_ATA_INTRQ2 (1<<3)
	40	#define PATA_IMX_DRIVE_DATA 0xA0
	41	#define PATA_IMX_DRIVE_CONTROL 0xD8
	42
fab43e14 VZ	43	static u32 pio_t4[] = { 30, 20, 15, 10, 10 };
	44	static u32 pio_t9[] = { 20, 15, 10, 10, 10 };
	45	static u32 pio_tA[] = { 35, 35, 35, 35, 35 };
	46
e39c75cf AP	47	struct pata_imx_priv {
	48	struct clk *clk;
	49	/* timings/interrupt/control regs */
51b5539c	50	void __iomem *host_regs;
e39c75cf AP	51	u32 ata_ctl;
	52	};
	53
fab43e14 VZ	54	static void pata_imx_set_timing(struct ata_device *adev,
	55	struct pata_imx_priv *priv)
	56	{
	57	struct ata_timing timing;
	58	unsigned long clkrate;
	59	u32 T, mode;
	60
	61	clkrate = clk_get_rate(priv->clk);
	62
	63	if (adev->pio_mode < XFER_PIO_0 \|\| adev->pio_mode > XFER_PIO_4 \|\|
	64	!clkrate)
	65	return;
	66
	67	T = 1000000000 / clkrate;
	68	ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0);
	69
	70	mode = adev->pio_mode - XFER_PIO_0;
	71
	72	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_OFF);
	73	writeb(3, priv->host_regs + PATA_IMX_ATA_TIME_ON);
	74	writeb(timing.setup, priv->host_regs + PATA_IMX_ATA_TIME_1);
	75	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2W);
	76	writeb(timing.act8b, priv->host_regs + PATA_IMX_ATA_TIME_2R);
	77	writeb(1, priv->host_regs + PATA_IMX_ATA_TIME_PIO_RDX);
	78
	79	writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4);
	80	writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9);
	81	writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX);
	82	}
	83
65a443ea	84	static void pata_imx_set_piomode(struct ata_port ap, struct ata_device adev)
e39c75cf	85	{
e39c75cf AP	86	struct pata_imx_priv *priv = ap->host->private_data;
	87	u32 val;
	88
fab43e14 VZ	89	pata_imx_set_timing(adev, priv);
fab43e14 VZ	90
65a443ea VZ	91	val = __raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
	92	if (ata_pio_need_iordy(adev))
	93	val \|= PATA_IMX_ATA_CTRL_IORDY_EN;
	94	else
	95	val &= ~PATA_IMX_ATA_CTRL_IORDY_EN;
	96	__raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL);
e39c75cf AP	97	}
	98
	99	static struct scsi_host_template pata_imx_sht = {
	100	ATA_PIO_SHT(DRV_NAME),
	101	};
	102
	103	static struct ata_port_operations pata_imx_port_ops = {
	104	.inherits = &ata_sff_port_ops,
	105	.sff_data_xfer = ata_sff_data_xfer_noirq,
	106	.cable_detect = ata_cable_unknown,
65a443ea	107	.set_piomode = pata_imx_set_piomode,
e39c75cf AP	108	};
	109
	110	static void pata_imx_setup_port(struct ata_ioports *ioaddr)
	111	{
	112	/* Fixup the port shift for platforms that need it */
	113	ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
	114	ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
	115	ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
	116	ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
	117	ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
	118	ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
	119	ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
	120	ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
	121	ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
	122	ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
	123	}
	124
0ec24914	125	static int pata_imx_probe(struct platform_device *pdev)
e39c75cf AP	126	{
	127	struct ata_host *host;
	128	struct ata_port *ap;
	129	struct pata_imx_priv *priv;
	130	int irq = 0;
	131	struct resource *io_res;
ff540d02	132	int ret;
e39c75cf	133
e39c75cf	134	irq = platform_get_irq(pdev, 0);
3ef9cc31 FE	135	if (irq < 0)
3ef9cc31 FE	136	return irq;
e39c75cf AP	137
	138	priv = devm_kzalloc(&pdev->dev,
	139	sizeof(struct pata_imx_priv), GFP_KERNEL);
	140	if (!priv)
	141	return -ENOMEM;
	142
50f5a341	143	priv->clk = devm_clk_get(&pdev->dev, NULL);
e39c75cf AP	144	if (IS_ERR(priv->clk)) {
	145	dev_err(&pdev->dev, "Failed to get clock\n");
	146	return PTR_ERR(priv->clk);
	147	}
	148
0475c947 FE	149	ret = clk_prepare_enable(priv->clk);
	150	if (ret)
	151	return ret;
e39c75cf AP	152
e39c75cf AP	153	host = ata_host_alloc(&pdev->dev, 1);
ff540d02 SH	154	if (!host) {
	155	ret = -ENOMEM;
	156	goto err;
	157	}
e39c75cf AP	158
	159	host->private_data = priv;
	160	ap = host->ports[0];
	161
	162	ap->ops = &pata_imx_port_ops;
b986723c	163	ap->pio_mask = ATA_PIO4;
e39c75cf AP	164	ap->flags \|= ATA_FLAG_SLAVE_POSS;
e39c75cf AP	165
b314fc77 FE	166	io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b314fc77 FE	167	priv->host_regs = devm_ioremap_resource(&pdev->dev, io_res);
13e8e78b BZ	168	if (IS_ERR(priv->host_regs)) {
13e8e78b BZ	169	ret = PTR_ERR(priv->host_regs);
ff540d02	170	goto err;
e39c75cf AP	171	}
	172
	173	ap->ioaddr.cmd_addr = priv->host_regs + PATA_IMX_DRIVE_DATA;
	174	ap->ioaddr.ctl_addr = priv->host_regs + PATA_IMX_DRIVE_CONTROL;
	175
	176	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	177
	178	pata_imx_setup_port(&ap->ioaddr);
	179
	180	ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
	181	(unsigned long long)io_res->start + PATA_IMX_DRIVE_DATA,
	182	(unsigned long long)io_res->start + PATA_IMX_DRIVE_CONTROL);
	183
	184	/* deassert resets */
	185	__raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B \|
	186	PATA_IMX_ATA_CTRL_ATA_RST_B,
	187	priv->host_regs + PATA_IMX_ATA_CONTROL);
	188	/* enable interrupts */
	189	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
	190	priv->host_regs + PATA_IMX_ATA_INT_EN);
	191
	192	/* activate */
ff540d02	193	ret = ata_host_activate(host, irq, ata_sff_interrupt, 0,
e39c75cf AP	194	&pata_imx_sht);
e39c75cf AP	195
ff540d02 SH	196	if (ret)
	197	goto err;
	198
	199	return 0;
	200	err:
a18dada0	201	clk_disable_unprepare(priv->clk);
50f5a341	202
ff540d02	203	return ret;
e39c75cf AP	204	}
e39c75cf AP	205
0ec24914	206	static int pata_imx_remove(struct platform_device *pdev)
e39c75cf	207	{
d89995db	208	struct ata_host *host = platform_get_drvdata(pdev);
e39c75cf AP	209	struct pata_imx_priv *priv = host->private_data;
	210
	211	ata_host_detach(host);
	212
	213	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
	214
a18dada0	215	clk_disable_unprepare(priv->clk);
e39c75cf AP	216
	217	return 0;
	218	}
	219
58eb8cd5	220	#ifdef CONFIG_PM_SLEEP
e39c75cf AP	221	static int pata_imx_suspend(struct device *dev)
	222	{
	223	struct ata_host *host = dev_get_drvdata(dev);
	224	struct pata_imx_priv *priv = host->private_data;
	225	int ret;
	226
	227	ret = ata_host_suspend(host, PMSG_SUSPEND);
	228	if (!ret) {
	229	__raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN);
	230	priv->ata_ctl =
	231	__raw_readl(priv->host_regs + PATA_IMX_ATA_CONTROL);
a18dada0	232	clk_disable_unprepare(priv->clk);
e39c75cf AP	233	}
	234
	235	return ret;
	236	}
	237
	238	static int pata_imx_resume(struct device *dev)
	239	{
	240	struct ata_host *host = dev_get_drvdata(dev);
	241	struct pata_imx_priv *priv = host->private_data;
	242
0475c947 FE	243	int ret = clk_prepare_enable(priv->clk);
	244	if (ret)
	245	return ret;
e39c75cf AP	246
	247	__raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL);
	248
	249	__raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2,
	250	priv->host_regs + PATA_IMX_ATA_INT_EN);
	251
	252	ata_host_resume(host);
	253
	254	return 0;
	255	}
e39c75cf AP	256	#endif
e39c75cf AP	257
36888e95 FE	258	static SIMPLE_DEV_PM_OPS(pata_imx_pm_ops, pata_imx_suspend, pata_imx_resume);
36888e95 FE	259
b9d15db2 SH	260	static const struct of_device_id imx_pata_dt_ids[] = {
	261	{
	262	.compatible = "fsl,imx27-pata",
	263	}, {
	264	/* sentinel */
	265	}
	266	};
71ab1d58	267	MODULE_DEVICE_TABLE(of, imx_pata_dt_ids);
b9d15db2	268
e39c75cf AP	269	static struct platform_driver pata_imx_driver = {
e39c75cf AP	270	.probe = pata_imx_probe,
0ec24914	271	.remove = pata_imx_remove,
e39c75cf AP	272	.driver = {
e39c75cf AP	273	.name = DRV_NAME,
b9d15db2	274	.of_match_table = imx_pata_dt_ids,
e39c75cf	275	.pm = &pata_imx_pm_ops,
e39c75cf AP	276	},
	277	};
	278
99c8ea3e	279	module_platform_driver(pata_imx_driver);
e39c75cf AP	280
	281	MODULE_AUTHOR("Arnaud Patard <[email protected]>");
	282	MODULE_DESCRIPTION("low-level driver for iMX PATA");
	283	MODULE_LICENSE("GPL");
	284	MODULE_ALIAS("platform:" DRV_NAME);