[linux.git] / drivers / pinctrl / pinctrl-tegra.h

/*
 * Driver for the NVIDIA Tegra pinmux
 *
 * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef __PINMUX_TEGRA_H__
#define __PINMUX_TEGRA_H__

enum tegra_pinconf_param {
	/* argument: tegra_pinconf_pull */
	TEGRA_PINCONF_PARAM_PULL,
	/* argument: tegra_pinconf_tristate */
	TEGRA_PINCONF_PARAM_TRISTATE,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_ENABLE_INPUT,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_OPEN_DRAIN,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_LOCK,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_IORESET,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_RCV_SEL,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_SCHMITT,
	/* argument: Boolean */
	TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
	/* argument: Integer, range is HW-dependant */
	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
	/* argument: Integer, range is HW-dependant */
	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
	/* argument: Integer, range is HW-dependant */
	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
	/* argument: Integer, range is HW-dependant */
	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
	/* argument: Integer, range is HW-dependant */
	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
};

enum tegra_pinconf_pull {
	TEGRA_PINCONFIG_PULL_NONE,
	TEGRA_PINCONFIG_PULL_DOWN,
	TEGRA_PINCONFIG_PULL_UP,
};

enum tegra_pinconf_tristate {
	TEGRA_PINCONFIG_DRIVEN,
	TEGRA_PINCONFIG_TRISTATE,
};

#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)

/**
 * struct tegra_function - Tegra pinctrl mux function
 * @name: The name of the function, exported to pinctrl core.
 * @groups: An array of pin groups that may select this function.
 * @ngroups: The number of entries in @groups.
 */
struct tegra_function {
	const char *name;
	const char **groups;
	unsigned ngroups;
};

/**
 * struct tegra_pingroup - Tegra pin group
 * @name		The name of the pin group.
 * @pins		An array of pin IDs included in this pin group.
 * @npins		The number of entries in @pins.
 * @funcs		The mux functions which can be muxed onto this group.
 * @mux_reg:		Mux register offset.
 *			This register contains the mux, einput, odrain, lock,
 *			ioreset, rcv_sel parameters.
 * @mux_bank:		Mux register bank.
 * @mux_bit:		Mux register bit.
 * @pupd_reg:		Pull-up/down register offset.
 * @pupd_bank:		Pull-up/down register bank.
 * @pupd_bit:		Pull-up/down register bit.
 * @tri_reg:		Tri-state register offset.
 * @tri_bank:		Tri-state register bank.
 * @tri_bit:		Tri-state register bit.
 * @einput_bit:		Enable-input register bit.
 * @odrain_bit:		Open-drain register bit.
 * @lock_bit:		Lock register bit.
 * @ioreset_bit:	IO reset register bit.
 * @rcv_sel_bit:	Receiver select bit.
 * @drv_reg:		Drive fields register offset.
 *			This register contains hsm, schmitt, lpmd, drvdn,
 *			drvup, slwr, slwf, and drvtype parameters.
 * @drv_bank:		Drive fields register bank.
 * @hsm_bit:		High Speed Mode register bit.
 * @schmitt_bit:	Scmitt register bit.
 * @lpmd_bit:		Low Power Mode register bit.
 * @drvdn_bit:		Drive Down register bit.
 * @drvdn_width:	Drive Down field width.
 * @drvup_bit:		Drive Up register bit.
 * @drvup_width:	Drive Up field width.
 * @slwr_bit:		Slew Rising register bit.
 * @slwr_width:		Slew Rising field width.
 * @slwf_bit:		Slew Falling register bit.
 * @slwf_width:		Slew Falling field width.
 * @drvtype_bit:	Drive type register bit.
 *
 * -1 in a *_reg field means that feature is unsupported for this group.
 * *_bank and *_reg values are irrelevant when *_reg is -1.
 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
 *
 * A representation of a group of pins (possibly just one pin) in the Tegra
 * pin controller. Each group allows some parameter or parameters to be
 * configured. The most common is mux function selection. Many others exist
 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
 * certain groups may only support configuring certain parameters, hence
 * each parameter is optional.
 */
struct tegra_pingroup {
	const char *name;
	const unsigned *pins;
	u8 npins;
	u8 funcs[4];
	s16 mux_reg;
	s16 pupd_reg;
	s16 tri_reg;
	s16 drv_reg;
	u32 mux_bank:2;
	u32 pupd_bank:2;
	u32 tri_bank:2;
	u32 drv_bank:2;
	s32 mux_bit:6;
	s32 pupd_bit:6;
	s32 tri_bit:6;
	s32 einput_bit:6;
	s32 odrain_bit:6;
	s32 lock_bit:6;
	s32 ioreset_bit:6;
	s32 rcv_sel_bit:6;
	s32 hsm_bit:6;
	s32 schmitt_bit:6;
	s32 lpmd_bit:6;
	s32 drvdn_bit:6;
	s32 drvup_bit:6;
	s32 slwr_bit:6;
	s32 slwf_bit:6;
	s32 drvtype_bit:6;
	s32 drvdn_width:6;
	s32 drvup_width:6;
	s32 slwr_width:6;
	s32 slwf_width:6;
};

/**
 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
 * @ngpios:	The number of GPIO pins the pin controller HW affects.
 * @pins:	An array describing all pins the pin controller affects.
 *		All pins which are also GPIOs must be listed first within the
 *		array, and be numbered identically to the GPIO controller's
 *		numbering.
 * @npins:	The numbmer of entries in @pins.
 * @functions:	An array describing all mux functions the SoC supports.
 * @nfunctions:	The numbmer of entries in @functions.
 * @groups:	An array describing all pin groups the pin SoC supports.
 * @ngroups:	The numbmer of entries in @groups.
 */
struct tegra_pinctrl_soc_data {
	unsigned ngpios;
	const struct pinctrl_pin_desc *pins;
	unsigned npins;
	struct tegra_function *functions;
	unsigned nfunctions;
	const struct tegra_pingroup *groups;
	unsigned ngroups;
	bool hsm_in_mux;
	bool schmitt_in_mux;
	bool drvtype_in_mux;
};

int tegra_pinctrl_probe(struct platform_device *pdev,
			const struct tegra_pinctrl_soc_data *soc_data);
int tegra_pinctrl_remove(struct platform_device *pdev);

#endif
Commit	Line	Data
971dac71 SW	1	/*
	2	* Driver for the NVIDIA Tegra pinmux
	3	*
	4	* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*/
	15
	16	#ifndef __PINMUX_TEGRA_H__
	17	#define __PINMUX_TEGRA_H__
	18
3b2f9412 SW	19	enum tegra_pinconf_param {
	20	/* argument: tegra_pinconf_pull */
	21	TEGRA_PINCONF_PARAM_PULL,
	22	/* argument: tegra_pinconf_tristate */
	23	TEGRA_PINCONF_PARAM_TRISTATE,
	24	/* argument: Boolean */
	25	TEGRA_PINCONF_PARAM_ENABLE_INPUT,
	26	/* argument: Boolean */
	27	TEGRA_PINCONF_PARAM_OPEN_DRAIN,
	28	/* argument: Boolean */
	29	TEGRA_PINCONF_PARAM_LOCK,
	30	/* argument: Boolean */
	31	TEGRA_PINCONF_PARAM_IORESET,
	32	/* argument: Boolean */
348d1bf7 PR	33	TEGRA_PINCONF_PARAM_RCV_SEL,
348d1bf7 PR	34	/* argument: Boolean */
3b2f9412 SW	35	TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
	36	/* argument: Boolean */
	37	TEGRA_PINCONF_PARAM_SCHMITT,
	38	/* argument: Boolean */
	39	TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
	40	/* argument: Integer, range is HW-dependant */
	41	TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
	42	/* argument: Integer, range is HW-dependant */
	43	TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
	44	/* argument: Integer, range is HW-dependant */
	45	TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
	46	/* argument: Integer, range is HW-dependant */
	47	TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
348d1bf7 PR	48	/* argument: Integer, range is HW-dependant */
348d1bf7 PR	49	TEGRA_PINCONF_PARAM_DRIVE_TYPE,
3b2f9412 SW	50	};
	51
	52	enum tegra_pinconf_pull {
	53	TEGRA_PINCONFIG_PULL_NONE,
	54	TEGRA_PINCONFIG_PULL_DOWN,
	55	TEGRA_PINCONFIG_PULL_UP,
	56	};
	57
	58	enum tegra_pinconf_tristate {
	59	TEGRA_PINCONFIG_DRIVEN,
	60	TEGRA_PINCONFIG_TRISTATE,
	61	};
	62
	63	#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 \| (_arg_))
	64	#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
	65	#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
	66
971dac71 SW	67	/**
	68	* struct tegra_function - Tegra pinctrl mux function
	69	* @name: The name of the function, exported to pinctrl core.
	70	* @groups: An array of pin groups that may select this function.
	71	* @ngroups: The number of entries in @groups.
	72	*/
	73	struct tegra_function {
	74	const char *name;
ce436254	75	const char **groups;
971dac71 SW	76	unsigned ngroups;
	77	};
	78
	79	/**
	80	* struct tegra_pingroup - Tegra pin group
443ac953 SW	81	* @name The name of the pin group.
	82	* @pins An array of pin IDs included in this pin group.
	83	* @npins The number of entries in @pins.
	84	* @funcs The mux functions which can be muxed onto this group.
e53b7974 SW	85	* @mux_reg: Mux register offset.
	86	* This register contains the mux, einput, odrain, lock,
	87	* ioreset, rcv_sel parameters.
	88	* @mux_bank: Mux register bank.
	89	* @mux_bit: Mux register bit.
	90	* @pupd_reg: Pull-up/down register offset.
	91	* @pupd_bank: Pull-up/down register bank.
	92	* @pupd_bit: Pull-up/down register bit.
	93	* @tri_reg: Tri-state register offset.
	94	* @tri_bank: Tri-state register bank.
	95	* @tri_bit: Tri-state register bit.
	96	* @einput_bit: Enable-input register bit.
	97	* @odrain_bit: Open-drain register bit.
	98	* @lock_bit: Lock register bit.
	99	* @ioreset_bit: IO reset register bit.
	100	* @rcv_sel_bit: Receiver select bit.
	101	* @drv_reg: Drive fields register offset.
	102	* This register contains hsm, schmitt, lpmd, drvdn,
	103	* drvup, slwr, slwf, and drvtype parameters.
	104	* @drv_bank: Drive fields register bank.
	105	* @hsm_bit: High Speed Mode register bit.
	106	* @schmitt_bit: Scmitt register bit.
	107	* @lpmd_bit: Low Power Mode register bit.
	108	* @drvdn_bit: Drive Down register bit.
	109	* @drvdn_width: Drive Down field width.
	110	* @drvup_bit: Drive Up register bit.
	111	* @drvup_width: Drive Up field width.
	112	* @slwr_bit: Slew Rising register bit.
	113	* @slwr_width: Slew Rising field width.
	114	* @slwf_bit: Slew Falling register bit.
	115	* @slwf_width: Slew Falling field width.
	116	* @drvtype_bit: Drive type register bit.
	117	*
	118	* -1 in a *_reg field means that feature is unsupported for this group.
	119	* _bank and _reg values are irrelevant when *_reg is -1.
	120	* When _reg is valid, _bit may be -1 to indicate an unsupported feature.
971dac71 SW	121	*
	122	* A representation of a group of pins (possibly just one pin) in the Tegra
	123	* pin controller. Each group allows some parameter or parameters to be
	124	* configured. The most common is mux function selection. Many others exist
	125	* such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
	126	* certain groups may only support configuring certain parameters, hence
e53b7974	127	* each parameter is optional.
971dac71 SW	128	*/
	129	struct tegra_pingroup {
	130	const char *name;
	131	const unsigned *pins;
0298fc3e SW	132	u8 npins;
0298fc3e SW	133	u8 funcs[4];
971dac71 SW	134	s16 mux_reg;
	135	s16 pupd_reg;
	136	s16 tri_reg;
971dac71 SW	137	s16 drv_reg;
	138	u32 mux_bank:2;
	139	u32 pupd_bank:2;
	140	u32 tri_bank:2;
971dac71	141	u32 drv_bank:2;
e4c02dce SA	142	s32 mux_bit:6;
	143	s32 pupd_bit:6;
	144	s32 tri_bit:6;
	145	s32 einput_bit:6;
	146	s32 odrain_bit:6;
	147	s32 lock_bit:6;
	148	s32 ioreset_bit:6;
	149	s32 rcv_sel_bit:6;
	150	s32 hsm_bit:6;
	151	s32 schmitt_bit:6;
	152	s32 lpmd_bit:6;
	153	s32 drvdn_bit:6;
	154	s32 drvup_bit:6;
	155	s32 slwr_bit:6;
	156	s32 slwf_bit:6;
	157	s32 drvtype_bit:6;
	158	s32 drvdn_width:6;
	159	s32 drvup_width:6;
	160	s32 slwr_width:6;
	161	s32 slwf_width:6;
971dac71 SW	162	};
	163
	164	/**
	165	* struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
	166	* @ngpios: The number of GPIO pins the pin controller HW affects.
	167	* @pins: An array describing all pins the pin controller affects.
	168	* All pins which are also GPIOs must be listed first within the
	169	* array, and be numbered identically to the GPIO controller's
	170	* numbering.
	171	* @npins: The numbmer of entries in @pins.
	172	* @functions: An array describing all mux functions the SoC supports.
	173	* @nfunctions: The numbmer of entries in @functions.
	174	* @groups: An array describing all pin groups the pin SoC supports.
	175	* @ngroups: The numbmer of entries in @groups.
	176	*/
	177	struct tegra_pinctrl_soc_data {
	178	unsigned ngpios;
	179	const struct pinctrl_pin_desc *pins;
	180	unsigned npins;
ce436254	181	struct tegra_function *functions;
971dac71 SW	182	unsigned nfunctions;
	183	const struct tegra_pingroup *groups;
	184	unsigned ngroups;
ea623061 SW	185	bool hsm_in_mux;
	186	bool schmitt_in_mux;
	187	bool drvtype_in_mux;
971dac71 SW	188	};
971dac71 SW	189
52f48fe0 SW	190	int tegra_pinctrl_probe(struct platform_device *pdev,
	191	const struct tegra_pinctrl_soc_data *soc_data);
	192	int tegra_pinctrl_remove(struct platform_device *pdev);
971dac71 SW	193
971dac71 SW	194	#endif