]> Git Repo - linux.git/blame - drivers/mfd/tc6393xb.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'compiler-attributes-for-linus-4.20-rc1' of https://github.com/ojeda/linux
[linux.git] / drivers / mfd / tc6393xb.c
CommitLineData
d6315949
DB		 1/*
2 * Toshiba TC6393XB SoC support
3 *
4 * Copyright(c) 2005-2006 Chris Humbert
5 * Copyright(c) 2005 Dirk Opfer
6 * Copyright(c) 2005 Ian Molton <[email protected]>
7 * Copyright(c) 2007 Dmitry Baryshkov
8 *
9 * Based on code written by Sharp/Lineo for 2.4 kernels
10 * Based on locomo.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/platform_device.h>
d6315949 22#include <linux/clk.h>
25d6cbd8 23#include <linux/err.h>
f024ff10
DB		 24#include <linux/mfd/core.h>
25#include <linux/mfd/tmio.h>
d6315949 26#include <linux/mfd/tc6393xb.h>
4e125f62 27#include <linux/gpio/driver.h>
5a0e3ad6 28#include <linux/slab.h>
d6315949
DB		 29
30#define SCR_REVID 0x08 /* b Revision ID */
31#define SCR_ISR 0x50 /* b Interrupt Status */
32#define SCR_IMR 0x52 /* b Interrupt Mask */
33#define SCR_IRR 0x54 /* b Interrupt Routing */
34#define SCR_GPER 0x60 /* w GP Enable */
35#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
36#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
37#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
38#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
39#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
40#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
41#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
42#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
43#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
44#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
45#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
46#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
47#define SCR_CCR 0x98 /* w Clock Control */
48#define SCR_PLL2CR 0x9a /* w PLL2 Control */
49#define SCR_PLL1CR 0x9c /* l PLL1 Control */
50#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
51#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
52#define SCR_FER 0xe0 /* b Function Enable */
53#define SCR_MCR 0xe4 /* w Mode Control */
54#define SCR_CONFIG 0xfc /* b Configuration Control */
55#define SCR_DEBUG 0xff /* b Debug */
56
57#define SCR_CCR_CK32K BIT(0)
58#define SCR_CCR_USBCK BIT(1)
59#define SCR_CCR_UNK1 BIT(4)
60#define SCR_CCR_MCLK_MASK (7 << 8)
61#define SCR_CCR_MCLK_OFF (0 << 8)
62#define SCR_CCR_MCLK_12 (1 << 8)
63#define SCR_CCR_MCLK_24 (2 << 8)
64#define SCR_CCR_MCLK_48 (3 << 8)
65#define SCR_CCR_HCLK_MASK (3 << 12)
66#define SCR_CCR_HCLK_24 (0 << 12)
67#define SCR_CCR_HCLK_48 (1 << 12)
68
69#define SCR_FER_USBEN BIT(0) /* USB host enable */
70#define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
71#define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
72
73#define SCR_MCR_RDY_MASK (3 << 0)
74#define SCR_MCR_RDY_OPENDRAIN (0 << 0)
75#define SCR_MCR_RDY_TRISTATE (1 << 0)
76#define SCR_MCR_RDY_PUSHPULL (2 << 0)
77#define SCR_MCR_RDY_UNK BIT(2)
78#define SCR_MCR_RDY_EN BIT(3)
79#define SCR_MCR_INT_MASK (3 << 4)
80#define SCR_MCR_INT_OPENDRAIN (0 << 4)
81#define SCR_MCR_INT_TRISTATE (1 << 4)
82#define SCR_MCR_INT_PUSHPULL (2 << 4)
83#define SCR_MCR_INT_UNK BIT(6)
84#define SCR_MCR_INT_EN BIT(7)
85/* bits 8 - 16 are unknown */
86
87#define TC_GPIO_BIT(i) (1 << (i & 0x7))
88
89/*--------------------------------------------------------------------------*/
90
91struct tc6393xb {
92 void __iomem *scr;
93
94 struct gpio_chip gpio;
95
96 struct clk *clk; /* 3,6 Mhz */
97
f5139c27 98 raw_spinlock_t lock; /* protects RMW cycles */
d6315949
DB		 99
100 struct {
101 u8 fer;
102 u16 ccr;
103 u8 gpi_bcr[3];
104 u8 gpo_dsr[3];
105 u8 gpo_doecr[3];
106 } suspend_state;
107
108 struct resource rscr;
109 struct resource *iomem;
110 int irq;
111 int irq_base;
112};
113
f024ff10
DB		 114enum {
115 TC6393XB_CELL_NAND,
25d6cbd8 116 TC6393XB_CELL_MMC,
51a55623 117 TC6393XB_CELL_OHCI,
9e78cfe5 118 TC6393XB_CELL_FB,
f024ff10
DB		 119};
120
121/*--------------------------------------------------------------------------*/
122
123static int tc6393xb_nand_enable(struct platform_device *nand)
124{
125 struct platform_device *dev = to_platform_device(nand->dev.parent);
126 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
127 unsigned long flags;
128
f5139c27 129 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
f024ff10
DB		 130
131 /* SMD buffer on */
132 dev_dbg(&dev->dev, "SMD buffer on\n");
25d6cbd8 133 tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
f024ff10 134
f5139c27 135 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
f024ff10
DB		 136
137 return 0;
138}
139
a9e9ce4c 140static struct resource tc6393xb_nand_resources[] = {
f024ff10 141 {
25d6cbd8
IM		 142 .start = 0x1000,
143 .end = 0x1007,
f024ff10
DB		 144 .flags = IORESOURCE_MEM,
145 },
146 {
25d6cbd8
IM		 147 .start = 0x0100,
148 .end = 0x01ff,
f024ff10
DB		 149 .flags = IORESOURCE_MEM,
150 },
151 {
f024ff10
DB		 152 .start = IRQ_TC6393_NAND,
153 .end = IRQ_TC6393_NAND,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
7745cc8c 158static struct resource tc6393xb_mmc_resources[] = {
25d6cbd8
IM		 159 {
160 .start = 0x800,
161 .end = 0x9ff,
162 .flags = IORESOURCE_MEM,
163 },
25d6cbd8
IM		 164 {
165 .start = IRQ_TC6393_MMC,
166 .end = IRQ_TC6393_MMC,
167 .flags = IORESOURCE_IRQ,
168 },
169};
170
3446d4bb 171static const struct resource tc6393xb_ohci_resources[] = {
51a55623
DB		 172 {
173 .start = 0x3000,
174 .end = 0x31ff,
175 .flags = IORESOURCE_MEM,
176 },
177 {
178 .start = 0x0300,
179 .end = 0x03ff,
180 .flags = IORESOURCE_MEM,
181 },
182 {
183 .start = 0x010000,
184 .end = 0x017fff,
185 .flags = IORESOURCE_MEM,
186 },
187 {
188 .start = 0x018000,
189 .end = 0x01ffff,
190 .flags = IORESOURCE_MEM,
191 },
192 {
193 .start = IRQ_TC6393_OHCI,
194 .end = IRQ_TC6393_OHCI,
195 .flags = IORESOURCE_IRQ,
196 },
197};
198
a9e9ce4c 199static struct resource tc6393xb_fb_resources[] = {
9e78cfe5
DB		 200 {
201 .start = 0x5000,
202 .end = 0x51ff,
203 .flags = IORESOURCE_MEM,
204 },
205 {
206 .start = 0x0500,
207 .end = 0x05ff,
208 .flags = IORESOURCE_MEM,
209 },
210 {
211 .start = 0x100000,
212 .end = 0x1fffff,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .start = IRQ_TC6393_FB,
217 .end = IRQ_TC6393_FB,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
51a55623
DB		 222static int tc6393xb_ohci_enable(struct platform_device *dev)
223{
224 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
225 unsigned long flags;
226 u16 ccr;
227 u8 fer;
228
f5139c27 229 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
51a55623
DB		 230
231 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
232 ccr |= SCR_CCR_USBCK;
233 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
234
235 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
236 fer |= SCR_FER_USBEN;
237 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
238
f5139c27 239 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
51a55623
DB		 240
241 return 0;
242}
243
244static int tc6393xb_ohci_disable(struct platform_device *dev)
245{
246 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
247 unsigned long flags;
248 u16 ccr;
249 u8 fer;
250
f5139c27 251 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
51a55623
DB		 252
253 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
254 fer &= ~SCR_FER_USBEN;
255 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
256
257 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
258 ccr &= ~SCR_CCR_USBCK;
259 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
260
f5139c27 261 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
51a55623
DB		 262
263 return 0;
264}
265
1a5fb99d
DB		 266static int tc6393xb_ohci_suspend(struct platform_device *dev)
267{
268 struct tc6393xb_platform_data *tcpd = dev_get_platdata(dev->dev.parent);
269
270 /* We can't properly store/restore OHCI state, so fail here */
271 if (tcpd->resume_restore)
272 return -EBUSY;
273
274 return tc6393xb_ohci_disable(dev);
275}
276
9e78cfe5
DB		 277static int tc6393xb_fb_enable(struct platform_device *dev)
278{
279 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
280 unsigned long flags;
281 u16 ccr;
282
f5139c27 283 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
9e78cfe5
DB		 284
285 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
286 ccr &= ~SCR_CCR_MCLK_MASK;
287 ccr |= SCR_CCR_MCLK_48;
288 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
289
f5139c27 290 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
9e78cfe5
DB		 291
292 return 0;
293}
294
295static int tc6393xb_fb_disable(struct platform_device *dev)
296{
297 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
298 unsigned long flags;
299 u16 ccr;
300
f5139c27 301 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
9e78cfe5
DB		 302
303 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
304 ccr &= ~SCR_CCR_MCLK_MASK;
305 ccr |= SCR_CCR_MCLK_OFF;
306 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
307
f5139c27 308 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
9e78cfe5
DB		 309
310 return 0;
311}
312
313int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
314{
315 struct platform_device *dev = to_platform_device(fb->dev.parent);
316 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
317 u8 fer;
318 unsigned long flags;
319
f5139c27 320 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
9e78cfe5
DB		 321
322 fer = ioread8(tc6393xb->scr + SCR_FER);
323 if (on)
324 fer |= SCR_FER_SLCDEN;
325 else
326 fer &= ~SCR_FER_SLCDEN;
327 iowrite8(fer, tc6393xb->scr + SCR_FER);
328
f5139c27 329 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
9e78cfe5
DB		 330
331 return 0;
332}
333EXPORT_SYMBOL(tc6393xb_lcd_set_power);
334
335int tc6393xb_lcd_mode(struct platform_device *fb,
336 const struct fb_videomode *mode) {
337 struct platform_device *dev = to_platform_device(fb->dev.parent);
338 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
339 unsigned long flags;
340
f5139c27 341 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
9e78cfe5
DB		 342
343 iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
344 iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
345
f5139c27 346 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
9e78cfe5
DB		 347
348 return 0;
349}
350EXPORT_SYMBOL(tc6393xb_lcd_mode);
351
64e8867b
IM		 352static int tc6393xb_mmc_enable(struct platform_device *mmc)
353{
354 struct platform_device *dev = to_platform_device(mmc->dev.parent);
355 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
356
357 tmio_core_mmc_enable(tc6393xb->scr + 0x200, 0,
358 tc6393xb_mmc_resources[0].start & 0xfffe);
359
360 return 0;
361}
362
363static int tc6393xb_mmc_resume(struct platform_device *mmc)
364{
365 struct platform_device *dev = to_platform_device(mmc->dev.parent);
366 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
367
368 tmio_core_mmc_resume(tc6393xb->scr + 0x200, 0,
369 tc6393xb_mmc_resources[0].start & 0xfffe);
370
371 return 0;
372}
373
374static void tc6393xb_mmc_pwr(struct platform_device *mmc, int state)
375{
376 struct platform_device *dev = to_platform_device(mmc->dev.parent);
377 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
378
379 tmio_core_mmc_pwr(tc6393xb->scr + 0x200, 0, state);
380}
381
382static void tc6393xb_mmc_clk_div(struct platform_device *mmc, int state)
383{
384 struct platform_device *dev = to_platform_device(mmc->dev.parent);
385 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
386
387 tmio_core_mmc_clk_div(tc6393xb->scr + 0x200, 0, state);
388}
389
390static struct tmio_mmc_data tc6393xb_mmc_data = {
391 .hclk = 24000000,
392 .set_pwr = tc6393xb_mmc_pwr,
393 .set_clk_div = tc6393xb_mmc_clk_div,
394};
395
a9e9ce4c 396static struct mfd_cell tc6393xb_cells[] = {
f024ff10
DB		 397 [TC6393XB_CELL_NAND] = {
398 .name = "tmio-nand",
399 .enable = tc6393xb_nand_enable,
400 .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
401 .resources = tc6393xb_nand_resources,
402 },
25d6cbd8
IM		 403 [TC6393XB_CELL_MMC] = {
404 .name = "tmio-mmc",
64e8867b
IM		 405 .enable = tc6393xb_mmc_enable,
406 .resume = tc6393xb_mmc_resume,
ec71974f
SO		 407 .platform_data = &tc6393xb_mmc_data,
408 .pdata_size = sizeof(tc6393xb_mmc_data),
25d6cbd8
IM		 409 .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
410 .resources = tc6393xb_mmc_resources,
411 },
51a55623
DB		 412 [TC6393XB_CELL_OHCI] = {
413 .name = "tmio-ohci",
414 .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
415 .resources = tc6393xb_ohci_resources,
416 .enable = tc6393xb_ohci_enable,
1a5fb99d 417 .suspend = tc6393xb_ohci_suspend,
51a55623
DB		 418 .resume = tc6393xb_ohci_enable,
419 .disable = tc6393xb_ohci_disable,
420 },
9e78cfe5
DB		 421 [TC6393XB_CELL_FB] = {
422 .name = "tmio-fb",
423 .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
424 .resources = tc6393xb_fb_resources,
425 .enable = tc6393xb_fb_enable,
426 .suspend = tc6393xb_fb_disable,
427 .resume = tc6393xb_fb_enable,
428 .disable = tc6393xb_fb_disable,
429 },
f024ff10
DB		 430};
431
d6315949
DB		 432/*--------------------------------------------------------------------------*/
433
434static int tc6393xb_gpio_get(struct gpio_chip *chip,
435 unsigned offset)
436{
4e125f62 437 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
d6315949
DB		 438
439 /* XXX: does dsr also represent inputs? */
2d5f72b8
LW		 440 return !!(tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
441 & TC_GPIO_BIT(offset));
d6315949
DB		 442}
443
444static void __tc6393xb_gpio_set(struct gpio_chip *chip,
445 unsigned offset, int value)
446{
4e125f62 447 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
d6315949
DB		 448 u8 dsr;
449
25d6cbd8 450 dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
d6315949
DB		 451 if (value)
452 dsr |= TC_GPIO_BIT(offset);
453 else
454 dsr &= ~TC_GPIO_BIT(offset);
455
25d6cbd8 456 tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
d6315949
DB		 457}
458
459static void tc6393xb_gpio_set(struct gpio_chip *chip,
460 unsigned offset, int value)
461{
4e125f62 462 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
d6315949
DB		 463 unsigned long flags;
464
f5139c27 465 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
d6315949
DB		 466
467 __tc6393xb_gpio_set(chip, offset, value);
468
f5139c27 469 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
d6315949
DB		 470}
471
472static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
473 unsigned offset)
474{
4e125f62 475 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
d6315949
DB		 476 unsigned long flags;
477 u8 doecr;
478
f5139c27 479 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
d6315949 480
25d6cbd8 481 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 482 doecr &= ~TC_GPIO_BIT(offset);
25d6cbd8 483 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 484
f5139c27 485 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
d6315949
DB		 486
487 return 0;
488}
489
490static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
491 unsigned offset, int value)
492{
4e125f62 493 struct tc6393xb *tc6393xb = gpiochip_get_data(chip);
d6315949
DB		 494 unsigned long flags;
495 u8 doecr;
496
f5139c27 497 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
d6315949
DB		 498
499 __tc6393xb_gpio_set(chip, offset, value);
500
25d6cbd8 501 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 502 doecr |= TC_GPIO_BIT(offset);
25d6cbd8 503 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
d6315949 504
f5139c27 505 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
d6315949
DB		 506
507 return 0;
508}
509
510static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
511{
512 tc6393xb->gpio.label = "tc6393xb";
513 tc6393xb->gpio.base = gpio_base;
514 tc6393xb->gpio.ngpio = 16;
515 tc6393xb->gpio.set = tc6393xb_gpio_set;
516 tc6393xb->gpio.get = tc6393xb_gpio_get;
517 tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
518 tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
519
4e125f62 520 return gpiochip_add_data(&tc6393xb->gpio, tc6393xb);
d6315949
DB		 521}
522
523/*--------------------------------------------------------------------------*/
524
bd0b9ac4 525static void tc6393xb_irq(struct irq_desc *desc)
d6315949 526{
1e84aa44 527 struct tc6393xb *tc6393xb = irq_desc_get_handler_data(desc);
d6315949
DB		 528 unsigned int isr;
529 unsigned int i, irq_base;
530
531 irq_base = tc6393xb->irq_base;
532
25d6cbd8
IM		 533 while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
534 ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
d6315949
DB		 535 for (i = 0; i < TC6393XB_NR_IRQS; i++) {
536 if (isr & (1 << i))
537 generic_handle_irq(irq_base + i);
538 }
539}
540
01af22eb 541static void tc6393xb_irq_ack(struct irq_data *data)
d6315949
DB		 542{
543}
544
01af22eb 545static void tc6393xb_irq_mask(struct irq_data *data)
d6315949 546{
01af22eb 547 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
d6315949
DB		 548 unsigned long flags;
549 u8 imr;
550
f5139c27 551 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
25d6cbd8 552 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
01af22eb 553 imr |= 1 << (data->irq - tc6393xb->irq_base);
25d6cbd8 554 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
f5139c27 555 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
d6315949
DB		 556}
557
01af22eb 558static void tc6393xb_irq_unmask(struct irq_data *data)
d6315949 559{
01af22eb 560 struct tc6393xb *tc6393xb = irq_data_get_irq_chip_data(data);
d6315949
DB		 561 unsigned long flags;
562 u8 imr;
563
f5139c27 564 raw_spin_lock_irqsave(&tc6393xb->lock, flags);
25d6cbd8 565 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
01af22eb 566 imr &= ~(1 << (data->irq - tc6393xb->irq_base));
25d6cbd8 567 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
f5139c27 568 raw_spin_unlock_irqrestore(&tc6393xb->lock, flags);
d6315949
DB		 569}
570
571static struct irq_chip tc6393xb_chip = {
01af22eb
MB		 572 .name = "tc6393xb",
573 .irq_ack = tc6393xb_irq_ack,
574 .irq_mask = tc6393xb_irq_mask,
575 .irq_unmask = tc6393xb_irq_unmask,
d6315949
DB		 576};
577
578static void tc6393xb_attach_irq(struct platform_device *dev)
579{
580 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
581 unsigned int irq, irq_base;
582
583 irq_base = tc6393xb->irq_base;
584
585 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
d6f7ce9f 586 irq_set_chip_and_handler(irq, &tc6393xb_chip, handle_edge_irq);
d5bb1221 587 irq_set_chip_data(irq, tc6393xb);
9bd09f34 588 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
d6315949
DB		 589 }
590
d5bb1221 591 irq_set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
079140f5
TG		 592 irq_set_chained_handler_and_data(tc6393xb->irq, tc6393xb_irq,
593 tc6393xb);
d6315949
DB		 594}
595
596static void tc6393xb_detach_irq(struct platform_device *dev)
597{
598 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
599 unsigned int irq, irq_base;
600
079140f5 601 irq_set_chained_handler_and_data(tc6393xb->irq, NULL, NULL);
d6315949
DB		 602
603 irq_base = tc6393xb->irq_base;
604
605 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
9bd09f34 606 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
d5bb1221
TG		 607 irq_set_chip(irq, NULL);
608 irq_set_chip_data(irq, NULL);
d6315949
DB		 609 }
610}
611
612/*--------------------------------------------------------------------------*/
613
f791be49 614static int tc6393xb_probe(struct platform_device *dev)
d6315949 615{
334a41ce 616 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
d6315949 617 struct tc6393xb *tc6393xb;
25d6cbd8 618 struct resource *iomem, *rscr;
88d5e520 619 int ret;
d6315949
DB		 620
621 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
622 if (!iomem)
623 return -EINVAL;
624
625 tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
626 if (!tc6393xb) {
25d6cbd8 627 ret = -ENOMEM;
d6315949
DB		 628 goto err_kzalloc;
629 }
630
f5139c27 631 raw_spin_lock_init(&tc6393xb->lock);
d6315949
DB		 632
633 platform_set_drvdata(dev, tc6393xb);
25d6cbd8
IM		 634
635 ret = platform_get_irq(dev, 0);
636 if (ret >= 0)
637 tc6393xb->irq = ret;
638 else
639 goto err_noirq;
640
d6315949 641 tc6393xb->iomem = iomem;
d6315949
DB		 642 tc6393xb->irq_base = tcpd->irq_base;
643
25d6cbd8 644 tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
d6315949 645 if (IS_ERR(tc6393xb->clk)) {
25d6cbd8 646 ret = PTR_ERR(tc6393xb->clk);
d6315949
DB		 647 goto err_clk_get;
648 }
649
650 rscr = &tc6393xb->rscr;
651 rscr->name = "tc6393xb-core";
652 rscr->start = iomem->start;
653 rscr->end = iomem->start + 0xff;
654 rscr->flags = IORESOURCE_MEM;
655
25d6cbd8
IM		 656 ret = request_resource(iomem, rscr);
657 if (ret)
d6315949
DB		 658 goto err_request_scr;
659
1ecc09e7 660 tc6393xb->scr = ioremap(rscr->start, resource_size(rscr));
d6315949 661 if (!tc6393xb->scr) {
25d6cbd8 662 ret = -ENOMEM;
d6315949
DB		 663 goto err_ioremap;
664 }
665
a64ab6b4 666 ret = clk_prepare_enable(tc6393xb->clk);
25d6cbd8 667 if (ret)
d6315949
DB		 668 goto err_clk_enable;
669
25d6cbd8
IM		 670 ret = tcpd->enable(dev);
671 if (ret)
d6315949
DB		 672 goto err_enable;
673
f98a0bd0
DB		 674 iowrite8(0, tc6393xb->scr + SCR_FER);
675 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
676 iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
677 tc6393xb->scr + SCR_CCR);
678 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
679 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
680 BIT(15), tc6393xb->scr + SCR_MCR);
681 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
682 iowrite8(0, tc6393xb->scr + SCR_IRR);
683 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
d6315949
DB		 684
685 printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
25d6cbd8 686 tmio_ioread8(tc6393xb->scr + SCR_REVID),
d6315949
DB		 687 (unsigned long) iomem->start, tc6393xb->irq);
688
689 tc6393xb->gpio.base = -1;
690
691 if (tcpd->gpio_base >= 0) {
25d6cbd8
IM		 692 ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
693 if (ret)
d6315949
DB		 694 goto err_gpio_add;
695 }
696
25d6cbd8 697 tc6393xb_attach_irq(dev);
d6315949 698
1c1b6ffc
DB		 699 if (tcpd->setup) {
700 ret = tcpd->setup(dev);
701 if (ret)
702 goto err_setup;
703 }
704
7dc00a0d
SO		 705 tc6393xb_cells[TC6393XB_CELL_NAND].platform_data = tcpd->nand_data;
706 tc6393xb_cells[TC6393XB_CELL_NAND].pdata_size =
707 sizeof(*tcpd->nand_data);
1f8c666c
SO		 708 tc6393xb_cells[TC6393XB_CELL_FB].platform_data = tcpd->fb_data;
709 tc6393xb_cells[TC6393XB_CELL_FB].pdata_size = sizeof(*tcpd->fb_data);
f024ff10 710
25d6cbd8 711 ret = mfd_add_devices(&dev->dev, dev->id,
0848c94f
MB		 712 tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
713 iomem, tcpd->irq_base, NULL);
f024ff10 714
25d6cbd8
IM		 715 if (!ret)
716 return 0;
d6315949 717
1c1b6ffc
DB		 718 if (tcpd->teardown)
719 tcpd->teardown(dev);
720
721err_setup:
25d6cbd8 722 tc6393xb_detach_irq(dev);
d6315949
DB		 723
724err_gpio_add:
725 if (tc6393xb->gpio.base != -1)
88d5e520 726 gpiochip_remove(&tc6393xb->gpio);
d6315949 727 tcpd->disable(dev);
d6315949 728err_enable:
a64ab6b4 729 clk_disable_unprepare(tc6393xb->clk);
fa6e4b18 730err_clk_enable:
d6315949
DB		 731 iounmap(tc6393xb->scr);
732err_ioremap:
733 release_resource(&tc6393xb->rscr);
734err_request_scr:
735 clk_put(tc6393xb->clk);
25d6cbd8 736err_noirq:
d6315949
DB		 737err_clk_get:
738 kfree(tc6393xb);
739err_kzalloc:
25d6cbd8 740 return ret;
d6315949
DB		 741}
742
4740f73f 743static int tc6393xb_remove(struct platform_device *dev)
d6315949 744{
334a41ce 745 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
d6315949
DB		 746 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
747 int ret;
748
424f525a 749 mfd_remove_devices(&dev->dev);
1c1b6ffc
DB		 750
751 if (tcpd->teardown)
752 tcpd->teardown(dev);
753
25d6cbd8 754 tc6393xb_detach_irq(dev);
d6315949 755
88d5e520 756 if (tc6393xb->gpio.base != -1)
757 gpiochip_remove(&tc6393xb->gpio);
d6315949
DB		 758
759 ret = tcpd->disable(dev);
a64ab6b4 760 clk_disable_unprepare(tc6393xb->clk);
d6315949 761 iounmap(tc6393xb->scr);
d6315949 762 release_resource(&tc6393xb->rscr);
d6315949 763 clk_put(tc6393xb->clk);
d6315949
DB		 764 kfree(tc6393xb);
765
766 return ret;
767}
768
769#ifdef CONFIG_PM
770static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
771{
334a41ce 772 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
d6315949 773 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
25d6cbd8 774 int i, ret;
d6315949
DB		 775
776 tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
777 tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
778
779 for (i = 0; i < 3; i++) {
780 tc6393xb->suspend_state.gpo_dsr[i] =
781 ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
782 tc6393xb->suspend_state.gpo_doecr[i] =
783 ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
784 tc6393xb->suspend_state.gpi_bcr[i] =
785 ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
786 }
25d6cbd8 787 ret = tcpd->suspend(dev);
a64ab6b4 788 clk_disable_unprepare(tc6393xb->clk);
d6315949 789
25d6cbd8 790 return ret;
d6315949
DB		 791}
792
793static int tc6393xb_resume(struct platform_device *dev)
794{
334a41ce 795 struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
25d6cbd8
IM		 796 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
797 int ret;
f98a0bd0 798 int i;
25d6cbd8 799
b6678050
AY		 800 ret = clk_prepare_enable(tc6393xb->clk);
801 if (ret)
802 return ret;
25d6cbd8
IM		 803
804 ret = tcpd->resume(dev);
d6315949
DB		 805 if (ret)
806 return ret;
807
f98a0bd0
DB		 808 if (!tcpd->resume_restore)
809 return 0;
810
811 iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
812 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
813 iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
814 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
815 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
816 BIT(15), tc6393xb->scr + SCR_MCR);
817 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
818 iowrite8(0, tc6393xb->scr + SCR_IRR);
819 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
820
821 for (i = 0; i < 3; i++) {
822 iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
823 tc6393xb->scr + SCR_GPO_DSR(i));
824 iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
825 tc6393xb->scr + SCR_GPO_DOECR(i));
826 iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
827 tc6393xb->scr + SCR_GPI_BCR(i));
828 }
829
830 return 0;
d6315949
DB		 831}
832#else
833#define tc6393xb_suspend NULL
834#define tc6393xb_resume NULL
835#endif
836
837static struct platform_driver tc6393xb_driver = {
838 .probe = tc6393xb_probe,
84449216 839 .remove = tc6393xb_remove,
d6315949
DB		 840 .suspend = tc6393xb_suspend,
841 .resume = tc6393xb_resume,
842
843 .driver = {
844 .name = "tc6393xb",
d6315949
DB		 845 },
846};
847
848static int __init tc6393xb_init(void)
849{
850 return platform_driver_register(&tc6393xb_driver);
851}
852
853static void __exit tc6393xb_exit(void)
854{
855 platform_driver_unregister(&tc6393xb_driver);
856}
857
858subsys_initcall(tc6393xb_init);
859module_exit(tc6393xb_exit);
860
25d6cbd8 861MODULE_LICENSE("GPL v2");
d6315949
DB		 862MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
863MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
864MODULE_ALIAS("platform:tc6393xb");
64e8867b 865
Empty description
This page took 0.80048 seconds and 4 git commands to generate.