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[PCMCIA] MPC8xx PCMCIA update
[linux.git] / drivers / pcmcia / i82365.c
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1da177e4
LT		 1/*======================================================================
2
3 Device driver for Intel 82365 and compatible PC Card controllers.
4
5 i82365.c 1.265 1999/11/10 18:36:21
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <[email protected]>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU General Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32======================================================================*/
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
36#include <linux/init.h>
37#include <linux/config.h>
38#include <linux/types.h>
39#include <linux/fcntl.h>
40#include <linux/string.h>
41#include <linux/kernel.h>
42#include <linux/errno.h>
43#include <linux/timer.h>
44#include <linux/sched.h>
45#include <linux/slab.h>
46#include <linux/ioport.h>
47#include <linux/delay.h>
48#include <linux/workqueue.h>
49#include <linux/interrupt.h>
d052d1be 50#include <linux/platform_device.h>
1da177e4
LT		 51#include <linux/bitops.h>
52#include <asm/irq.h>
53#include <asm/io.h>
54#include <asm/system.h>
55
1da177e4
LT		 56#include <pcmcia/cs_types.h>
57#include <pcmcia/ss.h>
58#include <pcmcia/cs.h>
59
60#include <linux/isapnp.h>
61
62/* ISA-bus controllers */
63#include "i82365.h"
64#include "cirrus.h"
65#include "vg468.h"
66#include "ricoh.h"
67
68#ifdef DEBUG
69static const char version[] =
70"i82365.c 1.265 1999/11/10 18:36:21 (David Hinds)";
71
72static int pc_debug;
73
74module_param(pc_debug, int, 0644);
75
76#define debug(lvl, fmt, arg...) do { \
77 if (pc_debug > (lvl)) \
78 printk(KERN_DEBUG "i82365: " fmt , ## arg); \
79} while (0)
80#else
81#define debug(lvl, fmt, arg...) do { } while (0)
82#endif
83
84static irqreturn_t i365_count_irq(int, void *, struct pt_regs *);
85static inline int _check_irq(int irq, int flags)
86{
87 if (request_irq(irq, i365_count_irq, flags, "x", i365_count_irq) != 0)
88 return -1;
89 free_irq(irq, i365_count_irq);
90 return 0;
91}
92
93/*====================================================================*/
94
95/* Parameters that can be set with 'insmod' */
96
97/* Default base address for i82365sl and other ISA chips */
98static unsigned long i365_base = 0x3e0;
99/* Should we probe at 0x3e2 for an extra ISA controller? */
100static int extra_sockets = 0;
101/* Specify a socket number to ignore */
102static int ignore = -1;
103/* Bit map or list of interrupts to choose from */
104static u_int irq_mask = 0xffff;
105static int irq_list[16];
106static int irq_list_count;
107/* The card status change interrupt -- 0 means autoselect */
108static int cs_irq = 0;
109
110/* Probe for safe interrupts? */
111static int do_scan = 1;
112/* Poll status interval -- 0 means default to interrupt */
113static int poll_interval = 0;
114/* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
115static int cycle_time = 120;
116
117/* Cirrus options */
118static int has_dma = -1;
119static int has_led = -1;
120static int has_ring = -1;
121static int dynamic_mode = 0;
122static int freq_bypass = -1;
123static int setup_time = -1;
124static int cmd_time = -1;
125static int recov_time = -1;
126
127/* Vadem options */
128static int async_clock = -1;
129static int cable_mode = -1;
130static int wakeup = 0;
131
132module_param(i365_base, ulong, 0444);
133module_param(ignore, int, 0444);
134module_param(extra_sockets, int, 0444);
135module_param(irq_mask, int, 0444);
136module_param_array(irq_list, int, &irq_list_count, 0444);
137module_param(cs_irq, int, 0444);
138module_param(async_clock, int, 0444);
139module_param(cable_mode, int, 0444);
140module_param(wakeup, int, 0444);
141
142module_param(do_scan, int, 0444);
143module_param(poll_interval, int, 0444);
144module_param(cycle_time, int, 0444);
145module_param(has_dma, int, 0444);
146module_param(has_led, int, 0444);
147module_param(has_ring, int, 0444);
148module_param(dynamic_mode, int, 0444);
149module_param(freq_bypass, int, 0444);
150module_param(setup_time, int, 0444);
151module_param(cmd_time, int, 0444);
152module_param(recov_time, int, 0444);
153
154/*====================================================================*/
155
156typedef struct cirrus_state_t {
157 u_char misc1, misc2;
158 u_char timer[6];
159} cirrus_state_t;
160
161typedef struct vg46x_state_t {
162 u_char ctl, ema;
163} vg46x_state_t;
164
165struct i82365_socket {
166 u_short type, flags;
167 struct pcmcia_socket socket;
168 unsigned int number;
169 kio_addr_t ioaddr;
170 u_short psock;
171 u_char cs_irq, intr;
172 union {
173 cirrus_state_t cirrus;
174 vg46x_state_t vg46x;
175 } state;
176};
177
178/* Where we keep track of our sockets... */
179static int sockets = 0;
180static struct i82365_socket socket[8] = {
181 { 0, }, /* ... */
182};
183
184/* Default ISA interrupt mask */
185#define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */
186
187static int grab_irq;
188static DEFINE_SPINLOCK(isa_lock);
189#define ISA_LOCK(n, f) spin_lock_irqsave(&isa_lock, f)
190#define ISA_UNLOCK(n, f) spin_unlock_irqrestore(&isa_lock, f)
191
192static struct timer_list poll_timer;
193
194/*====================================================================*/
195
196/* These definitions must match the pcic table! */
197typedef enum pcic_id {
198 IS_I82365A, IS_I82365B, IS_I82365DF,
199 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469,
200 IS_PD6710, IS_PD672X, IS_VT83C469,
201} pcic_id;
202
203/* Flags for classifying groups of controllers */
204#define IS_VADEM 0x0001
205#define IS_CIRRUS 0x0002
206#define IS_VIA 0x0010
207#define IS_UNKNOWN 0x0400
208#define IS_VG_PWR 0x0800
209#define IS_DF_PWR 0x1000
210#define IS_REGISTERED 0x2000
211#define IS_ALIVE 0x8000
212
213typedef struct pcic_t {
214 char *name;
215 u_short flags;
216} pcic_t;
217
218static pcic_t pcic[] = {
219 { "Intel i82365sl A step", 0 },
220 { "Intel i82365sl B step", 0 },
221 { "Intel i82365sl DF", IS_DF_PWR },
222 { "IBM Clone", 0 },
223 { "Ricoh RF5C296/396", 0 },
224 { "VLSI 82C146", 0 },
225 { "Vadem VG-468", IS_VADEM },
226 { "Vadem VG-469", IS_VADEM|IS_VG_PWR },
227 { "Cirrus PD6710", IS_CIRRUS },
228 { "Cirrus PD672x", IS_CIRRUS },
229 { "VIA VT83C469", IS_CIRRUS|IS_VIA },
230};
231
232#define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t))
233
234/*====================================================================*/
235
236static DEFINE_SPINLOCK(bus_lock);
237
238static u_char i365_get(u_short sock, u_short reg)
239{
240 unsigned long flags;
241 spin_lock_irqsave(&bus_lock,flags);
242 {
243 kio_addr_t port = socket[sock].ioaddr;
244 u_char val;
245 reg = I365_REG(socket[sock].psock, reg);
246 outb(reg, port); val = inb(port+1);
247 spin_unlock_irqrestore(&bus_lock,flags);
248 return val;
249 }
250}
251
252static void i365_set(u_short sock, u_short reg, u_char data)
253{
254 unsigned long flags;
255 spin_lock_irqsave(&bus_lock,flags);
256 {
257 kio_addr_t port = socket[sock].ioaddr;
258 u_char val = I365_REG(socket[sock].psock, reg);
259 outb(val, port); outb(data, port+1);
260 spin_unlock_irqrestore(&bus_lock,flags);
261 }
262}
263
264static void i365_bset(u_short sock, u_short reg, u_char mask)
265{
266 u_char d = i365_get(sock, reg);
267 d |= mask;
268 i365_set(sock, reg, d);
269}
270
271static void i365_bclr(u_short sock, u_short reg, u_char mask)
272{
273 u_char d = i365_get(sock, reg);
274 d &= ~mask;
275 i365_set(sock, reg, d);
276}
277
278static void i365_bflip(u_short sock, u_short reg, u_char mask, int b)
279{
280 u_char d = i365_get(sock, reg);
281 if (b)
282 d |= mask;
283 else
284 d &= ~mask;
285 i365_set(sock, reg, d);
286}
287
288static u_short i365_get_pair(u_short sock, u_short reg)
289{
290 u_short a, b;
291 a = i365_get(sock, reg);
292 b = i365_get(sock, reg+1);
293 return (a + (b<<8));
294}
295
296static void i365_set_pair(u_short sock, u_short reg, u_short data)
297{
298 i365_set(sock, reg, data & 0xff);
299 i365_set(sock, reg+1, data >> 8);
300}
301
302/*======================================================================
303
304 Code to save and restore global state information for Cirrus
305 PD67xx controllers, and to set and report global configuration
306 options.
307
308 The VIA controllers also use these routines, as they are mostly
309 Cirrus lookalikes, without the timing registers.
310
311======================================================================*/
312
313#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
314
315static void cirrus_get_state(u_short s)
316{
317 int i;
318 cirrus_state_t *p = &socket[s].state.cirrus;
319 p->misc1 = i365_get(s, PD67_MISC_CTL_1);
320 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
321 p->misc2 = i365_get(s, PD67_MISC_CTL_2);
322 for (i = 0; i < 6; i++)
323 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i);
324}
325
326static void cirrus_set_state(u_short s)
327{
328 int i;
329 u_char misc;
330 cirrus_state_t *p = &socket[s].state.cirrus;
331
332 misc = i365_get(s, PD67_MISC_CTL_2);
333 i365_set(s, PD67_MISC_CTL_2, p->misc2);
334 if (misc & PD67_MC2_SUSPEND) mdelay(50);
335 misc = i365_get(s, PD67_MISC_CTL_1);
336 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
337 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1);
338 for (i = 0; i < 6; i++)
339 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]);
340}
341
342static u_int __init cirrus_set_opts(u_short s, char *buf)
343{
344 struct i82365_socket *t = &socket[s];
345 cirrus_state_t *p = &socket[s].state.cirrus;
346 u_int mask = 0xffff;
347
348 if (has_ring == -1) has_ring = 1;
349 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring);
350 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
351 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
352 if (p->misc2 & PD67_MC2_IRQ15_RI)
353 strcat(buf, " [ring]");
354 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
355 strcat(buf, " [dyn mode]");
356 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
357 strcat(buf, " [freq bypass]");
358 if (p->misc1 & PD67_MC1_INPACK_ENA)
359 strcat(buf, " [inpack]");
360 if (p->misc2 & PD67_MC2_IRQ15_RI)
361 mask &= ~0x8000;
362 if (has_led > 0) {
363 strcat(buf, " [led]");
364 mask &= ~0x1000;
365 }
366 if (has_dma > 0) {
367 strcat(buf, " [dma]");
368 mask &= ~0x0600;
369 }
370 if (!(t->flags & IS_VIA)) {
371 if (setup_time >= 0)
372 p->timer[0] = p->timer[3] = setup_time;
373 if (cmd_time > 0) {
374 p->timer[1] = cmd_time;
375 p->timer[4] = cmd_time*2+4;
376 }
377 if (p->timer[1] == 0) {
378 p->timer[1] = 6; p->timer[4] = 16;
379 if (p->timer[0] == 0)
380 p->timer[0] = p->timer[3] = 1;
381 }
382 if (recov_time >= 0)
383 p->timer[2] = p->timer[5] = recov_time;
384 buf += strlen(buf);
385 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1],
386 p->timer[2], p->timer[3], p->timer[4], p->timer[5]);
387 }
388 return mask;
389}
390
391/*======================================================================
392
393 Code to save and restore global state information for Vadem VG468
394 and VG469 controllers, and to set and report global configuration
395 options.
396
397======================================================================*/
398
399static void vg46x_get_state(u_short s)
400{
401 vg46x_state_t *p = &socket[s].state.vg46x;
402 p->ctl = i365_get(s, VG468_CTL);
403 if (socket[s].type == IS_VG469)
404 p->ema = i365_get(s, VG469_EXT_MODE);
405}
406
407static void vg46x_set_state(u_short s)
408{
409 vg46x_state_t *p = &socket[s].state.vg46x;
410 i365_set(s, VG468_CTL, p->ctl);
411 if (socket[s].type == IS_VG469)
412 i365_set(s, VG469_EXT_MODE, p->ema);
413}
414
415static u_int __init vg46x_set_opts(u_short s, char *buf)
416{
417 vg46x_state_t *p = &socket[s].state.vg46x;
418
419 flip(p->ctl, VG468_CTL_ASYNC, async_clock);
420 flip(p->ema, VG469_MODE_CABLE, cable_mode);
421 if (p->ctl & VG468_CTL_ASYNC)
422 strcat(buf, " [async]");
423 if (p->ctl & VG468_CTL_INPACK)
424 strcat(buf, " [inpack]");
425 if (socket[s].type == IS_VG469) {
426 u_char vsel = i365_get(s, VG469_VSELECT);
427 if (vsel & VG469_VSEL_EXT_STAT) {
428 strcat(buf, " [ext mode]");
429 if (vsel & VG469_VSEL_EXT_BUS)
430 strcat(buf, " [isa buf]");
431 }
432 if (p->ema & VG469_MODE_CABLE)
433 strcat(buf, " [cable]");
434 if (p->ema & VG469_MODE_COMPAT)
435 strcat(buf, " [c step]");
436 }
437 return 0xffff;
438}
439
440/*======================================================================
441
442 Generic routines to get and set controller options
443
444======================================================================*/
445
446static void get_bridge_state(u_short s)
447{
448 struct i82365_socket *t = &socket[s];
449 if (t->flags & IS_CIRRUS)
450 cirrus_get_state(s);
451 else if (t->flags & IS_VADEM)
452 vg46x_get_state(s);
453}
454
455static void set_bridge_state(u_short s)
456{
457 struct i82365_socket *t = &socket[s];
458 if (t->flags & IS_CIRRUS)
459 cirrus_set_state(s);
460 else {
461 i365_set(s, I365_GBLCTL, 0x00);
462 i365_set(s, I365_GENCTL, 0x00);
463 }
464 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr);
465 if (t->flags & IS_VADEM)
466 vg46x_set_state(s);
467}
468
469static u_int __init set_bridge_opts(u_short s, u_short ns)
470{
471 u_short i;
472 u_int m = 0xffff;
473 char buf[128];
474
475 for (i = s; i < s+ns; i++) {
476 if (socket[i].flags & IS_ALIVE) {
477 printk(KERN_INFO " host opts [%d]: already alive!\n", i);
478 continue;
479 }
480 buf[0] = '\0';
481 get_bridge_state(i);
482 if (socket[i].flags & IS_CIRRUS)
483 m = cirrus_set_opts(i, buf);
484 else if (socket[i].flags & IS_VADEM)
485 m = vg46x_set_opts(i, buf);
486 set_bridge_state(i);
487 printk(KERN_INFO " host opts [%d]:%s\n", i,
488 (*buf) ? buf : " none");
489 }
490 return m;
491}
492
493/*======================================================================
494
495 Interrupt testing code, for ISA and PCI interrupts
496
497======================================================================*/
498
499static volatile u_int irq_hits;
500static u_short irq_sock;
501
502static irqreturn_t i365_count_irq(int irq, void *dev, struct pt_regs *regs)
503{
504 i365_get(irq_sock, I365_CSC);
505 irq_hits++;
506 debug(2, "-> hit on irq %d\n", irq);
507 return IRQ_HANDLED;
508}
509
510static u_int __init test_irq(u_short sock, int irq)
511{
512 debug(2, " testing ISA irq %d\n", irq);
513 if (request_irq(irq, i365_count_irq, 0, "scan", i365_count_irq) != 0)
514 return 1;
515 irq_hits = 0; irq_sock = sock;
516 msleep(10);
517 if (irq_hits) {
518 free_irq(irq, i365_count_irq);
519 debug(2, " spurious hit!\n");
520 return 1;
521 }
522
523 /* Generate one interrupt */
524 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (irq << 4));
525 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ);
526 udelay(1000);
527
528 free_irq(irq, i365_count_irq);
529
530 /* mask all interrupts */
531 i365_set(sock, I365_CSCINT, 0);
532 debug(2, " hits = %d\n", irq_hits);
533
534 return (irq_hits != 1);
535}
536
537static u_int __init isa_scan(u_short sock, u_int mask0)
538{
539 u_int mask1 = 0;
540 int i;
541
542#ifdef __alpha__
543#define PIC 0x4d0
544 /* Don't probe level-triggered interrupts -- reserved for PCI */
545 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8));
546#endif
547
548 if (do_scan) {
549 set_bridge_state(sock);
550 i365_set(sock, I365_CSCINT, 0);
551 for (i = 0; i < 16; i++)
552 if ((mask0 & (1 << i)) && (test_irq(sock, i) == 0))
553 mask1 |= (1 << i);
554 for (i = 0; i < 16; i++)
555 if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0))
556 mask1 ^= (1 << i);
557 }
558
559 printk(KERN_INFO " ISA irqs (");
560 if (mask1) {
561 printk("scanned");
562 } else {
563 /* Fallback: just find interrupts that aren't in use */
564 for (i = 0; i < 16; i++)
565 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0))
566 mask1 |= (1 << i);
567 printk("default");
568 /* If scan failed, default to polled status */
569 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ;
570 }
571 printk(") = ");
572
573 for (i = 0; i < 16; i++)
574 if (mask1 & (1<<i))
575 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
576 if (mask1 == 0) printk("none!");
577
578 return mask1;
579}
580
581/*====================================================================*/
582
583/* Time conversion functions */
584
585static int to_cycles(int ns)
586{
587 return ns/cycle_time;
588}
589
590/*====================================================================*/
591
592static int __init identify(kio_addr_t port, u_short sock)
593{
594 u_char val;
595 int type = -1;
596
597 /* Use the next free entry in the socket table */
598 socket[sockets].ioaddr = port;
599 socket[sockets].psock = sock;
600
601 /* Wake up a sleepy Cirrus controller */
602 if (wakeup) {
603 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND);
604 /* Pause at least 50 ms */
605 mdelay(50);
606 }
607
608 if ((val = i365_get(sockets, I365_IDENT)) & 0x70)
609 return -1;
610 switch (val) {
611 case 0x82:
612 type = IS_I82365A; break;
613 case 0x83:
614 type = IS_I82365B; break;
615 case 0x84:
616 type = IS_I82365DF; break;
617 case 0x88: case 0x89: case 0x8a:
618 type = IS_IBM; break;
619 }
620
621 /* Check for Vadem VG-468 chips */
622 outb(0x0e, port);
623 outb(0x37, port);
624 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV);
625 val = i365_get(sockets, I365_IDENT);
626 if (val & I365_IDENT_VADEM) {
627 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV);
628 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468;
629 }
630
631 /* Check for Ricoh chips */
632 val = i365_get(sockets, RF5C_CHIP_ID);
633 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396))
634 type = IS_RF5Cx96;
635
636 /* Check for Cirrus CL-PD67xx chips */
637 i365_set(sockets, PD67_CHIP_INFO, 0);
638 val = i365_get(sockets, PD67_CHIP_INFO);
639 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
640 val = i365_get(sockets, PD67_CHIP_INFO);
641 if ((val & PD67_INFO_CHIP_ID) == 0) {
642 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
643 i365_set(sockets, PD67_EXT_INDEX, 0xe5);
644 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5)
645 type = IS_VT83C469;
646 }
647 }
648 return type;
649} /* identify */
650
651/*======================================================================
652
653 See if a card is present, powered up, in IO mode, and already
654 bound to a (non PC Card) Linux driver. We leave these alone.
655
656 We make an exception for cards that seem to be serial devices.
657
658======================================================================*/
659
660static int __init is_alive(u_short sock)
661{
662 u_char stat;
663 kio_addr_t start, stop;
664
665 stat = i365_get(sock, I365_STATUS);
666 start = i365_get_pair(sock, I365_IO(0)+I365_W_START);
667 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP);
668 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) &&
669 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) &&
670 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) &&
f354942c
DB		 671 ((start & 0xfeef) != 0x02e8)) {
672 if (!request_region(start, stop-start+1, "i82365"))
673 return 1;
674 release_region(start, stop-start+1);
675 }
676
677 return 0;
1da177e4
LT		 678}
679
680/*====================================================================*/
681
682static void __init add_socket(kio_addr_t port, int psock, int type)
683{
684 socket[sockets].ioaddr = port;
685 socket[sockets].psock = psock;
686 socket[sockets].type = type;
687 socket[sockets].flags = pcic[type].flags;
688 if (is_alive(sockets))
689 socket[sockets].flags |= IS_ALIVE;
690 sockets++;
691}
692
693static void __init add_pcic(int ns, int type)
694{
695 u_int mask = 0, i, base;
696 int isa_irq = 0;
697 struct i82365_socket *t = &socket[sockets-ns];
698
699 base = sockets-ns;
1da177e4
LT		 700 if (base == 0) printk("\n");
701 printk(KERN_INFO " %s", pcic[type].name);
702 printk(" ISA-to-PCMCIA at port %#lx ofs 0x%02x",
703 t->ioaddr, t->psock*0x40);
704 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : ""));
705
706 /* Set host options, build basic interrupt mask */
707 if (irq_list_count == 0)
708 mask = irq_mask;
709 else
710 for (i = mask = 0; i < irq_list_count; i++)
711 mask |= (1<<irq_list[i]);
712 mask &= I365_MASK & set_bridge_opts(base, ns);
713 /* Scan for ISA interrupts */
714 mask = isa_scan(base, mask);
715
716 /* Poll if only two interrupts available */
717 if (!poll_interval) {
718 u_int tmp = (mask & 0xff20);
719 tmp = tmp & (tmp-1);
720 if ((tmp & (tmp-1)) == 0)
721 poll_interval = HZ;
722 }
723 /* Only try an ISA cs_irq if this is the first controller */
724 if (!grab_irq && (cs_irq || !poll_interval)) {
725 /* Avoid irq 12 unless it is explicitly requested */
726 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
727 for (cs_irq = 15; cs_irq > 0; cs_irq--)
728 if ((cs_mask & (1 << cs_irq)) &&
729 (_check_irq(cs_irq, 0) == 0))
730 break;
731 if (cs_irq) {
732 grab_irq = 1;
733 isa_irq = cs_irq;
734 printk(" status change on irq %d\n", cs_irq);
735 }
736 }
737
738 if (!isa_irq) {
739 if (poll_interval == 0)
740 poll_interval = HZ;
741 printk(" polling interval = %d ms\n",
742 poll_interval * 1000 / HZ);
743
744 }
745
746 /* Update socket interrupt information, capabilities */
747 for (i = 0; i < ns; i++) {
748 t[i].socket.features |= SS_CAP_PCCARD;
749 t[i].socket.map_size = 0x1000;
750 t[i].socket.irq_mask = mask;
751 t[i].cs_irq = isa_irq;
752 }
753
754} /* add_pcic */
755
756/*====================================================================*/
757
758#ifdef CONFIG_PNP
759static struct isapnp_device_id id_table[] __initdata = {
760 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'),
761 ISAPNP_FUNCTION(0x0e00), (unsigned long) "Intel 82365-Compatible" },
762 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'),
763 ISAPNP_FUNCTION(0x0e01), (unsigned long) "Cirrus Logic CL-PD6720" },
764 { ISAPNP_ANY_ID, ISAPNP_ANY_ID, ISAPNP_VENDOR('P', 'N', 'P'),
765 ISAPNP_FUNCTION(0x0e02), (unsigned long) "VLSI VL82C146" },
766 { 0 }
767};
768MODULE_DEVICE_TABLE(isapnp, id_table);
769
770static struct pnp_dev *i82365_pnpdev;
771#endif
772
773static void __init isa_probe(void)
774{
775 int i, j, sock, k, ns, id;
776 kio_addr_t port;
777#ifdef CONFIG_PNP
778 struct isapnp_device_id *devid;
779 struct pnp_dev *dev;
780
781 for (devid = id_table; devid->vendor; devid++) {
782 if ((dev = pnp_find_dev(NULL, devid->vendor, devid->function, NULL))) {
783
784 if (pnp_device_attach(dev) < 0)
785 continue;
786
787 if (pnp_activate_dev(dev) < 0) {
788 printk("activate failed\n");
789 pnp_device_detach(dev);
790 break;
791 }
792
793 if (!pnp_port_valid(dev, 0)) {
794 printk("invalid resources ?\n");
795 pnp_device_detach(dev);
796 break;
797 }
798 i365_base = pnp_port_start(dev, 0);
799 i82365_pnpdev = dev;
800 break;
801 }
802 }
803#endif
804
f354942c 805 if (!request_region(i365_base, 2, "i82365")) {
1da177e4
LT		 806 if (sockets == 0)
807 printk("port conflict at %#lx\n", i365_base);
808 return;
809 }
810
811 id = identify(i365_base, 0);
812 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) {
813 for (i = 0; i < 4; i++) {
814 if (i == ignore) continue;
815 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1);
816 sock = (i & 1) << 1;
817 if (identify(port, sock) == IS_I82365DF) {
818 add_socket(port, sock, IS_VLSI);
819 add_pcic(1, IS_VLSI);
820 }
821 }
822 } else {
823 for (i = 0; i < 8; i += 2) {
824 if (sockets && !extra_sockets && (i == 4))
825 break;
826 port = i365_base + 2*(i>>2);
827 sock = (i & 3);
828 id = identify(port, sock);
829 if (id < 0) continue;
830
831 for (j = ns = 0; j < 2; j++) {
832 /* Does the socket exist? */
833 if ((ignore == i+j) || (identify(port, sock+j) < 0))
834 continue;
835 /* Check for bad socket decode */
836 for (k = 0; k <= sockets; k++)
837 i365_set(k, I365_MEM(0)+I365_W_OFF, k);
838 for (k = 0; k <= sockets; k++)
839 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
840 break;
841 if (k <= sockets) break;
842 add_socket(port, sock+j, id); ns++;
843 }
844 if (ns != 0) add_pcic(ns, id);
845 }
846 }
847}
848
849/*====================================================================*/
850
851static irqreturn_t pcic_interrupt(int irq, void *dev,
852 struct pt_regs *regs)
853{
854 int i, j, csc;
855 u_int events, active;
856 u_long flags = 0;
857 int handled = 0;
858
859 debug(4, "pcic_interrupt(%d)\n", irq);
860
861 for (j = 0; j < 20; j++) {
862 active = 0;
863 for (i = 0; i < sockets; i++) {
864 if (socket[i].cs_irq != irq)
865 continue;
866 handled = 1;
867 ISA_LOCK(i, flags);
868 csc = i365_get(i, I365_CSC);
869 if ((csc == 0) || (i365_get(i, I365_IDENT) & 0x70)) {
870 ISA_UNLOCK(i, flags);
871 continue;
872 }
873 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
874
875 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD)
876 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
877 else {
878 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
879 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
880 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
881 }
882 ISA_UNLOCK(i, flags);
883 debug(2, "socket %d event 0x%02x\n", i, events);
884
885 if (events)
886 pcmcia_parse_events(&socket[i].socket, events);
887
888 active |= events;
889 }
890 if (!active) break;
891 }
892 if (j == 20)
893 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n");
894
895 debug(4, "interrupt done\n");
896 return IRQ_RETVAL(handled);
897} /* pcic_interrupt */
898
899static void pcic_interrupt_wrapper(u_long data)
900{
901 pcic_interrupt(0, NULL, NULL);
902 poll_timer.expires = jiffies + poll_interval;
903 add_timer(&poll_timer);
904}
905
906/*====================================================================*/
907
908static int i365_get_status(u_short sock, u_int *value)
909{
910 u_int status;
911
912 status = i365_get(sock, I365_STATUS);
913 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT)
914 ? SS_DETECT : 0;
915
916 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD)
917 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
918 else {
919 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
920 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
921 }
922 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
923 *value |= (status & I365_CS_READY) ? SS_READY : 0;
924 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
925
926 if (socket[sock].type == IS_VG469) {
927 status = i365_get(sock, VG469_VSENSE);
928 if (socket[sock].psock & 1) {
929 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD;
930 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD;
931 } else {
932 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD;
933 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD;
934 }
935 }
936
937 debug(1, "GetStatus(%d) = %#4.4x\n", sock, *value);
938 return 0;
939} /* i365_get_status */
940
941/*====================================================================*/
942
943static int i365_get_socket(u_short sock, socket_state_t *state)
944{
945 struct i82365_socket *t = &socket[sock];
946 u_char reg, vcc, vpp;
947
948 reg = i365_get(sock, I365_POWER);
949 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
950 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
951 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
952 state->Vcc = state->Vpp = 0;
953 if (t->flags & IS_CIRRUS) {
954 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
955 if (reg & I365_VCC_5V) state->Vcc = 33;
956 if (vpp == I365_VPP1_5V) state->Vpp = 33;
957 } else {
958 if (reg & I365_VCC_5V) state->Vcc = 50;
959 if (vpp == I365_VPP1_5V) state->Vpp = 50;
960 }
961 if (vpp == I365_VPP1_12V) state->Vpp = 120;
962 } else if (t->flags & IS_VG_PWR) {
963 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) {
964 if (reg & I365_VCC_5V) state->Vcc = 33;
965 if (vpp == I365_VPP1_5V) state->Vpp = 33;
966 } else {
967 if (reg & I365_VCC_5V) state->Vcc = 50;
968 if (vpp == I365_VPP1_5V) state->Vpp = 50;
969 }
970 if (vpp == I365_VPP1_12V) state->Vpp = 120;
971 } else if (t->flags & IS_DF_PWR) {
972 if (vcc == I365_VCC_3V) state->Vcc = 33;
973 if (vcc == I365_VCC_5V) state->Vcc = 50;
974 if (vpp == I365_VPP1_5V) state->Vpp = 50;
975 if (vpp == I365_VPP1_12V) state->Vpp = 120;
976 } else {
977 if (reg & I365_VCC_5V) {
978 state->Vcc = 50;
979 if (vpp == I365_VPP1_5V) state->Vpp = 50;
980 if (vpp == I365_VPP1_12V) state->Vpp = 120;
981 }
982 }
983
984 /* IO card, RESET flags, IO interrupt */
985 reg = i365_get(sock, I365_INTCTL);
986 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
987 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD;
988 state->io_irq = reg & I365_IRQ_MASK;
989
990 /* speaker control */
991 if (t->flags & IS_CIRRUS) {
992 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA)
993 state->flags |= SS_SPKR_ENA;
994 }
995
996 /* Card status change mask */
997 reg = i365_get(sock, I365_CSCINT);
998 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
999 if (state->flags & SS_IOCARD)
1000 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
1001 else {
1002 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
1003 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
1004 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
1005 }
1006
1007 debug(1, "GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
1008 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
1009 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1010 return 0;
1011} /* i365_get_socket */
1012
1013/*====================================================================*/
1014
1015static int i365_set_socket(u_short sock, socket_state_t *state)
1016{
1017 struct i82365_socket *t = &socket[sock];
1018 u_char reg;
1019
1020 debug(1, "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
1021 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
1022 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1023
1024 /* First set global controller options */
1025 set_bridge_state(sock);
1026
1027 /* IO card, RESET flag, IO interrupt */
1028 reg = t->intr;
1029 reg |= state->io_irq;
1030 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
1031 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
1032 i365_set(sock, I365_INTCTL, reg);
1033
1034 reg = I365_PWR_NORESET;
1035 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
1036 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
1037
1038 if (t->flags & IS_CIRRUS) {
1039 if (state->Vpp != 0) {
1040 if (state->Vpp == 120)
1041 reg |= I365_VPP1_12V;
1042 else if (state->Vpp == state->Vcc)
1043 reg |= I365_VPP1_5V;
1044 else return -EINVAL;
1045 }
1046 if (state->Vcc != 0) {
1047 reg |= I365_VCC_5V;
1048 if (state->Vcc == 33)
1049 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1050 else if (state->Vcc == 50)
1051 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1052 else return -EINVAL;
1053 }
1054 } else if (t->flags & IS_VG_PWR) {
1055 if (state->Vpp != 0) {
1056 if (state->Vpp == 120)
1057 reg |= I365_VPP1_12V;
1058 else if (state->Vpp == state->Vcc)
1059 reg |= I365_VPP1_5V;
1060 else return -EINVAL;
1061 }
1062 if (state->Vcc != 0) {
1063 reg |= I365_VCC_5V;
1064 if (state->Vcc == 33)
1065 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC);
1066 else if (state->Vcc == 50)
1067 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC);
1068 else return -EINVAL;
1069 }
1070 } else if (t->flags & IS_DF_PWR) {
1071 switch (state->Vcc) {
1072 case 0: break;
1073 case 33: reg |= I365_VCC_3V; break;
1074 case 50: reg |= I365_VCC_5V; break;
1075 default: return -EINVAL;
1076 }
1077 switch (state->Vpp) {
1078 case 0: break;
1079 case 50: reg |= I365_VPP1_5V; break;
1080 case 120: reg |= I365_VPP1_12V; break;
1081 default: return -EINVAL;
1082 }
1083 } else {
1084 switch (state->Vcc) {
1085 case 0: break;
1086 case 50: reg |= I365_VCC_5V; break;
1087 default: return -EINVAL;
1088 }
1089 switch (state->Vpp) {
1090 case 0: break;
1091 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break;
1092 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break;
1093 default: return -EINVAL;
1094 }
1095 }
1096
1097 if (reg != i365_get(sock, I365_POWER))
1098 i365_set(sock, I365_POWER, reg);
1099
1100 /* Chipset-specific functions */
1101 if (t->flags & IS_CIRRUS) {
1102 /* Speaker control */
1103 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA,
1104 state->flags & SS_SPKR_ENA);
1105 }
1106
1107 /* Card status change interrupt mask */
1108 reg = t->cs_irq << 4;
1109 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
1110 if (state->flags & SS_IOCARD) {
1111 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
1112 } else {
1113 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
1114 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
1115 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
1116 }
1117 i365_set(sock, I365_CSCINT, reg);
1118 i365_get(sock, I365_CSC);
1119
1120 return 0;
1121} /* i365_set_socket */
1122
1123/*====================================================================*/
1124
1125static int i365_set_io_map(u_short sock, struct pccard_io_map *io)
1126{
1127 u_char map, ioctl;
1128
1129 debug(1, "SetIOMap(%d, %d, %#2.2x, %d ns, "
1130 "%#lx-%#lx)\n", sock, io->map, io->flags,
1131 io->speed, io->start, io->stop);
1132 map = io->map;
1133 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
1134 (io->stop < io->start)) return -EINVAL;
1135 /* Turn off the window before changing anything */
1136 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map))
1137 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map));
1138 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start);
1139 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop);
1140 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
1141 if (io->speed) ioctl |= I365_IOCTL_WAIT(map);
1142 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
1143 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
1144 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
1145 i365_set(sock, I365_IOCTL, ioctl);
1146 /* Turn on the window if necessary */
1147 if (io->flags & MAP_ACTIVE)
1148 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map));
1149 return 0;
1150} /* i365_set_io_map */
1151
1152/*====================================================================*/
1153
1154static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem)
1155{
1156 u_short base, i;
1157 u_char map;
1158
1159 debug(1, "SetMemMap(%d, %d, %#2.2x, %d ns, %#lx-%#lx, "
1160 "%#x)\n", sock, mem->map, mem->flags, mem->speed,
1161 mem->res->start, mem->res->end, mem->card_start);
1162
1163 map = mem->map;
1164 if ((map > 4) || (mem->card_start > 0x3ffffff) ||
1165 (mem->res->start > mem->res->end) || (mem->speed > 1000))
1166 return -EINVAL;
1167 if ((mem->res->start > 0xffffff) || (mem->res->end > 0xffffff))
1168 return -EINVAL;
1169
1170 /* Turn off the window before changing anything */
1171 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
1172 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1173
1174 base = I365_MEM(map);
1175 i = (mem->res->start >> 12) & 0x0fff;
1176 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT;
1177 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS;
1178 i365_set_pair(sock, base+I365_W_START, i);
1179
1180 i = (mem->res->end >> 12) & 0x0fff;
1181 switch (to_cycles(mem->speed)) {
1182 case 0: break;
1183 case 1: i |= I365_MEM_WS0; break;
1184 case 2: i |= I365_MEM_WS1; break;
1185 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break;
1186 }
1187 i365_set_pair(sock, base+I365_W_STOP, i);
1188
1189 i = ((mem->card_start - mem->res->start) >> 12) & 0x3fff;
1190 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT;
1191 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG;
1192 i365_set_pair(sock, base+I365_W_OFF, i);
1193
1194 /* Turn on the window if necessary */
1195 if (mem->flags & MAP_ACTIVE)
1196 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1197 return 0;
1198} /* i365_set_mem_map */
1199
1200#if 0 /* driver model ordering issue */
1201/*======================================================================
1202
1203 Routines for accessing socket information and register dumps via
1204 /sys/class/pcmcia_socket/...
1205
1206======================================================================*/
1207
1208static ssize_t show_info(struct class_device *class_dev, char *buf)
1209{
1210 struct i82365_socket *s = container_of(class_dev, struct i82365_socket, socket.dev);
1211 return sprintf(buf, "type: %s\npsock: %d\n",
1212 pcic[s->type].name, s->psock);
1213}
1214
1215static ssize_t show_exca(struct class_device *class_dev, char *buf)
1216{
1217 struct i82365_socket *s = container_of(class_dev, struct i82365_socket, socket.dev);
1218 unsigned short sock;
1219 int i;
1220 ssize_t ret = 0;
1221 unsigned long flags = 0;
1222
1223 sock = s->number;
1224
1225 ISA_LOCK(sock, flags);
1226 for (i = 0; i < 0x40; i += 4) {
1227 ret += sprintf(buf, "%02x %02x %02x %02x%s",
1228 i365_get(sock,i), i365_get(sock,i+1),
1229 i365_get(sock,i+2), i365_get(sock,i+3),
1230 ((i % 16) == 12) ? "\n" : " ");
1231 buf += ret;
1232 }
1233 ISA_UNLOCK(sock, flags);
1234
1235 return ret;
1236}
1237
1238static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
1239static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
1240#endif
1241
1242/*====================================================================*/
1243
1244/* this is horribly ugly... proper locking needs to be done here at
1245 * some time... */
1246#define LOCKED(x) do { \
1247 int retval; \
1248 unsigned long flags; \
1249 spin_lock_irqsave(&isa_lock, flags); \
1250 retval = x; \
1251 spin_unlock_irqrestore(&isa_lock, flags); \
1252 return retval; \
1253} while (0)
1254
1255
1256static int pcic_get_status(struct pcmcia_socket *s, u_int *value)
1257{
1258 unsigned int sock = container_of(s, struct i82365_socket, socket)->number;
1259
1260 if (socket[sock].flags & IS_ALIVE) {
1261 *value = 0;
1262 return -EINVAL;
1263 }
1264
1265 LOCKED(i365_get_status(sock, value));
1266}
1267
1268static int pcic_get_socket(struct pcmcia_socket *s, socket_state_t *state)
1269{
1270 unsigned int sock = container_of(s, struct i82365_socket, socket)->number;
1271
1272 if (socket[sock].flags & IS_ALIVE)
1273 return -EINVAL;
1274
1275 LOCKED(i365_get_socket(sock, state));
1276}
1277
1278static int pcic_set_socket(struct pcmcia_socket *s, socket_state_t *state)
1279{
1280 unsigned int sock = container_of(s, struct i82365_socket, socket)->number;
1281
1282 if (socket[sock].flags & IS_ALIVE)
1283 return -EINVAL;
1284
1285 LOCKED(i365_set_socket(sock, state));
1286}
1287
1288static int pcic_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
1289{
1290 unsigned int sock = container_of(s, struct i82365_socket, socket)->number;
1291 if (socket[sock].flags & IS_ALIVE)
1292 return -EINVAL;
1293
1294 LOCKED(i365_set_io_map(sock, io));
1295}
1296
1297static int pcic_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
1298{
1299 unsigned int sock = container_of(s, struct i82365_socket, socket)->number;
1300 if (socket[sock].flags & IS_ALIVE)
1301 return -EINVAL;
1302
1303 LOCKED(i365_set_mem_map(sock, mem));
1304}
1305
1306static int pcic_init(struct pcmcia_socket *s)
1307{
1308 int i;
1309 struct resource res = { .start = 0, .end = 0x1000 };
1310 pccard_io_map io = { 0, 0, 0, 0, 1 };
1311 pccard_mem_map mem = { .res = &res, };
1312
1313 for (i = 0; i < 2; i++) {
1314 io.map = i;
1315 pcic_set_io_map(s, &io);
1316 }
1317 for (i = 0; i < 5; i++) {
1318 mem.map = i;
1319 pcic_set_mem_map(s, &mem);
1320 }
1321 return 0;
1322}
1323
1324static struct pccard_operations pcic_operations = {
1325 .init = pcic_init,
1326 .get_status = pcic_get_status,
1327 .get_socket = pcic_get_socket,
1328 .set_socket = pcic_set_socket,
1329 .set_io_map = pcic_set_io_map,
1330 .set_mem_map = pcic_set_mem_map,
1331};
1332
1333/*====================================================================*/
1334
1da177e4
LT		 1335static struct device_driver i82365_driver = {
1336 .name = "i82365",
1337 .bus = &platform_bus_type,
9480e307
RK		 1338 .suspend = pcmcia_socket_dev_suspend,
1339 .resume = pcmcia_socket_dev_resume,
1da177e4
LT		 1340};
1341
1342static struct platform_device i82365_device = {
1343 .name = "i82365",
1344 .id = 0,
1345};
1346
1347static int __init init_i82365(void)
1348{
1349 int i, ret;
1350
1351 ret = driver_register(&i82365_driver);
1352 if (ret)
1353 return ret;
1354
1355 ret = platform_device_register(&i82365_device);
1356 if (ret) {
1357 driver_unregister(&i82365_driver);
1358 return ret;
1359 }
1360
1361 printk(KERN_INFO "Intel ISA PCIC probe: ");
1362 sockets = 0;
1363
1364 isa_probe();
1365
1366 if (sockets == 0) {
1367 printk("not found.\n");
1368 platform_device_unregister(&i82365_device);
1369 driver_unregister(&i82365_driver);
1370 return -ENODEV;
1371 }
1372
1373 /* Set up interrupt handler(s) */
1374 if (grab_irq != 0)
1375 request_irq(cs_irq, pcic_interrupt, 0, "i82365", pcic_interrupt);
1376
1377 /* register sockets with the pcmcia core */
1378 for (i = 0; i < sockets; i++) {
1379 socket[i].socket.dev.dev = &i82365_device.dev;
1380 socket[i].socket.ops = &pcic_operations;
1381 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
1382 socket[i].socket.owner = THIS_MODULE;
1383 socket[i].number = i;
1384 ret = pcmcia_register_socket(&socket[i].socket);
1385 if (!ret)
1386 socket[i].flags |= IS_REGISTERED;
1387
1388#if 0 /* driver model ordering issue */
1389 class_device_create_file(&socket[i].socket.dev,
1390 &class_device_attr_info);
1391 class_device_create_file(&socket[i].socket.dev,
1392 &class_device_attr_exca);
1393#endif
1394 }
1395
1396 /* Finally, schedule a polling interrupt */
1397 if (poll_interval != 0) {
1398 poll_timer.function = pcic_interrupt_wrapper;
1399 poll_timer.data = 0;
1400 init_timer(&poll_timer);
1401 poll_timer.expires = jiffies + poll_interval;
1402 add_timer(&poll_timer);
1403 }
1404
1405 return 0;
1406
1407} /* init_i82365 */
1408
1409static void __exit exit_i82365(void)
1410{
1411 int i;
1412
1413 for (i = 0; i < sockets; i++) {
1414 if (socket[i].flags & IS_REGISTERED)
1415 pcmcia_unregister_socket(&socket[i].socket);
1416 }
1417 platform_device_unregister(&i82365_device);
1418 if (poll_interval != 0)
1419 del_timer_sync(&poll_timer);
1420 if (grab_irq != 0)
1421 free_irq(cs_irq, pcic_interrupt);
1422 for (i = 0; i < sockets; i++) {
1423 /* Turn off all interrupt sources! */
1424 i365_set(i, I365_CSCINT, 0);
1425 release_region(socket[i].ioaddr, 2);
1426 }
f354942c 1427 release_region(i365_base, 2);
1da177e4
LT		 1428#ifdef CONFIG_PNP
1429 if (i82365_pnpdev)
1430 pnp_disable_dev(i82365_pnpdev);
1431#endif
1432 driver_unregister(&i82365_driver);
1433} /* exit_i82365 */
1434
1435module_init(init_i82365);
1436module_exit(exit_i82365);
1437MODULE_LICENSE("Dual MPL/GPL");
1438/*====================================================================*/
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