[linux.git] / drivers / ata / pata_radisys.c

/*
 *    pata_radisys.c - Intel PATA/SATA controllers
 *
 *	(C) 2006 Red Hat <[email protected]>
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    A PIIX relative, this device has a single ATA channel and no
 *    slave timings, SITRE or PPE. In that sense it is a close relative
 *    of the original PIIX. It does however support UDMA 33/66 per channel
 *    although no other modes/timings. Also lacking is 32bit I/O on the ATA
 *    port.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_radisys"
#define DRV_VERSION	"0.4.4"

/**
 *	radisys_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: ATA port
 *	@adev: Device whose timings we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void radisys_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u16 idetm_data;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. Note that the early PIIX does not have the slave
	 *	timing port at 0x44. The Radisys is a relative of the PIIX
	 *	but not the same so be careful.
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },	/* Check me */
			    { 0, 0 },
			    { 1, 1 },
			    { 2, 2 },
			    { 3, 3 }, };

	if (pio > 0)
		control |= 1;	/* TIME1 enable */
	if (ata_pio_need_iordy(adev))
		control |= 2;	/* IE IORDY */

	pci_read_config_word(dev, 0x40, &idetm_data);

	/* Enable IE and TIME as appropriate. Clear the other
	   drive timing bits */
	idetm_data &= 0xCCCC;
	idetm_data |= (control << (4 * adev->devno));
	idetm_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	pci_write_config_word(dev, 0x40, idetm_data);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	radisys_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *	@isich: True if the device is an ICH and has IOCFG registers
 *
 *	Set MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void radisys_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u16 idetm_data;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 1 },
			    { 2, 2 },
			    { 3, 3 }, };

	/*
	 * MWDMA is driven by the PIO timings. We must also enable
	 * IORDY unconditionally.
	 */

	pci_read_config_word(dev, 0x40, &idetm_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (adev->dma_mode < XFER_UDMA_0) {
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;
		int control = 3;	/* IORDY|TIME0 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO0 for PIO cycles. */

		if (adev->pio_mode < needed_pio[mwdma])
			control = 1;

		/* Mask out the relevant control and timing bits we will load. Also
		   clear the other drive TIME register as a precaution */

		idetm_data &= 0xCCCC;
		idetm_data |= control << (4 * adev->devno);
		idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);

		udma_enable &= ~(1 << adev->devno);
	} else {
		u8 udma_mode;

		/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */

		pci_read_config_byte(dev, 0x4A, &udma_mode);

		if (adev->xfer_mode == XFER_UDMA_2)
			udma_mode &= ~ (1 << adev->devno);
		else /* UDMA 4 */
			udma_mode |= (1 << adev->devno);

		pci_write_config_byte(dev, 0x4A, udma_mode);

		udma_enable |= (1 << adev->devno);
	}
	pci_write_config_word(dev, 0x40, idetm_data);
	pci_write_config_byte(dev, 0x48, udma_enable);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	radisys_qc_issue	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	if (adev != ap->private_data) {
		/* UDMA timing is not shared */
		if (adev->dma_mode < XFER_UDMA_0) {
			if (adev->dma_mode)
				radisys_set_dmamode(ap, adev);
			else if (adev->pio_mode)
				radisys_set_piomode(ap, adev);
		}
	}
	return ata_sff_qc_issue(qc);
}


static struct scsi_host_template radisys_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations radisys_pata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.qc_issue		= radisys_qc_issue,
	.cable_detect		= ata_cable_unknown,
	.set_piomode		= radisys_set_piomode,
	.set_dmamode		= radisys_set_dmamode,
};


/**
 *	radisys_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in radisys_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int radisys_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	static const struct ata_port_info info = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma1-2 */
		.udma_mask	= 0x14, /* UDMA33/66 only */
		.port_ops	= &radisys_pata_ops,
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	return ata_pci_sff_init_one(pdev, ppi, &radisys_sht, NULL);
}

static const struct pci_device_id radisys_pci_tbl[] = {
	{ PCI_VDEVICE(RADISYS, 0x8201), },

	{ }	/* terminate list */
};

static struct pci_driver radisys_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= radisys_pci_tbl,
	.probe			= radisys_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

static int __init radisys_init(void)
{
	return pci_register_driver(&radisys_pci_driver);
}

static void __exit radisys_exit(void)
{
	pci_unregister_driver(&radisys_pci_driver);
}

module_init(radisys_init);
module_exit(radisys_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for Radisys R82600 controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, radisys_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_radisys.c - Intel PATA/SATA controllers
	3	*
ab771630	4	* (C) 2006 Red Hat <[email protected]>
669a5db4 JG	5	*
	6	* Some parts based on ata_piix.c by Jeff Garzik and others.
	7	*
	8	* A PIIX relative, this device has a single ATA channel and no
	9	* slave timings, SITRE or PPE. In that sense it is a close relative
	10	* of the original PIIX. It does however support UDMA 33/66 per channel
	11	* although no other modes/timings. Also lacking is 32bit I/O on the ATA
	12	* port.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/module.h>
	17	#include <linux/pci.h>
	18	#include <linux/init.h>
	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <linux/device.h>
	22	#include <scsi/scsi_host.h>
	23	#include <linux/libata.h>
	24	#include <linux/ata.h>
	25
	26	#define DRV_NAME "pata_radisys"
d36a7648	27	#define DRV_VERSION "0.4.4"
669a5db4 JG	28
	29	/**
	30	* radisys_set_piomode - Initialize host controller PATA PIO timings
d36a7648 AC	31	* @ap: ATA port
d36a7648 AC	32	* @adev: Device whose timings we are configuring
669a5db4 JG	33	*
	34	* Set PIO mode for device, in host controller PCI config space.
	35	*
	36	* LOCKING:
	37	* None (inherited from caller).
	38	*/
	39
	40	static void radisys_set_piomode (struct ata_port ap, struct ata_device adev)
	41	{
	42	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	43	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	44	u16 idetm_data;
	45	int control = 0;
	46
	47	/*
	48	* See Intel Document 298600-004 for the timing programing rules
	49	* for PIIX/ICH. Note that the early PIIX does not have the slave
	50	* timing port at 0x44. The Radisys is a relative of the PIIX
	51	* but not the same so be careful.
	52	*/
	53
	54	static const /* ISP RTC */
	55	u8 timings[][2] = { { 0, 0 }, /* Check me */
	56	{ 0, 0 },
	57	{ 1, 1 },
	58	{ 2, 2 },
	59	{ 3, 3 }, };
	60
	61	if (pio > 0)
	62	control \|= 1; /* TIME1 enable */
	63	if (ata_pio_need_iordy(adev))
	64	control \|= 2; /* IE IORDY */
	65
	66	pci_read_config_word(dev, 0x40, &idetm_data);
	67
	68	/* Enable IE and TIME as appropriate. Clear the other
	69	drive timing bits */
	70	idetm_data &= 0xCCCC;
	71	idetm_data \|= (control << (4 * adev->devno));
	72	idetm_data \|= (timings[pio][0] << 12) \|
	73	(timings[pio][1] << 8);
	74	pci_write_config_word(dev, 0x40, idetm_data);
	75
	76	/* Track which port is configured */
	77	ap->private_data = adev;
	78	}
	79
	80	/**
	81	* radisys_set_dmamode - Initialize host controller PATA DMA timings
	82	* @ap: Port whose timings we are configuring
	83	* @adev: Device to program
	84	* @isich: True if the device is an ICH and has IOCFG registers
	85	*
	86	* Set MWDMA mode for device, in host controller PCI config space.
	87	*
	88	* LOCKING:
	89	* None (inherited from caller).
	90	*/
	91
	92	static void radisys_set_dmamode (struct ata_port ap, struct ata_device adev)
	93	{
	94	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	95	u16 idetm_data;
	96	u8 udma_enable;
85cd7251	97
669a5db4 JG	98	static const /* ISP RTC */
	99	u8 timings[][2] = { { 0, 0 },
	100	{ 0, 0 },
	101	{ 1, 1 },
	102	{ 2, 2 },
	103	{ 3, 3 }, };
	104
	105	/*
	106	* MWDMA is driven by the PIO timings. We must also enable
	107	* IORDY unconditionally.
	108	*/
	109
	110	pci_read_config_word(dev, 0x40, &idetm_data);
	111	pci_read_config_byte(dev, 0x48, &udma_enable);
	112
	113	if (adev->dma_mode < XFER_UDMA_0) {
	114	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
	115	const unsigned int needed_pio[3] = {
	116	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	117	};
	118	int pio = needed_pio[mwdma] - XFER_PIO_0;
	119	int control = 3; /* IORDY\|TIME0 */
	120
	121	/* If the drive MWDMA is faster than it can do PIO then
	122	we must force PIO0 for PIO cycles. */
	123
	124	if (adev->pio_mode < needed_pio[mwdma])
	125	control = 1;
	126
	127	/* Mask out the relevant control and timing bits we will load. Also
	128	clear the other drive TIME register as a precaution */
85cd7251	129
669a5db4 JG	130	idetm_data &= 0xCCCC;
	131	idetm_data \|= control << (4 * adev->devno);
	132	idetm_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	133
	134	udma_enable &= ~(1 << adev->devno);
	135	} else {
	136	u8 udma_mode;
85cd7251	137
669a5db4	138	/* UDMA66 on: UDMA 33 and 66 are switchable via register 0x4A */
85cd7251	139
669a5db4	140	pci_read_config_byte(dev, 0x4A, &udma_mode);
85cd7251	141
669a5db4 JG	142	if (adev->xfer_mode == XFER_UDMA_2)
	143	udma_mode &= ~ (1 << adev->devno);
	144	else /* UDMA 4 */
	145	udma_mode \|= (1 << adev->devno);
85cd7251	146
669a5db4	147	pci_write_config_byte(dev, 0x4A, udma_mode);
85cd7251	148
669a5db4 JG	149	udma_enable \|= (1 << adev->devno);
	150	}
	151	pci_write_config_word(dev, 0x40, idetm_data);
	152	pci_write_config_byte(dev, 0x48, udma_enable);
	153
	154	/* Track which port is configured */
	155	ap->private_data = adev;
	156	}
	157
	158	/**
9363c382	159	* radisys_qc_issue - command issue
669a5db4 JG	160	* @qc: command pending
	161	*
	162	* Called when the libata layer is about to issue a command. We wrap
	163	* this interface so that we can load the correct ATA timings if
3a4fa0a2	164	* necessary. Our logic also clears TIME0/TIME1 for the other device so
669a5db4 JG	165	* that, even if we get this wrong, cycles to the other device will
	166	* be made PIO0.
	167	*/
	168
9363c382	169	static unsigned int radisys_qc_issue(struct ata_queued_cmd *qc)
669a5db4 JG	170	{
	171	struct ata_port *ap = qc->ap;
	172	struct ata_device *adev = qc->dev;
	173
	174	if (adev != ap->private_data) {
	175	/* UDMA timing is not shared */
	176	if (adev->dma_mode < XFER_UDMA_0) {
	177	if (adev->dma_mode)
	178	radisys_set_dmamode(ap, adev);
	179	else if (adev->pio_mode)
	180	radisys_set_piomode(ap, adev);
	181	}
	182	}
9363c382	183	return ata_sff_qc_issue(qc);
669a5db4 JG	184	}
	185
	186
	187	static struct scsi_host_template radisys_sht = {
68d1d07b	188	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	189	};
669a5db4 JG	190
029cfd6b TH	191	static struct ata_port_operations radisys_pata_ops = {
029cfd6b TH	192	.inherits = &ata_bmdma_port_ops,
9363c382	193	.qc_issue = radisys_qc_issue,
029cfd6b	194	.cable_detect = ata_cable_unknown,
669a5db4 JG	195	.set_piomode = radisys_set_piomode,
669a5db4 JG	196	.set_dmamode = radisys_set_dmamode,
669a5db4 JG	197	};
	198
	199
	200	/**
	201	* radisys_init_one - Register PIIX ATA PCI device with kernel services
	202	* @pdev: PCI device to register
	203	* @ent: Entry in radisys_pci_tbl matching with @pdev
	204	*
	205	* Called from kernel PCI layer. We probe for combined mode (sigh),
	206	* and then hand over control to libata, for it to do the rest.
	207	*
	208	* LOCKING:
	209	* Inherited from PCI layer (may sleep).
	210	*
	211	* RETURNS:
	212	* Zero on success, or -ERRNO value.
	213	*/
	214
	215	static int radisys_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	216	{
	217	static int printed_version;
1626aeb8	218	static const struct ata_port_info info = {
1d2808fd	219	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	220	.pio_mask = 0x1f, /* pio0-4 */
	221	.mwdma_mask = 0x07, /* mwdma1-2 */
	222	.udma_mask = 0x14, /* UDMA33/66 only */
	223	.port_ops = &radisys_pata_ops,
	224	};
1626aeb8	225	const struct ata_port_info *ppi[] = { &info, NULL };
669a5db4 JG	226
	227	if (!printed_version++)
	228	dev_printk(KERN_DEBUG, &pdev->dev,
	229	"version " DRV_VERSION "\n");
	230
9363c382	231	return ata_pci_sff_init_one(pdev, ppi, &radisys_sht, NULL);
669a5db4 JG	232	}
	233
	234	static const struct pci_device_id radisys_pci_tbl[] = {
2d2744fc JG	235	{ PCI_VDEVICE(RADISYS, 0x8201), },
2d2744fc JG	236
669a5db4 JG	237	{ } /* terminate list */
	238	};
	239
	240	static struct pci_driver radisys_pci_driver = {
	241	.name = DRV_NAME,
	242	.id_table = radisys_pci_tbl,
	243	.probe = radisys_init_one,
	244	.remove = ata_pci_remove_one,
438ac6d5	245	#ifdef CONFIG_PM
30ced0f0 AC	246	.suspend = ata_pci_device_suspend,
30ced0f0 AC	247	.resume = ata_pci_device_resume,
438ac6d5	248	#endif
669a5db4 JG	249	};
	250
	251	static int __init radisys_init(void)
	252	{
	253	return pci_register_driver(&radisys_pci_driver);
	254	}
	255
	256	static void __exit radisys_exit(void)
	257	{
	258	pci_unregister_driver(&radisys_pci_driver);
	259	}
	260
669a5db4 JG	261	module_init(radisys_init);
	262	module_exit(radisys_exit);
	263
	264	MODULE_AUTHOR("Alan Cox");
	265	MODULE_DESCRIPTION("SCSI low-level driver for Radisys R82600 controllers");
	266	MODULE_LICENSE("GPL");
	267	MODULE_DEVICE_TABLE(pci, radisys_pci_tbl);
	268	MODULE_VERSION(DRV_VERSION);
	269