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KVM: x86: simplify ept_misconfig
[linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <[email protected]>
13 * Yaniv Kamay <[email protected]>
4d5c5d0f
BAY		 14 * Amit Shah <[email protected]>
15 * Ben-Ami Yassour <[email protected]>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
18863bdd
AK		 137#define KVM_NR_SHARED_MSRS 16
138
139struct kvm_shared_msrs_global {
140 int nr;
2bf78fa7 141 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144struct kvm_shared_msrs {
145 struct user_return_notifier urn;
146 bool registered;
2bf78fa7
SY		 147 struct kvm_shared_msr_values {
148 u64 host;
149 u64 curr;
150 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 151};
152
153static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 154static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 155
417bc304 156struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 157 { "pf_fixed", VCPU_STAT(pf_fixed) },
158 { "pf_guest", VCPU_STAT(pf_guest) },
159 { "tlb_flush", VCPU_STAT(tlb_flush) },
160 { "invlpg", VCPU_STAT(invlpg) },
161 { "exits", VCPU_STAT(exits) },
162 { "io_exits", VCPU_STAT(io_exits) },
163 { "mmio_exits", VCPU_STAT(mmio_exits) },
164 { "signal_exits", VCPU_STAT(signal_exits) },
165 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 166 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 167 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 168 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 169 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 170 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 171 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 172 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 173 { "request_irq", VCPU_STAT(request_irq_exits) },
174 { "irq_exits", VCPU_STAT(irq_exits) },
175 { "host_state_reload", VCPU_STAT(host_state_reload) },
176 { "efer_reload", VCPU_STAT(efer_reload) },
177 { "fpu_reload", VCPU_STAT(fpu_reload) },
178 { "insn_emulation", VCPU_STAT(insn_emulation) },
179 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 180 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 181 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 182 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 193 { "max_mmu_page_hash_collisions",
194 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 195 { NULL }
196};
197
2acf923e
DC		 198u64 __read_mostly host_xcr0;
199
b6785def 200static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 201
af585b92
GN		 202static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
203{
204 int i;
205 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
206 vcpu->arch.apf.gfns[i] = ~0;
207}
208
18863bdd
AK		 209static void kvm_on_user_return(struct user_return_notifier *urn)
210{
211 unsigned slot;
18863bdd
AK		 212 struct kvm_shared_msrs *locals
213 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 214 struct kvm_shared_msr_values *values;
1650b4eb
IA		 215 unsigned long flags;
216
217 /*
218 * Disabling irqs at this point since the following code could be
219 * interrupted and executed through kvm_arch_hardware_disable()
220 */
221 local_irq_save(flags);
222 if (locals->registered) {
223 locals->registered = false;
224 user_return_notifier_unregister(urn);
225 }
226 local_irq_restore(flags);
18863bdd 227 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 228 values = &locals->values[slot];
229 if (values->host != values->curr) {
230 wrmsrl(shared_msrs_global.msrs[slot], values->host);
231 values->curr = values->host;
18863bdd
AK		 232 }
233 }
18863bdd
AK		 234}
235
2bf78fa7 236static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 237{
18863bdd 238 u64 value;
013f6a5d
MT		 239 unsigned int cpu = smp_processor_id();
240 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 241
2bf78fa7
SY		 242 /* only read, and nobody should modify it at this time,
243 * so don't need lock */
244 if (slot >= shared_msrs_global.nr) {
245 printk(KERN_ERR "kvm: invalid MSR slot!");
246 return;
247 }
248 rdmsrl_safe(msr, &value);
249 smsr->values[slot].host = value;
250 smsr->values[slot].curr = value;
251}
252
253void kvm_define_shared_msr(unsigned slot, u32 msr)
254{
0123be42 255 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 256 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 257 if (slot >= shared_msrs_global.nr)
258 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
261
262static void kvm_shared_msr_cpu_online(void)
263{
264 unsigned i;
18863bdd
AK		 265
266 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 267 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 268}
269
8b3c3104 270int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 274 int err;
18863bdd 275
2bf78fa7 276 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 277 return 0;
2bf78fa7 278 smsr->values[slot].curr = value;
8b3c3104
AH		 279 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
280 if (err)
281 return 1;
282
18863bdd
AK		 283 if (!smsr->registered) {
284 smsr->urn.on_user_return = kvm_on_user_return;
285 user_return_notifier_register(&smsr->urn);
286 smsr->registered = true;
287 }
8b3c3104 288 return 0;
18863bdd
AK		 289}
290EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
291
13a34e06 292static void drop_user_return_notifiers(void)
3548bab5 293{
013f6a5d
MT		 294 unsigned int cpu = smp_processor_id();
295 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 296
297 if (smsr->registered)
298 kvm_on_user_return(&smsr->urn);
299}
300
6866b83e
CO		 301u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
302{
8a5a87d9 303 return vcpu->arch.apic_base;
6866b83e
CO		 304}
305EXPORT_SYMBOL_GPL(kvm_get_apic_base);
306
58cb628d
JK		 307int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
308{
309 u64 old_state = vcpu->arch.apic_base &
310 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
311 u64 new_state = msr_info->data &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 313 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
314 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 315
d3802286
JM		 316 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
317 return 1;
58cb628d 318 if (!msr_info->host_initiated &&
d3802286 319 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 320 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
321 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
322 old_state == 0)))
323 return 1;
324
325 kvm_lapic_set_base(vcpu, msr_info->data);
326 return 0;
6866b83e
CO		 327}
328EXPORT_SYMBOL_GPL(kvm_set_apic_base);
329
2605fc21 330asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 331{
332 /* Fault while not rebooting. We want the trace. */
333 BUG();
334}
335EXPORT_SYMBOL_GPL(kvm_spurious_fault);
336
3fd28fce
ED		 337#define EXCPT_BENIGN 0
338#define EXCPT_CONTRIBUTORY 1
339#define EXCPT_PF 2
340
341static int exception_class(int vector)
342{
343 switch (vector) {
344 case PF_VECTOR:
345 return EXCPT_PF;
346 case DE_VECTOR:
347 case TS_VECTOR:
348 case NP_VECTOR:
349 case SS_VECTOR:
350 case GP_VECTOR:
351 return EXCPT_CONTRIBUTORY;
352 default:
353 break;
354 }
355 return EXCPT_BENIGN;
356}
357
d6e8c854
NA		 358#define EXCPT_FAULT 0
359#define EXCPT_TRAP 1
360#define EXCPT_ABORT 2
361#define EXCPT_INTERRUPT 3
362
363static int exception_type(int vector)
364{
365 unsigned int mask;
366
367 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
368 return EXCPT_INTERRUPT;
369
370 mask = 1 << vector;
371
372 /* #DB is trap, as instruction watchpoints are handled elsewhere */
373 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
374 return EXCPT_TRAP;
375
376 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
377 return EXCPT_ABORT;
378
379 /* Reserved exceptions will result in fault */
380 return EXCPT_FAULT;
381}
382
3fd28fce 383static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 384 unsigned nr, bool has_error, u32 error_code,
385 bool reinject)
3fd28fce
ED		 386{
387 u32 prev_nr;
388 int class1, class2;
389
3842d135
AK		 390 kvm_make_request(KVM_REQ_EVENT, vcpu);
391
3fd28fce
ED		 392 if (!vcpu->arch.exception.pending) {
393 queue:
3ffb2468
NA		 394 if (has_error && !is_protmode(vcpu))
395 has_error = false;
3fd28fce
ED		 396 vcpu->arch.exception.pending = true;
397 vcpu->arch.exception.has_error_code = has_error;
398 vcpu->arch.exception.nr = nr;
399 vcpu->arch.exception.error_code = error_code;
3f0fd292 400 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 401 return;
402 }
403
404 /* to check exception */
405 prev_nr = vcpu->arch.exception.nr;
406 if (prev_nr == DF_VECTOR) {
407 /* triple fault -> shutdown */
a8eeb04a 408 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 409 return;
410 }
411 class1 = exception_class(prev_nr);
412 class2 = exception_class(nr);
413 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
414 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
415 /* generate double fault per SDM Table 5-5 */
416 vcpu->arch.exception.pending = true;
417 vcpu->arch.exception.has_error_code = true;
418 vcpu->arch.exception.nr = DF_VECTOR;
419 vcpu->arch.exception.error_code = 0;
420 } else
421 /* replace previous exception with a new one in a hope
422 that instruction re-execution will regenerate lost
423 exception */
424 goto queue;
425}
426
298101da
AK		 427void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
428{
ce7ddec4 429 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 430}
431EXPORT_SYMBOL_GPL(kvm_queue_exception);
432
ce7ddec4
JR		 433void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
434{
435 kvm_multiple_exception(vcpu, nr, false, 0, true);
436}
437EXPORT_SYMBOL_GPL(kvm_requeue_exception);
438
6affcbed 439int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 440{
db8fcefa
AP		 441 if (err)
442 kvm_inject_gp(vcpu, 0);
443 else
6affcbed
KH		 444 return kvm_skip_emulated_instruction(vcpu);
445
446 return 1;
db8fcefa
AP		 447}
448EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 449
6389ee94 450void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 451{
452 ++vcpu->stat.pf_guest;
adfe20fb
WL		 453 vcpu->arch.exception.nested_apf =
454 is_guest_mode(vcpu) && fault->async_page_fault;
455 if (vcpu->arch.exception.nested_apf)
456 vcpu->arch.apf.nested_apf_token = fault->address;
457 else
458 vcpu->arch.cr2 = fault->address;
6389ee94 459 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 460}
27d6c865 461EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 462
ef54bcfe 463static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 464{
6389ee94
AK		 465 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
466 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 467 else
6389ee94 468 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 469
470 return fault->nested_page_fault;
d4f8cf66
JR		 471}
472
3419ffc8
SY		 473void kvm_inject_nmi(struct kvm_vcpu *vcpu)
474{
7460fb4a
AK		 475 atomic_inc(&vcpu->arch.nmi_queued);
476 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 477}
478EXPORT_SYMBOL_GPL(kvm_inject_nmi);
479
298101da
AK		 480void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
481{
ce7ddec4 482 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 483}
484EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
485
ce7ddec4
JR		 486void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
487{
488 kvm_multiple_exception(vcpu, nr, true, error_code, true);
489}
490EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
491
0a79b009
AK		 492/*
493 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
494 * a #GP and return false.
495 */
496bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 497{
0a79b009
AK		 498 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
499 return true;
500 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
501 return false;
298101da 502}
0a79b009 503EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 504
16f8a6f9
NA		 505bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
506{
507 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
508 return true;
509
510 kvm_queue_exception(vcpu, UD_VECTOR);
511 return false;
512}
513EXPORT_SYMBOL_GPL(kvm_require_dr);
514
ec92fe44
JR		 515/*
516 * This function will be used to read from the physical memory of the currently
54bf36aa 517 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 518 * can read from guest physical or from the guest's guest physical memory.
519 */
520int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
521 gfn_t ngfn, void *data, int offset, int len,
522 u32 access)
523{
54987b7a 524 struct x86_exception exception;
ec92fe44
JR		 525 gfn_t real_gfn;
526 gpa_t ngpa;
527
528 ngpa = gfn_to_gpa(ngfn);
54987b7a 529 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 530 if (real_gfn == UNMAPPED_GVA)
531 return -EFAULT;
532
533 real_gfn = gpa_to_gfn(real_gfn);
534
54bf36aa 535 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 536}
537EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
538
69b0049a 539static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 540 void *data, int offset, int len, u32 access)
541{
542 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
543 data, offset, len, access);
544}
545
a03490ed
CO		 546/*
547 * Load the pae pdptrs. Return true is they are all valid.
548 */
ff03a073 549int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 550{
551 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
552 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
553 int i;
554 int ret;
ff03a073 555 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 556
ff03a073
JR		 557 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
558 offset * sizeof(u64), sizeof(pdpte),
559 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 560 if (ret < 0) {
561 ret = 0;
562 goto out;
563 }
564 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 565 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 566 (pdpte[i] &
567 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 568 ret = 0;
569 goto out;
570 }
571 }
572 ret = 1;
573
ff03a073 574 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 575 __set_bit(VCPU_EXREG_PDPTR,
576 (unsigned long *)&vcpu->arch.regs_avail);
577 __set_bit(VCPU_EXREG_PDPTR,
578 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 579out:
a03490ed
CO		 580
581 return ret;
582}
cc4b6871 583EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 584
9ed38ffa 585bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 586{
ff03a073 587 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 588 bool changed = true;
3d06b8bf
JR		 589 int offset;
590 gfn_t gfn;
d835dfec
AK		 591 int r;
592
593 if (is_long_mode(vcpu) || !is_pae(vcpu))
594 return false;
595
6de4f3ad
AK		 596 if (!test_bit(VCPU_EXREG_PDPTR,
597 (unsigned long *)&vcpu->arch.regs_avail))
598 return true;
599
a512177e
PB		 600 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
601 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 602 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
603 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 604 if (r < 0)
605 goto out;
ff03a073 606 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 607out:
d835dfec
AK		 608
609 return changed;
610}
9ed38ffa 611EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 612
49a9b07e 613int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 614{
aad82703 615 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 616 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 617
f9a48e6a
AK		 618 cr0 |= X86_CR0_ET;
619
ab344828 620#ifdef CONFIG_X86_64
0f12244f
GN		 621 if (cr0 & 0xffffffff00000000UL)
622 return 1;
ab344828
GN		 623#endif
624
625 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
628 return 1;
a03490ed 629
0f12244f
GN		 630 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
631 return 1;
a03490ed
CO		 632
633 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
634#ifdef CONFIG_X86_64
f6801dff 635 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 636 int cs_db, cs_l;
637
0f12244f
GN		 638 if (!is_pae(vcpu))
639 return 1;
a03490ed 640 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 641 if (cs_l)
642 return 1;
a03490ed
CO		 643 } else
644#endif
ff03a073 645 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 646 kvm_read_cr3(vcpu)))
0f12244f 647 return 1;
a03490ed
CO		 648 }
649
ad756a16
MJ		 650 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
651 return 1;
652
a03490ed 653 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 654
d170c419 655 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 656 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 657 kvm_async_pf_hash_reset(vcpu);
658 }
e5f3f027 659
aad82703
SY		 660 if ((cr0 ^ old_cr0) & update_bits)
661 kvm_mmu_reset_context(vcpu);
b18d5431 662
879ae188
LE		 663 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
664 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
665 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 666 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
667
0f12244f
GN		 668 return 0;
669}
2d3ad1f4 670EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 671
2d3ad1f4 672void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 673{
49a9b07e 674 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 677
42bdf991
MT		 678static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
679{
680 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
681 !vcpu->guest_xcr0_loaded) {
682 /* kvm_set_xcr() also depends on this */
683 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
684 vcpu->guest_xcr0_loaded = 1;
685 }
686}
687
688static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->guest_xcr0_loaded) {
691 if (vcpu->arch.xcr0 != host_xcr0)
692 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
693 vcpu->guest_xcr0_loaded = 0;
694 }
695}
696
69b0049a 697static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 698{
56c103ec
LJ		 699 u64 xcr0 = xcr;
700 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 701 u64 valid_bits;
2acf923e
DC		 702
703 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
704 if (index != XCR_XFEATURE_ENABLED_MASK)
705 return 1;
d91cab78 706 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 709 return 1;
46c34cb0
PB		 710
711 /*
712 * Do not allow the guest to set bits that we do not support
713 * saving. However, xcr0 bit 0 is always set, even if the
714 * emulated CPU does not support XSAVE (see fx_init).
715 */
d91cab78 716 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 717 if (xcr0 & ~valid_bits)
2acf923e 718 return 1;
46c34cb0 719
d91cab78
DH		 720 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
721 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 722 return 1;
723
d91cab78
DH		 724 if (xcr0 & XFEATURE_MASK_AVX512) {
725 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 726 return 1;
d91cab78 727 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 728 return 1;
729 }
2acf923e 730 vcpu->arch.xcr0 = xcr0;
56c103ec 731
d91cab78 732 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 733 kvm_update_cpuid(vcpu);
2acf923e
DC		 734 return 0;
735}
736
737int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
738{
764bcbc5
Z		 739 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
740 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 741 kvm_inject_gp(vcpu, 0);
742 return 1;
743 }
744 return 0;
745}
746EXPORT_SYMBOL_GPL(kvm_set_xcr);
747
a83b29c6 748int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 749{
fc78f519 750 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 751 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 752 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 753
0f12244f
GN		 754 if (cr4 & CR4_RESERVED_BITS)
755 return 1;
a03490ed 756
d6321d49 757 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 758 return 1;
759
d6321d49 760 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
c68b734f
YW		 761 return 1;
762
d6321d49 763 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
97ec8c06
FW		 764 return 1;
765
d6321d49 766 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 767 return 1;
768
d6321d49 769 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
b9baba86
HH		 770 return 1;
771
a03490ed 772 if (is_long_mode(vcpu)) {
0f12244f
GN		 773 if (!(cr4 & X86_CR4_PAE))
774 return 1;
a2edf57f
AK		 775 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
776 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 777 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
778 kvm_read_cr3(vcpu)))
0f12244f
GN		 779 return 1;
780
ad756a16 781 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 783 return 1;
784
785 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
786 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
787 return 1;
788 }
789
5e1746d6 790 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 791 return 1;
a03490ed 792
ad756a16
MJ		 793 if (((cr4 ^ old_cr4) & pdptr_bits) ||
794 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 795 kvm_mmu_reset_context(vcpu);
0f12244f 796
b9baba86 797 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 798 kvm_update_cpuid(vcpu);
2acf923e 799
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 803
2390218b 804int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 805{
ac146235 806#ifdef CONFIG_X86_64
9d88fca7 807 cr3 &= ~CR3_PCID_INVD;
ac146235 808#endif
9d88fca7 809
9f8fe504 810 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 811 kvm_mmu_sync_roots(vcpu);
77c3913b 812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 813 return 0;
d835dfec
AK		 814 }
815
a03490ed 816 if (is_long_mode(vcpu)) {
d9f89b88
JK		 817 if (cr3 & CR3_L_MODE_RESERVED_BITS)
818 return 1;
819 } else if (is_pae(vcpu) && is_paging(vcpu) &&
820 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 821 return 1;
a03490ed 822
0f12244f 823 vcpu->arch.cr3 = cr3;
aff48baa 824 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 825 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 829
eea1cff9 830int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 831{
0f12244f
GN		 832 if (cr8 & CR8_RESERVED_BITS)
833 return 1;
35754c98 834 if (lapic_in_kernel(vcpu))
a03490ed
CO		 835 kvm_lapic_set_tpr(vcpu, cr8);
836 else
ad312c7c 837 vcpu->arch.cr8 = cr8;
0f12244f
GN		 838 return 0;
839}
2d3ad1f4 840EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 841
2d3ad1f4 842unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 843{
35754c98 844 if (lapic_in_kernel(vcpu))
a03490ed
CO		 845 return kvm_lapic_get_cr8(vcpu);
846 else
ad312c7c 847 return vcpu->arch.cr8;
a03490ed 848}
2d3ad1f4 849EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 850
ae561ede
NA		 851static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
852{
853 int i;
854
855 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
856 for (i = 0; i < KVM_NR_DB_REGS; i++)
857 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
858 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
859 }
860}
861
73aaf249
JK		 862static void kvm_update_dr6(struct kvm_vcpu *vcpu)
863{
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
866}
867
c8639010
JK		 868static void kvm_update_dr7(struct kvm_vcpu *vcpu)
869{
870 unsigned long dr7;
871
872 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
873 dr7 = vcpu->arch.guest_debug_dr7;
874 else
875 dr7 = vcpu->arch.dr7;
876 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 877 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
878 if (dr7 & DR7_BP_EN_MASK)
879 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 880}
881
6f43ed01
NA		 882static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
883{
884 u64 fixed = DR6_FIXED_1;
885
d6321d49 886 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 887 fixed |= DR6_RTM;
888 return fixed;
889}
890
338dbc97 891static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 892{
893 switch (dr) {
894 case 0 ... 3:
895 vcpu->arch.db[dr] = val;
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 vcpu->arch.eff_db[dr] = val;
898 break;
899 case 4:
020df079
GN		 900 /* fall through */
901 case 6:
338dbc97
GN		 902 if (val & 0xffffffff00000000ULL)
903 return -1; /* #GP */
6f43ed01 904 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 905 kvm_update_dr6(vcpu);
020df079
GN		 906 break;
907 case 5:
020df079
GN		 908 /* fall through */
909 default: /* 7 */
338dbc97
GN		 910 if (val & 0xffffffff00000000ULL)
911 return -1; /* #GP */
020df079 912 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 913 kvm_update_dr7(vcpu);
020df079
GN		 914 break;
915 }
916
917 return 0;
918}
338dbc97
GN		 919
920int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
921{
16f8a6f9 922 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 923 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 924 return 1;
925 }
926 return 0;
338dbc97 927}
020df079
GN		 928EXPORT_SYMBOL_GPL(kvm_set_dr);
929
16f8a6f9 930int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 *val = vcpu->arch.db[dr];
935 break;
936 case 4:
020df079
GN		 937 /* fall through */
938 case 6:
73aaf249
JK		 939 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
940 *val = vcpu->arch.dr6;
941 else
942 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 943 break;
944 case 5:
020df079
GN		 945 /* fall through */
946 default: /* 7 */
947 *val = vcpu->arch.dr7;
948 break;
949 }
338dbc97
GN		 950 return 0;
951}
020df079
GN		 952EXPORT_SYMBOL_GPL(kvm_get_dr);
953
022cd0e8
AK		 954bool kvm_rdpmc(struct kvm_vcpu *vcpu)
955{
956 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
957 u64 data;
958 int err;
959
c6702c9d 960 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 961 if (err)
962 return err;
963 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
964 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
965 return err;
966}
967EXPORT_SYMBOL_GPL(kvm_rdpmc);
968
043405e1
CO		 969/*
970 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
971 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
972 *
973 * This list is modified at module load time to reflect the
e3267cbb 974 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 975 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
976 * may depend on host virtualization features rather than host cpu features.
043405e1 977 */
e3267cbb 978
043405e1
CO		 979static u32 msrs_to_save[] = {
980 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 981 MSR_STAR,
043405e1
CO		 982#ifdef CONFIG_X86_64
983 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
984#endif
b3897a49 985 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 986 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 987};
988
989static unsigned num_msrs_to_save;
990
62ef68bb
PB		 991static u32 emulated_msrs[] = {
992 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
993 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
994 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
995 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 996 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 997 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
998 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 999 HV_X64_MSR_RESET,
11c4b1ca 1000 HV_X64_MSR_VP_INDEX,
9eec50b8 1001 HV_X64_MSR_VP_RUNTIME,
5c919412 1002 HV_X64_MSR_SCONTROL,
1f4b34f8 1003 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1004 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1005 MSR_KVM_PV_EOI_EN,
1006
ba904635 1007 MSR_IA32_TSC_ADJUST,
a3e06bbe 1008 MSR_IA32_TSCDEADLINE,
043405e1 1009 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1010 MSR_IA32_MCG_STATUS,
1011 MSR_IA32_MCG_CTL,
c45dcc71 1012 MSR_IA32_MCG_EXT_CTL,
64d60670 1013 MSR_IA32_SMBASE,
db2336a8
KH		 1014 MSR_PLATFORM_INFO,
1015 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1016};
1017
62ef68bb
PB		 1018static unsigned num_emulated_msrs;
1019
384bb783 1020bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1021{
b69e8cae 1022 if (efer & efer_reserved_bits)
384bb783 1023 return false;
15c4a640 1024
1b4d56b8 1025 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1026 return false;
1b2fd70c 1027
1b4d56b8 1028 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1029 return false;
d8017474 1030
384bb783
JK		 1031 return true;
1032}
1033EXPORT_SYMBOL_GPL(kvm_valid_efer);
1034
1035static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1036{
1037 u64 old_efer = vcpu->arch.efer;
1038
1039 if (!kvm_valid_efer(vcpu, efer))
1040 return 1;
1041
1042 if (is_paging(vcpu)
1043 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1044 return 1;
1045
15c4a640 1046 efer &= ~EFER_LMA;
f6801dff 1047 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1048
a3d204e2
SY		 1049 kvm_x86_ops->set_efer(vcpu, efer);
1050
aad82703
SY		 1051 /* Update reserved bits */
1052 if ((efer ^ old_efer) & EFER_NX)
1053 kvm_mmu_reset_context(vcpu);
1054
b69e8cae 1055 return 0;
15c4a640
CO		 1056}
1057
f2b4b7dd
JR		 1058void kvm_enable_efer_bits(u64 mask)
1059{
1060 efer_reserved_bits &= ~mask;
1061}
1062EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1063
15c4a640
CO		 1064/*
1065 * Writes msr value into into the appropriate "register".
1066 * Returns 0 on success, non-0 otherwise.
1067 * Assumes vcpu_load() was already called.
1068 */
8fe8ab46 1069int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1070{
854e8bb1
NA		 1071 switch (msr->index) {
1072 case MSR_FS_BASE:
1073 case MSR_GS_BASE:
1074 case MSR_KERNEL_GS_BASE:
1075 case MSR_CSTAR:
1076 case MSR_LSTAR:
1077 if (is_noncanonical_address(msr->data))
1078 return 1;
1079 break;
1080 case MSR_IA32_SYSENTER_EIP:
1081 case MSR_IA32_SYSENTER_ESP:
1082 /*
1083 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1084 * non-canonical address is written on Intel but not on
1085 * AMD (which ignores the top 32-bits, because it does
1086 * not implement 64-bit SYSENTER).
1087 *
1088 * 64-bit code should hence be able to write a non-canonical
1089 * value on AMD. Making the address canonical ensures that
1090 * vmentry does not fail on Intel after writing a non-canonical
1091 * value, and that something deterministic happens if the guest
1092 * invokes 64-bit SYSENTER.
1093 */
1094 msr->data = get_canonical(msr->data);
1095 }
8fe8ab46 1096 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1097}
854e8bb1 1098EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1099
313a3dc7
CO		 1100/*
1101 * Adapt set_msr() to msr_io()'s calling convention
1102 */
609e36d3
PB		 1103static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1104{
1105 struct msr_data msr;
1106 int r;
1107
1108 msr.index = index;
1109 msr.host_initiated = true;
1110 r = kvm_get_msr(vcpu, &msr);
1111 if (r)
1112 return r;
1113
1114 *data = msr.data;
1115 return 0;
1116}
1117
313a3dc7
CO		 1118static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1119{
8fe8ab46
WA		 1120 struct msr_data msr;
1121
1122 msr.data = *data;
1123 msr.index = index;
1124 msr.host_initiated = true;
1125 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1126}
1127
16e8d74d
MT		 1128#ifdef CONFIG_X86_64
1129struct pvclock_gtod_data {
1130 seqcount_t seq;
1131
1132 struct { /* extract of a clocksource struct */
1133 int vclock_mode;
a5a1d1c2
TG		 1134 u64 cycle_last;
1135 u64 mask;
16e8d74d
MT		 1136 u32 mult;
1137 u32 shift;
1138 } clock;
1139
cbcf2dd3
TG		 1140 u64 boot_ns;
1141 u64 nsec_base;
55dd00a7 1142 u64 wall_time_sec;
16e8d74d
MT		 1143};
1144
1145static struct pvclock_gtod_data pvclock_gtod_data;
1146
1147static void update_pvclock_gtod(struct timekeeper *tk)
1148{
1149 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1150 u64 boot_ns;
1151
876e7881 1152 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1153
1154 write_seqcount_begin(&vdata->seq);
1155
1156 /* copy pvclock gtod data */
876e7881
PZ		 1157 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1158 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1159 vdata->clock.mask = tk->tkr_mono.mask;
1160 vdata->clock.mult = tk->tkr_mono.mult;
1161 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1162
cbcf2dd3 1163 vdata->boot_ns = boot_ns;
876e7881 1164 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1165
55dd00a7
MT		 1166 vdata->wall_time_sec = tk->xtime_sec;
1167
16e8d74d
MT		 1168 write_seqcount_end(&vdata->seq);
1169}
1170#endif
1171
bab5bb39
NK		 1172void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1173{
1174 /*
1175 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1176 * vcpu_enter_guest. This function is only called from
1177 * the physical CPU that is running vcpu.
1178 */
1179 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1180}
16e8d74d 1181
18068523
GOC		 1182static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1183{
9ed3c444
AK		 1184 int version;
1185 int r;
50d0a0f9 1186 struct pvclock_wall_clock wc;
87aeb54f 1187 struct timespec64 boot;
18068523
GOC		 1188
1189 if (!wall_clock)
1190 return;
1191
9ed3c444
AK		 1192 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1193 if (r)
1194 return;
1195
1196 if (version & 1)
1197 ++version; /* first time write, random junk */
1198
1199 ++version;
18068523 1200
1dab1345
NK		 1201 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1202 return;
18068523 1203
50d0a0f9
GH		 1204 /*
1205 * The guest calculates current wall clock time by adding
34c238a1 1206 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1207 * wall clock specified here. guest system time equals host
1208 * system time for us, thus we must fill in host boot time here.
1209 */
87aeb54f 1210 getboottime64(&boot);
50d0a0f9 1211
4b648665 1212 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1213 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1214 boot = timespec64_sub(boot, ts);
4b648665 1215 }
87aeb54f 1216 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1217 wc.nsec = boot.tv_nsec;
1218 wc.version = version;
18068523
GOC		 1219
1220 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1221
1222 version++;
1223 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1224}
1225
50d0a0f9
GH		 1226static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1227{
b51012de
PB		 1228 do_shl32_div32(dividend, divisor);
1229 return dividend;
50d0a0f9
GH		 1230}
1231
3ae13faa 1232static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1233 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1234{
5f4e3f88 1235 uint64_t scaled64;
50d0a0f9
GH		 1236 int32_t shift = 0;
1237 uint64_t tps64;
1238 uint32_t tps32;
1239
3ae13faa
PB		 1240 tps64 = base_hz;
1241 scaled64 = scaled_hz;
50933623 1242 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1243 tps64 >>= 1;
1244 shift--;
1245 }
1246
1247 tps32 = (uint32_t)tps64;
50933623
JK		 1248 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1249 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1250 scaled64 >>= 1;
1251 else
1252 tps32 <<= 1;
50d0a0f9
GH		 1253 shift++;
1254 }
1255
5f4e3f88
ZA		 1256 *pshift = shift;
1257 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1258
3ae13faa
PB		 1259 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1260 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1261}
1262
d828199e 1263#ifdef CONFIG_X86_64
16e8d74d 1264static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1265#endif
16e8d74d 1266
c8076604 1267static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1268static unsigned long max_tsc_khz;
c8076604 1269
cc578287 1270static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1271{
cc578287
ZA		 1272 u64 v = (u64)khz * (1000000 + ppm);
1273 do_div(v, 1000000);
1274 return v;
1e993611
JR		 1275}
1276
381d585c
HZ		 1277static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1278{
1279 u64 ratio;
1280
1281 /* Guest TSC same frequency as host TSC? */
1282 if (!scale) {
1283 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1284 return 0;
1285 }
1286
1287 /* TSC scaling supported? */
1288 if (!kvm_has_tsc_control) {
1289 if (user_tsc_khz > tsc_khz) {
1290 vcpu->arch.tsc_catchup = 1;
1291 vcpu->arch.tsc_always_catchup = 1;
1292 return 0;
1293 } else {
1294 WARN(1, "user requested TSC rate below hardware speed\n");
1295 return -1;
1296 }
1297 }
1298
1299 /* TSC scaling required - calculate ratio */
1300 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1301 user_tsc_khz, tsc_khz);
1302
1303 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1304 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1305 user_tsc_khz);
1306 return -1;
1307 }
1308
1309 vcpu->arch.tsc_scaling_ratio = ratio;
1310 return 0;
1311}
1312
4941b8cb 1313static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1314{
cc578287
ZA		 1315 u32 thresh_lo, thresh_hi;
1316 int use_scaling = 0;
217fc9cf 1317
03ba32ca 1318 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1319 if (user_tsc_khz == 0) {
ad721883
HZ		 1320 /* set tsc_scaling_ratio to a safe value */
1321 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1322 return -1;
ad721883 1323 }
03ba32ca 1324
c285545f 1325 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1326 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1327 &vcpu->arch.virtual_tsc_shift,
1328 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1329 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1330
1331 /*
1332 * Compute the variation in TSC rate which is acceptable
1333 * within the range of tolerance and decide if the
1334 * rate being applied is within that bounds of the hardware
1335 * rate. If so, no scaling or compensation need be done.
1336 */
1337 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1338 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1339 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1340 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1341 use_scaling = 1;
1342 }
4941b8cb 1343 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1344}
1345
1346static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1347{
e26101b1 1348 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1349 vcpu->arch.virtual_tsc_mult,
1350 vcpu->arch.virtual_tsc_shift);
e26101b1 1351 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1352 return tsc;
1353}
1354
69b0049a 1355static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1356{
1357#ifdef CONFIG_X86_64
1358 bool vcpus_matched;
b48aa97e
MT		 1359 struct kvm_arch *ka = &vcpu->kvm->arch;
1360 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1361
1362 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1363 atomic_read(&vcpu->kvm->online_vcpus));
1364
7f187922
MT		 1365 /*
1366 * Once the masterclock is enabled, always perform request in
1367 * order to update it.
1368 *
1369 * In order to enable masterclock, the host clocksource must be TSC
1370 * and the vcpus need to have matched TSCs. When that happens,
1371 * perform request to enable masterclock.
1372 */
1373 if (ka->use_master_clock ||
1374 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1375 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1376
1377 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1378 atomic_read(&vcpu->kvm->online_vcpus),
1379 ka->use_master_clock, gtod->clock.vclock_mode);
1380#endif
1381}
1382
ba904635
WA		 1383static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1384{
3e3f5026 1385 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1386 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1387}
1388
35181e86
HZ		 1389/*
1390 * Multiply tsc by a fixed point number represented by ratio.
1391 *
1392 * The most significant 64-N bits (mult) of ratio represent the
1393 * integral part of the fixed point number; the remaining N bits
1394 * (frac) represent the fractional part, ie. ratio represents a fixed
1395 * point number (mult + frac * 2^(-N)).
1396 *
1397 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1398 */
1399static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1400{
1401 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1402}
1403
1404u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1405{
1406 u64 _tsc = tsc;
1407 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1408
1409 if (ratio != kvm_default_tsc_scaling_ratio)
1410 _tsc = __scale_tsc(ratio, tsc);
1411
1412 return _tsc;
1413}
1414EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1415
07c1419a
HZ		 1416static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1417{
1418 u64 tsc;
1419
1420 tsc = kvm_scale_tsc(vcpu, rdtsc());
1421
1422 return target_tsc - tsc;
1423}
1424
4ba76538
HZ		 1425u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1426{
ea26e4ec 1427 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1428}
1429EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1430
a545ab6a
LC		 1431static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1432{
1433 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1434 vcpu->arch.tsc_offset = offset;
1435}
1436
8fe8ab46 1437void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1438{
1439 struct kvm *kvm = vcpu->kvm;
f38e098f 1440 u64 offset, ns, elapsed;
99e3e30a 1441 unsigned long flags;
b48aa97e 1442 bool matched;
0d3da0d2 1443 bool already_matched;
8fe8ab46 1444 u64 data = msr->data;
c5e8ec8e 1445 bool synchronizing = false;
99e3e30a 1446
038f8c11 1447 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1448 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1449 ns = ktime_get_boot_ns();
f38e098f 1450 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1451
03ba32ca 1452 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1453 if (data == 0 && msr->host_initiated) {
1454 /*
1455 * detection of vcpu initialization -- need to sync
1456 * with other vCPUs. This particularly helps to keep
1457 * kvm_clock stable after CPU hotplug
1458 */
1459 synchronizing = true;
1460 } else {
1461 u64 tsc_exp = kvm->arch.last_tsc_write +
1462 nsec_to_cycles(vcpu, elapsed);
1463 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1464 /*
1465 * Special case: TSC write with a small delta (1 second)
1466 * of virtual cycle time against real time is
1467 * interpreted as an attempt to synchronize the CPU.
1468 */
1469 synchronizing = data < tsc_exp + tsc_hz &&
1470 data + tsc_hz > tsc_exp;
1471 }
c5e8ec8e 1472 }
f38e098f
ZA		 1473
1474 /*
5d3cb0f6
ZA		 1475 * For a reliable TSC, we can match TSC offsets, and for an unstable
1476 * TSC, we add elapsed time in this computation. We could let the
1477 * compensation code attempt to catch up if we fall behind, but
1478 * it's better to try to match offsets from the beginning.
1479 */
c5e8ec8e 1480 if (synchronizing &&
5d3cb0f6 1481 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1482 if (!check_tsc_unstable()) {
e26101b1 1483 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1484 pr_debug("kvm: matched tsc offset for %llu\n", data);
1485 } else {
857e4099 1486 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1487 data += delta;
07c1419a 1488 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1489 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1490 }
b48aa97e 1491 matched = true;
0d3da0d2 1492 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1493 } else {
1494 /*
1495 * We split periods of matched TSC writes into generations.
1496 * For each generation, we track the original measured
1497 * nanosecond time, offset, and write, so if TSCs are in
1498 * sync, we can match exact offset, and if not, we can match
4a969980 1499 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1500 *
1501 * These values are tracked in kvm->arch.cur_xxx variables.
1502 */
1503 kvm->arch.cur_tsc_generation++;
1504 kvm->arch.cur_tsc_nsec = ns;
1505 kvm->arch.cur_tsc_write = data;
1506 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1507 matched = false;
0d3da0d2 1508 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1509 kvm->arch.cur_tsc_generation, data);
f38e098f 1510 }
e26101b1
ZA		 1511
1512 /*
1513 * We also track th most recent recorded KHZ, write and time to
1514 * allow the matching interval to be extended at each write.
1515 */
f38e098f
ZA		 1516 kvm->arch.last_tsc_nsec = ns;
1517 kvm->arch.last_tsc_write = data;
5d3cb0f6 1518 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1519
b183aa58 1520 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1521
1522 /* Keep track of which generation this VCPU has synchronized to */
1523 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1524 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1525 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1526
d6321d49 1527 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1528 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1529
a545ab6a 1530 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1531 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1532
1533 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1534 if (!matched) {
b48aa97e 1535 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1536 } else if (!already_matched) {
1537 kvm->arch.nr_vcpus_matched_tsc++;
1538 }
b48aa97e
MT		 1539
1540 kvm_track_tsc_matching(vcpu);
1541 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1542}
e26101b1 1543
99e3e30a
ZA		 1544EXPORT_SYMBOL_GPL(kvm_write_tsc);
1545
58ea6767
HZ		 1546static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1547 s64 adjustment)
1548{
ea26e4ec 1549 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1550}
1551
1552static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1553{
1554 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1555 WARN_ON(adjustment < 0);
1556 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1557 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1558}
1559
d828199e
MT		 1560#ifdef CONFIG_X86_64
1561
a5a1d1c2 1562static u64 read_tsc(void)
d828199e 1563{
a5a1d1c2 1564 u64 ret = (u64)rdtsc_ordered();
03b9730b 1565 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1566
1567 if (likely(ret >= last))
1568 return ret;
1569
1570 /*
1571 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1572 * predictable (it's just a function of time and the likely is
d828199e
MT		 1573 * very likely) and there's a data dependence, so force GCC
1574 * to generate a branch instead. I don't barrier() because
1575 * we don't actually need a barrier, and if this function
1576 * ever gets inlined it will generate worse code.
1577 */
1578 asm volatile ("");
1579 return last;
1580}
1581
a5a1d1c2 1582static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1583{
1584 long v;
1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1586
1587 *cycle_now = read_tsc();
1588
1589 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1590 return v * gtod->clock.mult;
1591}
1592
a5a1d1c2 1593static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1594{
cbcf2dd3 1595 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1596 unsigned long seq;
d828199e 1597 int mode;
cbcf2dd3 1598 u64 ns;
d828199e 1599
d828199e
MT		 1600 do {
1601 seq = read_seqcount_begin(&gtod->seq);
1602 mode = gtod->clock.vclock_mode;
cbcf2dd3 1603 ns = gtod->nsec_base;
d828199e
MT		 1604 ns += vgettsc(cycle_now);
1605 ns >>= gtod->clock.shift;
cbcf2dd3 1606 ns += gtod->boot_ns;
d828199e 1607 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1608 *t = ns;
d828199e
MT		 1609
1610 return mode;
1611}
1612
55dd00a7
MT		 1613static int do_realtime(struct timespec *ts, u64 *cycle_now)
1614{
1615 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1616 unsigned long seq;
1617 int mode;
1618 u64 ns;
1619
1620 do {
1621 seq = read_seqcount_begin(&gtod->seq);
1622 mode = gtod->clock.vclock_mode;
1623 ts->tv_sec = gtod->wall_time_sec;
1624 ns = gtod->nsec_base;
1625 ns += vgettsc(cycle_now);
1626 ns >>= gtod->clock.shift;
1627 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1628
1629 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1630 ts->tv_nsec = ns;
1631
1632 return mode;
1633}
1634
d828199e 1635/* returns true if host is using tsc clocksource */
a5a1d1c2 1636static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1637{
d828199e
MT		 1638 /* checked again under seqlock below */
1639 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1640 return false;
1641
cbcf2dd3 1642 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1643}
55dd00a7
MT		 1644
1645/* returns true if host is using tsc clocksource */
1646static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1647 u64 *cycle_now)
1648{
1649 /* checked again under seqlock below */
1650 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1651 return false;
1652
1653 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1654}
d828199e
MT		 1655#endif
1656
1657/*
1658 *
b48aa97e
MT		 1659 * Assuming a stable TSC across physical CPUS, and a stable TSC
1660 * across virtual CPUs, the following condition is possible.
1661 * Each numbered line represents an event visible to both
d828199e
MT		 1662 * CPUs at the next numbered event.
1663 *
1664 * "timespecX" represents host monotonic time. "tscX" represents
1665 * RDTSC value.
1666 *
1667 * VCPU0 on CPU0 | VCPU1 on CPU1
1668 *
1669 * 1. read timespec0,tsc0
1670 * 2. | timespec1 = timespec0 + N
1671 * | tsc1 = tsc0 + M
1672 * 3. transition to guest | transition to guest
1673 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1674 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1675 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1676 *
1677 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1678 *
1679 * - ret0 < ret1
1680 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1681 * ...
1682 * - 0 < N - M => M < N
1683 *
1684 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1685 * always the case (the difference between two distinct xtime instances
1686 * might be smaller then the difference between corresponding TSC reads,
1687 * when updating guest vcpus pvclock areas).
1688 *
1689 * To avoid that problem, do not allow visibility of distinct
1690 * system_timestamp/tsc_timestamp values simultaneously: use a master
1691 * copy of host monotonic time values. Update that master copy
1692 * in lockstep.
1693 *
b48aa97e 1694 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1695 *
1696 */
1697
1698static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1699{
1700#ifdef CONFIG_X86_64
1701 struct kvm_arch *ka = &kvm->arch;
1702 int vclock_mode;
b48aa97e
MT		 1703 bool host_tsc_clocksource, vcpus_matched;
1704
1705 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1706 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1707
1708 /*
1709 * If the host uses TSC clock, then passthrough TSC as stable
1710 * to the guest.
1711 */
b48aa97e 1712 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1713 &ka->master_kernel_ns,
1714 &ka->master_cycle_now);
1715
16a96021 1716 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1717 && !ka->backwards_tsc_observed
54750f2c 1718 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1719
d828199e
MT		 1720 if (ka->use_master_clock)
1721 atomic_set(&kvm_guest_has_master_clock, 1);
1722
1723 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1724 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1725 vcpus_matched);
d828199e
MT		 1726#endif
1727}
1728
2860c4b1
PB		 1729void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1730{
1731 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1732}
1733
2e762ff7
MT		 1734static void kvm_gen_update_masterclock(struct kvm *kvm)
1735{
1736#ifdef CONFIG_X86_64
1737 int i;
1738 struct kvm_vcpu *vcpu;
1739 struct kvm_arch *ka = &kvm->arch;
1740
1741 spin_lock(&ka->pvclock_gtod_sync_lock);
1742 kvm_make_mclock_inprogress_request(kvm);
1743 /* no guest entries from this point */
1744 pvclock_update_vm_gtod_copy(kvm);
1745
1746 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1747 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1748
1749 /* guest entries allowed */
1750 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1751 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1752
1753 spin_unlock(&ka->pvclock_gtod_sync_lock);
1754#endif
1755}
1756
e891a32e 1757u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1758{
108b249c 1759 struct kvm_arch *ka = &kvm->arch;
8b953440 1760 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1761 u64 ret;
108b249c 1762
8b953440
PB		 1763 spin_lock(&ka->pvclock_gtod_sync_lock);
1764 if (!ka->use_master_clock) {
1765 spin_unlock(&ka->pvclock_gtod_sync_lock);
1766 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1767 }
1768
8b953440
PB		 1769 hv_clock.tsc_timestamp = ka->master_cycle_now;
1770 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1771 spin_unlock(&ka->pvclock_gtod_sync_lock);
1772
e2c2206a
WL		 1773 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1774 get_cpu();
1775
8b953440
PB		 1776 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1777 &hv_clock.tsc_shift,
1778 &hv_clock.tsc_to_system_mul);
e2c2206a
WL		 1779 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1780
1781 put_cpu();
1782
1783 return ret;
108b249c
PB		 1784}
1785
0d6dd2ff
PB		 1786static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1787{
1788 struct kvm_vcpu_arch *vcpu = &v->arch;
1789 struct pvclock_vcpu_time_info guest_hv_clock;
1790
4e335d9e 1791 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1792 &guest_hv_clock, sizeof(guest_hv_clock))))
1793 return;
1794
1795 /* This VCPU is paused, but it's legal for a guest to read another
1796 * VCPU's kvmclock, so we really have to follow the specification where
1797 * it says that version is odd if data is being modified, and even after
1798 * it is consistent.
1799 *
1800 * Version field updates must be kept separate. This is because
1801 * kvm_write_guest_cached might use a "rep movs" instruction, and
1802 * writes within a string instruction are weakly ordered. So there
1803 * are three writes overall.
1804 *
1805 * As a small optimization, only write the version field in the first
1806 * and third write. The vcpu->pv_time cache is still valid, because the
1807 * version field is the first in the struct.
1808 */
1809 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1810
1811 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1812 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1813 &vcpu->hv_clock,
1814 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1815
1816 smp_wmb();
1817
1818 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1819 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1820
1821 if (vcpu->pvclock_set_guest_stopped_request) {
1822 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1823 vcpu->pvclock_set_guest_stopped_request = false;
1824 }
1825
1826 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1827
4e335d9e
PB		 1828 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1829 &vcpu->hv_clock,
1830 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1831
1832 smp_wmb();
1833
1834 vcpu->hv_clock.version++;
4e335d9e
PB		 1835 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1838}
1839
34c238a1 1840static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1841{
78db6a50 1842 unsigned long flags, tgt_tsc_khz;
18068523 1843 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1844 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1845 s64 kernel_ns;
d828199e 1846 u64 tsc_timestamp, host_tsc;
51d59c6b 1847 u8 pvclock_flags;
d828199e
MT		 1848 bool use_master_clock;
1849
1850 kernel_ns = 0;
1851 host_tsc = 0;
18068523 1852
d828199e
MT		 1853 /*
1854 * If the host uses TSC clock, then passthrough TSC as stable
1855 * to the guest.
1856 */
1857 spin_lock(&ka->pvclock_gtod_sync_lock);
1858 use_master_clock = ka->use_master_clock;
1859 if (use_master_clock) {
1860 host_tsc = ka->master_cycle_now;
1861 kernel_ns = ka->master_kernel_ns;
1862 }
1863 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1864
1865 /* Keep irq disabled to prevent changes to the clock */
1866 local_irq_save(flags);
78db6a50
PB		 1867 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1868 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1869 local_irq_restore(flags);
1870 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1871 return 1;
1872 }
d828199e 1873 if (!use_master_clock) {
4ea1636b 1874 host_tsc = rdtsc();
108b249c 1875 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1876 }
1877
4ba76538 1878 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1879
c285545f
ZA		 1880 /*
1881 * We may have to catch up the TSC to match elapsed wall clock
1882 * time for two reasons, even if kvmclock is used.
1883 * 1) CPU could have been running below the maximum TSC rate
1884 * 2) Broken TSC compensation resets the base at each VCPU
1885 * entry to avoid unknown leaps of TSC even when running
1886 * again on the same CPU. This may cause apparent elapsed
1887 * time to disappear, and the guest to stand still or run
1888 * very slowly.
1889 */
1890 if (vcpu->tsc_catchup) {
1891 u64 tsc = compute_guest_tsc(v, kernel_ns);
1892 if (tsc > tsc_timestamp) {
f1e2b260 1893 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1894 tsc_timestamp = tsc;
1895 }
50d0a0f9
GH		 1896 }
1897
18068523
GOC		 1898 local_irq_restore(flags);
1899
0d6dd2ff 1900 /* With all the info we got, fill in the values */
18068523 1901
78db6a50
PB		 1902 if (kvm_has_tsc_control)
1903 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1904
1905 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1906 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1907 &vcpu->hv_clock.tsc_shift,
1908 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1909 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1910 }
1911
1d5f066e 1912 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1913 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1914 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1915
d828199e 1916 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1917 pvclock_flags = 0;
d828199e
MT		 1918 if (use_master_clock)
1919 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1920
78c0337a
MT		 1921 vcpu->hv_clock.flags = pvclock_flags;
1922
095cf55d
PB		 1923 if (vcpu->pv_time_enabled)
1924 kvm_setup_pvclock_page(v);
1925 if (v == kvm_get_vcpu(v->kvm, 0))
1926 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1927 return 0;
c8076604
GH		 1928}
1929
0061d53d
MT		 1930/*
1931 * kvmclock updates which are isolated to a given vcpu, such as
1932 * vcpu->cpu migration, should not allow system_timestamp from
1933 * the rest of the vcpus to remain static. Otherwise ntp frequency
1934 * correction applies to one vcpu's system_timestamp but not
1935 * the others.
1936 *
1937 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1938 * We need to rate-limit these requests though, as they can
1939 * considerably slow guests that have a large number of vcpus.
1940 * The time for a remote vcpu to update its kvmclock is bound
1941 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1942 */
1943
7e44e449
AJ		 1944#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1945
1946static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1947{
1948 int i;
7e44e449
AJ		 1949 struct delayed_work *dwork = to_delayed_work(work);
1950 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1951 kvmclock_update_work);
1952 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1953 struct kvm_vcpu *vcpu;
1954
1955 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1956 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1957 kvm_vcpu_kick(vcpu);
1958 }
1959}
1960
7e44e449
AJ		 1961static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1962{
1963 struct kvm *kvm = v->kvm;
1964
105b21bb 1965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1966 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1967 KVMCLOCK_UPDATE_DELAY);
1968}
1969
332967a3
AJ		 1970#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1971
1972static void kvmclock_sync_fn(struct work_struct *work)
1973{
1974 struct delayed_work *dwork = to_delayed_work(work);
1975 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1976 kvmclock_sync_work);
1977 struct kvm *kvm = container_of(ka, struct kvm, arch);
1978
630994b3
MT		 1979 if (!kvmclock_periodic_sync)
1980 return;
1981
332967a3
AJ		 1982 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1983 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1984 KVMCLOCK_SYNC_PERIOD);
1985}
1986
890ca9ae 1987static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1988{
890ca9ae
YH		 1989 u64 mcg_cap = vcpu->arch.mcg_cap;
1990 unsigned bank_num = mcg_cap & 0xff;
1991
15c4a640 1992 switch (msr) {
15c4a640 1993 case MSR_IA32_MCG_STATUS:
890ca9ae 1994 vcpu->arch.mcg_status = data;
15c4a640 1995 break;
c7ac679c 1996 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 1997 if (!(mcg_cap & MCG_CTL_P))
1998 return 1;
1999 if (data != 0 && data != ~(u64)0)
2000 return -1;
2001 vcpu->arch.mcg_ctl = data;
2002 break;
2003 default:
2004 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2005 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2006 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2007 /* only 0 or all 1s can be written to IA32_MCi_CTL
2008 * some Linux kernels though clear bit 10 in bank 4 to
2009 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2010 * this to avoid an uncatched #GP in the guest
2011 */
890ca9ae 2012 if ((offset & 0x3) == 0 &&
114be429 2013 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
YH		 2014 return -1;
2015 vcpu->arch.mce_banks[offset] = data;
2016 break;
2017 }
2018 return 1;
2019 }
2020 return 0;
2021}
2022
ffde22ac
ES		 2023static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2024{
2025 struct kvm *kvm = vcpu->kvm;
2026 int lm = is_long_mode(vcpu);
2027 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2028 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2029 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2030 : kvm->arch.xen_hvm_config.blob_size_32;
2031 u32 page_num = data & ~PAGE_MASK;
2032 u64 page_addr = data & PAGE_MASK;
2033 u8 *page;
2034 int r;
2035
2036 r = -E2BIG;
2037 if (page_num >= blob_size)
2038 goto out;
2039 r = -ENOMEM;
ff5c2c03
SL		 2040 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2041 if (IS_ERR(page)) {
2042 r = PTR_ERR(page);
ffde22ac 2043 goto out;
ff5c2c03 2044 }
54bf36aa 2045 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2046 goto out_free;
2047 r = 0;
2048out_free:
2049 kfree(page);
2050out:
2051 return r;
2052}
2053
344d9588
GN		 2054static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2055{
2056 gpa_t gpa = data & ~0x3f;
2057
52a5c155
WL		 2058 /* Bits 3:5 are reserved, Should be zero */
2059 if (data & 0x38)
344d9588
GN		 2060 return 1;
2061
2062 vcpu->arch.apf.msr_val = data;
2063
2064 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2065 kvm_clear_async_pf_completion_queue(vcpu);
2066 kvm_async_pf_hash_reset(vcpu);
2067 return 0;
2068 }
2069
4e335d9e 2070 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2071 sizeof(u32)))
344d9588
GN		 2072 return 1;
2073
6adba527 2074 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2075 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2076 kvm_async_pf_wakeup_all(vcpu);
2077 return 0;
2078}
2079
12f9a48f
GC		 2080static void kvmclock_reset(struct kvm_vcpu *vcpu)
2081{
0b79459b 2082 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2083}
2084
c9aaa895
GC		 2085static void record_steal_time(struct kvm_vcpu *vcpu)
2086{
2087 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2088 return;
2089
4e335d9e 2090 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2091 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2092 return;
2093
0b9f6c46
PX		 2094 vcpu->arch.st.steal.preempted = 0;
2095
35f3fae1
WL		 2096 if (vcpu->arch.st.steal.version & 1)
2097 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2098
2099 vcpu->arch.st.steal.version += 1;
2100
4e335d9e 2101 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2102 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2103
2104 smp_wmb();
2105
c54cdf14
LC		 2106 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2107 vcpu->arch.st.last_steal;
2108 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2109
4e335d9e 2110 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2111 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2112
2113 smp_wmb();
2114
2115 vcpu->arch.st.steal.version += 1;
c9aaa895 2116
4e335d9e 2117 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2118 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2119}
2120
8fe8ab46 2121int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2122{
5753785f 2123 bool pr = false;
8fe8ab46
WA		 2124 u32 msr = msr_info->index;
2125 u64 data = msr_info->data;
5753785f 2126
15c4a640 2127 switch (msr) {
2e32b719
BP		 2128 case MSR_AMD64_NB_CFG:
2129 case MSR_IA32_UCODE_REV:
2130 case MSR_IA32_UCODE_WRITE:
2131 case MSR_VM_HSAVE_PA:
2132 case MSR_AMD64_PATCH_LOADER:
2133 case MSR_AMD64_BU_CFG2:
405a353a 2134 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2135 break;
2136
15c4a640 2137 case MSR_EFER:
b69e8cae 2138 return set_efer(vcpu, data);
8f1589d9
AP		 2139 case MSR_K7_HWCR:
2140 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2141 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2142 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2143 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2144 if (data != 0) {
a737f256
CD		 2145 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2146 data);
8f1589d9
AP		 2147 return 1;
2148 }
15c4a640 2149 break;
f7c6d140
AP		 2150 case MSR_FAM10H_MMIO_CONF_BASE:
2151 if (data != 0) {
a737f256
CD		 2152 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2153 "0x%llx\n", data);
f7c6d140
AP		 2154 return 1;
2155 }
15c4a640 2156 break;
b5e2fec0
AG		 2157 case MSR_IA32_DEBUGCTLMSR:
2158 if (!data) {
2159 /* We support the non-activated case already */
2160 break;
2161 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2162 /* Values other than LBR and BTF are vendor-specific,
2163 thus reserved and should throw a #GP */
2164 return 1;
2165 }
a737f256
CD		 2166 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2167 __func__, data);
b5e2fec0 2168 break;
9ba075a6 2169 case 0x200 ... 0x2ff:
ff53604b 2170 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2171 case MSR_IA32_APICBASE:
58cb628d 2172 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2173 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2174 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2175 case MSR_IA32_TSCDEADLINE:
2176 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2177 break;
ba904635 2178 case MSR_IA32_TSC_ADJUST:
d6321d49 2179 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2180 if (!msr_info->host_initiated) {
d913b904 2181 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2182 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2183 }
2184 vcpu->arch.ia32_tsc_adjust_msr = data;
2185 }
2186 break;
15c4a640 2187 case MSR_IA32_MISC_ENABLE:
ad312c7c 2188 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2189 break;
64d60670
PB		 2190 case MSR_IA32_SMBASE:
2191 if (!msr_info->host_initiated)
2192 return 1;
2193 vcpu->arch.smbase = data;
2194 break;
11c6bffa 2195 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2196 case MSR_KVM_WALL_CLOCK:
2197 vcpu->kvm->arch.wall_clock = data;
2198 kvm_write_wall_clock(vcpu->kvm, data);
2199 break;
11c6bffa 2200 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2201 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2202 struct kvm_arch *ka = &vcpu->kvm->arch;
2203
12f9a48f 2204 kvmclock_reset(vcpu);
18068523 2205
54750f2c
MT		 2206 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2207 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2208
2209 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2210 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2211
2212 ka->boot_vcpu_runs_old_kvmclock = tmp;
2213 }
2214
18068523 2215 vcpu->arch.time = data;
0061d53d 2216 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2217
2218 /* we verify if the enable bit is set... */
2219 if (!(data & 1))
2220 break;
2221
4e335d9e 2222 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2223 &vcpu->arch.pv_time, data & ~1ULL,
2224 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2225 vcpu->arch.pv_time_enabled = false;
2226 else
2227 vcpu->arch.pv_time_enabled = true;
32cad84f 2228
18068523
GOC		 2229 break;
2230 }
344d9588
GN		 2231 case MSR_KVM_ASYNC_PF_EN:
2232 if (kvm_pv_enable_async_pf(vcpu, data))
2233 return 1;
2234 break;
c9aaa895
GC		 2235 case MSR_KVM_STEAL_TIME:
2236
2237 if (unlikely(!sched_info_on()))
2238 return 1;
2239
2240 if (data & KVM_STEAL_RESERVED_MASK)
2241 return 1;
2242
4e335d9e 2243 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2244 data & KVM_STEAL_VALID_BITS,
2245 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2246 return 1;
2247
2248 vcpu->arch.st.msr_val = data;
2249
2250 if (!(data & KVM_MSR_ENABLED))
2251 break;
2252
c9aaa895
GC		 2253 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2254
2255 break;
ae7a2a3f
MT		 2256 case MSR_KVM_PV_EOI_EN:
2257 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2258 return 1;
2259 break;
c9aaa895 2260
890ca9ae
YH		 2261 case MSR_IA32_MCG_CTL:
2262 case MSR_IA32_MCG_STATUS:
81760dcc 2263 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2264 return set_msr_mce(vcpu, msr, data);
71db6023 2265
6912ac32
WH		 2266 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2267 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2268 pr = true; /* fall through */
2269 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2270 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2271 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2272 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2273
2274 if (pr || data != 0)
a737f256
CD		 2275 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2276 "0x%x data 0x%llx\n", msr, data);
5753785f 2277 break;
84e0cefa
JS		 2278 case MSR_K7_CLK_CTL:
2279 /*
2280 * Ignore all writes to this no longer documented MSR.
2281 * Writes are only relevant for old K7 processors,
2282 * all pre-dating SVM, but a recommended workaround from
4a969980 2283 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2284 * affected processor models on the command line, hence
2285 * the need to ignore the workaround.
2286 */
2287 break;
55cd8e5a 2288 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2289 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2290 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2291 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2292 return kvm_hv_set_msr_common(vcpu, msr, data,
2293 msr_info->host_initiated);
91c9c3ed 2294 case MSR_IA32_BBL_CR_CTL3:
2295 /* Drop writes to this legacy MSR -- see rdmsr
2296 * counterpart for further detail.
2297 */
796f4687 2298 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2299 break;
2b036c6b 2300 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2301 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2302 return 1;
2303 vcpu->arch.osvw.length = data;
2304 break;
2305 case MSR_AMD64_OSVW_STATUS:
d6321d49 2306 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2307 return 1;
2308 vcpu->arch.osvw.status = data;
2309 break;
db2336a8
KH		 2310 case MSR_PLATFORM_INFO:
2311 if (!msr_info->host_initiated ||
2312 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2313 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2314 cpuid_fault_enabled(vcpu)))
2315 return 1;
2316 vcpu->arch.msr_platform_info = data;
2317 break;
2318 case MSR_MISC_FEATURES_ENABLES:
2319 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2320 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2321 !supports_cpuid_fault(vcpu)))
2322 return 1;
2323 vcpu->arch.msr_misc_features_enables = data;
2324 break;
15c4a640 2325 default:
ffde22ac
ES		 2326 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2327 return xen_hvm_config(vcpu, data);
c6702c9d 2328 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2329 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2330 if (!ignore_msrs) {
ae0f5499 2331 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2332 msr, data);
ed85c068
AP		 2333 return 1;
2334 } else {
796f4687 2335 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2336 msr, data);
ed85c068
AP		 2337 break;
2338 }
15c4a640
CO		 2339 }
2340 return 0;
2341}
2342EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2343
2344
2345/*
2346 * Reads an msr value (of 'msr_index') into 'pdata'.
2347 * Returns 0 on success, non-0 otherwise.
2348 * Assumes vcpu_load() was already called.
2349 */
609e36d3 2350int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2351{
609e36d3 2352 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2353}
ff651cb6 2354EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2355
890ca9ae 2356static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2357{
2358 u64 data;
890ca9ae
YH		 2359 u64 mcg_cap = vcpu->arch.mcg_cap;
2360 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2361
2362 switch (msr) {
15c4a640
CO		 2363 case MSR_IA32_P5_MC_ADDR:
2364 case MSR_IA32_P5_MC_TYPE:
890ca9ae
YH		 2365 data = 0;
2366 break;
15c4a640 2367 case MSR_IA32_MCG_CAP:
890ca9ae
YH		 2368 data = vcpu->arch.mcg_cap;
2369 break;
c7ac679c 2370 case MSR_IA32_MCG_CTL:
890ca9ae
YH		 2371 if (!(mcg_cap & MCG_CTL_P))
2372 return 1;
2373 data = vcpu->arch.mcg_ctl;
2374 break;
2375 case MSR_IA32_MCG_STATUS:
2376 data = vcpu->arch.mcg_status;
2377 break;
2378 default:
2379 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2380 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
YH		 2381 u32 offset = msr - MSR_IA32_MC0_CTL;
2382 data = vcpu->arch.mce_banks[offset];
2383 break;
2384 }
2385 return 1;
2386 }
2387 *pdata = data;
2388 return 0;
2389}
2390
609e36d3 2391int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2392{
609e36d3 2393 switch (msr_info->index) {
890ca9ae 2394 case MSR_IA32_PLATFORM_ID:
15c4a640 2395 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2396 case MSR_IA32_DEBUGCTLMSR:
2397 case MSR_IA32_LASTBRANCHFROMIP:
2398 case MSR_IA32_LASTBRANCHTOIP:
2399 case MSR_IA32_LASTINTFROMIP:
2400 case MSR_IA32_LASTINTTOIP:
60af2ecd 2401 case MSR_K8_SYSCFG:
3afb1121
PB		 2402 case MSR_K8_TSEG_ADDR:
2403 case MSR_K8_TSEG_MASK:
60af2ecd 2404 case MSR_K7_HWCR:
61a6bd67 2405 case MSR_VM_HSAVE_PA:
1fdbd48c 2406 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2407 case MSR_AMD64_NB_CFG:
f7c6d140 2408 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2409 case MSR_AMD64_BU_CFG2:
0c2df2a1 2410 case MSR_IA32_PERF_CTL:
405a353a 2411 case MSR_AMD64_DC_CFG:
609e36d3 2412 msr_info->data = 0;
15c4a640 2413 break;
6912ac32
WH		 2414 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2415 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2416 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2417 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2418 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2419 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2420 msr_info->data = 0;
5753785f 2421 break;
742bc670 2422 case MSR_IA32_UCODE_REV:
609e36d3 2423 msr_info->data = 0x100000000ULL;
742bc670 2424 break;
9ba075a6 2425 case MSR_MTRRcap:
9ba075a6 2426 case 0x200 ... 0x2ff:
ff53604b 2427 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2428 case 0xcd: /* fsb frequency */
609e36d3 2429 msr_info->data = 3;
15c4a640 2430 break;
7b914098
JS		 2431 /*
2432 * MSR_EBC_FREQUENCY_ID
2433 * Conservative value valid for even the basic CPU models.
2434 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2435 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2436 * and 266MHz for model 3, or 4. Set Core Clock
2437 * Frequency to System Bus Frequency Ratio to 1 (bits
2438 * 31:24) even though these are only valid for CPU
2439 * models > 2, however guests may end up dividing or
2440 * multiplying by zero otherwise.
2441 */
2442 case MSR_EBC_FREQUENCY_ID:
609e36d3 2443 msr_info->data = 1 << 24;
7b914098 2444 break;
15c4a640 2445 case MSR_IA32_APICBASE:
609e36d3 2446 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2447 break;
0105d1a5 2448 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2449 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2450 break;
a3e06bbe 2451 case MSR_IA32_TSCDEADLINE:
609e36d3 2452 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2453 break;
ba904635 2454 case MSR_IA32_TSC_ADJUST:
609e36d3 2455 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2456 break;
15c4a640 2457 case MSR_IA32_MISC_ENABLE:
609e36d3 2458 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2459 break;
64d60670
PB		 2460 case MSR_IA32_SMBASE:
2461 if (!msr_info->host_initiated)
2462 return 1;
2463 msr_info->data = vcpu->arch.smbase;
15c4a640 2464 break;
847f0ad8
AG		 2465 case MSR_IA32_PERF_STATUS:
2466 /* TSC increment by tick */
609e36d3 2467 msr_info->data = 1000ULL;
847f0ad8 2468 /* CPU multiplier */
b0996ae4 2469 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2470 break;
15c4a640 2471 case MSR_EFER:
609e36d3 2472 msr_info->data = vcpu->arch.efer;
15c4a640 2473 break;
18068523 2474 case MSR_KVM_WALL_CLOCK:
11c6bffa 2475 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2476 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2477 break;
2478 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2479 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2480 msr_info->data = vcpu->arch.time;
18068523 2481 break;
344d9588 2482 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2483 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2484 break;
c9aaa895 2485 case MSR_KVM_STEAL_TIME:
609e36d3 2486 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2487 break;
1d92128f 2488 case MSR_KVM_PV_EOI_EN:
609e36d3 2489 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2490 break;
890ca9ae
YH		 2491 case MSR_IA32_P5_MC_ADDR:
2492 case MSR_IA32_P5_MC_TYPE:
2493 case MSR_IA32_MCG_CAP:
2494 case MSR_IA32_MCG_CTL:
2495 case MSR_IA32_MCG_STATUS:
81760dcc 2496 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2497 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2498 case MSR_K7_CLK_CTL:
2499 /*
2500 * Provide expected ramp-up count for K7. All other
2501 * are set to zero, indicating minimum divisors for
2502 * every field.
2503 *
2504 * This prevents guest kernels on AMD host with CPU
2505 * type 6, model 8 and higher from exploding due to
2506 * the rdmsr failing.
2507 */
609e36d3 2508 msr_info->data = 0x20000000;
84e0cefa 2509 break;
55cd8e5a 2510 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2511 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2512 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2513 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2514 return kvm_hv_get_msr_common(vcpu,
2515 msr_info->index, &msr_info->data);
55cd8e5a 2516 break;
91c9c3ed 2517 case MSR_IA32_BBL_CR_CTL3:
2518 /* This legacy MSR exists but isn't fully documented in current
2519 * silicon. It is however accessed by winxp in very narrow
2520 * scenarios where it sets bit #19, itself documented as
2521 * a "reserved" bit. Best effort attempt to source coherent
2522 * read data here should the balance of the register be
2523 * interpreted by the guest:
2524 *
2525 * L2 cache control register 3: 64GB range, 256KB size,
2526 * enabled, latency 0x1, configured
2527 */
609e36d3 2528 msr_info->data = 0xbe702111;
91c9c3ed 2529 break;
2b036c6b 2530 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2531 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2532 return 1;
609e36d3 2533 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2534 break;
2535 case MSR_AMD64_OSVW_STATUS:
d6321d49 2536 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2537 return 1;
609e36d3 2538 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2539 break;
db2336a8
KH		 2540 case MSR_PLATFORM_INFO:
2541 msr_info->data = vcpu->arch.msr_platform_info;
2542 break;
2543 case MSR_MISC_FEATURES_ENABLES:
2544 msr_info->data = vcpu->arch.msr_misc_features_enables;
2545 break;
15c4a640 2546 default:
c6702c9d 2547 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2548 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2549 if (!ignore_msrs) {
ae0f5499
BD		 2550 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2551 msr_info->index);
ed85c068
AP		 2552 return 1;
2553 } else {
609e36d3
PB		 2554 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2555 msr_info->data = 0;
ed85c068
AP		 2556 }
2557 break;
15c4a640 2558 }
15c4a640
CO		 2559 return 0;
2560}
2561EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2562
313a3dc7
CO		 2563/*
2564 * Read or write a bunch of msrs. All parameters are kernel addresses.
2565 *
2566 * @return number of msrs set successfully.
2567 */
2568static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2569 struct kvm_msr_entry *entries,
2570 int (*do_msr)(struct kvm_vcpu *vcpu,
2571 unsigned index, u64 *data))
2572{
f656ce01 2573 int i, idx;
313a3dc7 2574
f656ce01 2575 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2576 for (i = 0; i < msrs->nmsrs; ++i)
2577 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2578 break;
f656ce01 2579 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2580
313a3dc7
CO		 2581 return i;
2582}
2583
2584/*
2585 * Read or write a bunch of msrs. Parameters are user addresses.
2586 *
2587 * @return number of msrs set successfully.
2588 */
2589static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2590 int (*do_msr)(struct kvm_vcpu *vcpu,
2591 unsigned index, u64 *data),
2592 int writeback)
2593{
2594 struct kvm_msrs msrs;
2595 struct kvm_msr_entry *entries;
2596 int r, n;
2597 unsigned size;
2598
2599 r = -EFAULT;
2600 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2601 goto out;
2602
2603 r = -E2BIG;
2604 if (msrs.nmsrs >= MAX_IO_MSRS)
2605 goto out;
2606
313a3dc7 2607 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2608 entries = memdup_user(user_msrs->entries, size);
2609 if (IS_ERR(entries)) {
2610 r = PTR_ERR(entries);
313a3dc7 2611 goto out;
ff5c2c03 2612 }
313a3dc7
CO		 2613
2614 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2615 if (r < 0)
2616 goto out_free;
2617
2618 r = -EFAULT;
2619 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2620 goto out_free;
2621
2622 r = n;
2623
2624out_free:
7a73c028 2625 kfree(entries);
313a3dc7
CO		 2626out:
2627 return r;
2628}
2629
784aa3d7 2630int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2631{
2632 int r;
2633
2634 switch (ext) {
2635 case KVM_CAP_IRQCHIP:
2636 case KVM_CAP_HLT:
2637 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2638 case KVM_CAP_SET_TSS_ADDR:
07716717 2639 case KVM_CAP_EXT_CPUID:
9c15bb1d 2640 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2641 case KVM_CAP_CLOCKSOURCE:
7837699f 2642 case KVM_CAP_PIT:
a28e4f5a 2643 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2644 case KVM_CAP_MP_STATE:
ed848624 2645 case KVM_CAP_SYNC_MMU:
a355c85c 2646 case KVM_CAP_USER_NMI:
52d939a0 2647 case KVM_CAP_REINJECT_CONTROL:
4925663a 2648 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2649 case KVM_CAP_IOEVENTFD:
f848a5a8 2650 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2651 case KVM_CAP_PIT2:
e9f42757 2652 case KVM_CAP_PIT_STATE2:
b927a3ce 2653 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2654 case KVM_CAP_XEN_HVM:
3cfc3092 2655 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2656 case KVM_CAP_HYPERV:
10388a07 2657 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2658 case KVM_CAP_HYPERV_SPIN:
5c919412 2659 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2660 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2661 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2662 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2663 case KVM_CAP_DEBUGREGS:
d2be1651 2664 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2665 case KVM_CAP_XSAVE:
344d9588 2666 case KVM_CAP_ASYNC_PF:
92a1f12d 2667 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2668 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2669 case KVM_CAP_READONLY_MEM:
5f66b620 2670 case KVM_CAP_HYPERV_TIME:
100943c5 2671 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2672 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2673 case KVM_CAP_ENABLE_CAP_VM:
2674 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2675 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2676 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2677 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2678 r = 1;
2679 break;
e3fd9a93
PB		 2680 case KVM_CAP_ADJUST_CLOCK:
2681 r = KVM_CLOCK_TSC_STABLE;
2682 break;
668fffa3
MT		 2683 case KVM_CAP_X86_GUEST_MWAIT:
2684 r = kvm_mwait_in_guest();
2685 break;
6d396b55
PB		 2686 case KVM_CAP_X86_SMM:
2687 /* SMBASE is usually relocated above 1M on modern chipsets,
2688 * and SMM handlers might indeed rely on 4G segment limits,
2689 * so do not report SMM to be available if real mode is
2690 * emulated via vm86 mode. Still, do not go to great lengths
2691 * to avoid userspace's usage of the feature, because it is a
2692 * fringe case that is not enabled except via specific settings
2693 * of the module parameters.
2694 */
2695 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2696 break;
774ead3a
AK		 2697 case KVM_CAP_VAPIC:
2698 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2699 break;
f725230a 2700 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2701 r = KVM_SOFT_MAX_VCPUS;
2702 break;
2703 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2704 r = KVM_MAX_VCPUS;
2705 break;
a988b910 2706 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2707 r = KVM_USER_MEM_SLOTS;
a988b910 2708 break;
a68a6a72
MT		 2709 case KVM_CAP_PV_MMU: /* obsolete */
2710 r = 0;
2f333bcb 2711 break;
890ca9ae
YH		 2712 case KVM_CAP_MCE:
2713 r = KVM_MAX_MCE_BANKS;
2714 break;
2d5b5a66 2715 case KVM_CAP_XCRS:
d366bf7e 2716 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2717 break;
92a1f12d
JR		 2718 case KVM_CAP_TSC_CONTROL:
2719 r = kvm_has_tsc_control;
2720 break;
37131313
RK		 2721 case KVM_CAP_X2APIC_API:
2722 r = KVM_X2APIC_API_VALID_FLAGS;
2723 break;
018d00d2
ZX		 2724 default:
2725 r = 0;
2726 break;
2727 }
2728 return r;
2729
2730}
2731
043405e1
CO		 2732long kvm_arch_dev_ioctl(struct file *filp,
2733 unsigned int ioctl, unsigned long arg)
2734{
2735 void __user *argp = (void __user *)arg;
2736 long r;
2737
2738 switch (ioctl) {
2739 case KVM_GET_MSR_INDEX_LIST: {
2740 struct kvm_msr_list __user *user_msr_list = argp;
2741 struct kvm_msr_list msr_list;
2742 unsigned n;
2743
2744 r = -EFAULT;
2745 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2746 goto out;
2747 n = msr_list.nmsrs;
62ef68bb 2748 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2749 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2750 goto out;
2751 r = -E2BIG;
e125e7b6 2752 if (n < msr_list.nmsrs)
043405e1
CO		 2753 goto out;
2754 r = -EFAULT;
2755 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2756 num_msrs_to_save * sizeof(u32)))
2757 goto out;
e125e7b6 2758 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2759 &emulated_msrs,
62ef68bb 2760 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2761 goto out;
2762 r = 0;
2763 break;
2764 }
9c15bb1d
BP		 2765 case KVM_GET_SUPPORTED_CPUID:
2766 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2767 struct kvm_cpuid2 __user *cpuid_arg = argp;
2768 struct kvm_cpuid2 cpuid;
2769
2770 r = -EFAULT;
2771 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2772 goto out;
9c15bb1d
BP		 2773
2774 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2775 ioctl);
674eea0f
AK		 2776 if (r)
2777 goto out;
2778
2779 r = -EFAULT;
2780 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2781 goto out;
2782 r = 0;
2783 break;
2784 }
890ca9ae 2785 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2786 r = -EFAULT;
c45dcc71
AR		 2787 if (copy_to_user(argp, &kvm_mce_cap_supported,
2788 sizeof(kvm_mce_cap_supported)))
890ca9ae
YH		 2789 goto out;
2790 r = 0;
2791 break;
2792 }
043405e1
CO		 2793 default:
2794 r = -EINVAL;
2795 }
2796out:
2797 return r;
2798}
2799
f5f48ee1
SY		 2800static void wbinvd_ipi(void *garbage)
2801{
2802 wbinvd();
2803}
2804
2805static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2806{
e0f0bbc5 2807 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2808}
2809
313a3dc7
CO		 2810void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2811{
f5f48ee1
SY		 2812 /* Address WBINVD may be executed by guest */
2813 if (need_emulate_wbinvd(vcpu)) {
2814 if (kvm_x86_ops->has_wbinvd_exit())
2815 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2816 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2817 smp_call_function_single(vcpu->cpu,
2818 wbinvd_ipi, NULL, 1);
2819 }
2820
313a3dc7 2821 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2822
0dd6a6ed
ZA		 2823 /* Apply any externally detected TSC adjustments (due to suspend) */
2824 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2825 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2826 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2827 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2828 }
8f6055cb 2829
48434c20 2830 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2831 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2832 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2833 if (tsc_delta < 0)
2834 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2835
c285545f 2836 if (check_tsc_unstable()) {
07c1419a 2837 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2838 vcpu->arch.last_guest_tsc);
a545ab6a 2839 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2840 vcpu->arch.tsc_catchup = 1;
c285545f 2841 }
a749e247
PB		 2842
2843 if (kvm_lapic_hv_timer_in_use(vcpu))
2844 kvm_lapic_restart_hv_timer(vcpu);
2845
d98d07ca
MT		 2846 /*
2847 * On a host with synchronized TSC, there is no need to update
2848 * kvmclock on vcpu->cpu migration
2849 */
2850 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2851 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2852 if (vcpu->cpu != cpu)
1bd2009e 2853 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2854 vcpu->cpu = cpu;
6b7d7e76 2855 }
c9aaa895 2856
c9aaa895 2857 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2858}
2859
0b9f6c46
PX		 2860static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2861{
2862 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2863 return;
2864
2865 vcpu->arch.st.steal.preempted = 1;
2866
4e335d9e 2867 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2868 &vcpu->arch.st.steal.preempted,
2869 offsetof(struct kvm_steal_time, preempted),
2870 sizeof(vcpu->arch.st.steal.preempted));
2871}
2872
313a3dc7
CO		 2873void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2874{
cc0d907c 2875 int idx;
de63ad4c
LM		 2876
2877 if (vcpu->preempted)
2878 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2879
931f261b
AA		 2880 /*
2881 * Disable page faults because we're in atomic context here.
2882 * kvm_write_guest_offset_cached() would call might_fault()
2883 * that relies on pagefault_disable() to tell if there's a
2884 * bug. NOTE: the write to guest memory may not go through if
2885 * during postcopy live migration or if there's heavy guest
2886 * paging.
2887 */
2888 pagefault_disable();
cc0d907c
AA		 2889 /*
2890 * kvm_memslots() will be called by
2891 * kvm_write_guest_offset_cached() so take the srcu lock.
2892 */
2893 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2894 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2895 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2896 pagefault_enable();
02daab21 2897 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2898 kvm_put_guest_fpu(vcpu);
4ea1636b 2899 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2900}
2901
313a3dc7
CO		 2902static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2903 struct kvm_lapic_state *s)
2904{
76dfafd5 2905 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2906 kvm_x86_ops->sync_pir_to_irr(vcpu);
2907
a92e2543 2908 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2909}
2910
2911static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2912 struct kvm_lapic_state *s)
2913{
a92e2543
RK		 2914 int r;
2915
2916 r = kvm_apic_set_state(vcpu, s);
2917 if (r)
2918 return r;
cb142eb7 2919 update_cr8_intercept(vcpu);
313a3dc7
CO		 2920
2921 return 0;
2922}
2923
127a457a
MG		 2924static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2925{
2926 return (!lapic_in_kernel(vcpu) ||
2927 kvm_apic_accept_pic_intr(vcpu));
2928}
2929
782d422b
MG		 2930/*
2931 * if userspace requested an interrupt window, check that the
2932 * interrupt window is open.
2933 *
2934 * No need to exit to userspace if we already have an interrupt queued.
2935 */
2936static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2937{
2938 return kvm_arch_interrupt_allowed(vcpu) &&
2939 !kvm_cpu_has_interrupt(vcpu) &&
2940 !kvm_event_needs_reinjection(vcpu) &&
2941 kvm_cpu_accept_dm_intr(vcpu);
2942}
2943
f77bc6a4
ZX		 2944static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2945 struct kvm_interrupt *irq)
2946{
02cdb50f 2947 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2948 return -EINVAL;
1c1a9ce9
SR		 2949
2950 if (!irqchip_in_kernel(vcpu->kvm)) {
2951 kvm_queue_interrupt(vcpu, irq->irq, false);
2952 kvm_make_request(KVM_REQ_EVENT, vcpu);
2953 return 0;
2954 }
2955
2956 /*
2957 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2958 * fail for in-kernel 8259.
2959 */
2960 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2961 return -ENXIO;
f77bc6a4 2962
1c1a9ce9
SR		 2963 if (vcpu->arch.pending_external_vector != -1)
2964 return -EEXIST;
f77bc6a4 2965
1c1a9ce9 2966 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2967 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2968 return 0;
2969}
2970
c4abb7c9
JK		 2971static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2972{
c4abb7c9 2973 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2974
2975 return 0;
2976}
2977
f077825a
PB		 2978static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2979{
64d60670
PB		 2980 kvm_make_request(KVM_REQ_SMI, vcpu);
2981
f077825a
PB		 2982 return 0;
2983}
2984
b209749f
AK		 2985static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2986 struct kvm_tpr_access_ctl *tac)
2987{
2988 if (tac->flags)
2989 return -EINVAL;
2990 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2991 return 0;
2992}
2993
890ca9ae
YH		 2994static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2995 u64 mcg_cap)
2996{
2997 int r;
2998 unsigned bank_num = mcg_cap & 0xff, bank;
2999
3000 r = -EINVAL;
a9e38c3e 3001 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3002 goto out;
c45dcc71 3003 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
YH		 3004 goto out;
3005 r = 0;
3006 vcpu->arch.mcg_cap = mcg_cap;
3007 /* Init IA32_MCG_CTL to all 1s */
3008 if (mcg_cap & MCG_CTL_P)
3009 vcpu->arch.mcg_ctl = ~(u64)0;
3010 /* Init IA32_MCi_CTL to all 1s */
3011 for (bank = 0; bank < bank_num; bank++)
3012 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3013
3014 if (kvm_x86_ops->setup_mce)
3015 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
YH		 3016out:
3017 return r;
3018}
3019
3020static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3021 struct kvm_x86_mce *mce)
3022{
3023 u64 mcg_cap = vcpu->arch.mcg_cap;
3024 unsigned bank_num = mcg_cap & 0xff;
3025 u64 *banks = vcpu->arch.mce_banks;
3026
3027 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3028 return -EINVAL;
3029 /*
3030 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3031 * reporting is disabled
3032 */
3033 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3034 vcpu->arch.mcg_ctl != ~(u64)0)
3035 return 0;
3036 banks += 4 * mce->bank;
3037 /*
3038 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3039 * reporting is disabled for the bank
3040 */
3041 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3042 return 0;
3043 if (mce->status & MCI_STATUS_UC) {
3044 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3045 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3046 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
YH		 3047 return 0;
3048 }
3049 if (banks[1] & MCI_STATUS_VAL)
3050 mce->status |= MCI_STATUS_OVER;
3051 banks[2] = mce->addr;
3052 banks[3] = mce->misc;
3053 vcpu->arch.mcg_status = mce->mcg_status;
3054 banks[1] = mce->status;
3055 kvm_queue_exception(vcpu, MC_VECTOR);
3056 } else if (!(banks[1] & MCI_STATUS_VAL)
3057 || !(banks[1] & MCI_STATUS_UC)) {
3058 if (banks[1] & MCI_STATUS_VAL)
3059 mce->status |= MCI_STATUS_OVER;
3060 banks[2] = mce->addr;
3061 banks[3] = mce->misc;
3062 banks[1] = mce->status;
3063 } else
3064 banks[1] |= MCI_STATUS_OVER;
3065 return 0;
3066}
3067
3cfc3092
JK		 3068static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3069 struct kvm_vcpu_events *events)
3070{
7460fb4a 3071 process_nmi(vcpu);
03b82a30
JK		 3072 events->exception.injected =
3073 vcpu->arch.exception.pending &&
3074 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3075 events->exception.nr = vcpu->arch.exception.nr;
3076 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3077 events->exception.pad = 0;
3cfc3092
JK		 3078 events->exception.error_code = vcpu->arch.exception.error_code;
3079
03b82a30
JK		 3080 events->interrupt.injected =
3081 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3082 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3083 events->interrupt.soft = 0;
37ccdcbe 3084 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3085
3086 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3087 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3088 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3089 events->nmi.pad = 0;
3cfc3092 3090
66450a21 3091 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3092
f077825a
PB		 3093 events->smi.smm = is_smm(vcpu);
3094 events->smi.pending = vcpu->arch.smi_pending;
3095 events->smi.smm_inside_nmi =
3096 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3097 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3098
dab4b911 3099 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3100 | KVM_VCPUEVENT_VALID_SHADOW
3101 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3102 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3103}
3104
6ef4e07e
XG		 3105static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3106
3cfc3092
JK		 3107static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3108 struct kvm_vcpu_events *events)
3109{
dab4b911 3110 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3111 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3112 | KVM_VCPUEVENT_VALID_SHADOW
3113 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3114 return -EINVAL;
3115
78e546c8 3116 if (events->exception.injected &&
28d06353
JM		 3117 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3118 is_guest_mode(vcpu)))
78e546c8
PB		 3119 return -EINVAL;
3120
28bf2888
DH		 3121 /* INITs are latched while in SMM */
3122 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3123 (events->smi.smm || events->smi.pending) &&
3124 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3125 return -EINVAL;
3126
7460fb4a 3127 process_nmi(vcpu);
3cfc3092
JK		 3128 vcpu->arch.exception.pending = events->exception.injected;
3129 vcpu->arch.exception.nr = events->exception.nr;
3130 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3131 vcpu->arch.exception.error_code = events->exception.error_code;
3132
3133 vcpu->arch.interrupt.pending = events->interrupt.injected;
3134 vcpu->arch.interrupt.nr = events->interrupt.nr;
3135 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3136 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3137 kvm_x86_ops->set_interrupt_shadow(vcpu,
3138 events->interrupt.shadow);
3cfc3092
JK		 3139
3140 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3141 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3142 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3143 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3144
66450a21 3145 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3146 lapic_in_kernel(vcpu))
66450a21 3147 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3148
f077825a 3149 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3150 u32 hflags = vcpu->arch.hflags;
f077825a 3151 if (events->smi.smm)
6ef4e07e 3152 hflags |= HF_SMM_MASK;
f077825a 3153 else
6ef4e07e
XG		 3154 hflags &= ~HF_SMM_MASK;
3155 kvm_set_hflags(vcpu, hflags);
3156
f077825a 3157 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3158
3159 if (events->smi.smm) {
3160 if (events->smi.smm_inside_nmi)
3161 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3162 else
f4ef1910
WL		 3163 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3164 if (lapic_in_kernel(vcpu)) {
3165 if (events->smi.latched_init)
3166 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3167 else
3168 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3169 }
f077825a
PB		 3170 }
3171 }
3172
3842d135
AK		 3173 kvm_make_request(KVM_REQ_EVENT, vcpu);
3174
3cfc3092
JK		 3175 return 0;
3176}
3177
a1efbe77
JK		 3178static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3179 struct kvm_debugregs *dbgregs)
3180{
73aaf249
JK		 3181 unsigned long val;
3182
a1efbe77 3183 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3184 kvm_get_dr(vcpu, 6, &val);
73aaf249 3185 dbgregs->dr6 = val;
a1efbe77
JK		 3186 dbgregs->dr7 = vcpu->arch.dr7;
3187 dbgregs->flags = 0;
97e69aa6 3188 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3189}
3190
3191static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3192 struct kvm_debugregs *dbgregs)
3193{
3194 if (dbgregs->flags)
3195 return -EINVAL;
3196
d14bdb55
PB		 3197 if (dbgregs->dr6 & ~0xffffffffull)
3198 return -EINVAL;
3199 if (dbgregs->dr7 & ~0xffffffffull)
3200 return -EINVAL;
3201
a1efbe77 3202 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3203 kvm_update_dr0123(vcpu);
a1efbe77 3204 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3205 kvm_update_dr6(vcpu);
a1efbe77 3206 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3207 kvm_update_dr7(vcpu);
a1efbe77 3208
a1efbe77
JK		 3209 return 0;
3210}
3211
df1daba7
PB		 3212#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3213
3214static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3215{
c47ada30 3216 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3217 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3218 u64 valid;
3219
3220 /*
3221 * Copy legacy XSAVE area, to avoid complications with CPUID
3222 * leaves 0 and 1 in the loop below.
3223 */
3224 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3225
3226 /* Set XSTATE_BV */
00c87e9a 3227 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3228 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3229
3230 /*
3231 * Copy each region from the possibly compacted offset to the
3232 * non-compacted offset.
3233 */
d91cab78 3234 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3235 while (valid) {
3236 u64 feature = valid & -valid;
3237 int index = fls64(feature) - 1;
3238 void *src = get_xsave_addr(xsave, feature);
3239
3240 if (src) {
3241 u32 size, offset, ecx, edx;
3242 cpuid_count(XSTATE_CPUID, index,
3243 &size, &offset, &ecx, &edx);
3244 memcpy(dest + offset, src, size);
3245 }
3246
3247 valid -= feature;
3248 }
3249}
3250
3251static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3252{
c47ada30 3253 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3254 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3255 u64 valid;
3256
3257 /*
3258 * Copy legacy XSAVE area, to avoid complications with CPUID
3259 * leaves 0 and 1 in the loop below.
3260 */
3261 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3262
3263 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3264 xsave->header.xfeatures = xstate_bv;
782511b0 3265 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3266 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3267
3268 /*
3269 * Copy each region from the non-compacted offset to the
3270 * possibly compacted offset.
3271 */
d91cab78 3272 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3273 while (valid) {
3274 u64 feature = valid & -valid;
3275 int index = fls64(feature) - 1;
3276 void *dest = get_xsave_addr(xsave, feature);
3277
3278 if (dest) {
3279 u32 size, offset, ecx, edx;
3280 cpuid_count(XSTATE_CPUID, index,
3281 &size, &offset, &ecx, &edx);
3282 memcpy(dest, src + offset, size);
ee4100da 3283 }
df1daba7
PB		 3284
3285 valid -= feature;
3286 }
3287}
3288
2d5b5a66
SY		 3289static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3290 struct kvm_xsave *guest_xsave)
3291{
d366bf7e 3292 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3293 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3294 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3295 } else {
2d5b5a66 3296 memcpy(guest_xsave->region,
7366ed77 3297 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3298 sizeof(struct fxregs_state));
2d5b5a66 3299 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3300 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3301 }
3302}
3303
a575813b
WL		 3304#define XSAVE_MXCSR_OFFSET 24
3305
2d5b5a66
SY		 3306static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3307 struct kvm_xsave *guest_xsave)
3308{
3309 u64 xstate_bv =
3310 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3311 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3312
d366bf7e 3313 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3314 /*
3315 * Here we allow setting states that are not present in
3316 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3317 * with old userspace.
3318 */
a575813b
WL		 3319 if (xstate_bv & ~kvm_supported_xcr0() ||
3320 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3321 return -EINVAL;
df1daba7 3322 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3323 } else {
a575813b
WL		 3324 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3325 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3326 return -EINVAL;
7366ed77 3327 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3328 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3329 }
3330 return 0;
3331}
3332
3333static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3334 struct kvm_xcrs *guest_xcrs)
3335{
d366bf7e 3336 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3337 guest_xcrs->nr_xcrs = 0;
3338 return;
3339 }
3340
3341 guest_xcrs->nr_xcrs = 1;
3342 guest_xcrs->flags = 0;
3343 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3344 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3345}
3346
3347static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3348 struct kvm_xcrs *guest_xcrs)
3349{
3350 int i, r = 0;
3351
d366bf7e 3352 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3353 return -EINVAL;
3354
3355 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3356 return -EINVAL;
3357
3358 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3359 /* Only support XCR0 currently */
c67a04cb 3360 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3361 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3362 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3363 break;
3364 }
3365 if (r)
3366 r = -EINVAL;
3367 return r;
3368}
3369
1c0b28c2
EM		 3370/*
3371 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3372 * stopped by the hypervisor. This function will be called from the host only.
3373 * EINVAL is returned when the host attempts to set the flag for a guest that
3374 * does not support pv clocks.
3375 */
3376static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3377{
0b79459b 3378 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3379 return -EINVAL;
51d59c6b 3380 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3381 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3382 return 0;
3383}
3384
5c919412
AS		 3385static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3386 struct kvm_enable_cap *cap)
3387{
3388 if (cap->flags)
3389 return -EINVAL;
3390
3391 switch (cap->cap) {
efc479e6
RK		 3392 case KVM_CAP_HYPERV_SYNIC2:
3393 if (cap->args[0])
3394 return -EINVAL;
5c919412 3395 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3396 if (!irqchip_in_kernel(vcpu->kvm))
3397 return -EINVAL;
efc479e6
RK		 3398 return kvm_hv_activate_synic(vcpu, cap->cap ==
3399 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3400 default:
3401 return -EINVAL;
3402 }
3403}
3404
313a3dc7
CO		 3405long kvm_arch_vcpu_ioctl(struct file *filp,
3406 unsigned int ioctl, unsigned long arg)
3407{
3408 struct kvm_vcpu *vcpu = filp->private_data;
3409 void __user *argp = (void __user *)arg;
3410 int r;
d1ac91d8
AK		 3411 union {
3412 struct kvm_lapic_state *lapic;
3413 struct kvm_xsave *xsave;
3414 struct kvm_xcrs *xcrs;
3415 void *buffer;
3416 } u;
3417
3418 u.buffer = NULL;
313a3dc7
CO		 3419 switch (ioctl) {
3420 case KVM_GET_LAPIC: {
2204ae3c 3421 r = -EINVAL;
bce87cce 3422 if (!lapic_in_kernel(vcpu))
2204ae3c 3423 goto out;
d1ac91d8 3424 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3425
b772ff36 3426 r = -ENOMEM;
d1ac91d8 3427 if (!u.lapic)
b772ff36 3428 goto out;
d1ac91d8 3429 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3430 if (r)
3431 goto out;
3432 r = -EFAULT;
d1ac91d8 3433 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3434 goto out;
3435 r = 0;
3436 break;
3437 }
3438 case KVM_SET_LAPIC: {
2204ae3c 3439 r = -EINVAL;
bce87cce 3440 if (!lapic_in_kernel(vcpu))
2204ae3c 3441 goto out;
ff5c2c03 3442 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3443 if (IS_ERR(u.lapic))
3444 return PTR_ERR(u.lapic);
ff5c2c03 3445
d1ac91d8 3446 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3447 break;
3448 }
f77bc6a4
ZX		 3449 case KVM_INTERRUPT: {
3450 struct kvm_interrupt irq;
3451
3452 r = -EFAULT;
3453 if (copy_from_user(&irq, argp, sizeof irq))
3454 goto out;
3455 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3456 break;
3457 }
c4abb7c9
JK		 3458 case KVM_NMI: {
3459 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3460 break;
3461 }
f077825a
PB		 3462 case KVM_SMI: {
3463 r = kvm_vcpu_ioctl_smi(vcpu);
3464 break;
3465 }
313a3dc7
CO		 3466 case KVM_SET_CPUID: {
3467 struct kvm_cpuid __user *cpuid_arg = argp;
3468 struct kvm_cpuid cpuid;
3469
3470 r = -EFAULT;
3471 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3472 goto out;
3473 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3474 break;
3475 }
07716717
DK		 3476 case KVM_SET_CPUID2: {
3477 struct kvm_cpuid2 __user *cpuid_arg = argp;
3478 struct kvm_cpuid2 cpuid;
3479
3480 r = -EFAULT;
3481 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3482 goto out;
3483 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3484 cpuid_arg->entries);
07716717
DK		 3485 break;
3486 }
3487 case KVM_GET_CPUID2: {
3488 struct kvm_cpuid2 __user *cpuid_arg = argp;
3489 struct kvm_cpuid2 cpuid;
3490
3491 r = -EFAULT;
3492 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3493 goto out;
3494 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3495 cpuid_arg->entries);
07716717
DK		 3496 if (r)
3497 goto out;
3498 r = -EFAULT;
3499 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3500 goto out;
3501 r = 0;
3502 break;
3503 }
313a3dc7 3504 case KVM_GET_MSRS:
609e36d3 3505 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3506 break;
3507 case KVM_SET_MSRS:
3508 r = msr_io(vcpu, argp, do_set_msr, 0);
3509 break;
b209749f
AK		 3510 case KVM_TPR_ACCESS_REPORTING: {
3511 struct kvm_tpr_access_ctl tac;
3512
3513 r = -EFAULT;
3514 if (copy_from_user(&tac, argp, sizeof tac))
3515 goto out;
3516 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3517 if (r)
3518 goto out;
3519 r = -EFAULT;
3520 if (copy_to_user(argp, &tac, sizeof tac))
3521 goto out;
3522 r = 0;
3523 break;
3524 };
b93463aa
AK		 3525 case KVM_SET_VAPIC_ADDR: {
3526 struct kvm_vapic_addr va;
7301d6ab 3527 int idx;
b93463aa
AK		 3528
3529 r = -EINVAL;
35754c98 3530 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3531 goto out;
3532 r = -EFAULT;
3533 if (copy_from_user(&va, argp, sizeof va))
3534 goto out;
7301d6ab 3535 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3536 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3537 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3538 break;
3539 }
890ca9ae
YH		 3540 case KVM_X86_SETUP_MCE: {
3541 u64 mcg_cap;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3545 goto out;
3546 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3547 break;
3548 }
3549 case KVM_X86_SET_MCE: {
3550 struct kvm_x86_mce mce;
3551
3552 r = -EFAULT;
3553 if (copy_from_user(&mce, argp, sizeof mce))
3554 goto out;
3555 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3556 break;
3557 }
3cfc3092
JK		 3558 case KVM_GET_VCPU_EVENTS: {
3559 struct kvm_vcpu_events events;
3560
3561 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3562
3563 r = -EFAULT;
3564 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3565 break;
3566 r = 0;
3567 break;
3568 }
3569 case KVM_SET_VCPU_EVENTS: {
3570 struct kvm_vcpu_events events;
3571
3572 r = -EFAULT;
3573 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3574 break;
3575
3576 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3577 break;
3578 }
a1efbe77
JK		 3579 case KVM_GET_DEBUGREGS: {
3580 struct kvm_debugregs dbgregs;
3581
3582 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3583
3584 r = -EFAULT;
3585 if (copy_to_user(argp, &dbgregs,
3586 sizeof(struct kvm_debugregs)))
3587 break;
3588 r = 0;
3589 break;
3590 }
3591 case KVM_SET_DEBUGREGS: {
3592 struct kvm_debugregs dbgregs;
3593
3594 r = -EFAULT;
3595 if (copy_from_user(&dbgregs, argp,
3596 sizeof(struct kvm_debugregs)))
3597 break;
3598
3599 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3600 break;
3601 }
2d5b5a66 3602 case KVM_GET_XSAVE: {
d1ac91d8 3603 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3604 r = -ENOMEM;
d1ac91d8 3605 if (!u.xsave)
2d5b5a66
SY		 3606 break;
3607
d1ac91d8 3608 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3609
3610 r = -EFAULT;
d1ac91d8 3611 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3612 break;
3613 r = 0;
3614 break;
3615 }
3616 case KVM_SET_XSAVE: {
ff5c2c03 3617 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3618 if (IS_ERR(u.xsave))
3619 return PTR_ERR(u.xsave);
2d5b5a66 3620
d1ac91d8 3621 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3622 break;
3623 }
3624 case KVM_GET_XCRS: {
d1ac91d8 3625 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3626 r = -ENOMEM;
d1ac91d8 3627 if (!u.xcrs)
2d5b5a66
SY		 3628 break;
3629
d1ac91d8 3630 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3631
3632 r = -EFAULT;
d1ac91d8 3633 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3634 sizeof(struct kvm_xcrs)))
3635 break;
3636 r = 0;
3637 break;
3638 }
3639 case KVM_SET_XCRS: {
ff5c2c03 3640 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3641 if (IS_ERR(u.xcrs))
3642 return PTR_ERR(u.xcrs);
2d5b5a66 3643
d1ac91d8 3644 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3645 break;
3646 }
92a1f12d
JR		 3647 case KVM_SET_TSC_KHZ: {
3648 u32 user_tsc_khz;
3649
3650 r = -EINVAL;
92a1f12d
JR		 3651 user_tsc_khz = (u32)arg;
3652
3653 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3654 goto out;
3655
cc578287
ZA		 3656 if (user_tsc_khz == 0)
3657 user_tsc_khz = tsc_khz;
3658
381d585c
HZ		 3659 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3660 r = 0;
92a1f12d 3661
92a1f12d
JR		 3662 goto out;
3663 }
3664 case KVM_GET_TSC_KHZ: {
cc578287 3665 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3666 goto out;
3667 }
1c0b28c2
EM		 3668 case KVM_KVMCLOCK_CTRL: {
3669 r = kvm_set_guest_paused(vcpu);
3670 goto out;
3671 }
5c919412
AS		 3672 case KVM_ENABLE_CAP: {
3673 struct kvm_enable_cap cap;
3674
3675 r = -EFAULT;
3676 if (copy_from_user(&cap, argp, sizeof(cap)))
3677 goto out;
3678 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3679 break;
3680 }
313a3dc7
CO		 3681 default:
3682 r = -EINVAL;
3683 }
3684out:
d1ac91d8 3685 kfree(u.buffer);
313a3dc7
CO		 3686 return r;
3687}
3688
5b1c1493
CO		 3689int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3690{
3691 return VM_FAULT_SIGBUS;
3692}
3693
1fe779f8
CO		 3694static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3695{
3696 int ret;
3697
3698 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3699 return -EINVAL;
1fe779f8
CO		 3700 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3701 return ret;
3702}
3703
b927a3ce
SY		 3704static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3705 u64 ident_addr)
3706{
3707 kvm->arch.ept_identity_map_addr = ident_addr;
3708 return 0;
3709}
3710
1fe779f8
CO		 3711static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3712 u32 kvm_nr_mmu_pages)
3713{
3714 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3715 return -EINVAL;
3716
79fac95e 3717 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3718
3719 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3720 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3721
79fac95e 3722 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3723 return 0;
3724}
3725
3726static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3727{
39de71ec 3728 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3729}
3730
1fe779f8
CO		 3731static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3732{
90bca052 3733 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3734 int r;
3735
3736 r = 0;
3737 switch (chip->chip_id) {
3738 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3739 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3740 sizeof(struct kvm_pic_state));
3741 break;
3742 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3743 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3744 sizeof(struct kvm_pic_state));
3745 break;
3746 case KVM_IRQCHIP_IOAPIC:
33392b49 3747 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3748 break;
3749 default:
3750 r = -EINVAL;
3751 break;
3752 }
3753 return r;
3754}
3755
3756static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3757{
90bca052 3758 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3759 int r;
3760
3761 r = 0;
3762 switch (chip->chip_id) {
3763 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3764 spin_lock(&pic->lock);
3765 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3766 sizeof(struct kvm_pic_state));
90bca052 3767 spin_unlock(&pic->lock);
1fe779f8
CO		 3768 break;
3769 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3770 spin_lock(&pic->lock);
3771 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3772 sizeof(struct kvm_pic_state));
90bca052 3773 spin_unlock(&pic->lock);
1fe779f8
CO		 3774 break;
3775 case KVM_IRQCHIP_IOAPIC:
33392b49 3776 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3777 break;
3778 default:
3779 r = -EINVAL;
3780 break;
3781 }
90bca052 3782 kvm_pic_update_irq(pic);
1fe779f8
CO		 3783 return r;
3784}
3785
e0f63cb9
SY		 3786static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3787{
34f3941c
RK		 3788 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3789
3790 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3791
3792 mutex_lock(&kps->lock);
3793 memcpy(ps, &kps->channels, sizeof(*ps));
3794 mutex_unlock(&kps->lock);
2da29bcc 3795 return 0;
e0f63cb9
SY		 3796}
3797
3798static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3799{
0185604c 3800 int i;
09edea72
RK		 3801 struct kvm_pit *pit = kvm->arch.vpit;
3802
3803 mutex_lock(&pit->pit_state.lock);
34f3941c 3804 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3805 for (i = 0; i < 3; i++)
09edea72
RK		 3806 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3807 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3808 return 0;
e9f42757
BK		 3809}
3810
3811static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3812{
e9f42757
BK		 3813 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3814 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3815 sizeof(ps->channels));
3816 ps->flags = kvm->arch.vpit->pit_state.flags;
3817 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3818 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3819 return 0;
e9f42757
BK		 3820}
3821
3822static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3823{
2da29bcc 3824 int start = 0;
0185604c 3825 int i;
e9f42757 3826 u32 prev_legacy, cur_legacy;
09edea72
RK		 3827 struct kvm_pit *pit = kvm->arch.vpit;
3828
3829 mutex_lock(&pit->pit_state.lock);
3830 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3831 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3832 if (!prev_legacy && cur_legacy)
3833 start = 1;
09edea72
RK		 3834 memcpy(&pit->pit_state.channels, &ps->channels,
3835 sizeof(pit->pit_state.channels));
3836 pit->pit_state.flags = ps->flags;
0185604c 3837 for (i = 0; i < 3; i++)
09edea72 3838 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3839 start && i == 0);
09edea72 3840 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3841 return 0;
e0f63cb9
SY		 3842}
3843
52d939a0
MT		 3844static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3845 struct kvm_reinject_control *control)
3846{
71474e2f
RK		 3847 struct kvm_pit *pit = kvm->arch.vpit;
3848
3849 if (!pit)
52d939a0 3850 return -ENXIO;
b39c90b6 3851
71474e2f
RK		 3852 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3853 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3854 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3855 */
3856 mutex_lock(&pit->pit_state.lock);
3857 kvm_pit_set_reinject(pit, control->pit_reinject);
3858 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3859
52d939a0
MT		 3860 return 0;
3861}
3862
95d4c16c 3863/**
60c34612
TY		 3864 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3865 * @kvm: kvm instance
3866 * @log: slot id and address to which we copy the log
95d4c16c 3867 *
e108ff2f
PB		 3868 * Steps 1-4 below provide general overview of dirty page logging. See
3869 * kvm_get_dirty_log_protect() function description for additional details.
3870 *
3871 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3872 * always flush the TLB (step 4) even if previous step failed and the dirty
3873 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3874 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3875 * writes will be marked dirty for next log read.
95d4c16c 3876 *
60c34612
TY		 3877 * 1. Take a snapshot of the bit and clear it if needed.
3878 * 2. Write protect the corresponding page.
e108ff2f
PB		 3879 * 3. Copy the snapshot to the userspace.
3880 * 4. Flush TLB's if needed.
5bb064dc 3881 */
60c34612 3882int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3883{
60c34612 3884 bool is_dirty = false;
e108ff2f 3885 int r;
5bb064dc 3886
79fac95e 3887 mutex_lock(&kvm->slots_lock);
5bb064dc 3888
88178fd4
KH		 3889 /*
3890 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3891 */
3892 if (kvm_x86_ops->flush_log_dirty)
3893 kvm_x86_ops->flush_log_dirty(kvm);
3894
e108ff2f 3895 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3896
3897 /*
3898 * All the TLBs can be flushed out of mmu lock, see the comments in
3899 * kvm_mmu_slot_remove_write_access().
3900 */
e108ff2f 3901 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3902 if (is_dirty)
3903 kvm_flush_remote_tlbs(kvm);
3904
79fac95e 3905 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3906 return r;
3907}
3908
aa2fbe6d
YZ		 3909int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3910 bool line_status)
23d43cf9
CD		 3911{
3912 if (!irqchip_in_kernel(kvm))
3913 return -ENXIO;
3914
3915 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3916 irq_event->irq, irq_event->level,
3917 line_status);
23d43cf9
CD		 3918 return 0;
3919}
3920
90de4a18
NA		 3921static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3922 struct kvm_enable_cap *cap)
3923{
3924 int r;
3925
3926 if (cap->flags)
3927 return -EINVAL;
3928
3929 switch (cap->cap) {
3930 case KVM_CAP_DISABLE_QUIRKS:
3931 kvm->arch.disabled_quirks = cap->args[0];
3932 r = 0;
3933 break;
49df6397
SR		 3934 case KVM_CAP_SPLIT_IRQCHIP: {
3935 mutex_lock(&kvm->lock);
b053b2ae
SR		 3936 r = -EINVAL;
3937 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3938 goto split_irqchip_unlock;
49df6397
SR		 3939 r = -EEXIST;
3940 if (irqchip_in_kernel(kvm))
3941 goto split_irqchip_unlock;
557abc40 3942 if (kvm->created_vcpus)
49df6397
SR		 3943 goto split_irqchip_unlock;
3944 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 3945 if (r)
49df6397
SR		 3946 goto split_irqchip_unlock;
3947 /* Pairs with irqchip_in_kernel. */
3948 smp_wmb();
49776faf 3949 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3950 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3951 r = 0;
3952split_irqchip_unlock:
3953 mutex_unlock(&kvm->lock);
3954 break;
3955 }
37131313
RK		 3956 case KVM_CAP_X2APIC_API:
3957 r = -EINVAL;
3958 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3959 break;
3960
3961 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3962 kvm->arch.x2apic_format = true;
c519265f
RK		 3963 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3964 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3965
3966 r = 0;
3967 break;
90de4a18
NA		 3968 default:
3969 r = -EINVAL;
3970 break;
3971 }
3972 return r;
3973}
3974
1fe779f8
CO		 3975long kvm_arch_vm_ioctl(struct file *filp,
3976 unsigned int ioctl, unsigned long arg)
3977{
3978 struct kvm *kvm = filp->private_data;
3979 void __user *argp = (void __user *)arg;
367e1319 3980 int r = -ENOTTY;
f0d66275
DH		 3981 /*
3982 * This union makes it completely explicit to gcc-3.x
3983 * that these two variables' stack usage should be
3984 * combined, not added together.
3985 */
3986 union {
3987 struct kvm_pit_state ps;
e9f42757 3988 struct kvm_pit_state2 ps2;
c5ff41ce 3989 struct kvm_pit_config pit_config;
f0d66275 3990 } u;
1fe779f8
CO		 3991
3992 switch (ioctl) {
3993 case KVM_SET_TSS_ADDR:
3994 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3995 break;
b927a3ce
SY		 3996 case KVM_SET_IDENTITY_MAP_ADDR: {
3997 u64 ident_addr;
3998
3999 r = -EFAULT;
4000 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
4001 goto out;
4002 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4003 break;
4004 }
1fe779f8
CO		 4005 case KVM_SET_NR_MMU_PAGES:
4006 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4007 break;
4008 case KVM_GET_NR_MMU_PAGES:
4009 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4010 break;
3ddea128 4011 case KVM_CREATE_IRQCHIP: {
3ddea128 4012 mutex_lock(&kvm->lock);
09941366 4013
3ddea128 4014 r = -EEXIST;
35e6eaa3 4015 if (irqchip_in_kernel(kvm))
3ddea128 4016 goto create_irqchip_unlock;
09941366 4017
3e515705 4018 r = -EINVAL;
557abc40 4019 if (kvm->created_vcpus)
3e515705 4020 goto create_irqchip_unlock;
09941366
RK		 4021
4022 r = kvm_pic_init(kvm);
4023 if (r)
3ddea128 4024 goto create_irqchip_unlock;
09941366
RK		 4025
4026 r = kvm_ioapic_init(kvm);
4027 if (r) {
09941366 4028 kvm_pic_destroy(kvm);
3ddea128 4029 goto create_irqchip_unlock;
09941366
RK		 4030 }
4031
399ec807
AK		 4032 r = kvm_setup_default_irq_routing(kvm);
4033 if (r) {
72bb2fcd 4034 kvm_ioapic_destroy(kvm);
09941366 4035 kvm_pic_destroy(kvm);
71ba994c 4036 goto create_irqchip_unlock;
399ec807 4037 }
49776faf 4038 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4039 smp_wmb();
49776faf 4040 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4041 create_irqchip_unlock:
4042 mutex_unlock(&kvm->lock);
1fe779f8 4043 break;
3ddea128 4044 }
7837699f 4045 case KVM_CREATE_PIT:
c5ff41ce
JK		 4046 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4047 goto create_pit;
4048 case KVM_CREATE_PIT2:
4049 r = -EFAULT;
4050 if (copy_from_user(&u.pit_config, argp,
4051 sizeof(struct kvm_pit_config)))
4052 goto out;
4053 create_pit:
250715a6 4054 mutex_lock(&kvm->lock);
269e05e4
AK		 4055 r = -EEXIST;
4056 if (kvm->arch.vpit)
4057 goto create_pit_unlock;
7837699f 4058 r = -ENOMEM;
c5ff41ce 4059 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4060 if (kvm->arch.vpit)
4061 r = 0;
269e05e4 4062 create_pit_unlock:
250715a6 4063 mutex_unlock(&kvm->lock);
7837699f 4064 break;
1fe779f8
CO		 4065 case KVM_GET_IRQCHIP: {
4066 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4067 struct kvm_irqchip *chip;
1fe779f8 4068
ff5c2c03
SL		 4069 chip = memdup_user(argp, sizeof(*chip));
4070 if (IS_ERR(chip)) {
4071 r = PTR_ERR(chip);
1fe779f8 4072 goto out;
ff5c2c03
SL		 4073 }
4074
1fe779f8 4075 r = -ENXIO;
826da321 4076 if (!irqchip_kernel(kvm))
f0d66275
DH		 4077 goto get_irqchip_out;
4078 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4079 if (r)
f0d66275 4080 goto get_irqchip_out;
1fe779f8 4081 r = -EFAULT;
f0d66275
DH		 4082 if (copy_to_user(argp, chip, sizeof *chip))
4083 goto get_irqchip_out;
1fe779f8 4084 r = 0;
f0d66275
DH		 4085 get_irqchip_out:
4086 kfree(chip);
1fe779f8
CO		 4087 break;
4088 }
4089 case KVM_SET_IRQCHIP: {
4090 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4091 struct kvm_irqchip *chip;
1fe779f8 4092
ff5c2c03
SL		 4093 chip = memdup_user(argp, sizeof(*chip));
4094 if (IS_ERR(chip)) {
4095 r = PTR_ERR(chip);
1fe779f8 4096 goto out;
ff5c2c03
SL		 4097 }
4098
1fe779f8 4099 r = -ENXIO;
826da321 4100 if (!irqchip_kernel(kvm))
f0d66275
DH		 4101 goto set_irqchip_out;
4102 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4103 if (r)
f0d66275 4104 goto set_irqchip_out;
1fe779f8 4105 r = 0;
f0d66275
DH		 4106 set_irqchip_out:
4107 kfree(chip);
1fe779f8
CO		 4108 break;
4109 }
e0f63cb9 4110 case KVM_GET_PIT: {
e0f63cb9 4111 r = -EFAULT;
f0d66275 4112 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4113 goto out;
4114 r = -ENXIO;
4115 if (!kvm->arch.vpit)
4116 goto out;
f0d66275 4117 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4118 if (r)
4119 goto out;
4120 r = -EFAULT;
f0d66275 4121 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4122 goto out;
4123 r = 0;
4124 break;
4125 }
4126 case KVM_SET_PIT: {
e0f63cb9 4127 r = -EFAULT;
f0d66275 4128 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4129 goto out;
4130 r = -ENXIO;
4131 if (!kvm->arch.vpit)
4132 goto out;
f0d66275 4133 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4134 break;
4135 }
e9f42757
BK		 4136 case KVM_GET_PIT2: {
4137 r = -ENXIO;
4138 if (!kvm->arch.vpit)
4139 goto out;
4140 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4141 if (r)
4142 goto out;
4143 r = -EFAULT;
4144 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4145 goto out;
4146 r = 0;
4147 break;
4148 }
4149 case KVM_SET_PIT2: {
4150 r = -EFAULT;
4151 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4152 goto out;
4153 r = -ENXIO;
4154 if (!kvm->arch.vpit)
4155 goto out;
4156 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4157 break;
4158 }
52d939a0
MT		 4159 case KVM_REINJECT_CONTROL: {
4160 struct kvm_reinject_control control;
4161 r = -EFAULT;
4162 if (copy_from_user(&control, argp, sizeof(control)))
4163 goto out;
4164 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4165 break;
4166 }
d71ba788
PB		 4167 case KVM_SET_BOOT_CPU_ID:
4168 r = 0;
4169 mutex_lock(&kvm->lock);
557abc40 4170 if (kvm->created_vcpus)
d71ba788
PB		 4171 r = -EBUSY;
4172 else
4173 kvm->arch.bsp_vcpu_id = arg;
4174 mutex_unlock(&kvm->lock);
4175 break;
ffde22ac
ES		 4176 case KVM_XEN_HVM_CONFIG: {
4177 r = -EFAULT;
4178 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4179 sizeof(struct kvm_xen_hvm_config)))
4180 goto out;
4181 r = -EINVAL;
4182 if (kvm->arch.xen_hvm_config.flags)
4183 goto out;
4184 r = 0;
4185 break;
4186 }
afbcf7ab 4187 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4188 struct kvm_clock_data user_ns;
4189 u64 now_ns;
afbcf7ab
GC		 4190
4191 r = -EFAULT;
4192 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4193 goto out;
4194
4195 r = -EINVAL;
4196 if (user_ns.flags)
4197 goto out;
4198
4199 r = 0;
0bc48bea
RK		 4200 /*
4201 * TODO: userspace has to take care of races with VCPU_RUN, so
4202 * kvm_gen_update_masterclock() can be cut down to locked
4203 * pvclock_update_vm_gtod_copy().
4204 */
4205 kvm_gen_update_masterclock(kvm);
e891a32e 4206 now_ns = get_kvmclock_ns(kvm);
108b249c 4207 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4208 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4209 break;
4210 }
4211 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4212 struct kvm_clock_data user_ns;
4213 u64 now_ns;
4214
e891a32e 4215 now_ns = get_kvmclock_ns(kvm);
108b249c 4216 user_ns.clock = now_ns;
e3fd9a93 4217 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4218 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4219
4220 r = -EFAULT;
4221 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4222 goto out;
4223 r = 0;
4224 break;
4225 }
90de4a18
NA		 4226 case KVM_ENABLE_CAP: {
4227 struct kvm_enable_cap cap;
afbcf7ab 4228
90de4a18
NA		 4229 r = -EFAULT;
4230 if (copy_from_user(&cap, argp, sizeof(cap)))
4231 goto out;
4232 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4233 break;
4234 }
1fe779f8 4235 default:
ad6260da 4236 r = -ENOTTY;
1fe779f8
CO		 4237 }
4238out:
4239 return r;
4240}
4241
a16b043c 4242static void kvm_init_msr_list(void)
043405e1
CO		 4243{
4244 u32 dummy[2];
4245 unsigned i, j;
4246
62ef68bb 4247 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4248 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4249 continue;
93c4adc7
PB		 4250
4251 /*
4252 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4253 * to the guests in some cases.
93c4adc7
PB		 4254 */
4255 switch (msrs_to_save[i]) {
4256 case MSR_IA32_BNDCFGS:
4257 if (!kvm_x86_ops->mpx_supported())
4258 continue;
4259 break;
9dbe6cf9
PB		 4260 case MSR_TSC_AUX:
4261 if (!kvm_x86_ops->rdtscp_supported())
4262 continue;
4263 break;
93c4adc7
PB		 4264 default:
4265 break;
4266 }
4267
043405e1
CO		 4268 if (j < i)
4269 msrs_to_save[j] = msrs_to_save[i];
4270 j++;
4271 }
4272 num_msrs_to_save = j;
62ef68bb
PB		 4273
4274 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4275 switch (emulated_msrs[i]) {
6d396b55
PB		 4276 case MSR_IA32_SMBASE:
4277 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4278 continue;
4279 break;
62ef68bb
PB		 4280 default:
4281 break;
4282 }
4283
4284 if (j < i)
4285 emulated_msrs[j] = emulated_msrs[i];
4286 j++;
4287 }
4288 num_emulated_msrs = j;
043405e1
CO		 4289}
4290
bda9020e
MT		 4291static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4292 const void *v)
bbd9b64e 4293{
70252a10
AK		 4294 int handled = 0;
4295 int n;
4296
4297 do {
4298 n = min(len, 8);
bce87cce 4299 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4300 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4301 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4302 break;
4303 handled += n;
4304 addr += n;
4305 len -= n;
4306 v += n;
4307 } while (len);
bbd9b64e 4308
70252a10 4309 return handled;
bbd9b64e
CO		 4310}
4311
bda9020e 4312static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4313{
70252a10
AK		 4314 int handled = 0;
4315 int n;
4316
4317 do {
4318 n = min(len, 8);
bce87cce 4319 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4320 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4321 addr, n, v))
4322 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4323 break;
4324 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4325 handled += n;
4326 addr += n;
4327 len -= n;
4328 v += n;
4329 } while (len);
bbd9b64e 4330
70252a10 4331 return handled;
bbd9b64e
CO		 4332}
4333
2dafc6c2
GN		 4334static void kvm_set_segment(struct kvm_vcpu *vcpu,
4335 struct kvm_segment *var, int seg)
4336{
4337 kvm_x86_ops->set_segment(vcpu, var, seg);
4338}
4339
4340void kvm_get_segment(struct kvm_vcpu *vcpu,
4341 struct kvm_segment *var, int seg)
4342{
4343 kvm_x86_ops->get_segment(vcpu, var, seg);
4344}
4345
54987b7a
PB		 4346gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4347 struct x86_exception *exception)
02f59dc9
JR		 4348{
4349 gpa_t t_gpa;
02f59dc9
JR		 4350
4351 BUG_ON(!mmu_is_nested(vcpu));
4352
4353 /* NPT walks are always user-walks */
4354 access |= PFERR_USER_MASK;
54987b7a 4355 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4356
4357 return t_gpa;
4358}
4359
ab9ae313
AK		 4360gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4361 struct x86_exception *exception)
1871c602
GN		 4362{
4363 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4364 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4365}
4366
ab9ae313
AK		 4367 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4368 struct x86_exception *exception)
1871c602
GN		 4369{
4370 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4371 access |= PFERR_FETCH_MASK;
ab9ae313 4372 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4373}
4374
ab9ae313
AK		 4375gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4376 struct x86_exception *exception)
1871c602
GN		 4377{
4378 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4379 access |= PFERR_WRITE_MASK;
ab9ae313 4380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4381}
4382
4383/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4384gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4385 struct x86_exception *exception)
1871c602 4386{
ab9ae313 4387 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4388}
4389
4390static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4391 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4392 struct x86_exception *exception)
bbd9b64e
CO		 4393{
4394 void *data = val;
10589a46 4395 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4396
4397 while (bytes) {
14dfe855 4398 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4399 exception);
bbd9b64e 4400 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4401 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4402 int ret;
4403
bcc55cba 4404 if (gpa == UNMAPPED_GVA)
ab9ae313 4405 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4406 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4407 offset, toread);
10589a46 4408 if (ret < 0) {
c3cd7ffa 4409 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4410 goto out;
4411 }
bbd9b64e 4412
77c2002e
IE		 4413 bytes -= toread;
4414 data += toread;
4415 addr += toread;
bbd9b64e 4416 }
10589a46 4417out:
10589a46 4418 return r;
bbd9b64e 4419}
77c2002e 4420
1871c602 4421/* used for instruction fetching */
0f65dd70
AK		 4422static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4423 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4424 struct x86_exception *exception)
1871c602 4425{
0f65dd70 4426 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4427 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4428 unsigned offset;
4429 int ret;
0f65dd70 4430
44583cba
PB		 4431 /* Inline kvm_read_guest_virt_helper for speed. */
4432 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4433 exception);
4434 if (unlikely(gpa == UNMAPPED_GVA))
4435 return X86EMUL_PROPAGATE_FAULT;
4436
4437 offset = addr & (PAGE_SIZE-1);
4438 if (WARN_ON(offset + bytes > PAGE_SIZE))
4439 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4440 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4441 offset, bytes);
44583cba
PB		 4442 if (unlikely(ret < 0))
4443 return X86EMUL_IO_NEEDED;
4444
4445 return X86EMUL_CONTINUE;
1871c602
GN		 4446}
4447
064aea77 4448int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4449 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4450 struct x86_exception *exception)
1871c602 4451{
0f65dd70 4452 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4453 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4454
1871c602 4455 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4456 exception);
1871c602 4457}
064aea77 4458EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4459
0f65dd70
AK		 4460static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4461 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4462 struct x86_exception *exception)
1871c602 4463{
0f65dd70 4464 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4465 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4466}
4467
7a036a6f
RK		 4468static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4469 unsigned long addr, void *val, unsigned int bytes)
4470{
4471 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4472 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4473
4474 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4475}
4476
6a4d7550 4477int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4478 gva_t addr, void *val,
2dafc6c2 4479 unsigned int bytes,
bcc55cba 4480 struct x86_exception *exception)
77c2002e 4481{
0f65dd70 4482 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4483 void *data = val;
4484 int r = X86EMUL_CONTINUE;
4485
4486 while (bytes) {
14dfe855
JR		 4487 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4488 PFERR_WRITE_MASK,
ab9ae313 4489 exception);
77c2002e
IE		 4490 unsigned offset = addr & (PAGE_SIZE-1);
4491 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4492 int ret;
4493
bcc55cba 4494 if (gpa == UNMAPPED_GVA)
ab9ae313 4495 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4496 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4497 if (ret < 0) {
c3cd7ffa 4498 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4499 goto out;
4500 }
4501
4502 bytes -= towrite;
4503 data += towrite;
4504 addr += towrite;
4505 }
4506out:
4507 return r;
4508}
6a4d7550 4509EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4510
0f89b207
TL		 4511static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4512 gpa_t gpa, bool write)
4513{
4514 /* For APIC access vmexit */
4515 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4516 return 1;
4517
4518 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4519 trace_vcpu_match_mmio(gva, gpa, write, true);
4520 return 1;
4521 }
4522
4523 return 0;
4524}
4525
af7cc7d1
XG		 4526static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4527 gpa_t *gpa, struct x86_exception *exception,
4528 bool write)
4529{
97d64b78
AK		 4530 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4531 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4532
be94f6b7
HH		 4533 /*
4534 * currently PKRU is only applied to ept enabled guest so
4535 * there is no pkey in EPT page table for L1 guest or EPT
4536 * shadow page table for L2 guest.
4537 */
97d64b78 4538 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4539 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4540 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4541 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4542 (gva & (PAGE_SIZE - 1));
4f022648 4543 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4544 return 1;
4545 }
4546
af7cc7d1
XG		 4547 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4548
4549 if (*gpa == UNMAPPED_GVA)
4550 return -1;
4551
0f89b207 4552 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4553}
4554
3200f405 4555int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4556 const void *val, int bytes)
bbd9b64e
CO		 4557{
4558 int ret;
4559
54bf36aa 4560 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4561 if (ret < 0)
bbd9b64e 4562 return 0;
0eb05bf2 4563 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4564 return 1;
4565}
4566
77d197b2
XG		 4567struct read_write_emulator_ops {
4568 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4569 int bytes);
4570 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4571 void *val, int bytes);
4572 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4573 int bytes, void *val);
4574 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4575 void *val, int bytes);
4576 bool write;
4577};
4578
4579static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4580{
4581 if (vcpu->mmio_read_completed) {
77d197b2 4582 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4583 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4584 vcpu->mmio_read_completed = 0;
4585 return 1;
4586 }
4587
4588 return 0;
4589}
4590
4591static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4592 void *val, int bytes)
4593{
54bf36aa 4594 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4595}
4596
4597static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4598 void *val, int bytes)
4599{
4600 return emulator_write_phys(vcpu, gpa, val, bytes);
4601}
4602
4603static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4604{
4605 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4606 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4607}
4608
4609static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4610 void *val, int bytes)
4611{
4612 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4613 return X86EMUL_IO_NEEDED;
4614}
4615
4616static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4617 void *val, int bytes)
4618{
f78146b0
AK		 4619 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4620
87da7e66 4621 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4622 return X86EMUL_CONTINUE;
4623}
4624
0fbe9b0b 4625static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4626 .read_write_prepare = read_prepare,
4627 .read_write_emulate = read_emulate,
4628 .read_write_mmio = vcpu_mmio_read,
4629 .read_write_exit_mmio = read_exit_mmio,
4630};
4631
0fbe9b0b 4632static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4633 .read_write_emulate = write_emulate,
4634 .read_write_mmio = write_mmio,
4635 .read_write_exit_mmio = write_exit_mmio,
4636 .write = true,
4637};
4638
22388a3c
XG		 4639static int emulator_read_write_onepage(unsigned long addr, void *val,
4640 unsigned int bytes,
4641 struct x86_exception *exception,
4642 struct kvm_vcpu *vcpu,
0fbe9b0b 4643 const struct read_write_emulator_ops *ops)
bbd9b64e 4644{
af7cc7d1
XG		 4645 gpa_t gpa;
4646 int handled, ret;
22388a3c 4647 bool write = ops->write;
f78146b0 4648 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4649 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4650
4651 /*
4652 * If the exit was due to a NPF we may already have a GPA.
4653 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4654 * Note, this cannot be used on string operations since string
4655 * operation using rep will only have the initial GPA from the NPF
4656 * occurred.
4657 */
4658 if (vcpu->arch.gpa_available &&
4659 emulator_can_use_gpa(ctxt) &&
4660 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4661 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4662 gpa = exception->address;
4663 goto mmio;
4664 }
10589a46 4665
22388a3c 4666 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4667
af7cc7d1 4668 if (ret < 0)
bbd9b64e 4669 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4670
4671 /* For APIC access vmexit */
af7cc7d1 4672 if (ret)
bbd9b64e
CO		 4673 goto mmio;
4674
22388a3c 4675 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4676 return X86EMUL_CONTINUE;
4677
4678mmio:
4679 /*
4680 * Is this MMIO handled locally?
4681 */
22388a3c 4682 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4683 if (handled == bytes)
bbd9b64e 4684 return X86EMUL_CONTINUE;
bbd9b64e 4685
70252a10
AK		 4686 gpa += handled;
4687 bytes -= handled;
4688 val += handled;
4689
87da7e66
XG		 4690 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4691 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4692 frag->gpa = gpa;
4693 frag->data = val;
4694 frag->len = bytes;
f78146b0 4695 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4696}
4697
52eb5a6d
XL		 4698static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4699 unsigned long addr,
22388a3c
XG		 4700 void *val, unsigned int bytes,
4701 struct x86_exception *exception,
0fbe9b0b 4702 const struct read_write_emulator_ops *ops)
bbd9b64e 4703{
0f65dd70 4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4705 gpa_t gpa;
4706 int rc;
4707
4708 if (ops->read_write_prepare &&
4709 ops->read_write_prepare(vcpu, val, bytes))
4710 return X86EMUL_CONTINUE;
4711
4712 vcpu->mmio_nr_fragments = 0;
0f65dd70 4713
bbd9b64e
CO		 4714 /* Crossing a page boundary? */
4715 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4716 int now;
bbd9b64e
CO		 4717
4718 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4719 rc = emulator_read_write_onepage(addr, val, now, exception,
4720 vcpu, ops);
4721
bbd9b64e
CO		 4722 if (rc != X86EMUL_CONTINUE)
4723 return rc;
4724 addr += now;
bac15531
NA		 4725 if (ctxt->mode != X86EMUL_MODE_PROT64)
4726 addr = (u32)addr;
bbd9b64e
CO		 4727 val += now;
4728 bytes -= now;
4729 }
22388a3c 4730
f78146b0
AK		 4731 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4732 vcpu, ops);
4733 if (rc != X86EMUL_CONTINUE)
4734 return rc;
4735
4736 if (!vcpu->mmio_nr_fragments)
4737 return rc;
4738
4739 gpa = vcpu->mmio_fragments[0].gpa;
4740
4741 vcpu->mmio_needed = 1;
4742 vcpu->mmio_cur_fragment = 0;
4743
87da7e66 4744 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4745 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4746 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4747 vcpu->run->mmio.phys_addr = gpa;
4748
4749 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4750}
4751
4752static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4753 unsigned long addr,
4754 void *val,
4755 unsigned int bytes,
4756 struct x86_exception *exception)
4757{
4758 return emulator_read_write(ctxt, addr, val, bytes,
4759 exception, &read_emultor);
4760}
4761
52eb5a6d 4762static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4763 unsigned long addr,
4764 const void *val,
4765 unsigned int bytes,
4766 struct x86_exception *exception)
4767{
4768 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4769 exception, &write_emultor);
bbd9b64e 4770}
bbd9b64e 4771
daea3e73
AK		 4772#define CMPXCHG_TYPE(t, ptr, old, new) \
4773 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4774
4775#ifdef CONFIG_X86_64
4776# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4777#else
4778# define CMPXCHG64(ptr, old, new) \
9749a6c0 4779 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4780#endif
4781
0f65dd70
AK		 4782static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4783 unsigned long addr,
bbd9b64e
CO		 4784 const void *old,
4785 const void *new,
4786 unsigned int bytes,
0f65dd70 4787 struct x86_exception *exception)
bbd9b64e 4788{
0f65dd70 4789 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4790 gpa_t gpa;
4791 struct page *page;
4792 char *kaddr;
4793 bool exchanged;
2bacc55c 4794
daea3e73
AK		 4795 /* guests cmpxchg8b have to be emulated atomically */
4796 if (bytes > 8 || (bytes & (bytes - 1)))
4797 goto emul_write;
10589a46 4798
daea3e73 4799 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4800
daea3e73
AK		 4801 if (gpa == UNMAPPED_GVA ||
4802 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4803 goto emul_write;
2bacc55c 4804
daea3e73
AK		 4805 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4806 goto emul_write;
72dc67a6 4807
54bf36aa 4808 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4809 if (is_error_page(page))
c19b8bd6 4810 goto emul_write;
72dc67a6 4811
8fd75e12 4812 kaddr = kmap_atomic(page);
daea3e73
AK		 4813 kaddr += offset_in_page(gpa);
4814 switch (bytes) {
4815 case 1:
4816 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4817 break;
4818 case 2:
4819 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4820 break;
4821 case 4:
4822 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4823 break;
4824 case 8:
4825 exchanged = CMPXCHG64(kaddr, old, new);
4826 break;
4827 default:
4828 BUG();
2bacc55c 4829 }
8fd75e12 4830 kunmap_atomic(kaddr);
daea3e73
AK		 4831 kvm_release_page_dirty(page);
4832
4833 if (!exchanged)
4834 return X86EMUL_CMPXCHG_FAILED;
4835
54bf36aa 4836 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4837 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4838
4839 return X86EMUL_CONTINUE;
4a5f48f6 4840
3200f405 4841emul_write:
daea3e73 4842 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4843
0f65dd70 4844 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4845}
4846
cf8f70bf
GN		 4847static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4848{
cbfc6c91 4849 int r = 0, i;
cf8f70bf 4850
cbfc6c91
WL		 4851 for (i = 0; i < vcpu->arch.pio.count; i++) {
4852 if (vcpu->arch.pio.in)
4853 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4854 vcpu->arch.pio.size, pd);
4855 else
4856 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4857 vcpu->arch.pio.port, vcpu->arch.pio.size,
4858 pd);
4859 if (r)
4860 break;
4861 pd += vcpu->arch.pio.size;
4862 }
cf8f70bf
GN		 4863 return r;
4864}
4865
6f6fbe98
XG		 4866static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4867 unsigned short port, void *val,
4868 unsigned int count, bool in)
cf8f70bf 4869{
cf8f70bf 4870 vcpu->arch.pio.port = port;
6f6fbe98 4871 vcpu->arch.pio.in = in;
7972995b 4872 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4873 vcpu->arch.pio.size = size;
4874
4875 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4876 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4877 return 1;
4878 }
4879
4880 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4881 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4882 vcpu->run->io.size = size;
4883 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4884 vcpu->run->io.count = count;
4885 vcpu->run->io.port = port;
4886
4887 return 0;
4888}
4889
6f6fbe98
XG		 4890static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4891 int size, unsigned short port, void *val,
4892 unsigned int count)
cf8f70bf 4893{
ca1d4a9e 4894 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4895 int ret;
ca1d4a9e 4896
6f6fbe98
XG		 4897 if (vcpu->arch.pio.count)
4898 goto data_avail;
cf8f70bf 4899
cbfc6c91
WL		 4900 memset(vcpu->arch.pio_data, 0, size * count);
4901
6f6fbe98
XG		 4902 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4903 if (ret) {
4904data_avail:
4905 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4906 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4907 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4908 return 1;
4909 }
4910
cf8f70bf
GN		 4911 return 0;
4912}
4913
6f6fbe98
XG		 4914static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4915 int size, unsigned short port,
4916 const void *val, unsigned int count)
4917{
4918 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4919
4920 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4921 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4922 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4923}
4924
bbd9b64e
CO		 4925static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4926{
4927 return kvm_x86_ops->get_segment_base(vcpu, seg);
4928}
4929
3cb16fe7 4930static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4931{
3cb16fe7 4932 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4933}
4934
ae6a2375 4935static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4936{
4937 if (!need_emulate_wbinvd(vcpu))
4938 return X86EMUL_CONTINUE;
4939
4940 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4941 int cpu = get_cpu();
4942
4943 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4944 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4945 wbinvd_ipi, NULL, 1);
2eec7343 4946 put_cpu();
f5f48ee1 4947 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4948 } else
4949 wbinvd();
f5f48ee1
SY		 4950 return X86EMUL_CONTINUE;
4951}
5cb56059
JS		 4952
4953int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4954{
6affcbed
KH		 4955 kvm_emulate_wbinvd_noskip(vcpu);
4956 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4957}
f5f48ee1
SY		 4958EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4959
5cb56059
JS		 4960
4961
bcaf5cc5
AK		 4962static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4963{
5cb56059 4964 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4965}
4966
52eb5a6d
XL		 4967static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4968 unsigned long *dest)
bbd9b64e 4969{
16f8a6f9 4970 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4971}
4972
52eb5a6d
XL		 4973static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4974 unsigned long value)
bbd9b64e 4975{
338dbc97 4976
717746e3 4977 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4978}
4979
52a46617 4980static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4981{
52a46617 4982 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4983}
4984
717746e3 4985static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4986{
717746e3 4987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4988 unsigned long value;
4989
4990 switch (cr) {
4991 case 0:
4992 value = kvm_read_cr0(vcpu);
4993 break;
4994 case 2:
4995 value = vcpu->arch.cr2;
4996 break;
4997 case 3:
9f8fe504 4998 value = kvm_read_cr3(vcpu);
52a46617
GN		 4999 break;
5000 case 4:
5001 value = kvm_read_cr4(vcpu);
5002 break;
5003 case 8:
5004 value = kvm_get_cr8(vcpu);
5005 break;
5006 default:
a737f256 5007 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5008 return 0;
5009 }
5010
5011 return value;
5012}
5013
717746e3 5014static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5015{
717746e3 5016 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5017 int res = 0;
5018
52a46617
GN		 5019 switch (cr) {
5020 case 0:
49a9b07e 5021 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5022 break;
5023 case 2:
5024 vcpu->arch.cr2 = val;
5025 break;
5026 case 3:
2390218b 5027 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5028 break;
5029 case 4:
a83b29c6 5030 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5031 break;
5032 case 8:
eea1cff9 5033 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5034 break;
5035 default:
a737f256 5036 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5037 res = -1;
52a46617 5038 }
0f12244f
GN		 5039
5040 return res;
52a46617
GN		 5041}
5042
717746e3 5043static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5044{
717746e3 5045 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5046}
5047
4bff1e86 5048static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5049{
4bff1e86 5050 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5051}
5052
4bff1e86 5053static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5054{
4bff1e86 5055 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5056}
5057
1ac9d0cf
AK		 5058static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5059{
5060 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5061}
5062
5063static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5064{
5065 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5066}
5067
4bff1e86
AK		 5068static unsigned long emulator_get_cached_segment_base(
5069 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5070{
4bff1e86 5071 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5072}
5073
1aa36616
AK		 5074static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5075 struct desc_struct *desc, u32 *base3,
5076 int seg)
2dafc6c2
GN		 5077{
5078 struct kvm_segment var;
5079
4bff1e86 5080 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5081 *selector = var.selector;
2dafc6c2 5082
378a8b09
GN		 5083 if (var.unusable) {
5084 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5085 if (base3)
5086 *base3 = 0;
2dafc6c2 5087 return false;
378a8b09 5088 }
2dafc6c2
GN		 5089
5090 if (var.g)
5091 var.limit >>= 12;
5092 set_desc_limit(desc, var.limit);
5093 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5094#ifdef CONFIG_X86_64
5095 if (base3)
5096 *base3 = var.base >> 32;
5097#endif
2dafc6c2
GN		 5098 desc->type = var.type;
5099 desc->s = var.s;
5100 desc->dpl = var.dpl;
5101 desc->p = var.present;
5102 desc->avl = var.avl;
5103 desc->l = var.l;
5104 desc->d = var.db;
5105 desc->g = var.g;
5106
5107 return true;
5108}
5109
1aa36616
AK		 5110static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5111 struct desc_struct *desc, u32 base3,
5112 int seg)
2dafc6c2 5113{
4bff1e86 5114 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5115 struct kvm_segment var;
5116
1aa36616 5117 var.selector = selector;
2dafc6c2 5118 var.base = get_desc_base(desc);
5601d05b
GN		 5119#ifdef CONFIG_X86_64
5120 var.base |= ((u64)base3) << 32;
5121#endif
2dafc6c2
GN		 5122 var.limit = get_desc_limit(desc);
5123 if (desc->g)
5124 var.limit = (var.limit << 12) | 0xfff;
5125 var.type = desc->type;
2dafc6c2
GN		 5126 var.dpl = desc->dpl;
5127 var.db = desc->d;
5128 var.s = desc->s;
5129 var.l = desc->l;
5130 var.g = desc->g;
5131 var.avl = desc->avl;
5132 var.present = desc->p;
5133 var.unusable = !var.present;
5134 var.padding = 0;
5135
5136 kvm_set_segment(vcpu, &var, seg);
5137 return;
5138}
5139
717746e3
AK		 5140static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5141 u32 msr_index, u64 *pdata)
5142{
609e36d3
PB		 5143 struct msr_data msr;
5144 int r;
5145
5146 msr.index = msr_index;
5147 msr.host_initiated = false;
5148 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5149 if (r)
5150 return r;
5151
5152 *pdata = msr.data;
5153 return 0;
717746e3
AK		 5154}
5155
5156static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5157 u32 msr_index, u64 data)
5158{
8fe8ab46
WA		 5159 struct msr_data msr;
5160
5161 msr.data = data;
5162 msr.index = msr_index;
5163 msr.host_initiated = false;
5164 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5165}
5166
64d60670
PB		 5167static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5168{
5169 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5170
5171 return vcpu->arch.smbase;
5172}
5173
5174static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5175{
5176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5177
5178 vcpu->arch.smbase = smbase;
5179}
5180
67f4d428
NA		 5181static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5182 u32 pmc)
5183{
c6702c9d 5184 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5185}
5186
222d21aa
AK		 5187static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5188 u32 pmc, u64 *pdata)
5189{
c6702c9d 5190 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5191}
5192
6c3287f7
AK		 5193static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5194{
5195 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5196}
5197
5037f6f3
AK		 5198static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5199{
5200 preempt_disable();
5197b808 5201 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5202}
5203
5204static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5205{
5206 preempt_enable();
5207}
5208
2953538e 5209static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5210 struct x86_instruction_info *info,
c4f035c6
AK		 5211 enum x86_intercept_stage stage)
5212{
2953538e 5213 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5214}
5215
0017f93a 5216static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5217 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5218{
0017f93a 5219 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5220}
5221
dd856efa
AK		 5222static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5223{
5224 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5225}
5226
5227static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5228{
5229 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5230}
5231
801806d9
NA		 5232static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5233{
5234 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5235}
5236
6ed071f0
LP		 5237static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5238{
5239 return emul_to_vcpu(ctxt)->arch.hflags;
5240}
5241
5242static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5243{
5244 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5245}
5246
0225fb50 5247static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5248 .read_gpr = emulator_read_gpr,
5249 .write_gpr = emulator_write_gpr,
1871c602 5250 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5251 .write_std = kvm_write_guest_virt_system,
7a036a6f 5252 .read_phys = kvm_read_guest_phys_system,
1871c602 5253 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5254 .read_emulated = emulator_read_emulated,
5255 .write_emulated = emulator_write_emulated,
5256 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5257 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5258 .pio_in_emulated = emulator_pio_in_emulated,
5259 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5260 .get_segment = emulator_get_segment,
5261 .set_segment = emulator_set_segment,
5951c442 5262 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5263 .get_gdt = emulator_get_gdt,
160ce1f1 5264 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5265 .set_gdt = emulator_set_gdt,
5266 .set_idt = emulator_set_idt,
52a46617
GN		 5267 .get_cr = emulator_get_cr,
5268 .set_cr = emulator_set_cr,
9c537244 5269 .cpl = emulator_get_cpl,
35aa5375
GN		 5270 .get_dr = emulator_get_dr,
5271 .set_dr = emulator_set_dr,
64d60670
PB		 5272 .get_smbase = emulator_get_smbase,
5273 .set_smbase = emulator_set_smbase,
717746e3
AK		 5274 .set_msr = emulator_set_msr,
5275 .get_msr = emulator_get_msr,
67f4d428 5276 .check_pmc = emulator_check_pmc,
222d21aa 5277 .read_pmc = emulator_read_pmc,
6c3287f7 5278 .halt = emulator_halt,
bcaf5cc5 5279 .wbinvd = emulator_wbinvd,
d6aa1000 5280 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5281 .get_fpu = emulator_get_fpu,
5282 .put_fpu = emulator_put_fpu,
c4f035c6 5283 .intercept = emulator_intercept,
bdb42f5a 5284 .get_cpuid = emulator_get_cpuid,
801806d9 5285 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5286 .get_hflags = emulator_get_hflags,
5287 .set_hflags = emulator_set_hflags,
bbd9b64e
CO		 5288};
5289
95cb2295
GN		 5290static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5291{
37ccdcbe 5292 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5293 /*
5294 * an sti; sti; sequence only disable interrupts for the first
5295 * instruction. So, if the last instruction, be it emulated or
5296 * not, left the system with the INT_STI flag enabled, it
5297 * means that the last instruction is an sti. We should not
5298 * leave the flag on in this case. The same goes for mov ss
5299 */
37ccdcbe
PB		 5300 if (int_shadow & mask)
5301 mask = 0;
6addfc42 5302 if (unlikely(int_shadow || mask)) {
95cb2295 5303 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5304 if (!mask)
5305 kvm_make_request(KVM_REQ_EVENT, vcpu);
5306 }
95cb2295
GN		 5307}
5308
ef54bcfe 5309static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5310{
5311 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5312 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5313 return kvm_propagate_fault(vcpu, &ctxt->exception);
5314
5315 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5316 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5317 ctxt->exception.error_code);
54b8486f 5318 else
da9cb575 5319 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5320 return false;
54b8486f
GN		 5321}
5322
8ec4722d
MG		 5323static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5324{
adf52235 5325 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5326 int cs_db, cs_l;
5327
8ec4722d
MG		 5328 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5329
adf52235 5330 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5331 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5332
adf52235
TY		 5333 ctxt->eip = kvm_rip_read(vcpu);
5334 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5335 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5336 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5337 cs_db ? X86EMUL_MODE_PROT32 :
5338 X86EMUL_MODE_PROT16;
a584539b 5339 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5340 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5341 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5342
dd856efa 5343 init_decode_cache(ctxt);
7ae441ea 5344 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5345}
5346
71f9833b 5347int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5348{
9d74191a 5349 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5350 int ret;
5351
5352 init_emulate_ctxt(vcpu);
5353
9dac77fa
AK		 5354 ctxt->op_bytes = 2;
5355 ctxt->ad_bytes = 2;
5356 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5357 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5358
5359 if (ret != X86EMUL_CONTINUE)
5360 return EMULATE_FAIL;
5361
9dac77fa 5362 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5363 kvm_rip_write(vcpu, ctxt->eip);
5364 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5365
5366 if (irq == NMI_VECTOR)
7460fb4a 5367 vcpu->arch.nmi_pending = 0;
63995653
MG		 5368 else
5369 vcpu->arch.interrupt.pending = false;
5370
5371 return EMULATE_DONE;
5372}
5373EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5374
6d77dbfc
GN		 5375static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5376{
fc3a9157
JR		 5377 int r = EMULATE_DONE;
5378
6d77dbfc
GN		 5379 ++vcpu->stat.insn_emulation_fail;
5380 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5381 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5382 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5383 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5384 vcpu->run->internal.ndata = 0;
5385 r = EMULATE_FAIL;
5386 }
6d77dbfc 5387 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5388
5389 return r;
6d77dbfc
GN		 5390}
5391
93c05d3e 5392static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5393 bool write_fault_to_shadow_pgtable,
5394 int emulation_type)
a6f177ef 5395{
95b3cf69 5396 gpa_t gpa = cr2;
ba049e93 5397 kvm_pfn_t pfn;
a6f177ef 5398
991eebf9
GN		 5399 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5400 return false;
5401
95b3cf69
XG		 5402 if (!vcpu->arch.mmu.direct_map) {
5403 /*
5404 * Write permission should be allowed since only
5405 * write access need to be emulated.
5406 */
5407 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5408
95b3cf69
XG		 5409 /*
5410 * If the mapping is invalid in guest, let cpu retry
5411 * it to generate fault.
5412 */
5413 if (gpa == UNMAPPED_GVA)
5414 return true;
5415 }
a6f177ef 5416
8e3d9d06
XG		 5417 /*
5418 * Do not retry the unhandleable instruction if it faults on the
5419 * readonly host memory, otherwise it will goto a infinite loop:
5420 * retry instruction -> write #PF -> emulation fail -> retry
5421 * instruction -> ...
5422 */
5423 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5424
5425 /*
5426 * If the instruction failed on the error pfn, it can not be fixed,
5427 * report the error to userspace.
5428 */
5429 if (is_error_noslot_pfn(pfn))
5430 return false;
5431
5432 kvm_release_pfn_clean(pfn);
5433
5434 /* The instructions are well-emulated on direct mmu. */
5435 if (vcpu->arch.mmu.direct_map) {
5436 unsigned int indirect_shadow_pages;
5437
5438 spin_lock(&vcpu->kvm->mmu_lock);
5439 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5440 spin_unlock(&vcpu->kvm->mmu_lock);
5441
5442 if (indirect_shadow_pages)
5443 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5444
a6f177ef 5445 return true;
8e3d9d06 5446 }
a6f177ef 5447
95b3cf69
XG		 5448 /*
5449 * if emulation was due to access to shadowed page table
5450 * and it failed try to unshadow page and re-enter the
5451 * guest to let CPU execute the instruction.
5452 */
5453 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5454
5455 /*
5456 * If the access faults on its page table, it can not
5457 * be fixed by unprotecting shadow page and it should
5458 * be reported to userspace.
5459 */
5460 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5461}
5462
1cb3f3ae
XG		 5463static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5464 unsigned long cr2, int emulation_type)
5465{
5466 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5467 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5468
5469 last_retry_eip = vcpu->arch.last_retry_eip;
5470 last_retry_addr = vcpu->arch.last_retry_addr;
5471
5472 /*
5473 * If the emulation is caused by #PF and it is non-page_table
5474 * writing instruction, it means the VM-EXIT is caused by shadow
5475 * page protected, we can zap the shadow page and retry this
5476 * instruction directly.
5477 *
5478 * Note: if the guest uses a non-page-table modifying instruction
5479 * on the PDE that points to the instruction, then we will unmap
5480 * the instruction and go to an infinite loop. So, we cache the
5481 * last retried eip and the last fault address, if we meet the eip
5482 * and the address again, we can break out of the potential infinite
5483 * loop.
5484 */
5485 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5486
5487 if (!(emulation_type & EMULTYPE_RETRY))
5488 return false;
5489
5490 if (x86_page_table_writing_insn(ctxt))
5491 return false;
5492
5493 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5494 return false;
5495
5496 vcpu->arch.last_retry_eip = ctxt->eip;
5497 vcpu->arch.last_retry_addr = cr2;
5498
5499 if (!vcpu->arch.mmu.direct_map)
5500 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5501
22368028 5502 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5503
5504 return true;
5505}
5506
716d51ab
GN		 5507static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5508static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5509
64d60670 5510static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5511{
64d60670 5512 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5513 /* This is a good place to trace that we are exiting SMM. */
5514 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5515
c43203ca
PB		 5516 /* Process a latched INIT or SMI, if any. */
5517 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5518 }
699023e2
PB		 5519
5520 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5521}
5522
5523static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5524{
5525 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5526
a584539b 5527 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5528
5529 if (changed & HF_SMM_MASK)
5530 kvm_smm_changed(vcpu);
a584539b
PB		 5531}
5532
4a1e10d5
PB		 5533static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5534 unsigned long *db)
5535{
5536 u32 dr6 = 0;
5537 int i;
5538 u32 enable, rwlen;
5539
5540 enable = dr7;
5541 rwlen = dr7 >> 16;
5542 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5543 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5544 dr6 |= (1 << i);
5545 return dr6;
5546}
5547
c8401dda 5548static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5549{
5550 struct kvm_run *kvm_run = vcpu->run;
5551
c8401dda
PB		 5552 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5553 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5554 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5555 kvm_run->debug.arch.exception = DB_VECTOR;
5556 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5557 *r = EMULATE_USER_EXIT;
5558 } else {
5559 /*
5560 * "Certain debug exceptions may clear bit 0-3. The
5561 * remaining contents of the DR6 register are never
5562 * cleared by the processor".
5563 */
5564 vcpu->arch.dr6 &= ~15;
5565 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5566 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5567 }
5568}
5569
6affcbed
KH		 5570int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5571{
5572 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5573 int r = EMULATE_DONE;
5574
5575 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5576
5577 /*
5578 * rflags is the old, "raw" value of the flags. The new value has
5579 * not been saved yet.
5580 *
5581 * This is correct even for TF set by the guest, because "the
5582 * processor will not generate this exception after the instruction
5583 * that sets the TF flag".
5584 */
5585 if (unlikely(rflags & X86_EFLAGS_TF))
5586 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5587 return r == EMULATE_DONE;
5588}
5589EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5590
4a1e10d5
PB		 5591static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5592{
4a1e10d5
PB		 5593 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5594 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5595 struct kvm_run *kvm_run = vcpu->run;
5596 unsigned long eip = kvm_get_linear_rip(vcpu);
5597 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5598 vcpu->arch.guest_debug_dr7,
5599 vcpu->arch.eff_db);
5600
5601 if (dr6 != 0) {
6f43ed01 5602 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5603 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5604 kvm_run->debug.arch.exception = DB_VECTOR;
5605 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5606 *r = EMULATE_USER_EXIT;
5607 return true;
5608 }
5609 }
5610
4161a569
NA		 5611 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5612 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5613 unsigned long eip = kvm_get_linear_rip(vcpu);
5614 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5615 vcpu->arch.dr7,
5616 vcpu->arch.db);
5617
5618 if (dr6 != 0) {
5619 vcpu->arch.dr6 &= ~15;
6f43ed01 5620 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5621 kvm_queue_exception(vcpu, DB_VECTOR);
5622 *r = EMULATE_DONE;
5623 return true;
5624 }
5625 }
5626
5627 return false;
5628}
5629
51d8b661
AP		 5630int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5631 unsigned long cr2,
dc25e89e
AP		 5632 int emulation_type,
5633 void *insn,
5634 int insn_len)
bbd9b64e 5635{
95cb2295 5636 int r;
9d74191a 5637 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5638 bool writeback = true;
93c05d3e 5639 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5640
93c05d3e
XG		 5641 /*
5642 * Clear write_fault_to_shadow_pgtable here to ensure it is
5643 * never reused.
5644 */
5645 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5646 kvm_clear_exception_queue(vcpu);
8d7d8102 5647
571008da 5648 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5649 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5650
5651 /*
5652 * We will reenter on the same instruction since
5653 * we do not set complete_userspace_io. This does not
5654 * handle watchpoints yet, those would be handled in
5655 * the emulate_ops.
5656 */
5657 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5658 return r;
5659
9d74191a
TY		 5660 ctxt->interruptibility = 0;
5661 ctxt->have_exception = false;
e0ad0b47 5662 ctxt->exception.vector = -1;
9d74191a 5663 ctxt->perm_ok = false;
bbd9b64e 5664
b51e974f 5665 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5666
9d74191a 5667 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5668
e46479f8 5669 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5670 ++vcpu->stat.insn_emulation;
1d2887e2 5671 if (r != EMULATION_OK) {
4005996e
AK		 5672 if (emulation_type & EMULTYPE_TRAP_UD)
5673 return EMULATE_FAIL;
991eebf9
GN		 5674 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5675 emulation_type))
bbd9b64e 5676 return EMULATE_DONE;
6d77dbfc
GN		 5677 if (emulation_type & EMULTYPE_SKIP)
5678 return EMULATE_FAIL;
5679 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5680 }
5681 }
5682
ba8afb6b 5683 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5684 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5685 if (ctxt->eflags & X86_EFLAGS_RF)
5686 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5687 return EMULATE_DONE;
5688 }
5689
1cb3f3ae
XG		 5690 if (retry_instruction(ctxt, cr2, emulation_type))
5691 return EMULATE_DONE;
5692
7ae441ea 5693 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5694 changes registers values during IO operation */
7ae441ea
GN		 5695 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5696 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5697 emulator_invalidate_register_cache(ctxt);
7ae441ea 5698 }
4d2179e1 5699
5cd21917 5700restart:
0f89b207
TL		 5701 /* Save the faulting GPA (cr2) in the address field */
5702 ctxt->exception.address = cr2;
5703
9d74191a 5704 r = x86_emulate_insn(ctxt);
bbd9b64e 5705
775fde86
JR		 5706 if (r == EMULATION_INTERCEPTED)
5707 return EMULATE_DONE;
5708
d2ddd1c4 5709 if (r == EMULATION_FAILED) {
991eebf9
GN		 5710 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5711 emulation_type))
c3cd7ffa
GN		 5712 return EMULATE_DONE;
5713
6d77dbfc 5714 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5715 }
5716
9d74191a 5717 if (ctxt->have_exception) {
d2ddd1c4 5718 r = EMULATE_DONE;
ef54bcfe
PB		 5719 if (inject_emulated_exception(vcpu))
5720 return r;
d2ddd1c4 5721 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5722 if (!vcpu->arch.pio.in) {
5723 /* FIXME: return into emulator if single-stepping. */
3457e419 5724 vcpu->arch.pio.count = 0;
0912c977 5725 } else {
7ae441ea 5726 writeback = false;
716d51ab
GN		 5727 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5728 }
ac0a48c3 5729 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5730 } else if (vcpu->mmio_needed) {
5731 if (!vcpu->mmio_is_write)
5732 writeback = false;
ac0a48c3 5733 r = EMULATE_USER_EXIT;
716d51ab 5734 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5735 } else if (r == EMULATION_RESTART)
5cd21917 5736 goto restart;
d2ddd1c4
GN		 5737 else
5738 r = EMULATE_DONE;
f850e2e6 5739
7ae441ea 5740 if (writeback) {
6addfc42 5741 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5742 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5743 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5744 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5745 if (r == EMULATE_DONE &&
5746 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5747 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5748 if (!ctxt->have_exception ||
5749 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5750 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5751
5752 /*
5753 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5754 * do nothing, and it will be requested again as soon as
5755 * the shadow expires. But we still need to check here,
5756 * because POPF has no interrupt shadow.
5757 */
5758 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5759 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5760 } else
5761 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5762
5763 return r;
de7d789a 5764}
51d8b661 5765EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5766
cf8f70bf 5767int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5768{
cf8f70bf 5769 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5770 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5771 size, port, &val, 1);
cf8f70bf 5772 /* do not return to emulator after return from userspace */
7972995b 5773 vcpu->arch.pio.count = 0;
de7d789a
CO		 5774 return ret;
5775}
cf8f70bf 5776EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5777
8370c3d0
TL		 5778static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5779{
5780 unsigned long val;
5781
5782 /* We should only ever be called with arch.pio.count equal to 1 */
5783 BUG_ON(vcpu->arch.pio.count != 1);
5784
5785 /* For size less than 4 we merge, else we zero extend */
5786 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5787 : 0;
5788
5789 /*
5790 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5791 * the copy and tracing
5792 */
5793 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5794 vcpu->arch.pio.port, &val, 1);
5795 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5796
5797 return 1;
5798}
5799
5800int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5801{
5802 unsigned long val;
5803 int ret;
5804
5805 /* For size less than 4 we merge, else we zero extend */
5806 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5807
5808 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5809 &val, 1);
5810 if (ret) {
5811 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5812 return ret;
5813 }
5814
5815 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5816
5817 return 0;
5818}
5819EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5820
251a5fd6 5821static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5822{
0a3aee0d 5823 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5824 return 0;
8cfdc000
ZA		 5825}
5826
5827static void tsc_khz_changed(void *data)
c8076604 5828{
8cfdc000
ZA		 5829 struct cpufreq_freqs *freq = data;
5830 unsigned long khz = 0;
5831
5832 if (data)
5833 khz = freq->new;
5834 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5835 khz = cpufreq_quick_get(raw_smp_processor_id());
5836 if (!khz)
5837 khz = tsc_khz;
0a3aee0d 5838 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5839}
5840
c8076604
GH		 5841static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5842 void *data)
5843{
5844 struct cpufreq_freqs *freq = data;
5845 struct kvm *kvm;
5846 struct kvm_vcpu *vcpu;
5847 int i, send_ipi = 0;
5848
8cfdc000
ZA		 5849 /*
5850 * We allow guests to temporarily run on slowing clocks,
5851 * provided we notify them after, or to run on accelerating
5852 * clocks, provided we notify them before. Thus time never
5853 * goes backwards.
5854 *
5855 * However, we have a problem. We can't atomically update
5856 * the frequency of a given CPU from this function; it is
5857 * merely a notifier, which can be called from any CPU.
5858 * Changing the TSC frequency at arbitrary points in time
5859 * requires a recomputation of local variables related to
5860 * the TSC for each VCPU. We must flag these local variables
5861 * to be updated and be sure the update takes place with the
5862 * new frequency before any guests proceed.
5863 *
5864 * Unfortunately, the combination of hotplug CPU and frequency
5865 * change creates an intractable locking scenario; the order
5866 * of when these callouts happen is undefined with respect to
5867 * CPU hotplug, and they can race with each other. As such,
5868 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5869 * undefined; you can actually have a CPU frequency change take
5870 * place in between the computation of X and the setting of the
5871 * variable. To protect against this problem, all updates of
5872 * the per_cpu tsc_khz variable are done in an interrupt
5873 * protected IPI, and all callers wishing to update the value
5874 * must wait for a synchronous IPI to complete (which is trivial
5875 * if the caller is on the CPU already). This establishes the
5876 * necessary total order on variable updates.
5877 *
5878 * Note that because a guest time update may take place
5879 * anytime after the setting of the VCPU's request bit, the
5880 * correct TSC value must be set before the request. However,
5881 * to ensure the update actually makes it to any guest which
5882 * starts running in hardware virtualization between the set
5883 * and the acquisition of the spinlock, we must also ping the
5884 * CPU after setting the request bit.
5885 *
5886 */
5887
c8076604
GH		 5888 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5889 return 0;
5890 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5891 return 0;
8cfdc000
ZA		 5892
5893 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5894
2f303b74 5895 spin_lock(&kvm_lock);
c8076604 5896 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5897 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5898 if (vcpu->cpu != freq->cpu)
5899 continue;
c285545f 5900 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5901 if (vcpu->cpu != smp_processor_id())
8cfdc000 5902 send_ipi = 1;
c8076604
GH		 5903 }
5904 }
2f303b74 5905 spin_unlock(&kvm_lock);
c8076604
GH		 5906
5907 if (freq->old < freq->new && send_ipi) {
5908 /*
5909 * We upscale the frequency. Must make the guest
5910 * doesn't see old kvmclock values while running with
5911 * the new frequency, otherwise we risk the guest sees
5912 * time go backwards.
5913 *
5914 * In case we update the frequency for another cpu
5915 * (which might be in guest context) send an interrupt
5916 * to kick the cpu out of guest context. Next time
5917 * guest context is entered kvmclock will be updated,
5918 * so the guest will not see stale values.
5919 */
8cfdc000 5920 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5921 }
5922 return 0;
5923}
5924
5925static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5926 .notifier_call = kvmclock_cpufreq_notifier
5927};
5928
251a5fd6 5929static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5930{
251a5fd6
SAS		 5931 tsc_khz_changed(NULL);
5932 return 0;
8cfdc000
ZA		 5933}
5934
b820cc0c
ZA		 5935static void kvm_timer_init(void)
5936{
c285545f 5937 max_tsc_khz = tsc_khz;
460dd42e 5938
b820cc0c 5939 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5940#ifdef CONFIG_CPU_FREQ
5941 struct cpufreq_policy policy;
758f588d
BP		 5942 int cpu;
5943
c285545f 5944 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5945 cpu = get_cpu();
5946 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5947 if (policy.cpuinfo.max_freq)
5948 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5949 put_cpu();
c285545f 5950#endif
b820cc0c
ZA		 5951 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5952 CPUFREQ_TRANSITION_NOTIFIER);
5953 }
c285545f 5954 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5955
73c1b41e 5956 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5957 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5958}
5959
ff9d07a0
ZY		 5960static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5961
f5132b01 5962int kvm_is_in_guest(void)
ff9d07a0 5963{
086c9855 5964 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5965}
5966
5967static int kvm_is_user_mode(void)
5968{
5969 int user_mode = 3;
dcf46b94 5970
086c9855
AS		 5971 if (__this_cpu_read(current_vcpu))
5972 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5973
ff9d07a0
ZY		 5974 return user_mode != 0;
5975}
5976
5977static unsigned long kvm_get_guest_ip(void)
5978{
5979 unsigned long ip = 0;
dcf46b94 5980
086c9855
AS		 5981 if (__this_cpu_read(current_vcpu))
5982 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5983
ff9d07a0
ZY		 5984 return ip;
5985}
5986
5987static struct perf_guest_info_callbacks kvm_guest_cbs = {
5988 .is_in_guest = kvm_is_in_guest,
5989 .is_user_mode = kvm_is_user_mode,
5990 .get_guest_ip = kvm_get_guest_ip,
5991};
5992
5993void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5994{
086c9855 5995 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5996}
5997EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5998
5999void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6000{
086c9855 6001 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6002}
6003EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6004
ce88decf
XG		 6005static void kvm_set_mmio_spte_mask(void)
6006{
6007 u64 mask;
6008 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6009
6010 /*
6011 * Set the reserved bits and the present bit of an paging-structure
6012 * entry to generate page fault with PFER.RSV = 1.
6013 */
885032b9 6014 /* Mask the reserved physical address bits. */
d1431483 6015 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6016
885032b9 6017 /* Set the present bit. */
ce88decf
XG		 6018 mask |= 1ull;
6019
6020#ifdef CONFIG_X86_64
6021 /*
6022 * If reserved bit is not supported, clear the present bit to disable
6023 * mmio page fault.
6024 */
6025 if (maxphyaddr == 52)
6026 mask &= ~1ull;
6027#endif
6028
dcdca5fe 6029 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6030}
6031
16e8d74d
MT		 6032#ifdef CONFIG_X86_64
6033static void pvclock_gtod_update_fn(struct work_struct *work)
6034{
d828199e
MT		 6035 struct kvm *kvm;
6036
6037 struct kvm_vcpu *vcpu;
6038 int i;
6039
2f303b74 6040 spin_lock(&kvm_lock);
d828199e
MT		 6041 list_for_each_entry(kvm, &vm_list, vm_list)
6042 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6043 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6044 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6045 spin_unlock(&kvm_lock);
16e8d74d
MT		 6046}
6047
6048static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6049
6050/*
6051 * Notification about pvclock gtod data update.
6052 */
6053static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6054 void *priv)
6055{
6056 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6057 struct timekeeper *tk = priv;
6058
6059 update_pvclock_gtod(tk);
6060
6061 /* disable master clock if host does not trust, or does not
6062 * use, TSC clocksource
6063 */
6064 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6065 atomic_read(&kvm_guest_has_master_clock) != 0)
6066 queue_work(system_long_wq, &pvclock_gtod_work);
6067
6068 return 0;
6069}
6070
6071static struct notifier_block pvclock_gtod_notifier = {
6072 .notifier_call = pvclock_gtod_notify,
6073};
6074#endif
6075
f8c16bba 6076int kvm_arch_init(void *opaque)
043405e1 6077{
b820cc0c 6078 int r;
6b61edf7 6079 struct kvm_x86_ops *ops = opaque;
f8c16bba 6080
f8c16bba
ZX		 6081 if (kvm_x86_ops) {
6082 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6083 r = -EEXIST;
6084 goto out;
f8c16bba
ZX		 6085 }
6086
6087 if (!ops->cpu_has_kvm_support()) {
6088 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6089 r = -EOPNOTSUPP;
6090 goto out;
f8c16bba
ZX		 6091 }
6092 if (ops->disabled_by_bios()) {
6093 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6094 r = -EOPNOTSUPP;
6095 goto out;
f8c16bba
ZX		 6096 }
6097
013f6a5d
MT		 6098 r = -ENOMEM;
6099 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6100 if (!shared_msrs) {
6101 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6102 goto out;
6103 }
6104
97db56ce
AK		 6105 r = kvm_mmu_module_init();
6106 if (r)
013f6a5d 6107 goto out_free_percpu;
97db56ce 6108
ce88decf 6109 kvm_set_mmio_spte_mask();
97db56ce 6110
f8c16bba 6111 kvm_x86_ops = ops;
920c8377 6112
7b52345e 6113 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6114 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6115 PT_PRESENT_MASK, 0);
b820cc0c 6116 kvm_timer_init();
c8076604 6117
ff9d07a0
ZY		 6118 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6119
d366bf7e 6120 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6121 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6122
c5cc421b 6123 kvm_lapic_init();
16e8d74d
MT		 6124#ifdef CONFIG_X86_64
6125 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6126#endif
6127
f8c16bba 6128 return 0;
56c6d28a 6129
013f6a5d
MT		 6130out_free_percpu:
6131 free_percpu(shared_msrs);
56c6d28a 6132out:
56c6d28a 6133 return r;
043405e1 6134}
8776e519 6135
f8c16bba
ZX		 6136void kvm_arch_exit(void)
6137{
cef84c30 6138 kvm_lapic_exit();
ff9d07a0
ZY		 6139 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6140
888d256e
JK		 6141 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6142 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6143 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6144 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6145#ifdef CONFIG_X86_64
6146 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6147#endif
f8c16bba 6148 kvm_x86_ops = NULL;
56c6d28a 6149 kvm_mmu_module_exit();
013f6a5d 6150 free_percpu(shared_msrs);
56c6d28a 6151}
f8c16bba 6152
5cb56059 6153int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6154{
6155 ++vcpu->stat.halt_exits;
35754c98 6156 if (lapic_in_kernel(vcpu)) {
a4535290 6157 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6158 return 1;
6159 } else {
6160 vcpu->run->exit_reason = KVM_EXIT_HLT;
6161 return 0;
6162 }
6163}
5cb56059
JS		 6164EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6165
6166int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6167{
6affcbed
KH		 6168 int ret = kvm_skip_emulated_instruction(vcpu);
6169 /*
6170 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6171 * KVM_EXIT_DEBUG here.
6172 */
6173 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6174}
8776e519
HB		 6175EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6176
8ef81a9a 6177#ifdef CONFIG_X86_64
55dd00a7
MT		 6178static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6179 unsigned long clock_type)
6180{
6181 struct kvm_clock_pairing clock_pairing;
6182 struct timespec ts;
80fbd89c 6183 u64 cycle;
55dd00a7
MT		 6184 int ret;
6185
6186 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6187 return -KVM_EOPNOTSUPP;
6188
6189 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6190 return -KVM_EOPNOTSUPP;
6191
6192 clock_pairing.sec = ts.tv_sec;
6193 clock_pairing.nsec = ts.tv_nsec;
6194 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6195 clock_pairing.flags = 0;
6196
6197 ret = 0;
6198 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6199 sizeof(struct kvm_clock_pairing)))
6200 ret = -KVM_EFAULT;
6201
6202 return ret;
6203}
8ef81a9a 6204#endif
55dd00a7 6205
6aef266c
SV		 6206/*
6207 * kvm_pv_kick_cpu_op: Kick a vcpu.
6208 *
6209 * @apicid - apicid of vcpu to be kicked.
6210 */
6211static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6212{
24d2166b 6213 struct kvm_lapic_irq lapic_irq;
6aef266c 6214
24d2166b
R		 6215 lapic_irq.shorthand = 0;
6216 lapic_irq.dest_mode = 0;
ebd28fcb 6217 lapic_irq.level = 0;
24d2166b 6218 lapic_irq.dest_id = apicid;
93bbf0b8 6219 lapic_irq.msi_redir_hint = false;
6aef266c 6220
24d2166b 6221 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6222 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6223}
6224
d62caabb
AS		 6225void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6226{
6227 vcpu->arch.apicv_active = false;
6228 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6229}
6230
8776e519
HB		 6231int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6232{
6233 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6234 int op_64_bit, r;
8776e519 6235
6affcbed 6236 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6237
55cd8e5a
GN		 6238 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6239 return kvm_hv_hypercall(vcpu);
6240
5fdbf976
MT		 6241 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6242 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6243 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6244 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6245 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6246
229456fc 6247 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6248
a449c7aa
NA		 6249 op_64_bit = is_64_bit_mode(vcpu);
6250 if (!op_64_bit) {
8776e519
HB		 6251 nr &= 0xFFFFFFFF;
6252 a0 &= 0xFFFFFFFF;
6253 a1 &= 0xFFFFFFFF;
6254 a2 &= 0xFFFFFFFF;
6255 a3 &= 0xFFFFFFFF;
6256 }
6257
07708c4a
JK		 6258 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6259 ret = -KVM_EPERM;
6260 goto out;
6261 }
6262
8776e519 6263 switch (nr) {
b93463aa
AK		 6264 case KVM_HC_VAPIC_POLL_IRQ:
6265 ret = 0;
6266 break;
6aef266c
SV		 6267 case KVM_HC_KICK_CPU:
6268 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6269 ret = 0;
6270 break;
8ef81a9a 6271#ifdef CONFIG_X86_64
55dd00a7
MT		 6272 case KVM_HC_CLOCK_PAIRING:
6273 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6274 break;
8ef81a9a 6275#endif
8776e519
HB		 6276 default:
6277 ret = -KVM_ENOSYS;
6278 break;
6279 }
07708c4a 6280out:
a449c7aa
NA		 6281 if (!op_64_bit)
6282 ret = (u32)ret;
5fdbf976 6283 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6284 ++vcpu->stat.hypercalls;
2f333bcb 6285 return r;
8776e519
HB		 6286}
6287EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6288
b6785def 6289static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6290{
d6aa1000 6291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6292 char instruction[3];
5fdbf976 6293 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6294
8776e519 6295 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6296
ce2e852e
DV		 6297 return emulator_write_emulated(ctxt, rip, instruction, 3,
6298 &ctxt->exception);
8776e519
HB		 6299}
6300
851ba692 6301static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6302{
782d422b
MG		 6303 return vcpu->run->request_interrupt_window &&
6304 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6305}
6306
851ba692 6307static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6308{
851ba692
AK		 6309 struct kvm_run *kvm_run = vcpu->run;
6310
91586a3b 6311 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6312 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6313 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6314 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6315 kvm_run->ready_for_interrupt_injection =
6316 pic_in_kernel(vcpu->kvm) ||
782d422b 6317 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6318}
6319
95ba8273
GN		 6320static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6321{
6322 int max_irr, tpr;
6323
6324 if (!kvm_x86_ops->update_cr8_intercept)
6325 return;
6326
bce87cce 6327 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6328 return;
6329
d62caabb
AS		 6330 if (vcpu->arch.apicv_active)
6331 return;
6332
8db3baa2
GN		 6333 if (!vcpu->arch.apic->vapic_addr)
6334 max_irr = kvm_lapic_find_highest_irr(vcpu);
6335 else
6336 max_irr = -1;
95ba8273
GN		 6337
6338 if (max_irr != -1)
6339 max_irr >>= 4;
6340
6341 tpr = kvm_lapic_get_cr8(vcpu);
6342
6343 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6344}
6345
b6b8a145 6346static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6347{
b6b8a145
JK		 6348 int r;
6349
95ba8273 6350 /* try to reinject previous events if any */
b59bb7bd 6351 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6352 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6353 vcpu->arch.exception.has_error_code,
6354 vcpu->arch.exception.error_code);
d6e8c854
NA		 6355
6356 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6357 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6358 X86_EFLAGS_RF);
6359
6bdf0662
NA		 6360 if (vcpu->arch.exception.nr == DB_VECTOR &&
6361 (vcpu->arch.dr7 & DR7_GD)) {
6362 vcpu->arch.dr7 &= ~DR7_GD;
6363 kvm_update_dr7(vcpu);
6364 }
6365
cfcd20e5 6366 kvm_x86_ops->queue_exception(vcpu);
b6b8a145 6367 return 0;
b59bb7bd
GN		 6368 }
6369
95ba8273
GN		 6370 if (vcpu->arch.nmi_injected) {
6371 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6372 return 0;
95ba8273
GN		 6373 }
6374
6375 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6376 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6377 return 0;
6378 }
6379
6380 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6381 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6382 if (r != 0)
6383 return r;
95ba8273
GN		 6384 }
6385
6386 /* try to inject new event if pending */
c43203ca
PB		 6387 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6388 vcpu->arch.smi_pending = false;
ee2cd4b7 6389 enter_smm(vcpu);
c43203ca 6390 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6391 --vcpu->arch.nmi_pending;
6392 vcpu->arch.nmi_injected = true;
6393 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6394 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6395 /*
6396 * Because interrupts can be injected asynchronously, we are
6397 * calling check_nested_events again here to avoid a race condition.
6398 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6399 * proposal and current concerns. Perhaps we should be setting
6400 * KVM_REQ_EVENT only on certain events and not unconditionally?
6401 */
6402 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6403 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6404 if (r != 0)
6405 return r;
6406 }
95ba8273 6407 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6408 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6409 false);
6410 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6411 }
6412 }
ee2cd4b7 6413
b6b8a145 6414 return 0;
95ba8273
GN		 6415}
6416
7460fb4a
AK		 6417static void process_nmi(struct kvm_vcpu *vcpu)
6418{
6419 unsigned limit = 2;
6420
6421 /*
6422 * x86 is limited to one NMI running, and one NMI pending after it.
6423 * If an NMI is already in progress, limit further NMIs to just one.
6424 * Otherwise, allow two (and we'll inject the first one immediately).
6425 */
6426 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6427 limit = 1;
6428
6429 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6430 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6431 kvm_make_request(KVM_REQ_EVENT, vcpu);
6432}
6433
660a5d51
PB		 6434#define put_smstate(type, buf, offset, val) \
6435 *(type *)((buf) + (offset) - 0x7e00) = val
6436
ee2cd4b7 6437static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6438{
6439 u32 flags = 0;
6440 flags |= seg->g << 23;
6441 flags |= seg->db << 22;
6442 flags |= seg->l << 21;
6443 flags |= seg->avl << 20;
6444 flags |= seg->present << 15;
6445 flags |= seg->dpl << 13;
6446 flags |= seg->s << 12;
6447 flags |= seg->type << 8;
6448 return flags;
6449}
6450
ee2cd4b7 6451static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6452{
6453 struct kvm_segment seg;
6454 int offset;
6455
6456 kvm_get_segment(vcpu, &seg, n);
6457 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6458
6459 if (n < 3)
6460 offset = 0x7f84 + n * 12;
6461 else
6462 offset = 0x7f2c + (n - 3) * 12;
6463
6464 put_smstate(u32, buf, offset + 8, seg.base);
6465 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6466 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6467}
6468
efbb288a 6469#ifdef CONFIG_X86_64
ee2cd4b7 6470static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6471{
6472 struct kvm_segment seg;
6473 int offset;
6474 u16 flags;
6475
6476 kvm_get_segment(vcpu, &seg, n);
6477 offset = 0x7e00 + n * 16;
6478
ee2cd4b7 6479 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6480 put_smstate(u16, buf, offset, seg.selector);
6481 put_smstate(u16, buf, offset + 2, flags);
6482 put_smstate(u32, buf, offset + 4, seg.limit);
6483 put_smstate(u64, buf, offset + 8, seg.base);
6484}
efbb288a 6485#endif
660a5d51 6486
ee2cd4b7 6487static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6488{
6489 struct desc_ptr dt;
6490 struct kvm_segment seg;
6491 unsigned long val;
6492 int i;
6493
6494 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6495 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6496 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6497 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6498
6499 for (i = 0; i < 8; i++)
6500 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6501
6502 kvm_get_dr(vcpu, 6, &val);
6503 put_smstate(u32, buf, 0x7fcc, (u32)val);
6504 kvm_get_dr(vcpu, 7, &val);
6505 put_smstate(u32, buf, 0x7fc8, (u32)val);
6506
6507 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6508 put_smstate(u32, buf, 0x7fc4, seg.selector);
6509 put_smstate(u32, buf, 0x7f64, seg.base);
6510 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6511 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6512
6513 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6514 put_smstate(u32, buf, 0x7fc0, seg.selector);
6515 put_smstate(u32, buf, 0x7f80, seg.base);
6516 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6517 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6518
6519 kvm_x86_ops->get_gdt(vcpu, &dt);
6520 put_smstate(u32, buf, 0x7f74, dt.address);
6521 put_smstate(u32, buf, 0x7f70, dt.size);
6522
6523 kvm_x86_ops->get_idt(vcpu, &dt);
6524 put_smstate(u32, buf, 0x7f58, dt.address);
6525 put_smstate(u32, buf, 0x7f54, dt.size);
6526
6527 for (i = 0; i < 6; i++)
ee2cd4b7 6528 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6529
6530 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6531
6532 /* revision id */
6533 put_smstate(u32, buf, 0x7efc, 0x00020000);
6534 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6535}
6536
ee2cd4b7 6537static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6538{
6539#ifdef CONFIG_X86_64
6540 struct desc_ptr dt;
6541 struct kvm_segment seg;
6542 unsigned long val;
6543 int i;
6544
6545 for (i = 0; i < 16; i++)
6546 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6547
6548 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6549 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6550
6551 kvm_get_dr(vcpu, 6, &val);
6552 put_smstate(u64, buf, 0x7f68, val);
6553 kvm_get_dr(vcpu, 7, &val);
6554 put_smstate(u64, buf, 0x7f60, val);
6555
6556 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6557 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6558 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6559
6560 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6561
6562 /* revision id */
6563 put_smstate(u32, buf, 0x7efc, 0x00020064);
6564
6565 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6566
6567 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6568 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6569 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6570 put_smstate(u32, buf, 0x7e94, seg.limit);
6571 put_smstate(u64, buf, 0x7e98, seg.base);
6572
6573 kvm_x86_ops->get_idt(vcpu, &dt);
6574 put_smstate(u32, buf, 0x7e84, dt.size);
6575 put_smstate(u64, buf, 0x7e88, dt.address);
6576
6577 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6578 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6579 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6580 put_smstate(u32, buf, 0x7e74, seg.limit);
6581 put_smstate(u64, buf, 0x7e78, seg.base);
6582
6583 kvm_x86_ops->get_gdt(vcpu, &dt);
6584 put_smstate(u32, buf, 0x7e64, dt.size);
6585 put_smstate(u64, buf, 0x7e68, dt.address);
6586
6587 for (i = 0; i < 6; i++)
ee2cd4b7 6588 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6589#else
6590 WARN_ON_ONCE(1);
6591#endif
6592}
6593
ee2cd4b7 6594static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6595{
660a5d51 6596 struct kvm_segment cs, ds;
18c3626e 6597 struct desc_ptr dt;
660a5d51
PB		 6598 char buf[512];
6599 u32 cr0;
6600
660a5d51
PB		 6601 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6602 vcpu->arch.hflags |= HF_SMM_MASK;
6603 memset(buf, 0, 512);
d6321d49 6604 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6605 enter_smm_save_state_64(vcpu, buf);
660a5d51 6606 else
ee2cd4b7 6607 enter_smm_save_state_32(vcpu, buf);
660a5d51 6608
54bf36aa 6609 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6610
6611 if (kvm_x86_ops->get_nmi_mask(vcpu))
6612 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6613 else
6614 kvm_x86_ops->set_nmi_mask(vcpu, true);
6615
6616 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6617 kvm_rip_write(vcpu, 0x8000);
6618
6619 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6620 kvm_x86_ops->set_cr0(vcpu, cr0);
6621 vcpu->arch.cr0 = cr0;
6622
6623 kvm_x86_ops->set_cr4(vcpu, 0);
6624
18c3626e
PB		 6625 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6626 dt.address = dt.size = 0;
6627 kvm_x86_ops->set_idt(vcpu, &dt);
6628
660a5d51
PB		 6629 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6630
6631 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6632 cs.base = vcpu->arch.smbase;
6633
6634 ds.selector = 0;
6635 ds.base = 0;
6636
6637 cs.limit = ds.limit = 0xffffffff;
6638 cs.type = ds.type = 0x3;
6639 cs.dpl = ds.dpl = 0;
6640 cs.db = ds.db = 0;
6641 cs.s = ds.s = 1;
6642 cs.l = ds.l = 0;
6643 cs.g = ds.g = 1;
6644 cs.avl = ds.avl = 0;
6645 cs.present = ds.present = 1;
6646 cs.unusable = ds.unusable = 0;
6647 cs.padding = ds.padding = 0;
6648
6649 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6650 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6651 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6652 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6653 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6654 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6655
d6321d49 6656 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6657 kvm_x86_ops->set_efer(vcpu, 0);
6658
6659 kvm_update_cpuid(vcpu);
6660 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6661}
6662
ee2cd4b7 6663static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6664{
6665 vcpu->arch.smi_pending = true;
6666 kvm_make_request(KVM_REQ_EVENT, vcpu);
6667}
6668
2860c4b1
PB		 6669void kvm_make_scan_ioapic_request(struct kvm *kvm)
6670{
6671 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6672}
6673
3d81bc7e 6674static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6675{
5c919412
AS		 6676 u64 eoi_exit_bitmap[4];
6677
3d81bc7e
YZ		 6678 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6679 return;
c7c9c56c 6680
6308630b 6681 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6682
b053b2ae 6683 if (irqchip_split(vcpu->kvm))
6308630b 6684 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6685 else {
76dfafd5 6686 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6687 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6688 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6689 }
5c919412
AS		 6690 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6691 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6692 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6693}
6694
a70656b6
RK		 6695static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6696{
6697 ++vcpu->stat.tlb_flush;
6698 kvm_x86_ops->tlb_flush(vcpu);
6699}
6700
4256f43f
TC		 6701void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6702{
c24ae0dc
TC		 6703 struct page *page = NULL;
6704
35754c98 6705 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6706 return;
6707
4256f43f
TC		 6708 if (!kvm_x86_ops->set_apic_access_page_addr)
6709 return;
6710
c24ae0dc 6711 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6712 if (is_error_page(page))
6713 return;
c24ae0dc
TC		 6714 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6715
6716 /*
6717 * Do not pin apic access page in memory, the MMU notifier
6718 * will call us again if it is migrated or swapped out.
6719 */
6720 put_page(page);
4256f43f
TC		 6721}
6722EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6723
fe71557a
TC		 6724void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6725 unsigned long address)
6726{
c24ae0dc
TC		 6727 /*
6728 * The physical address of apic access page is stored in the VMCS.
6729 * Update it when it becomes invalid.
6730 */
6731 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6732 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6733}
6734
9357d939 6735/*
362c698f 6736 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6737 * exiting to the userspace. Otherwise, the value will be returned to the
6738 * userspace.
6739 */
851ba692 6740static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6741{
6742 int r;
62a193ed
MG		 6743 bool req_int_win =
6744 dm_request_for_irq_injection(vcpu) &&
6745 kvm_cpu_accept_dm_intr(vcpu);
6746
730dca42 6747 bool req_immediate_exit = false;
b6c7a5dc 6748
2fa6e1e1 6749 if (kvm_request_pending(vcpu)) {
a8eeb04a 6750 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6751 kvm_mmu_unload(vcpu);
a8eeb04a 6752 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6753 __kvm_migrate_timers(vcpu);
d828199e
MT		 6754 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6755 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6756 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6757 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6758 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6759 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6760 if (unlikely(r))
6761 goto out;
6762 }
a8eeb04a 6763 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6764 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6765 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6766 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6767 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6768 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6769 r = 0;
6770 goto out;
6771 }
a8eeb04a 6772 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6773 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6774 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6775 r = 0;
6776 goto out;
6777 }
af585b92
GN		 6778 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6779 /* Page is swapped out. Do synthetic halt */
6780 vcpu->arch.apf.halted = true;
6781 r = 1;
6782 goto out;
6783 }
c9aaa895
GC		 6784 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6785 record_steal_time(vcpu);
64d60670
PB		 6786 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6787 process_smi(vcpu);
7460fb4a
AK		 6788 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6789 process_nmi(vcpu);
f5132b01 6790 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6791 kvm_pmu_handle_event(vcpu);
f5132b01 6792 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6793 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6794 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6795 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6796 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6797 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6798 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6799 vcpu->run->eoi.vector =
6800 vcpu->arch.pending_ioapic_eoi;
6801 r = 0;
6802 goto out;
6803 }
6804 }
3d81bc7e
YZ		 6805 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6806 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6807 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6808 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6809 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6810 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6811 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6812 r = 0;
6813 goto out;
6814 }
e516cebb
AS		 6815 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6816 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6817 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6818 r = 0;
6819 goto out;
6820 }
db397571
AS		 6821 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6822 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6823 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6824 r = 0;
6825 goto out;
6826 }
f3b138c5
AS		 6827
6828 /*
6829 * KVM_REQ_HV_STIMER has to be processed after
6830 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6831 * depend on the guest clock being up-to-date
6832 */
1f4b34f8
AS		 6833 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6834 kvm_hv_process_stimers(vcpu);
2f52d58c 6835 }
b93463aa 6836
b463a6f7 6837 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6838 ++vcpu->stat.req_event;
66450a21
JK		 6839 kvm_apic_accept_events(vcpu);
6840 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6841 r = 1;
6842 goto out;
6843 }
6844
b6b8a145
JK		 6845 if (inject_pending_event(vcpu, req_int_win) != 0)
6846 req_immediate_exit = true;
321c5658 6847 else {
c43203ca
PB		 6848 /* Enable NMI/IRQ window open exits if needed.
6849 *
6850 * SMIs have two cases: 1) they can be nested, and
6851 * then there is nothing to do here because RSM will
6852 * cause a vmexit anyway; 2) or the SMI can be pending
6853 * because inject_pending_event has completed the
6854 * injection of an IRQ or NMI from the previous vmexit,
6855 * and then we request an immediate exit to inject the SMI.
6856 */
6857 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6858 req_immediate_exit = true;
321c5658
YS		 6859 if (vcpu->arch.nmi_pending)
6860 kvm_x86_ops->enable_nmi_window(vcpu);
6861 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6862 kvm_x86_ops->enable_irq_window(vcpu);
6863 }
b463a6f7
AK		 6864
6865 if (kvm_lapic_enabled(vcpu)) {
6866 update_cr8_intercept(vcpu);
6867 kvm_lapic_sync_to_vapic(vcpu);
6868 }
6869 }
6870
d8368af8
AK		 6871 r = kvm_mmu_reload(vcpu);
6872 if (unlikely(r)) {
d905c069 6873 goto cancel_injection;
d8368af8
AK		 6874 }
6875
b6c7a5dc
HB		 6876 preempt_disable();
6877
6878 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6879 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6880
6881 /*
6882 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6883 * IPI are then delayed after guest entry, which ensures that they
6884 * result in virtual interrupt delivery.
6885 */
6886 local_irq_disable();
6b7e2d09
XG		 6887 vcpu->mode = IN_GUEST_MODE;
6888
01b71917
MT		 6889 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6890
0f127d12 6891 /*
b95234c8 6892 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6893 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6894 *
6895 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6896 * pairs with the memory barrier implicit in pi_test_and_set_on
6897 * (see vmx_deliver_posted_interrupt).
6898 *
6899 * 3) This also orders the write to mode from any reads to the page
6900 * tables done while the VCPU is running. Please see the comment
6901 * in kvm_flush_remote_tlbs.
6b7e2d09 6902 */
01b71917 6903 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6904
b95234c8
PB		 6905 /*
6906 * This handles the case where a posted interrupt was
6907 * notified with kvm_vcpu_kick.
6908 */
6909 if (kvm_lapic_enabled(vcpu)) {
6910 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6911 kvm_x86_ops->sync_pir_to_irr(vcpu);
6912 }
32f88400 6913
2fa6e1e1 6914 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 6915 || need_resched() || signal_pending(current)) {
6b7e2d09 6916 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6917 smp_wmb();
6c142801
AK		 6918 local_irq_enable();
6919 preempt_enable();
01b71917 6920 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6921 r = 1;
d905c069 6922 goto cancel_injection;
6c142801
AK		 6923 }
6924
fc5b7f3b
DM		 6925 kvm_load_guest_xcr0(vcpu);
6926
c43203ca
PB		 6927 if (req_immediate_exit) {
6928 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6929 smp_send_reschedule(vcpu->cpu);
c43203ca 6930 }
d6185f20 6931
8b89fe1f
PB		 6932 trace_kvm_entry(vcpu->vcpu_id);
6933 wait_lapic_expire(vcpu);
6edaa530 6934 guest_enter_irqoff();
b6c7a5dc 6935
42dbaa5a 6936 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6937 set_debugreg(0, 7);
6938 set_debugreg(vcpu->arch.eff_db[0], 0);
6939 set_debugreg(vcpu->arch.eff_db[1], 1);
6940 set_debugreg(vcpu->arch.eff_db[2], 2);
6941 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6942 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6943 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6944 }
b6c7a5dc 6945
851ba692 6946 kvm_x86_ops->run(vcpu);
b6c7a5dc 6947
c77fb5fe
PB		 6948 /*
6949 * Do this here before restoring debug registers on the host. And
6950 * since we do this before handling the vmexit, a DR access vmexit
6951 * can (a) read the correct value of the debug registers, (b) set
6952 * KVM_DEBUGREG_WONT_EXIT again.
6953 */
6954 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6955 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6956 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6957 kvm_update_dr0123(vcpu);
6958 kvm_update_dr6(vcpu);
6959 kvm_update_dr7(vcpu);
6960 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6961 }
6962
24f1e32c
FW		 6963 /*
6964 * If the guest has used debug registers, at least dr7
6965 * will be disabled while returning to the host.
6966 * If we don't have active breakpoints in the host, we don't
6967 * care about the messed up debug address registers. But if
6968 * we have some of them active, restore the old state.
6969 */
59d8eb53 6970 if (hw_breakpoint_active())
24f1e32c 6971 hw_breakpoint_restore();
42dbaa5a 6972
4ba76538 6973 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6974
6b7e2d09 6975 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6976 smp_wmb();
a547c6db 6977
fc5b7f3b
DM		 6978 kvm_put_guest_xcr0(vcpu);
6979
a547c6db 6980 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6981
6982 ++vcpu->stat.exits;
6983
f2485b3e 6984 guest_exit_irqoff();
b6c7a5dc 6985
f2485b3e 6986 local_irq_enable();
b6c7a5dc
HB		 6987 preempt_enable();
6988
f656ce01 6989 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6990
b6c7a5dc
HB		 6991 /*
6992 * Profile KVM exit RIPs:
6993 */
6994 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6995 unsigned long rip = kvm_rip_read(vcpu);
6996 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6997 }
6998
cc578287
ZA		 6999 if (unlikely(vcpu->arch.tsc_always_catchup))
7000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7001
5cfb1d5a
MT		 7002 if (vcpu->arch.apic_attention)
7003 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7004
851ba692 7005 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7006 return r;
7007
7008cancel_injection:
7009 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7010 if (unlikely(vcpu->arch.apic_attention))
7011 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7012out:
7013 return r;
7014}
b6c7a5dc 7015
362c698f
PB		 7016static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7017{
bf9f6ac8
FW		 7018 if (!kvm_arch_vcpu_runnable(vcpu) &&
7019 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7020 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7021 kvm_vcpu_block(vcpu);
7022 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7023
7024 if (kvm_x86_ops->post_block)
7025 kvm_x86_ops->post_block(vcpu);
7026
9c8fd1ba
PB		 7027 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7028 return 1;
7029 }
362c698f
PB		 7030
7031 kvm_apic_accept_events(vcpu);
7032 switch(vcpu->arch.mp_state) {
7033 case KVM_MP_STATE_HALTED:
7034 vcpu->arch.pv.pv_unhalted = false;
7035 vcpu->arch.mp_state =
7036 KVM_MP_STATE_RUNNABLE;
7037 case KVM_MP_STATE_RUNNABLE:
7038 vcpu->arch.apf.halted = false;
7039 break;
7040 case KVM_MP_STATE_INIT_RECEIVED:
7041 break;
7042 default:
7043 return -EINTR;
7044 break;
7045 }
7046 return 1;
7047}
09cec754 7048
5d9bc648
PB		 7049static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7050{
0ad3bed6
PB		 7051 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7052 kvm_x86_ops->check_nested_events(vcpu, false);
7053
5d9bc648
PB		 7054 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7055 !vcpu->arch.apf.halted);
7056}
7057
362c698f 7058static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7059{
7060 int r;
f656ce01 7061 struct kvm *kvm = vcpu->kvm;
d7690175 7062
f656ce01 7063 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7064
362c698f 7065 for (;;) {
58f800d5 7066 if (kvm_vcpu_running(vcpu)) {
851ba692 7067 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7068 } else {
362c698f 7069 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7070 }
7071
09cec754
GN		 7072 if (r <= 0)
7073 break;
7074
72875d8a 7075 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7076 if (kvm_cpu_has_pending_timer(vcpu))
7077 kvm_inject_pending_timer_irqs(vcpu);
7078
782d422b
MG		 7079 if (dm_request_for_irq_injection(vcpu) &&
7080 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7081 r = 0;
7082 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7083 ++vcpu->stat.request_irq_exits;
362c698f 7084 break;
09cec754 7085 }
af585b92
GN		 7086
7087 kvm_check_async_pf_completion(vcpu);
7088
09cec754
GN		 7089 if (signal_pending(current)) {
7090 r = -EINTR;
851ba692 7091 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7092 ++vcpu->stat.signal_exits;
362c698f 7093 break;
09cec754
GN		 7094 }
7095 if (need_resched()) {
f656ce01 7096 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7097 cond_resched();
f656ce01 7098 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7099 }
b6c7a5dc
HB		 7100 }
7101
f656ce01 7102 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7103
7104 return r;
7105}
7106
716d51ab
GN		 7107static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7108{
7109 int r;
7110 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7111 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7112 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7113 if (r != EMULATE_DONE)
7114 return 0;
7115 return 1;
7116}
7117
7118static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7119{
7120 BUG_ON(!vcpu->arch.pio.count);
7121
7122 return complete_emulated_io(vcpu);
7123}
7124
f78146b0
AK		 7125/*
7126 * Implements the following, as a state machine:
7127 *
7128 * read:
7129 * for each fragment
87da7e66
XG		 7130 * for each mmio piece in the fragment
7131 * write gpa, len
7132 * exit
7133 * copy data
f78146b0
AK		 7134 * execute insn
7135 *
7136 * write:
7137 * for each fragment
87da7e66
XG		 7138 * for each mmio piece in the fragment
7139 * write gpa, len
7140 * copy data
7141 * exit
f78146b0 7142 */
716d51ab 7143static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7144{
7145 struct kvm_run *run = vcpu->run;
f78146b0 7146 struct kvm_mmio_fragment *frag;
87da7e66 7147 unsigned len;
5287f194 7148
716d51ab 7149 BUG_ON(!vcpu->mmio_needed);
5287f194 7150
716d51ab 7151 /* Complete previous fragment */
87da7e66
XG		 7152 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7153 len = min(8u, frag->len);
716d51ab 7154 if (!vcpu->mmio_is_write)
87da7e66
XG		 7155 memcpy(frag->data, run->mmio.data, len);
7156
7157 if (frag->len <= 8) {
7158 /* Switch to the next fragment. */
7159 frag++;
7160 vcpu->mmio_cur_fragment++;
7161 } else {
7162 /* Go forward to the next mmio piece. */
7163 frag->data += len;
7164 frag->gpa += len;
7165 frag->len -= len;
7166 }
7167
a08d3b3b 7168 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7169 vcpu->mmio_needed = 0;
0912c977
PB		 7170
7171 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7172 if (vcpu->mmio_is_write)
716d51ab
GN		 7173 return 1;
7174 vcpu->mmio_read_completed = 1;
7175 return complete_emulated_io(vcpu);
7176 }
87da7e66 7177
716d51ab
GN		 7178 run->exit_reason = KVM_EXIT_MMIO;
7179 run->mmio.phys_addr = frag->gpa;
7180 if (vcpu->mmio_is_write)
87da7e66
XG		 7181 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7182 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7183 run->mmio.is_write = vcpu->mmio_is_write;
7184 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7185 return 0;
5287f194
AK		 7186}
7187
716d51ab 7188
b6c7a5dc
HB		 7189int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7190{
c5bedc68 7191 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7192 int r;
7193 sigset_t sigsaved;
7194
c4d72e2d 7195 fpu__activate_curr(fpu);
e5c30142 7196
ac9f6dc0
AK		 7197 if (vcpu->sigset_active)
7198 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7199
a4535290 7200 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7201 kvm_vcpu_block(vcpu);
66450a21 7202 kvm_apic_accept_events(vcpu);
72875d8a 7203 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0
AK		 7204 r = -EAGAIN;
7205 goto out;
b6c7a5dc
HB		 7206 }
7207
b6c7a5dc 7208 /* re-sync apic's tpr */
35754c98 7209 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7210 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7211 r = -EINVAL;
7212 goto out;
7213 }
7214 }
b6c7a5dc 7215
716d51ab
GN		 7216 if (unlikely(vcpu->arch.complete_userspace_io)) {
7217 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7218 vcpu->arch.complete_userspace_io = NULL;
7219 r = cui(vcpu);
7220 if (r <= 0)
7221 goto out;
7222 } else
7223 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7224
460df4c1
PB		 7225 if (kvm_run->immediate_exit)
7226 r = -EINTR;
7227 else
7228 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7229
7230out:
f1d86e46 7231 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7232 if (vcpu->sigset_active)
7233 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7234
b6c7a5dc
HB		 7235 return r;
7236}
7237
7238int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7239{
7ae441ea
GN		 7240 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7241 /*
7242 * We are here if userspace calls get_regs() in the middle of
7243 * instruction emulation. Registers state needs to be copied
4a969980 7244 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7245 * that usually, but some bad designed PV devices (vmware
7246 * backdoor interface) need this to work
7247 */
dd856efa 7248 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7249 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7250 }
5fdbf976
MT		 7251 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7252 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7253 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7254 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7255 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7256 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7257 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7258 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7259#ifdef CONFIG_X86_64
5fdbf976
MT		 7260 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7261 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7262 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7263 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7264 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7265 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7266 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7267 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7268#endif
7269
5fdbf976 7270 regs->rip = kvm_rip_read(vcpu);
91586a3b 7271 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7272
b6c7a5dc
HB		 7273 return 0;
7274}
7275
7276int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7277{
7ae441ea
GN		 7278 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7279 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7280
5fdbf976
MT		 7281 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7282 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7283 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7284 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7285 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7286 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7287 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7288 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7289#ifdef CONFIG_X86_64
5fdbf976
MT		 7290 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7291 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7292 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7293 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7294 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7295 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7296 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7297 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7298#endif
7299
5fdbf976 7300 kvm_rip_write(vcpu, regs->rip);
91586a3b 7301 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7302
b4f14abd
JK		 7303 vcpu->arch.exception.pending = false;
7304
3842d135
AK		 7305 kvm_make_request(KVM_REQ_EVENT, vcpu);
7306
b6c7a5dc
HB		 7307 return 0;
7308}
7309
b6c7a5dc
HB		 7310void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7311{
7312 struct kvm_segment cs;
7313
3e6e0aab 7314 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7315 *db = cs.db;
7316 *l = cs.l;
7317}
7318EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7319
7320int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7321 struct kvm_sregs *sregs)
7322{
89a27f4d 7323 struct desc_ptr dt;
b6c7a5dc 7324
3e6e0aab
GT		 7325 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7326 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7327 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7328 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7329 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7330 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7331
3e6e0aab
GT		 7332 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7333 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7334
7335 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7336 sregs->idt.limit = dt.size;
7337 sregs->idt.base = dt.address;
b6c7a5dc 7338 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7339 sregs->gdt.limit = dt.size;
7340 sregs->gdt.base = dt.address;
b6c7a5dc 7341
4d4ec087 7342 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7343 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7344 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7345 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7346 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7347 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7348 sregs->apic_base = kvm_get_apic_base(vcpu);
7349
923c61bb 7350 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7351
36752c9b 7352 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7353 set_bit(vcpu->arch.interrupt.nr,
7354 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7355
b6c7a5dc
HB		 7356 return 0;
7357}
7358
62d9f0db
MT		 7359int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7360 struct kvm_mp_state *mp_state)
7361{
66450a21 7362 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7363 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7364 vcpu->arch.pv.pv_unhalted)
7365 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7366 else
7367 mp_state->mp_state = vcpu->arch.mp_state;
7368
62d9f0db
MT		 7369 return 0;
7370}
7371
7372int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7373 struct kvm_mp_state *mp_state)
7374{
bce87cce 7375 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7376 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7377 return -EINVAL;
7378
28bf2888
DH		 7379 /* INITs are latched while in SMM */
7380 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7381 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7382 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7383 return -EINVAL;
7384
66450a21
JK		 7385 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7386 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7387 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7388 } else
7389 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7390 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7391 return 0;
7392}
7393
7f3d35fd
KW		 7394int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7395 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7396{
9d74191a 7397 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7398 int ret;
e01c2426 7399
8ec4722d 7400 init_emulate_ctxt(vcpu);
c697518a 7401
7f3d35fd 7402 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7403 has_error_code, error_code);
c697518a 7404
c697518a 7405 if (ret)
19d04437 7406 return EMULATE_FAIL;
37817f29 7407
9d74191a
TY		 7408 kvm_rip_write(vcpu, ctxt->eip);
7409 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7410 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7411 return EMULATE_DONE;
37817f29
IE		 7412}
7413EXPORT_SYMBOL_GPL(kvm_task_switch);
7414
b6c7a5dc
HB		 7415int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7416 struct kvm_sregs *sregs)
7417{
58cb628d 7418 struct msr_data apic_base_msr;
b6c7a5dc 7419 int mmu_reset_needed = 0;
63f42e02 7420 int pending_vec, max_bits, idx;
89a27f4d 7421 struct desc_ptr dt;
b6c7a5dc 7422
d6321d49
RK		 7423 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7424 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7425 return -EINVAL;
7426
d3802286
JM		 7427 apic_base_msr.data = sregs->apic_base;
7428 apic_base_msr.host_initiated = true;
7429 if (kvm_set_apic_base(vcpu, &apic_base_msr))
7430 return -EINVAL;
7431
89a27f4d
GN		 7432 dt.size = sregs->idt.limit;
7433 dt.address = sregs->idt.base;
b6c7a5dc 7434 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7435 dt.size = sregs->gdt.limit;
7436 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7437 kvm_x86_ops->set_gdt(vcpu, &dt);
7438
ad312c7c 7439 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7440 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7441 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7442 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7443
2d3ad1f4 7444 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7445
f6801dff 7446 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7447 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7448
4d4ec087 7449 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7450 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7451 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7452
fc78f519 7453 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7454 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7455 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7456 kvm_update_cpuid(vcpu);
63f42e02
XG		 7457
7458 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7459 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7460 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7461 mmu_reset_needed = 1;
7462 }
63f42e02 7463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7464
7465 if (mmu_reset_needed)
7466 kvm_mmu_reset_context(vcpu);
7467
a50abc3b 7468 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7469 pending_vec = find_first_bit(
7470 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7471 if (pending_vec < max_bits) {
66fd3f7f 7472 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7473 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7474 }
7475
3e6e0aab
GT		 7476 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7477 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7478 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7479 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7480 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7481 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7482
3e6e0aab
GT		 7483 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7484 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7485
5f0269f5
ME		 7486 update_cr8_intercept(vcpu);
7487
9c3e4aab 7488 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7489 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7490 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7491 !is_protmode(vcpu))
9c3e4aab
MT		 7492 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7493
3842d135
AK		 7494 kvm_make_request(KVM_REQ_EVENT, vcpu);
7495
b6c7a5dc
HB		 7496 return 0;
7497}
7498
d0bfb940
JK		 7499int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7500 struct kvm_guest_debug *dbg)
b6c7a5dc 7501{
355be0b9 7502 unsigned long rflags;
ae675ef0 7503 int i, r;
b6c7a5dc 7504
4f926bf2
JK		 7505 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7506 r = -EBUSY;
7507 if (vcpu->arch.exception.pending)
2122ff5e 7508 goto out;
4f926bf2
JK		 7509 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7510 kvm_queue_exception(vcpu, DB_VECTOR);
7511 else
7512 kvm_queue_exception(vcpu, BP_VECTOR);
7513 }
7514
91586a3b
JK		 7515 /*
7516 * Read rflags as long as potentially injected trace flags are still
7517 * filtered out.
7518 */
7519 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7520
7521 vcpu->guest_debug = dbg->control;
7522 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7523 vcpu->guest_debug = 0;
7524
7525 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7526 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7527 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7528 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7529 } else {
7530 for (i = 0; i < KVM_NR_DB_REGS; i++)
7531 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7532 }
c8639010 7533 kvm_update_dr7(vcpu);
ae675ef0 7534
f92653ee
JK		 7535 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7536 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7537 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7538
91586a3b
JK		 7539 /*
7540 * Trigger an rflags update that will inject or remove the trace
7541 * flags.
7542 */
7543 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7544
a96036b8 7545 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7546
4f926bf2 7547 r = 0;
d0bfb940 7548
2122ff5e 7549out:
b6c7a5dc
HB		 7550
7551 return r;
7552}
7553
8b006791
ZX		 7554/*
7555 * Translate a guest virtual address to a guest physical address.
7556 */
7557int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7558 struct kvm_translation *tr)
7559{
7560 unsigned long vaddr = tr->linear_address;
7561 gpa_t gpa;
f656ce01 7562 int idx;
8b006791 7563
f656ce01 7564 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7565 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7566 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7567 tr->physical_address = gpa;
7568 tr->valid = gpa != UNMAPPED_GVA;
7569 tr->writeable = 1;
7570 tr->usermode = 0;
8b006791
ZX		 7571
7572 return 0;
7573}
7574
d0752060
HB		 7575int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7576{
c47ada30 7577 struct fxregs_state *fxsave =
7366ed77 7578 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7579
d0752060
HB		 7580 memcpy(fpu->fpr, fxsave->st_space, 128);
7581 fpu->fcw = fxsave->cwd;
7582 fpu->fsw = fxsave->swd;
7583 fpu->ftwx = fxsave->twd;
7584 fpu->last_opcode = fxsave->fop;
7585 fpu->last_ip = fxsave->rip;
7586 fpu->last_dp = fxsave->rdp;
7587 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7588
d0752060
HB		 7589 return 0;
7590}
7591
7592int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7593{
c47ada30 7594 struct fxregs_state *fxsave =
7366ed77 7595 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7596
d0752060
HB		 7597 memcpy(fxsave->st_space, fpu->fpr, 128);
7598 fxsave->cwd = fpu->fcw;
7599 fxsave->swd = fpu->fsw;
7600 fxsave->twd = fpu->ftwx;
7601 fxsave->fop = fpu->last_opcode;
7602 fxsave->rip = fpu->last_ip;
7603 fxsave->rdp = fpu->last_dp;
7604 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7605
d0752060
HB		 7606 return 0;
7607}
7608
0ee6a517 7609static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7610{
bf935b0b 7611 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7612 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7613 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7614 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7615
2acf923e
DC		 7616 /*
7617 * Ensure guest xcr0 is valid for loading
7618 */
d91cab78 7619 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7620
ad312c7c 7621 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7622}
d0752060
HB		 7623
7624void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7625{
2608d7a1 7626 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7627 return;
7628
2acf923e
DC		 7629 /*
7630 * Restore all possible states in the guest,
7631 * and assume host would use all available bits.
7632 * Guest xcr0 would be loaded later.
7633 */
d0752060 7634 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7635 __kernel_fpu_begin();
003e2e8b 7636 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7637 trace_kvm_fpu(1);
d0752060 7638}
d0752060
HB		 7639
7640void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7641{
3d42de25 7642 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7643 return;
7644
7645 vcpu->guest_fpu_loaded = 0;
4f836347 7646 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7647 __kernel_fpu_end();
f096ed85 7648 ++vcpu->stat.fpu_reload;
0c04851c 7649 trace_kvm_fpu(0);
d0752060 7650}
e9b11c17
ZX		 7651
7652void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7653{
bd768e14
IY		 7654 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7655
12f9a48f 7656 kvmclock_reset(vcpu);
7f1ea208 7657
e9b11c17 7658 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7659 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7660}
7661
7662struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7663 unsigned int id)
7664{
c447e76b
LL		 7665 struct kvm_vcpu *vcpu;
7666
6755bae8
ZA		 7667 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7668 printk_once(KERN_WARNING
7669 "kvm: SMP vm created on host with unstable TSC; "
7670 "guest TSC will not be reliable\n");
c447e76b
LL		 7671
7672 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7673
c447e76b 7674 return vcpu;
26e5215f 7675}
e9b11c17 7676
26e5215f
AK		 7677int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7678{
7679 int r;
e9b11c17 7680
19efffa2 7681 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7682 r = vcpu_load(vcpu);
7683 if (r)
7684 return r;
d28bc9dd 7685 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7686 kvm_mmu_setup(vcpu);
e9b11c17 7687 vcpu_put(vcpu);
26e5215f 7688 return r;
e9b11c17
ZX		 7689}
7690
31928aa5 7691void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7692{
8fe8ab46 7693 struct msr_data msr;
332967a3 7694 struct kvm *kvm = vcpu->kvm;
42897d86 7695
d3457c87
RK		 7696 kvm_hv_vcpu_postcreate(vcpu);
7697
31928aa5
DD		 7698 if (vcpu_load(vcpu))
7699 return;
8fe8ab46
WA		 7700 msr.data = 0x0;
7701 msr.index = MSR_IA32_TSC;
7702 msr.host_initiated = true;
7703 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7704 vcpu_put(vcpu);
7705
630994b3
MT		 7706 if (!kvmclock_periodic_sync)
7707 return;
7708
332967a3
AJ		 7709 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7710 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7711}
7712
d40ccc62 7713void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7714{
9fc77441 7715 int r;
344d9588
GN		 7716 vcpu->arch.apf.msr_val = 0;
7717
9fc77441
MT		 7718 r = vcpu_load(vcpu);
7719 BUG_ON(r);
e9b11c17
ZX		 7720 kvm_mmu_unload(vcpu);
7721 vcpu_put(vcpu);
7722
7723 kvm_x86_ops->vcpu_free(vcpu);
7724}
7725
d28bc9dd 7726void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7727{
e69fab5d
PB		 7728 vcpu->arch.hflags = 0;
7729
c43203ca 7730 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7731 atomic_set(&vcpu->arch.nmi_queued, 0);
7732 vcpu->arch.nmi_pending = 0;
448fa4a9 7733 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7734 kvm_clear_interrupt_queue(vcpu);
7735 kvm_clear_exception_queue(vcpu);
448fa4a9 7736
42dbaa5a 7737 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7738 kvm_update_dr0123(vcpu);
6f43ed01 7739 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7740 kvm_update_dr6(vcpu);
42dbaa5a 7741 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7742 kvm_update_dr7(vcpu);
42dbaa5a 7743
1119022c
NA		 7744 vcpu->arch.cr2 = 0;
7745
3842d135 7746 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7747 vcpu->arch.apf.msr_val = 0;
c9aaa895 7748 vcpu->arch.st.msr_val = 0;
3842d135 7749
12f9a48f
GC		 7750 kvmclock_reset(vcpu);
7751
af585b92
GN		 7752 kvm_clear_async_pf_completion_queue(vcpu);
7753 kvm_async_pf_hash_reset(vcpu);
7754 vcpu->arch.apf.halted = false;
3842d135 7755
64d60670 7756 if (!init_event) {
d28bc9dd 7757 kvm_pmu_reset(vcpu);
64d60670 7758 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7759
7760 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7761 vcpu->arch.msr_misc_features_enables = 0;
64d60670 7762 }
f5132b01 7763
66f7b72e
JS		 7764 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7765 vcpu->arch.regs_avail = ~0;
7766 vcpu->arch.regs_dirty = ~0;
7767
d28bc9dd 7768 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7769}
7770
2b4a273b 7771void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7772{
7773 struct kvm_segment cs;
7774
7775 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7776 cs.selector = vector << 8;
7777 cs.base = vector << 12;
7778 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7779 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7780}
7781
13a34e06 7782int kvm_arch_hardware_enable(void)
e9b11c17 7783{
ca84d1a2
ZA		 7784 struct kvm *kvm;
7785 struct kvm_vcpu *vcpu;
7786 int i;
0dd6a6ed
ZA		 7787 int ret;
7788 u64 local_tsc;
7789 u64 max_tsc = 0;
7790 bool stable, backwards_tsc = false;
18863bdd
AK		 7791
7792 kvm_shared_msr_cpu_online();
13a34e06 7793 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7794 if (ret != 0)
7795 return ret;
7796
4ea1636b 7797 local_tsc = rdtsc();
0dd6a6ed
ZA		 7798 stable = !check_tsc_unstable();
7799 list_for_each_entry(kvm, &vm_list, vm_list) {
7800 kvm_for_each_vcpu(i, vcpu, kvm) {
7801 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7802 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7803 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7804 backwards_tsc = true;
7805 if (vcpu->arch.last_host_tsc > max_tsc)
7806 max_tsc = vcpu->arch.last_host_tsc;
7807 }
7808 }
7809 }
7810
7811 /*
7812 * Sometimes, even reliable TSCs go backwards. This happens on
7813 * platforms that reset TSC during suspend or hibernate actions, but
7814 * maintain synchronization. We must compensate. Fortunately, we can
7815 * detect that condition here, which happens early in CPU bringup,
7816 * before any KVM threads can be running. Unfortunately, we can't
7817 * bring the TSCs fully up to date with real time, as we aren't yet far
7818 * enough into CPU bringup that we know how much real time has actually
108b249c 7819 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7820 * variables that haven't been updated yet.
7821 *
7822 * So we simply find the maximum observed TSC above, then record the
7823 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7824 * the adjustment will be applied. Note that we accumulate
7825 * adjustments, in case multiple suspend cycles happen before some VCPU
7826 * gets a chance to run again. In the event that no KVM threads get a
7827 * chance to run, we will miss the entire elapsed period, as we'll have
7828 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7829 * loose cycle time. This isn't too big a deal, since the loss will be
7830 * uniform across all VCPUs (not to mention the scenario is extremely
7831 * unlikely). It is possible that a second hibernate recovery happens
7832 * much faster than a first, causing the observed TSC here to be
7833 * smaller; this would require additional padding adjustment, which is
7834 * why we set last_host_tsc to the local tsc observed here.
7835 *
7836 * N.B. - this code below runs only on platforms with reliable TSC,
7837 * as that is the only way backwards_tsc is set above. Also note
7838 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7839 * have the same delta_cyc adjustment applied if backwards_tsc
7840 * is detected. Note further, this adjustment is only done once,
7841 * as we reset last_host_tsc on all VCPUs to stop this from being
7842 * called multiple times (one for each physical CPU bringup).
7843 *
4a969980 7844 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7845 * will be compensated by the logic in vcpu_load, which sets the TSC to
7846 * catchup mode. This will catchup all VCPUs to real time, but cannot
7847 * guarantee that they stay in perfect synchronization.
7848 */
7849 if (backwards_tsc) {
7850 u64 delta_cyc = max_tsc - local_tsc;
7851 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 7852 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 7853 kvm_for_each_vcpu(i, vcpu, kvm) {
7854 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7855 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7856 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7857 }
7858
7859 /*
7860 * We have to disable TSC offset matching.. if you were
7861 * booting a VM while issuing an S4 host suspend....
7862 * you may have some problem. Solving this issue is
7863 * left as an exercise to the reader.
7864 */
7865 kvm->arch.last_tsc_nsec = 0;
7866 kvm->arch.last_tsc_write = 0;
7867 }
7868
7869 }
7870 return 0;
e9b11c17
ZX		 7871}
7872
13a34e06 7873void kvm_arch_hardware_disable(void)
e9b11c17 7874{
13a34e06
RK		 7875 kvm_x86_ops->hardware_disable();
7876 drop_user_return_notifiers();
e9b11c17
ZX		 7877}
7878
7879int kvm_arch_hardware_setup(void)
7880{
9e9c3fe4
NA		 7881 int r;
7882
7883 r = kvm_x86_ops->hardware_setup();
7884 if (r != 0)
7885 return r;
7886
35181e86
HZ		 7887 if (kvm_has_tsc_control) {
7888 /*
7889 * Make sure the user can only configure tsc_khz values that
7890 * fit into a signed integer.
7891 * A min value is not calculated needed because it will always
7892 * be 1 on all machines.
7893 */
7894 u64 max = min(0x7fffffffULL,
7895 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7896 kvm_max_guest_tsc_khz = max;
7897
ad721883 7898 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7899 }
ad721883 7900
9e9c3fe4
NA		 7901 kvm_init_msr_list();
7902 return 0;
e9b11c17
ZX		 7903}
7904
7905void kvm_arch_hardware_unsetup(void)
7906{
7907 kvm_x86_ops->hardware_unsetup();
7908}
7909
7910void kvm_arch_check_processor_compat(void *rtn)
7911{
7912 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7913}
7914
7915bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7916{
7917 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7918}
7919EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7920
7921bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7922{
7923 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7924}
7925
54e9818f 7926struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7927EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7928
e9b11c17
ZX		 7929int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7930{
7931 struct page *page;
7932 struct kvm *kvm;
7933 int r;
7934
7935 BUG_ON(vcpu->kvm == NULL);
7936 kvm = vcpu->kvm;
7937
d62caabb 7938 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7939 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7940 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7941 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7942 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7943 else
a4535290 7944 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7945
7946 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7947 if (!page) {
7948 r = -ENOMEM;
7949 goto fail;
7950 }
ad312c7c 7951 vcpu->arch.pio_data = page_address(page);
e9b11c17 7952
cc578287 7953 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7954
e9b11c17
ZX		 7955 r = kvm_mmu_create(vcpu);
7956 if (r < 0)
7957 goto fail_free_pio_data;
7958
7959 if (irqchip_in_kernel(kvm)) {
7960 r = kvm_create_lapic(vcpu);
7961 if (r < 0)
7962 goto fail_mmu_destroy;
54e9818f
GN		 7963 } else
7964 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7965
890ca9ae
YH		 7966 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7967 GFP_KERNEL);
7968 if (!vcpu->arch.mce_banks) {
7969 r = -ENOMEM;
443c39bc 7970 goto fail_free_lapic;
890ca9ae
YH		 7971 }
7972 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7973
f1797359
WY		 7974 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7975 r = -ENOMEM;
f5f48ee1 7976 goto fail_free_mce_banks;
f1797359 7977 }
f5f48ee1 7978
0ee6a517 7979 fx_init(vcpu);
66f7b72e 7980
ba904635 7981 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7982 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7983
7984 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7985 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7986
5a4f55cd
EK		 7987 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7988
74545705
RK		 7989 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7990
af585b92 7991 kvm_async_pf_hash_reset(vcpu);
f5132b01 7992 kvm_pmu_init(vcpu);
af585b92 7993
1c1a9ce9 7994 vcpu->arch.pending_external_vector = -1;
de63ad4c 7995 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 7996
5c919412
AS		 7997 kvm_hv_vcpu_init(vcpu);
7998
e9b11c17 7999 return 0;
0ee6a517 8000
f5f48ee1
SY		 8001fail_free_mce_banks:
8002 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8003fail_free_lapic:
8004 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8005fail_mmu_destroy:
8006 kvm_mmu_destroy(vcpu);
8007fail_free_pio_data:
ad312c7c 8008 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8009fail:
8010 return r;
8011}
8012
8013void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8014{
f656ce01
MT		 8015 int idx;
8016
1f4b34f8 8017 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8018 kvm_pmu_destroy(vcpu);
36cb93fd 8019 kfree(vcpu->arch.mce_banks);
e9b11c17 8020 kvm_free_lapic(vcpu);
f656ce01 8021 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8022 kvm_mmu_destroy(vcpu);
f656ce01 8023 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8024 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8025 if (!lapic_in_kernel(vcpu))
54e9818f 8026 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8027}
d19a9cd2 8028
e790d9ef
RK		 8029void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8030{
ae97a3b8 8031 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8032}
8033
e08b9637 8034int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8035{
e08b9637
CO		 8036 if (type)
8037 return -EINVAL;
8038
6ef768fa 8039 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8040 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8041 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8042 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8043 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8044
5550af4d
SY		 8045 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8046 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8047 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8048 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8049 &kvm->arch.irq_sources_bitmap);
5550af4d 8050
038f8c11 8051 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8052 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8053 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8054 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8055
108b249c 8056 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8057 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8058
7e44e449 8059 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8060 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8061
0eb05bf2 8062 kvm_page_track_init(kvm);
13d268ca 8063 kvm_mmu_init_vm(kvm);
0eb05bf2 8064
03543133
SS		 8065 if (kvm_x86_ops->vm_init)
8066 return kvm_x86_ops->vm_init(kvm);
8067
d89f5eff 8068 return 0;
d19a9cd2
ZX		 8069}
8070
8071static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8072{
9fc77441
MT		 8073 int r;
8074 r = vcpu_load(vcpu);
8075 BUG_ON(r);
d19a9cd2
ZX		 8076 kvm_mmu_unload(vcpu);
8077 vcpu_put(vcpu);
8078}
8079
8080static void kvm_free_vcpus(struct kvm *kvm)
8081{
8082 unsigned int i;
988a2cae 8083 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8084
8085 /*
8086 * Unpin any mmu pages first.
8087 */
af585b92
GN		 8088 kvm_for_each_vcpu(i, vcpu, kvm) {
8089 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8090 kvm_unload_vcpu_mmu(vcpu);
af585b92 8091 }
988a2cae
GN		 8092 kvm_for_each_vcpu(i, vcpu, kvm)
8093 kvm_arch_vcpu_free(vcpu);
8094
8095 mutex_lock(&kvm->lock);
8096 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8097 kvm->vcpus[i] = NULL;
d19a9cd2 8098
988a2cae
GN		 8099 atomic_set(&kvm->online_vcpus, 0);
8100 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8101}
8102
ad8ba2cd
SY		 8103void kvm_arch_sync_events(struct kvm *kvm)
8104{
332967a3 8105 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8106 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8107 kvm_free_pit(kvm);
ad8ba2cd
SY		 8108}
8109
1d8007bd 8110int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8111{
8112 int i, r;
25188b99 8113 unsigned long hva;
f0d648bd
PB		 8114 struct kvm_memslots *slots = kvm_memslots(kvm);
8115 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8116
8117 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8118 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8119 return -EINVAL;
9da0e4d5 8120
f0d648bd
PB		 8121 slot = id_to_memslot(slots, id);
8122 if (size) {
b21629da 8123 if (slot->npages)
f0d648bd
PB		 8124 return -EEXIST;
8125
8126 /*
8127 * MAP_SHARED to prevent internal slot pages from being moved
8128 * by fork()/COW.
8129 */
8130 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8131 MAP_SHARED | MAP_ANONYMOUS, 0);
8132 if (IS_ERR((void *)hva))
8133 return PTR_ERR((void *)hva);
8134 } else {
8135 if (!slot->npages)
8136 return 0;
8137
8138 hva = 0;
8139 }
8140
8141 old = *slot;
9da0e4d5 8142 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8143 struct kvm_userspace_memory_region m;
9da0e4d5 8144
1d8007bd
PB		 8145 m.slot = id | (i << 16);
8146 m.flags = 0;
8147 m.guest_phys_addr = gpa;
f0d648bd 8148 m.userspace_addr = hva;
1d8007bd 8149 m.memory_size = size;
9da0e4d5
PB		 8150 r = __kvm_set_memory_region(kvm, &m);
8151 if (r < 0)
8152 return r;
8153 }
8154
f0d648bd
PB		 8155 if (!size) {
8156 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8157 WARN_ON(r < 0);
8158 }
8159
9da0e4d5
PB		 8160 return 0;
8161}
8162EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8163
1d8007bd 8164int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8165{
8166 int r;
8167
8168 mutex_lock(&kvm->slots_lock);
1d8007bd 8169 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8170 mutex_unlock(&kvm->slots_lock);
8171
8172 return r;
8173}
8174EXPORT_SYMBOL_GPL(x86_set_memory_region);
8175
d19a9cd2
ZX		 8176void kvm_arch_destroy_vm(struct kvm *kvm)
8177{
27469d29
AH		 8178 if (current->mm == kvm->mm) {
8179 /*
8180 * Free memory regions allocated on behalf of userspace,
8181 * unless the the memory map has changed due to process exit
8182 * or fd copying.
8183 */
1d8007bd
PB		 8184 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8185 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8186 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8187 }
03543133
SS		 8188 if (kvm_x86_ops->vm_destroy)
8189 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8190 kvm_pic_destroy(kvm);
8191 kvm_ioapic_destroy(kvm);
d19a9cd2 8192 kvm_free_vcpus(kvm);
af1bae54 8193 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8194 kvm_mmu_uninit_vm(kvm);
2beb6dad 8195 kvm_page_track_cleanup(kvm);
d19a9cd2 8196}
0de10343 8197
5587027c 8198void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8199 struct kvm_memory_slot *dont)
8200{
8201 int i;
8202
d89cc617
TY		 8203 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8204 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8205 kvfree(free->arch.rmap[i]);
d89cc617 8206 free->arch.rmap[i] = NULL;
77d11309 8207 }
d89cc617
TY		 8208 if (i == 0)
8209 continue;
8210
8211 if (!dont || free->arch.lpage_info[i - 1] !=
8212 dont->arch.lpage_info[i - 1]) {
548ef284 8213 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8214 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8215 }
8216 }
21ebbeda
XG		 8217
8218 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8219}
8220
5587027c
AK		 8221int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8222 unsigned long npages)
db3fe4eb
TY		 8223{
8224 int i;
8225
d89cc617 8226 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8227 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8228 unsigned long ugfn;
8229 int lpages;
d89cc617 8230 int level = i + 1;
db3fe4eb
TY		 8231
8232 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8233 slot->base_gfn, level) + 1;
8234
d89cc617 8235 slot->arch.rmap[i] =
a7c3e901 8236 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8237 if (!slot->arch.rmap[i])
77d11309 8238 goto out_free;
d89cc617
TY		 8239 if (i == 0)
8240 continue;
77d11309 8241
a7c3e901 8242 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8243 if (!linfo)
db3fe4eb
TY		 8244 goto out_free;
8245
92f94f1e
XG		 8246 slot->arch.lpage_info[i - 1] = linfo;
8247
db3fe4eb 8248 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8249 linfo[0].disallow_lpage = 1;
db3fe4eb 8250 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8251 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8252 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8253 /*
8254 * If the gfn and userspace address are not aligned wrt each
8255 * other, or if explicitly asked to, disable large page
8256 * support for this slot
8257 */
8258 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8259 !kvm_largepages_enabled()) {
8260 unsigned long j;
8261
8262 for (j = 0; j < lpages; ++j)
92f94f1e 8263 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8264 }
8265 }
8266
21ebbeda
XG		 8267 if (kvm_page_track_create_memslot(slot, npages))
8268 goto out_free;
8269
db3fe4eb
TY		 8270 return 0;
8271
8272out_free:
d89cc617 8273 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8274 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8275 slot->arch.rmap[i] = NULL;
8276 if (i == 0)
8277 continue;
8278
548ef284 8279 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8280 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8281 }
8282 return -ENOMEM;
8283}
8284
15f46015 8285void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8286{
e6dff7d1
TY		 8287 /*
8288 * memslots->generation has been incremented.
8289 * mmio generation may have reached its maximum value.
8290 */
54bf36aa 8291 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8292}
8293
f7784b8e
MT		 8294int kvm_arch_prepare_memory_region(struct kvm *kvm,
8295 struct kvm_memory_slot *memslot,
09170a49 8296 const struct kvm_userspace_memory_region *mem,
7b6195a9 8297 enum kvm_mr_change change)
0de10343 8298{
f7784b8e
MT		 8299 return 0;
8300}
8301
88178fd4
KH		 8302static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8303 struct kvm_memory_slot *new)
8304{
8305 /* Still write protect RO slot */
8306 if (new->flags & KVM_MEM_READONLY) {
8307 kvm_mmu_slot_remove_write_access(kvm, new);
8308 return;
8309 }
8310
8311 /*
8312 * Call kvm_x86_ops dirty logging hooks when they are valid.
8313 *
8314 * kvm_x86_ops->slot_disable_log_dirty is called when:
8315 *
8316 * - KVM_MR_CREATE with dirty logging is disabled
8317 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8318 *
8319 * The reason is, in case of PML, we need to set D-bit for any slots
8320 * with dirty logging disabled in order to eliminate unnecessary GPA
8321 * logging in PML buffer (and potential PML buffer full VMEXT). This
8322 * guarantees leaving PML enabled during guest's lifetime won't have
8323 * any additonal overhead from PML when guest is running with dirty
8324 * logging disabled for memory slots.
8325 *
8326 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8327 * to dirty logging mode.
8328 *
8329 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8330 *
8331 * In case of write protect:
8332 *
8333 * Write protect all pages for dirty logging.
8334 *
8335 * All the sptes including the large sptes which point to this
8336 * slot are set to readonly. We can not create any new large
8337 * spte on this slot until the end of the logging.
8338 *
8339 * See the comments in fast_page_fault().
8340 */
8341 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8342 if (kvm_x86_ops->slot_enable_log_dirty)
8343 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8344 else
8345 kvm_mmu_slot_remove_write_access(kvm, new);
8346 } else {
8347 if (kvm_x86_ops->slot_disable_log_dirty)
8348 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8349 }
8350}
8351
f7784b8e 8352void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8353 const struct kvm_userspace_memory_region *mem,
8482644a 8354 const struct kvm_memory_slot *old,
f36f3f28 8355 const struct kvm_memory_slot *new,
8482644a 8356 enum kvm_mr_change change)
f7784b8e 8357{
8482644a 8358 int nr_mmu_pages = 0;
f7784b8e 8359
48c0e4e9
XG		 8360 if (!kvm->arch.n_requested_mmu_pages)
8361 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8362
48c0e4e9 8363 if (nr_mmu_pages)
0de10343 8364 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8365
3ea3b7fa
WL		 8366 /*
8367 * Dirty logging tracks sptes in 4k granularity, meaning that large
8368 * sptes have to be split. If live migration is successful, the guest
8369 * in the source machine will be destroyed and large sptes will be
8370 * created in the destination. However, if the guest continues to run
8371 * in the source machine (for example if live migration fails), small
8372 * sptes will remain around and cause bad performance.
8373 *
8374 * Scan sptes if dirty logging has been stopped, dropping those
8375 * which can be collapsed into a single large-page spte. Later
8376 * page faults will create the large-page sptes.
8377 */
8378 if ((change != KVM_MR_DELETE) &&
8379 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8380 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8381 kvm_mmu_zap_collapsible_sptes(kvm, new);
8382
c972f3b1 8383 /*
88178fd4 8384 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8385 *
88178fd4
KH		 8386 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8387 * been zapped so no dirty logging staff is needed for old slot. For
8388 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8389 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8390 *
8391 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8392 */
88178fd4 8393 if (change != KVM_MR_DELETE)
f36f3f28 8394 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8395}
1d737c8a 8396
2df72e9b 8397void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8398{
6ca18b69 8399 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8400}
8401
2df72e9b
MT		 8402void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8403 struct kvm_memory_slot *slot)
8404{
ae7cd873 8405 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8406}
8407
5d9bc648
PB		 8408static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8409{
8410 if (!list_empty_careful(&vcpu->async_pf.done))
8411 return true;
8412
8413 if (kvm_apic_has_events(vcpu))
8414 return true;
8415
8416 if (vcpu->arch.pv.pv_unhalted)
8417 return true;
8418
47a66eed
Z		 8419 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8420 (vcpu->arch.nmi_pending &&
8421 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8422 return true;
8423
47a66eed
Z		 8424 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8425 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8426 return true;
8427
5d9bc648
PB		 8428 if (kvm_arch_interrupt_allowed(vcpu) &&
8429 kvm_cpu_has_interrupt(vcpu))
8430 return true;
8431
1f4b34f8
AS		 8432 if (kvm_hv_has_stimer_pending(vcpu))
8433 return true;
8434
5d9bc648
PB		 8435 return false;
8436}
8437
1d737c8a
ZX		 8438int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8439{
5d9bc648 8440 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8441}
5736199a 8442
199b5763
LM		 8443bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8444{
de63ad4c 8445 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8446}
8447
b6d33834 8448int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8449{
b6d33834 8450 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8451}
78646121
GN		 8452
8453int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8454{
8455 return kvm_x86_ops->interrupt_allowed(vcpu);
8456}
229456fc 8457
82b32774 8458unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8459{
82b32774
NA		 8460 if (is_64_bit_mode(vcpu))
8461 return kvm_rip_read(vcpu);
8462 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8463 kvm_rip_read(vcpu));
8464}
8465EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8466
82b32774
NA		 8467bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8468{
8469 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8470}
8471EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8472
94fe45da
JK		 8473unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8474{
8475 unsigned long rflags;
8476
8477 rflags = kvm_x86_ops->get_rflags(vcpu);
8478 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8479 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8480 return rflags;
8481}
8482EXPORT_SYMBOL_GPL(kvm_get_rflags);
8483
6addfc42 8484static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8485{
8486 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8487 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8488 rflags |= X86_EFLAGS_TF;
94fe45da 8489 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8490}
8491
8492void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8493{
8494 __kvm_set_rflags(vcpu, rflags);
3842d135 8495 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8496}
8497EXPORT_SYMBOL_GPL(kvm_set_rflags);
8498
56028d08
GN		 8499void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8500{
8501 int r;
8502
fb67e14f 8503 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8504 work->wakeup_all)
56028d08
GN		 8505 return;
8506
8507 r = kvm_mmu_reload(vcpu);
8508 if (unlikely(r))
8509 return;
8510
fb67e14f
XG		 8511 if (!vcpu->arch.mmu.direct_map &&
8512 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8513 return;
8514
56028d08
GN		 8515 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8516}
8517
af585b92
GN		 8518static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8519{
8520 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8521}
8522
8523static inline u32 kvm_async_pf_next_probe(u32 key)
8524{
8525 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8526}
8527
8528static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8529{
8530 u32 key = kvm_async_pf_hash_fn(gfn);
8531
8532 while (vcpu->arch.apf.gfns[key] != ~0)
8533 key = kvm_async_pf_next_probe(key);
8534
8535 vcpu->arch.apf.gfns[key] = gfn;
8536}
8537
8538static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8539{
8540 int i;
8541 u32 key = kvm_async_pf_hash_fn(gfn);
8542
8543 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8544 (vcpu->arch.apf.gfns[key] != gfn &&
8545 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8546 key = kvm_async_pf_next_probe(key);
8547
8548 return key;
8549}
8550
8551bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8552{
8553 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8554}
8555
8556static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8557{
8558 u32 i, j, k;
8559
8560 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8561 while (true) {
8562 vcpu->arch.apf.gfns[i] = ~0;
8563 do {
8564 j = kvm_async_pf_next_probe(j);
8565 if (vcpu->arch.apf.gfns[j] == ~0)
8566 return;
8567 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8568 /*
8569 * k lies cyclically in ]i,j]
8570 * | i.k.j |
8571 * |....j i.k.| or |.k..j i...|
8572 */
8573 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8574 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8575 i = j;
8576 }
8577}
8578
7c90705b
GN		 8579static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8580{
4e335d9e
PB		 8581
8582 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8583 sizeof(val));
7c90705b
GN		 8584}
8585
af585b92
GN		 8586void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8587 struct kvm_async_pf *work)
8588{
6389ee94
AK		 8589 struct x86_exception fault;
8590
7c90705b 8591 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8592 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8593
8594 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8595 (vcpu->arch.apf.send_user_only &&
8596 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8597 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8598 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8599 fault.vector = PF_VECTOR;
8600 fault.error_code_valid = true;
8601 fault.error_code = 0;
8602 fault.nested_page_fault = false;
8603 fault.address = work->arch.token;
adfe20fb 8604 fault.async_page_fault = true;
6389ee94 8605 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8606 }
af585b92
GN		 8607}
8608
8609void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8610 struct kvm_async_pf *work)
8611{
6389ee94
AK		 8612 struct x86_exception fault;
8613
f2e10669 8614 if (work->wakeup_all)
7c90705b
GN		 8615 work->arch.token = ~0; /* broadcast wakeup */
8616 else
8617 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8618 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8619
8620 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8621 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8622 fault.vector = PF_VECTOR;
8623 fault.error_code_valid = true;
8624 fault.error_code = 0;
8625 fault.nested_page_fault = false;
8626 fault.address = work->arch.token;
adfe20fb 8627 fault.async_page_fault = true;
6389ee94 8628 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8629 }
e6d53e3b 8630 vcpu->arch.apf.halted = false;
a4fa1635 8631 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8632}
8633
8634bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8635{
8636 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8637 return true;
8638 else
9bc1f09f 8639 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8640}
8641
5544eb9b
PB		 8642void kvm_arch_start_assignment(struct kvm *kvm)
8643{
8644 atomic_inc(&kvm->arch.assigned_device_count);
8645}
8646EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8647
8648void kvm_arch_end_assignment(struct kvm *kvm)
8649{
8650 atomic_dec(&kvm->arch.assigned_device_count);
8651}
8652EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8653
8654bool kvm_arch_has_assigned_device(struct kvm *kvm)
8655{
8656 return atomic_read(&kvm->arch.assigned_device_count);
8657}
8658EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8659
e0f0bbc5
AW		 8660void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8661{
8662 atomic_inc(&kvm->arch.noncoherent_dma_count);
8663}
8664EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8665
8666void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8667{
8668 atomic_dec(&kvm->arch.noncoherent_dma_count);
8669}
8670EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8671
8672bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8673{
8674 return atomic_read(&kvm->arch.noncoherent_dma_count);
8675}
8676EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8677
14717e20
AW		 8678bool kvm_arch_has_irq_bypass(void)
8679{
8680 return kvm_x86_ops->update_pi_irte != NULL;
8681}
8682
87276880
FW		 8683int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8684 struct irq_bypass_producer *prod)
8685{
8686 struct kvm_kernel_irqfd *irqfd =
8687 container_of(cons, struct kvm_kernel_irqfd, consumer);
8688
14717e20 8689 irqfd->producer = prod;
87276880 8690
14717e20
AW		 8691 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8692 prod->irq, irqfd->gsi, 1);
87276880
FW		 8693}
8694
8695void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8696 struct irq_bypass_producer *prod)
8697{
8698 int ret;
8699 struct kvm_kernel_irqfd *irqfd =
8700 container_of(cons, struct kvm_kernel_irqfd, consumer);
8701
87276880
FW		 8702 WARN_ON(irqfd->producer != prod);
8703 irqfd->producer = NULL;
8704
8705 /*
8706 * When producer of consumer is unregistered, we change back to
8707 * remapped mode, so we can re-use the current implementation
bb3541f1 8708 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8709 * int this case doesn't want to receive the interrupts.
8710 */
8711 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8712 if (ret)
8713 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8714 " fails: %d\n", irqfd->consumer.token, ret);
8715}
8716
8717int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8718 uint32_t guest_irq, bool set)
8719{
8720 if (!kvm_x86_ops->update_pi_irte)
8721 return -EINVAL;
8722
8723 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8724}
8725
52004014
FW		 8726bool kvm_vector_hashing_enabled(void)
8727{
8728 return vector_hashing;
8729}
8730EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8731
229456fc 8732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8745EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8746EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8747EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8748EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8749EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8750EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
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