[linux.git] / drivers / edac / amd76x_edac.c

/*
 * AMD 76x Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include "edac_mc.h"

#define amd76x_printk(level, fmt, arg...) \
	edac_printk(level, "amd76x", fmt, ##arg)

#define amd76x_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)

#define AMD76X_NR_CSROWS 8
#define AMD76X_NR_CHANS  1
#define AMD76X_NR_DIMMS  4

/* AMD 76x register addresses - device 0 function 0 - PCI bridge */

#define AMD76X_ECC_MODE_STATUS	0x48	/* Mode and status of ECC (32b)
					 *
					 * 31:16 reserved
					 * 15:14 SERR enabled: x1=ue 1x=ce
					 * 13    reserved
					 * 12    diag: disabled, enabled
					 * 11:10 mode: dis, EC, ECC, ECC+scrub
					 *  9:8  status: x1=ue 1x=ce
					 *  7:4  UE cs row
					 *  3:0  CE cs row
					 */

#define AMD76X_DRAM_MODE_STATUS	0x58	/* DRAM Mode and status (32b)
					 *
					 * 31:26 clock disable 5 - 0
					 * 25    SDRAM init
					 * 24    reserved
					 * 23    mode register service
					 * 22:21 suspend to RAM
					 * 20    burst refresh enable
					 * 19    refresh disable
					 * 18    reserved
					 * 17:16 cycles-per-refresh
					 * 15:8  reserved
					 *  7:0  x4 mode enable 7 - 0
					 */

#define AMD76X_MEM_BASE_ADDR	0xC0	/* Memory base address (8 x 32b)
					 *
					 * 31:23 chip-select base
					 * 22:16 reserved
					 * 15:7  chip-select mask
					 *  6:3  reserved
					 *  2:1  address mode
					 *  0    chip-select enable
					 */

struct amd76x_error_info {
	u32 ecc_mode_status;
};

enum amd76x_chips {
	AMD761 = 0,
	AMD762
};

struct amd76x_dev_info {
	const char *ctl_name;
};

static const struct amd76x_dev_info amd76x_devs[] = {
	[AMD761] = {
		.ctl_name = "AMD761"
	},
	[AMD762] = {
		.ctl_name = "AMD762"
	},
};

/**
 *	amd76x_get_error_info	-	fetch error information
 *	@mci: Memory controller
 *	@info: Info to fill in
 *
 *	Fetch and store the AMD76x ECC status. Clear pending status
 *	on the chip so that further errors will be reported
 */
static void amd76x_get_error_info(struct mem_ctl_info *mci,
		struct amd76x_error_info *info)
{
	pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
				&info->ecc_mode_status);

	if (info->ecc_mode_status & BIT(8))
		pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
				(u32) BIT(8), (u32) BIT(8));

	if (info->ecc_mode_status & BIT(9))
		pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
				(u32) BIT(9), (u32) BIT(9));
}

/**
 *	amd76x_process_error_info	-	Error check
 *	@mci: Memory controller
 *	@info: Previously fetched information from chip
 *	@handle_errors: 1 if we should do recovery
 *
 *	Process the chip state and decide if an error has occurred.
 *	A return of 1 indicates an error. Also if handle_errors is true
 *	then attempt to handle and clean up after the error
 */
static int amd76x_process_error_info(struct mem_ctl_info *mci,
		struct amd76x_error_info *info, int handle_errors)
{
	int error_found;
	u32 row;

	error_found = 0;

	/*
	 *	Check for an uncorrectable error
	 */
	if (info->ecc_mode_status & BIT(8)) {
		error_found = 1;

		if (handle_errors) {
			row = (info->ecc_mode_status >> 4) & 0xf;
			edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
				row, mci->ctl_name);
		}
	}

	/*
	 *	Check for a correctable error
	 */
	if (info->ecc_mode_status & BIT(9)) {
		error_found = 1;

		if (handle_errors) {
			row = info->ecc_mode_status & 0xf;
			edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
				0, row, 0, mci->ctl_name);
		}
	}

	return error_found;
}

/**
 *	amd76x_check	-	Poll the controller
 *	@mci: Memory controller
 *
 *	Called by the poll handlers this function reads the status
 *	from the controller and checks for errors.
 */
static void amd76x_check(struct mem_ctl_info *mci)
{
	struct amd76x_error_info info;
	debugf3("%s()\n", __func__);
	amd76x_get_error_info(mci, &info);
	amd76x_process_error_info(mci, &info, 1);
}

/**
 *	amd76x_probe1	-	Perform set up for detected device
 *	@pdev; PCI device detected
 *	@dev_idx: Device type index
 *
 *	We have found an AMD76x and now need to set up the memory
 *	controller status reporting. We configure and set up the
 *	memory controller reporting and claim the device.
 */
static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	int index;
	struct mem_ctl_info *mci = NULL;
	enum edac_type ems_modes[] = {
		EDAC_NONE,
		EDAC_EC,
		EDAC_SECDED,
		EDAC_SECDED
	};
	u32 ems;
	u32 ems_mode;
	struct amd76x_error_info discard;

	debugf0("%s()\n", __func__);
	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
	ems_mode = (ems >> 10) & 0x3;
	mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);

	if (mci == NULL) {
		rc = -ENOMEM;
		goto fail;
	}

	debugf0("%s(): mci = %p\n", __func__, mci);
	mci->pdev = pdev;
	mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	mci->edac_cap = ems_mode ?
			(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = "$Revision: 1.4.2.5 $";
	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
	mci->edac_check = amd76x_check;
	mci->ctl_page_to_phys = NULL;

	for (index = 0; index < mci->nr_csrows; index++) {
		struct csrow_info *csrow = &mci->csrows[index];
		u32 mba;
		u32 mba_base;
		u32 mba_mask;
		u32 dms;

		/* find the DRAM Chip Select Base address and mask */
		pci_read_config_dword(mci->pdev,
				AMD76X_MEM_BASE_ADDR + (index * 4), &mba);

		if (!(mba & BIT(0)))
			continue;

		mba_base = mba & 0xff800000UL;
		mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
		pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
				&dms);
		csrow->first_page = mba_base >> PAGE_SHIFT;
		csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
		csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
		csrow->page_mask = mba_mask >> PAGE_SHIFT;
		csrow->grain = csrow->nr_pages << PAGE_SHIFT;
		csrow->mtype = MEM_RDDR;
		csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
		csrow->edac_mode = ems_modes[ems_mode];
	}

	amd76x_get_error_info(mci, &discard);  /* clear counters */

	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* get this far and it's successful */
	debugf3("%s(): success\n", __func__);
	return 0;

fail:
	if (mci != NULL)
		edac_mc_free(mci);
	return rc;
}

/* returns count (>= 0), or negative on error */
static int __devinit amd76x_init_one(struct pci_dev *pdev,
		const struct pci_device_id *ent)
{
	debugf0("%s()\n", __func__);

	/* don't need to call pci_device_enable() */
	return amd76x_probe1(pdev, ent->driver_data);
}

/**
 *	amd76x_remove_one	-	driver shutdown
 *	@pdev: PCI device being handed back
 *
 *	Called when the driver is unloaded. Find the matching mci
 *	structure for the device then delete the mci and free the
 *	resources.
 */
static void __devexit amd76x_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	if ((mci = edac_mc_del_mc(pdev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
	{
		PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
		AMD762
	},
	{
		PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
		AMD761
	},
	{
		0,
	}	/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);

static struct pci_driver amd76x_driver = {
	.name = EDAC_MOD_STR,
	.probe = amd76x_init_one,
	.remove = __devexit_p(amd76x_remove_one),
	.id_table = amd76x_pci_tbl,
};

static int __init amd76x_init(void)
{
	return pci_register_driver(&amd76x_driver);
}

static void __exit amd76x_exit(void)
{
	pci_unregister_driver(&amd76x_driver);
}

module_init(amd76x_init);
module_exit(amd76x_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
Commit	Line	Data
806c35f5 AC	1	/*
	2	* AMD 76x Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	9	* http://www.anime.net/~goemon/linux-ecc/
	10	*
	11	* $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	*/
	14
806c35f5 AC	15	#include <linux/config.h>
	16	#include <linux/module.h>
	17	#include <linux/init.h>
806c35f5 AC	18	#include <linux/pci.h>
806c35f5 AC	19	#include <linux/pci_ids.h>
806c35f5	20	#include <linux/slab.h>
806c35f5 AC	21	#include "edac_mc.h"
806c35f5 AC	22
537fba28	23	#define amd76x_printk(level, fmt, arg...) \
e7ecd891	24	edac_printk(level, "amd76x", fmt, ##arg)
537fba28 DP	25
537fba28 DP	26	#define amd76x_mc_printk(mci, level, fmt, arg...) \
e7ecd891	27	edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
537fba28	28
806c35f5 AC	29	#define AMD76X_NR_CSROWS 8
	30	#define AMD76X_NR_CHANS 1
	31	#define AMD76X_NR_DIMMS 4
	32
806c35f5	33	/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
e7ecd891	34
806c35f5 AC	35	#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
	36	*
	37	* 31:16 reserved
	38	* 15:14 SERR enabled: x1=ue 1x=ce
	39	* 13 reserved
	40	* 12 diag: disabled, enabled
	41	* 11:10 mode: dis, EC, ECC, ECC+scrub
	42	* 9:8 status: x1=ue 1x=ce
	43	* 7:4 UE cs row
	44	* 3:0 CE cs row
	45	*/
e7ecd891	46
806c35f5 AC	47	#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
	48	*
	49	* 31:26 clock disable 5 - 0
	50	* 25 SDRAM init
	51	* 24 reserved
	52	* 23 mode register service
	53	* 22:21 suspend to RAM
	54	* 20 burst refresh enable
	55	* 19 refresh disable
	56	* 18 reserved
	57	* 17:16 cycles-per-refresh
	58	* 15:8 reserved
	59	* 7:0 x4 mode enable 7 - 0
	60	*/
e7ecd891	61
806c35f5 AC	62	#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
	63	*
	64	* 31:23 chip-select base
	65	* 22:16 reserved
	66	* 15:7 chip-select mask
	67	* 6:3 reserved
	68	* 2:1 address mode
	69	* 0 chip-select enable
	70	*/
	71
806c35f5 AC	72	struct amd76x_error_info {
	73	u32 ecc_mode_status;
	74	};
	75
806c35f5 AC	76	enum amd76x_chips {
	77	AMD761 = 0,
	78	AMD762
	79	};
	80
806c35f5 AC	81	struct amd76x_dev_info {
	82	const char *ctl_name;
	83	};
	84
806c35f5	85	static const struct amd76x_dev_info amd76x_devs[] = {
e7ecd891 DP	86	[AMD761] = {
	87	.ctl_name = "AMD761"
	88	},
	89	[AMD762] = {
	90	.ctl_name = "AMD762"
	91	},
806c35f5 AC	92	};
806c35f5 AC	93
806c35f5 AC	94	/**
	95	* amd76x_get_error_info - fetch error information
	96	* @mci: Memory controller
	97	* @info: Info to fill in
	98	*
	99	* Fetch and store the AMD76x ECC status. Clear pending status
	100	* on the chip so that further errors will be reported
	101	*/
e7ecd891 DP	102	static void amd76x_get_error_info(struct mem_ctl_info *mci,
e7ecd891 DP	103	struct amd76x_error_info *info)
806c35f5 AC	104	{
	105	pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
	106	&info->ecc_mode_status);
	107
	108	if (info->ecc_mode_status & BIT(8))
	109	pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
e7ecd891	110	(u32) BIT(8), (u32) BIT(8));
806c35f5 AC	111
	112	if (info->ecc_mode_status & BIT(9))
	113	pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
e7ecd891	114	(u32) BIT(9), (u32) BIT(9));
806c35f5 AC	115	}
806c35f5 AC	116
806c35f5 AC	117	/**
	118	* amd76x_process_error_info - Error check
	119	* @mci: Memory controller
	120	* @info: Previously fetched information from chip
	121	* @handle_errors: 1 if we should do recovery
	122	*
	123	* Process the chip state and decide if an error has occurred.
	124	* A return of 1 indicates an error. Also if handle_errors is true
	125	* then attempt to handle and clean up after the error
	126	*/
e7ecd891	127	static int amd76x_process_error_info(struct mem_ctl_info *mci,
806c35f5 AC	128	struct amd76x_error_info *info, int handle_errors)
	129	{
	130	int error_found;
	131	u32 row;
	132
	133	error_found = 0;
	134
	135	/*
	136	* Check for an uncorrectable error
	137	*/
	138	if (info->ecc_mode_status & BIT(8)) {
	139	error_found = 1;
	140
	141	if (handle_errors) {
	142	row = (info->ecc_mode_status >> 4) & 0xf;
e7ecd891 DP	143	edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
e7ecd891 DP	144	row, mci->ctl_name);
806c35f5 AC	145	}
	146	}
	147
	148	/*
	149	* Check for a correctable error
	150	*/
	151	if (info->ecc_mode_status & BIT(9)) {
	152	error_found = 1;
	153
	154	if (handle_errors) {
	155	row = info->ecc_mode_status & 0xf;
e7ecd891 DP	156	edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
e7ecd891 DP	157	0, row, 0, mci->ctl_name);
806c35f5 AC	158	}
806c35f5 AC	159	}
e7ecd891	160
806c35f5 AC	161	return error_found;
	162	}
	163
	164	/**
	165	* amd76x_check - Poll the controller
	166	* @mci: Memory controller
	167	*
	168	* Called by the poll handlers this function reads the status
	169	* from the controller and checks for errors.
	170	*/
806c35f5 AC	171	static void amd76x_check(struct mem_ctl_info *mci)
	172	{
	173	struct amd76x_error_info info;
537fba28	174	debugf3("%s()\n", __func__);
806c35f5 AC	175	amd76x_get_error_info(mci, &info);
	176	amd76x_process_error_info(mci, &info, 1);
	177	}
	178
806c35f5 AC	179	/**
	180	* amd76x_probe1 - Perform set up for detected device
	181	* @pdev; PCI device detected
	182	* @dev_idx: Device type index
	183	*
	184	* We have found an AMD76x and now need to set up the memory
	185	* controller status reporting. We configure and set up the
	186	* memory controller reporting and claim the device.
	187	*/
806c35f5 AC	188	static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
	189	{
	190	int rc = -ENODEV;
	191	int index;
	192	struct mem_ctl_info *mci = NULL;
	193	enum edac_type ems_modes[] = {
	194	EDAC_NONE,
	195	EDAC_EC,
	196	EDAC_SECDED,
	197	EDAC_SECDED
	198	};
	199	u32 ems;
	200	u32 ems_mode;
749ede57	201	struct amd76x_error_info discard;
806c35f5	202
537fba28	203	debugf0("%s()\n", __func__);
806c35f5 AC	204	pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
806c35f5 AC	205	ems_mode = (ems >> 10) & 0x3;
806c35f5 AC	206	mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
	207
	208	if (mci == NULL) {
	209	rc = -ENOMEM;
	210	goto fail;
	211	}
	212
537fba28	213	debugf0("%s(): mci = %p\n", __func__, mci);
225159bd	214	mci->pdev = pdev;
806c35f5	215	mci->mtype_cap = MEM_FLAG_RDDR;
806c35f5 AC	216	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
806c35f5 AC	217	mci->edac_cap = ems_mode ?
e7ecd891	218	(EDAC_FLAG_EC \| EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
680cbbbb	219	mci->mod_name = EDAC_MOD_STR;
806c35f5 AC	220	mci->mod_ver = "$Revision: 1.4.2.5 $";
	221	mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
	222	mci->edac_check = amd76x_check;
	223	mci->ctl_page_to_phys = NULL;
	224
	225	for (index = 0; index < mci->nr_csrows; index++) {
	226	struct csrow_info *csrow = &mci->csrows[index];
	227	u32 mba;
	228	u32 mba_base;
	229	u32 mba_mask;
	230	u32 dms;
	231
	232	/* find the DRAM Chip Select Base address and mask */
	233	pci_read_config_dword(mci->pdev,
e7ecd891	234	AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
806c35f5 AC	235
	236	if (!(mba & BIT(0)))
	237	continue;
	238
	239	mba_base = mba & 0xff800000UL;
	240	mba_mask = ((mba & 0xff80) << 16) \| 0x7fffffUL;
806c35f5	241	pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
e7ecd891	242	&dms);
806c35f5 AC	243	csrow->first_page = mba_base >> PAGE_SHIFT;
	244	csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
	245	csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
	246	csrow->page_mask = mba_mask >> PAGE_SHIFT;
	247	csrow->grain = csrow->nr_pages << PAGE_SHIFT;
	248	csrow->mtype = MEM_RDDR;
	249	csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
	250	csrow->edac_mode = ems_modes[ems_mode];
	251	}
	252
749ede57	253	amd76x_get_error_info(mci, &discard); /* clear counters */
806c35f5 AC	254
806c35f5 AC	255	if (edac_mc_add_mc(mci)) {
537fba28	256	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5 AC	257	goto fail;
	258	}
	259
	260	/* get this far and it's successful */
537fba28	261	debugf3("%s(): success\n", __func__);
806c35f5 AC	262	return 0;
	263
	264	fail:
225159bd	265	if (mci != NULL)
806c35f5	266	edac_mc_free(mci);
806c35f5 AC	267	return rc;
	268	}
	269
	270	/* returns count (>= 0), or negative on error */
	271	static int __devinit amd76x_init_one(struct pci_dev *pdev,
e7ecd891	272	const struct pci_device_id *ent)
806c35f5	273	{
537fba28	274	debugf0("%s()\n", __func__);
806c35f5 AC	275
	276	/* don't need to call pci_device_enable() */
	277	return amd76x_probe1(pdev, ent->driver_data);
	278	}
	279
806c35f5 AC	280	/**
	281	* amd76x_remove_one - driver shutdown
	282	* @pdev: PCI device being handed back
	283	*
	284	* Called when the driver is unloaded. Find the matching mci
	285	* structure for the device then delete the mci and free the
	286	* resources.
	287	*/
806c35f5 AC	288	static void __devexit amd76x_remove_one(struct pci_dev *pdev)
	289	{
	290	struct mem_ctl_info *mci;
	291
537fba28	292	debugf0("%s()\n", __func__);
806c35f5	293
18dbc337	294	if ((mci = edac_mc_del_mc(pdev)) == NULL)
806c35f5	295	return;
18dbc337	296
806c35f5 AC	297	edac_mc_free(mci);
	298	}
	299
806c35f5	300	static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
e7ecd891 DP	301	{
	302	PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	303	AMD762
	304	},
	305	{
	306	PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	307	AMD761
	308	},
	309	{
	310	0,
	311	} /* 0 terminated list. */
806c35f5 AC	312	};
	313
	314	MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
	315
806c35f5	316	static struct pci_driver amd76x_driver = {
680cbbbb	317	.name = EDAC_MOD_STR,
806c35f5 AC	318	.probe = amd76x_init_one,
	319	.remove = __devexit_p(amd76x_remove_one),
	320	.id_table = amd76x_pci_tbl,
	321	};
	322
da9bb1d2	323	static int __init amd76x_init(void)
806c35f5 AC	324	{
	325	return pci_register_driver(&amd76x_driver);
	326	}
	327
	328	static void __exit amd76x_exit(void)
	329	{
	330	pci_unregister_driver(&amd76x_driver);
	331	}
	332
	333	module_init(amd76x_init);
	334	module_exit(amd76x_exit);
	335
	336	MODULE_LICENSE("GPL");
	337	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	338	MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");