[linux.git] / arch / arm / mm / proc-macros.S

/*
 * We need constants.h for:
 *  VMA_VM_MM
 *  VMA_VM_FLAGS
 *  VM_EXEC
 */
#include <asm/asm-offsets.h>
#include <asm/thread_info.h>

/*
 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
 */
	.macro	vma_vm_mm, rd, rn
	ldr	\rd, [\rn, #VMA_VM_MM]
	.endm

/*
 * vma_vm_flags - get vma->vm_flags
 */
	.macro	vma_vm_flags, rd, rn
	ldr	\rd, [\rn, #VMA_VM_FLAGS]
	.endm

	.macro	tsk_mm, rd, rn
	ldr	\rd, [\rn, #TI_TASK]
	ldr	\rd, [\rd, #TSK_ACTIVE_MM]
	.endm

/*
 * act_mm - get current->active_mm
 */
	.macro	act_mm, rd
	bic	\rd, sp, #8128
	bic	\rd, \rd, #63
	ldr	\rd, [\rd, #TI_TASK]
	ldr	\rd, [\rd, #TSK_ACTIVE_MM]
	.endm

/*
 * mmid - get context id from mm pointer (mm->context.id)
 */
	.macro	mmid, rd, rn
	ldr	\rd, [\rn, #MM_CONTEXT_ID]
	.endm

/*
 * mask_asid - mask the ASID from the context ID
 */
	.macro	asid, rd, rn
	and	\rd, \rn, #255
	.endm

	.macro	crval, clear, mmuset, ucset
#ifdef CONFIG_MMU
	.word	\clear
	.word	\mmuset
#else
	.word	\clear
	.word	\ucset
#endif
	.endm

/*
 * dcache_line_size - get the minimum D-cache line size from the CTR register
 * on ARMv7.
 */
	.macro	dcache_line_size, reg, tmp
	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
	lsr	\tmp, \tmp, #16
	and	\tmp, \tmp, #0xf		@ cache line size encoding
	mov	\reg, #4			@ bytes per word
	mov	\reg, \reg, lsl \tmp		@ actual cache line size
	.endm

/*
 * icache_line_size - get the minimum I-cache line size from the CTR register
 * on ARMv7.
 */
	.macro	icache_line_size, reg, tmp
	mrc	p15, 0, \tmp, c0, c0, 1		@ read ctr
	and	\tmp, \tmp, #0xf		@ cache line size encoding
	mov	\reg, #4			@ bytes per word
	mov	\reg, \reg, lsl \tmp		@ actual cache line size
	.endm

/*
 * Sanity check the PTE configuration for the code below - which makes
 * certain assumptions about how these bits are laid out.
 */
#ifdef CONFIG_MMU
#if L_PTE_SHARED != PTE_EXT_SHARED
#error PTE shared bit mismatch
#endif
#if !defined (CONFIG_ARM_LPAE) && \
	(L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
	 L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
#error Invalid Linux PTE bit settings
#endif
#endif	/* CONFIG_MMU */

/*
 * The ARMv6 and ARMv7 set_pte_ext translation function.
 *
 * Permission translation:
 *  YUWD  APX AP1 AP0	SVC	User
 *  0xxx   0   0   0	no acc	no acc
 *  100x   1   0   1	r/o	no acc
 *  10x0   1   0   1	r/o	no acc
 *  1011   0   0   1	r/w	no acc
 *  110x   0   1   0	r/w	r/o
 *  11x0   0   1   0	r/w	r/o
 *  1111   0   1   1	r/w	r/w
 *
 * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
 *  110x   1   1   1	r/o	r/o
 *  11x0   1   1   1	r/o	r/o
 */
	.macro	armv6_mt_table pfx
\pfx\()_mt_table:
	.long	0x00						@ L_PTE_MT_UNCACHED
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_BUFFERABLE
	.long	PTE_CACHEABLE					@ L_PTE_MT_WRITETHROUGH
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_WRITEBACK
	.long	PTE_BUFFERABLE					@ L_PTE_MT_DEV_SHARED
	.long	0x00						@ unused
	.long	0x00						@ L_PTE_MT_MINICACHE (not present)
	.long	PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE	@ L_PTE_MT_WRITEALLOC
	.long	0x00						@ unused
	.long	PTE_EXT_TEX(1)					@ L_PTE_MT_DEV_WC
	.long	0x00						@ unused
	.long	PTE_CACHEABLE | PTE_BUFFERABLE			@ L_PTE_MT_DEV_CACHED
	.long	PTE_EXT_TEX(2)					@ L_PTE_MT_DEV_NONSHARED
	.long	0x00						@ unused
	.long	0x00						@ unused
	.long	0x00						@ unused
	.endm

	.macro	armv6_set_pte_ext pfx
	str	r1, [r0], #2048			@ linux version

	bic	r3, r1, #0x000003fc
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	adr	ip, \pfx\()_mt_table
	and	r2, r1, #L_PTE_MT_MASK
	ldr	r2, [ip, r2]

	eor	r1, r1, #L_PTE_DIRTY
	tst	r1, #L_PTE_DIRTY|L_PTE_RDONLY
	orrne	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
#ifdef CONFIG_CPU_USE_DOMAINS
	@ allow kernel read/write access to read-only user pages
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
#endif

	tst	r1, #L_PTE_XN
	orrne	r3, r3, #PTE_EXT_XN

	orr	r3, r3, r2

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

	str	r3, [r0]
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
	.endm


/*
 * The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
 * covering most CPUs except Xscale and Xscale 3.
 *
 * Permission translation:
 *  YUWD   AP	SVC	User
 *  0xxx  0x00	no acc	no acc
 *  100x  0x00	r/o	no acc
 *  10x0  0x00	r/o	no acc
 *  1011  0x55	r/w	no acc
 *  110x  0xaa	r/w	r/o
 *  11x0  0xaa	r/w	r/o
 *  1111  0xff	r/w	r/w
 */
	.macro	armv3_set_pte_ext wc_disable=1
	str	r1, [r0], #2048			@ linux version

	eor	r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK	@ keep C, B bits
	bic	r2, r2, #PTE_TYPE_MASK
	orr	r2, r2, #PTE_TYPE_SMALL

	tst	r3, #L_PTE_USER			@ user?
	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

	tst	r3, #L_PTE_RDONLY | L_PTE_DIRTY	@ write and dirty?
	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

	tst	r3, #L_PTE_PRESENT | L_PTE_YOUNG	@ present and young?
	movne	r2, #0

	.if	\wc_disable
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r2, #PTE_CACHEABLE
	bicne	r2, r2, #PTE_BUFFERABLE
#endif
	.endif
	str	r2, [r0]		@ hardware version
	.endm


/*
 * Xscale set_pte_ext translation, split into two halves to cope
 * with work-arounds.  r3 must be preserved by code between these
 * two macros.
 *
 * Permission translation:
 *  YUWD  AP	SVC	User
 *  0xxx  00	no acc	no acc
 *  100x  00	r/o	no acc
 *  10x0  00	r/o	no acc
 *  1011  01	r/w	no acc
 *  110x  10	r/w	r/o
 *  11x0  10	r/w	r/o
 *  1111  11	r/w	r/w
 */
	.macro	xscale_set_pte_ext_prologue
	str	r1, [r0]			@ linux version

	eor	r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY

	bic	r2, r1, #PTE_SMALL_AP_MASK	@ keep C, B bits
	orr	r2, r2, #PTE_TYPE_EXT		@ extended page

	tst	r3, #L_PTE_USER			@ user?
	orrne	r2, r2, #PTE_EXT_AP_URO_SRW	@ yes -> user r/o, system r/w

	tst	r3, #L_PTE_RDONLY | L_PTE_DIRTY	@ write and dirty?
	orreq	r2, r2, #PTE_EXT_AP_UNO_SRW	@ yes -> user n/a, system r/w
						@ combined with user -> user r/w
	.endm

	.macro	xscale_set_pte_ext_epilogue
	tst	r3, #L_PTE_PRESENT | L_PTE_YOUNG	@ present and young?
	movne	r2, #0				@ no -> fault

	str	r2, [r0, #2048]!		@ hardware version
	mov	ip, #0
	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	.endm

.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
	.type	\name\()_processor_functions, #object
	.align 2
ENTRY(\name\()_processor_functions)
	.word	\dabort
	.word	\pabort
	.word	cpu_\name\()_proc_init
	.word	cpu_\name\()_proc_fin
	.word	cpu_\name\()_reset
	.word	cpu_\name\()_do_idle
	.word	cpu_\name\()_dcache_clean_area
	.word	cpu_\name\()_switch_mm

	.if \nommu
	.word	0
	.else
	.word	cpu_\name\()_set_pte_ext
	.endif

	.if \suspend
	.word	cpu_\name\()_suspend_size
#ifdef CONFIG_PM_SLEEP
	.word	cpu_\name\()_do_suspend
	.word	cpu_\name\()_do_resume
#else
	.word	0
	.word	0
#endif
	.else
	.word	0
	.word	0
	.word	0
	.endif

	.size	\name\()_processor_functions, . - \name\()_processor_functions
.endm

.macro define_cache_functions name:req
	.align 2
	.type	\name\()_cache_fns, #object
ENTRY(\name\()_cache_fns)
	.long	\name\()_flush_icache_all
	.long	\name\()_flush_kern_cache_all
	.long   \name\()_flush_kern_cache_louis
	.long	\name\()_flush_user_cache_all
	.long	\name\()_flush_user_cache_range
	.long	\name\()_coherent_kern_range
	.long	\name\()_coherent_user_range
	.long	\name\()_flush_kern_dcache_area
	.long	\name\()_dma_map_area
	.long	\name\()_dma_unmap_area
	.long	\name\()_dma_flush_range
	.size	\name\()_cache_fns, . - \name\()_cache_fns
.endm

.macro define_tlb_functions name:req, flags_up:req, flags_smp
	.type	\name\()_tlb_fns, #object
ENTRY(\name\()_tlb_fns)
	.long	\name\()_flush_user_tlb_range
	.long	\name\()_flush_kern_tlb_range
	.ifnb \flags_smp
		ALT_SMP(.long	\flags_smp )
		ALT_UP(.long	\flags_up )
	.else
		.long	\flags_up
	.endif
	.size	\name\()_tlb_fns, . - \name\()_tlb_fns
.endm
Commit	Line	Data
1da177e4 LT	1	/*
	2	* We need constants.h for:
	3	* VMA_VM_MM
	4	* VMA_VM_FLAGS
	5	* VM_EXEC
	6	*/
e6ae744d	7	#include <asm/asm-offsets.h>
1da177e4 LT	8	#include <asm/thread_info.h>
	9
	10	/*
	11	* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
	12	*/
	13	.macro vma_vm_mm, rd, rn
	14	ldr \rd, [\rn, #VMA_VM_MM]
	15	.endm
	16
	17	/*
	18	* vma_vm_flags - get vma->vm_flags
	19	*/
	20	.macro vma_vm_flags, rd, rn
	21	ldr \rd, [\rn, #VMA_VM_FLAGS]
	22	.endm
	23
	24	.macro tsk_mm, rd, rn
	25	ldr \rd, [\rn, #TI_TASK]
	26	ldr \rd, [\rd, #TSK_ACTIVE_MM]
	27	.endm
	28
	29	/*
	30	* act_mm - get current->active_mm
	31	*/
	32	.macro act_mm, rd
	33	bic \rd, sp, #8128
	34	bic \rd, \rd, #63
	35	ldr \rd, [\rd, #TI_TASK]
	36	ldr \rd, [\rd, #TSK_ACTIVE_MM]
	37	.endm
	38
	39	/*
	40	* mmid - get context id from mm pointer (mm->context.id)
	41	*/
	42	.macro mmid, rd, rn
	43	ldr \rd, [\rn, #MM_CONTEXT_ID]
	44	.endm
	45
	46	/*
	47	* mask_asid - mask the ASID from the context ID
	48	*/
	49	.macro asid, rd, rn
	50	and \rd, \rn, #255
	51	.endm
22b19086 RK	52
	53	.macro crval, clear, mmuset, ucset
	54	#ifdef CONFIG_MMU
	55	.word \clear
	56	.word \mmuset
	57	#else
	58	.word \clear
	59	.word \ucset
	60	#endif
	61	.endm
bbe88886 CM	62
bbe88886 CM	63	/*
f91e2c3b CM	64	* dcache_line_size - get the minimum D-cache line size from the CTR register
f91e2c3b CM	65	* on ARMv7.
bbe88886 CM	66	*/
bbe88886 CM	67	.macro dcache_line_size, reg, tmp
f91e2c3b CM	68	mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
	69	lsr \tmp, \tmp, #16
	70	and \tmp, \tmp, #0xf @ cache line size encoding
	71	mov \reg, #4 @ bytes per word
bbe88886 CM	72	mov \reg, \reg, lsl \tmp @ actual cache line size
bbe88886 CM	73	.endm
da091653	74
da30e0ac CM	75	/*
	76	* icache_line_size - get the minimum I-cache line size from the CTR register
	77	* on ARMv7.
	78	*/
	79	.macro icache_line_size, reg, tmp
	80	mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
	81	and \tmp, \tmp, #0xf @ cache line size encoding
	82	mov \reg, #4 @ bytes per word
	83	mov \reg, \reg, lsl \tmp @ actual cache line size
	84	.endm
da091653 RK	85
	86	/*
	87	* Sanity check the PTE configuration for the code below - which makes
25985edc	88	* certain assumptions about how these bits are laid out.
da091653	89	*/
8b79d5f2	90	#ifdef CONFIG_MMU
da091653 RK	91	#if L_PTE_SHARED != PTE_EXT_SHARED
	92	#error PTE shared bit mismatch
	93	#endif
1b6ba46b CM	94	#if !defined (CONFIG_ARM_LPAE) && \
	95	(L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
	96	L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
da091653 RK	97	#error Invalid Linux PTE bit settings
da091653 RK	98	#endif
8b79d5f2	99	#endif /* CONFIG_MMU */
da091653 RK	100
	101	/*
	102	* The ARMv6 and ARMv7 set_pte_ext translation function.
	103	*
	104	* Permission translation:
	105	* YUWD APX AP1 AP0 SVC User
	106	* 0xxx 0 0 0 no acc no acc
	107	* 100x 1 0 1 r/o no acc
	108	* 10x0 1 0 1 r/o no acc
	109	* 1011 0 0 1 r/w no acc
	110	* 110x 0 1 0 r/w r/o
	111	* 11x0 0 1 0 r/w r/o
	112	* 1111 0 1 1 r/w r/w
247055aa CM	113	*
	114	* If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
	115	* 110x 1 1 1 r/o r/o
	116	* 11x0 1 1 1 r/o r/o
da091653	117	*/
639b0ae7 RK	118	.macro armv6_mt_table pfx
	119	\pfx\()_mt_table:
	120	.long 0x00 @ L_PTE_MT_UNCACHED
	121	.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
	122	.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
	123	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
	124	.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
	125	.long 0x00 @ unused
	126	.long 0x00 @ L_PTE_MT_MINICACHE (not present)
	127	.long PTE_EXT_TEX(1) \| PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
	128	.long 0x00 @ unused
	129	.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
	130	.long 0x00 @ unused
	131	.long PTE_CACHEABLE \| PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
	132	.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
db5b7169	133	.long 0x00 @ unused
639b0ae7 RK	134	.long 0x00 @ unused
	135	.long 0x00 @ unused
	136	.endm
	137
	138	.macro armv6_set_pte_ext pfx
d30e45ee	139	str r1, [r0], #2048 @ linux version
da091653	140
639b0ae7	141	bic r3, r1, #0x000003fc
da091653 RK	142	bic r3, r3, #PTE_TYPE_MASK
	143	orr r3, r3, r2
	144	orr r3, r3, #PTE_EXT_AP0 \| 2
	145
639b0ae7 RK	146	adr ip, \pfx\()_mt_table
	147	and r2, r1, #L_PTE_MT_MASK
	148	ldr r2, [ip, r2]
	149
36bb94ba RK	150	eor r1, r1, #L_PTE_DIRTY
	151	tst r1, #L_PTE_DIRTY\|L_PTE_RDONLY
	152	orrne r3, r3, #PTE_EXT_APX
da091653 RK	153
	154	tst r1, #L_PTE_USER
	155	orrne r3, r3, #PTE_EXT_AP1
247055aa CM	156	#ifdef CONFIG_CPU_USE_DOMAINS
247055aa CM	157	@ allow kernel read/write access to read-only user pages
da091653 RK	158	tstne r3, #PTE_EXT_APX
da091653 RK	159	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
247055aa	160	#endif
da091653	161
9522d7e4 RK	162	tst r1, #L_PTE_XN
9522d7e4 RK	163	orrne r3, r3, #PTE_EXT_XN
da091653	164
639b0ae7 RK	165	orr r3, r3, r2
639b0ae7 RK	166
da091653 RK	167	tst r1, #L_PTE_YOUNG
	168	tstne r1, #L_PTE_PRESENT
	169	moveq r3, #0
	170
	171	str r3, [r0]
	172	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
	173	.endm
	174
	175
	176	/*
	177	* The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
	178	* covering most CPUs except Xscale and Xscale 3.
	179	*
	180	* Permission translation:
	181	* YUWD AP SVC User
	182	* 0xxx 0x00 no acc no acc
	183	* 100x 0x00 r/o no acc
	184	* 10x0 0x00 r/o no acc
	185	* 1011 0x55 r/w no acc
	186	* 110x 0xaa r/w r/o
	187	* 11x0 0xaa r/w r/o
	188	* 1111 0xff r/w r/w
	189	*/
	190	.macro armv3_set_pte_ext wc_disable=1
d30e45ee	191	str r1, [r0], #2048 @ linux version
da091653	192
36bb94ba	193	eor r3, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_DIRTY
da091653 RK	194
	195	bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
	196	bic r2, r2, #PTE_TYPE_MASK
	197	orr r2, r2, #PTE_TYPE_SMALL
	198
	199	tst r3, #L_PTE_USER @ user?
	200	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	201
36bb94ba	202	tst r3, #L_PTE_RDONLY \| L_PTE_DIRTY @ write and dirty?
da091653 RK	203	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	204
	205	tst r3, #L_PTE_PRESENT \| L_PTE_YOUNG @ present and young?
	206	movne r2, #0
	207
	208	.if \wc_disable
	209	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	210	tst r2, #PTE_CACHEABLE
	211	bicne r2, r2, #PTE_BUFFERABLE
	212	#endif
	213	.endif
d30e45ee	214	str r2, [r0] @ hardware version
da091653 RK	215	.endm
	216
	217
	218	/*
	219	* Xscale set_pte_ext translation, split into two halves to cope
	220	* with work-arounds. r3 must be preserved by code between these
	221	* two macros.
	222	*
	223	* Permission translation:
	224	* YUWD AP SVC User
	225	* 0xxx 00 no acc no acc
	226	* 100x 00 r/o no acc
	227	* 10x0 00 r/o no acc
	228	* 1011 01 r/w no acc
	229	* 110x 10 r/w r/o
	230	* 11x0 10 r/w r/o
	231	* 1111 11 r/w r/w
	232	*/
	233	.macro xscale_set_pte_ext_prologue
d30e45ee	234	str r1, [r0] @ linux version
da091653	235
36bb94ba	236	eor r3, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_DIRTY
da091653 RK	237
	238	bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
	239	orr r2, r2, #PTE_TYPE_EXT @ extended page
	240
	241	tst r3, #L_PTE_USER @ user?
	242	orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
	243
36bb94ba	244	tst r3, #L_PTE_RDONLY \| L_PTE_DIRTY @ write and dirty?
da091653 RK	245	orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
	246	@ combined with user -> user r/w
	247	.endm
	248
	249	.macro xscale_set_pte_ext_epilogue
	250	tst r3, #L_PTE_PRESENT \| L_PTE_YOUNG @ present and young?
	251	movne r2, #0 @ no -> fault
	252
d30e45ee	253	str r2, [r0, #2048]! @ hardware version
da091653 RK	254	mov ip, #0
	255	mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
	256	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	257	.endm
66a625a8 DM	258
	259	.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
	260	.type \name\()_processor_functions, #object
	261	.align 2
	262	ENTRY(\name\()_processor_functions)
	263	.word \dabort
	264	.word \pabort
	265	.word cpu_\name\()_proc_init
	266	.word cpu_\name\()_proc_fin
	267	.word cpu_\name\()_reset
	268	.word cpu_\name\()_do_idle
	269	.word cpu_\name\()_dcache_clean_area
	270	.word cpu_\name\()_switch_mm
	271
	272	.if \nommu
	273	.word 0
	274	.else
	275	.word cpu_\name\()_set_pte_ext
	276	.endif
	277
	278	.if \suspend
	279	.word cpu_\name\()_suspend_size
6645cb61	280	#ifdef CONFIG_PM_SLEEP
66a625a8 DM	281	.word cpu_\name\()_do_suspend
66a625a8 DM	282	.word cpu_\name\()_do_resume
6645cb61 RK	283	#else
	284	.word 0
	285	.word 0
	286	#endif
66a625a8 DM	287	.else
	288	.word 0
	289	.word 0
	290	.word 0
	291	.endif
	292
	293	.size \name\()_processor_functions, . - \name\()_processor_functions
	294	.endm
	295
	296	.macro define_cache_functions name:req
	297	.align 2
	298	.type \name\()_cache_fns, #object
	299	ENTRY(\name\()_cache_fns)
	300	.long \name\()_flush_icache_all
	301	.long \name\()_flush_kern_cache_all
031bd879	302	.long \name\()_flush_kern_cache_louis
66a625a8 DM	303	.long \name\()_flush_user_cache_all
	304	.long \name\()_flush_user_cache_range
	305	.long \name\()_coherent_kern_range
	306	.long \name\()_coherent_user_range
	307	.long \name\()_flush_kern_dcache_area
	308	.long \name\()_dma_map_area
	309	.long \name\()_dma_unmap_area
	310	.long \name\()_dma_flush_range
	311	.size \name\()_cache_fns, . - \name\()_cache_fns
	312	.endm
	313
	314	.macro define_tlb_functions name:req, flags_up:req, flags_smp
	315	.type \name\()_tlb_fns, #object
	316	ENTRY(\name\()_tlb_fns)
	317	.long \name\()_flush_user_tlb_range
	318	.long \name\()_flush_kern_tlb_range
	319	.ifnb \flags_smp
	320	ALT_SMP(.long \flags_smp )
	321	ALT_UP(.long \flags_up )
	322	.else
	323	.long \flags_up
	324	.endif
	325	.size \name\()_tlb_fns, . - \name\()_tlb_fns
	326	.endm