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Merge branch 'net-dsa-Global-2-cosmetics'
[linux.git] / drivers / net / dsa / mv88e6xxx / global2.c
CommitLineData
ec561276 1/*
1d90016d 2 * Marvell 88E6xxx Switch Global 2 Registers support
ec561276
VD		 3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
4333d619
VD		 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <[email protected]>
ec561276
VD		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
e289ef0d 15#include <linux/bitfield.h>
282ccf6e 16#include <linux/interrupt.h>
dc30c35b 17#include <linux/irqdomain.h>
4d5f2ba7
VD		 18
19#include "chip.h"
82466921 20#include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
ec561276
VD		 21#include "global2.h"
22
9fe850fb
VD		 23static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
24{
1d90016d 25 return mv88e6xxx_read(chip, MV88E6XXX_G2, reg, val);
9fe850fb
VD		 26}
27
28static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
29{
1d90016d 30 return mv88e6xxx_write(chip, MV88E6XXX_G2, reg, val);
9fe850fb
VD		 31}
32
33static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
34{
1d90016d 35 return mv88e6xxx_update(chip, MV88E6XXX_G2, reg, update);
9fe850fb
VD		 36}
37
38static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
39{
1d90016d 40 return mv88e6xxx_wait(chip, MV88E6XXX_G2, reg, mask);
9fe850fb
VD		 41}
42
6e55f698
AL		 43/* Offset 0x02: Management Enable 2x */
44/* Offset 0x03: Management Enable 0x */
45
46int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
47{
48 int err;
49
50 /* Consider the frames with reserved multicast destination
51 * addresses matching 01:80:c2:00:00:2x as MGMT.
52 */
53 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
6bff47be 54 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, 0xffff);
6e55f698
AL		 55 if (err)
56 return err;
57 }
58
59 /* Consider the frames with reserved multicast destination
60 * addresses matching 01:80:c2:00:00:0x as MGMT.
61 */
62 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))
6bff47be
VD		 63 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X,
64 0xffff);
6e55f698
AL		 65
66 return 0;
67}
68
ec561276
VD		 69/* Offset 0x06: Device Mapping Table register */
70
71static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
72 int target, int port)
73{
74 u16 val = (target << 8) | (port & 0xf);
75
067e474a 76 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_DEVICE_MAPPING, val);
ec561276
VD		 77}
78
79static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
80{
81 int target, port;
82 int err;
83
84 /* Initialize the routing port to the 32 possible target devices */
85 for (target = 0; target < 32; ++target) {
86 port = 0xf;
87
88 if (target < DSA_MAX_SWITCHES) {
89 port = chip->ds->rtable[target];
90 if (port == DSA_RTABLE_NONE)
91 port = 0xf;
92 }
93
94 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
95 if (err)
96 break;
97 }
98
99 return err;
100}
101
102/* Offset 0x07: Trunk Mask Table register */
103
104static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
56dc7347 105 bool hash, u16 mask)
ec561276 106{
56dc7347 107 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
ec561276 108
56dc7347
VD		 109 if (hash)
110 val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
ec561276 111
56dc7347 112 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MASK, val);
ec561276
VD		 113}
114
115/* Offset 0x08: Trunk Mapping Table register */
116
117static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
118 u16 map)
119{
370b4ffb 120 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
ec561276
VD		 121 u16 val = (id << 11) | (map & port_mask);
122
56dc7347 123 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_TRUNK_MAPPING, val);
ec561276
VD		 124}
125
126static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
127{
370b4ffb 128 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
ec561276
VD		 129 int i, err;
130
131 /* Clear all eight possible Trunk Mask vectors */
132 for (i = 0; i < 8; ++i) {
133 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
134 if (err)
135 return err;
136 }
137
138 /* Clear all sixteen possible Trunk ID routing vectors */
139 for (i = 0; i < 16; ++i) {
140 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
141 if (err)
142 return err;
143 }
144
145 return 0;
146}
147
148/* Offset 0x09: Ingress Rate Command register
149 * Offset 0x0A: Ingress Rate Data register
150 */
151
cd8da8bb 152static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
ec561276 153{
cd8da8bb
VD		 154 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_IRL_CMD,
155 MV88E6XXX_G2_IRL_CMD_BUSY);
156}
ec561276 157
cd8da8bb
VD		 158static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
159 int res, int reg)
160{
161 int err;
ec561276 162
cd8da8bb
VD		 163 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
164 MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
165 (res << 5) | reg);
166 if (err)
167 return err;
168
169 return mv88e6xxx_g2_irl_wait(chip);
170}
171
172int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
173{
174 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
175 0, 0);
176}
177
178int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
179{
180 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
181 0, 0);
ec561276
VD		 182}
183
17a1594e
VD		 184/* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
185 * Offset 0x0C: Cross-chip Port VLAN Data Register
186 */
187
188static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
189{
67d1ea8e
VD		 190 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_PVT_ADDR,
191 MV88E6XXX_G2_PVT_ADDR_BUSY);
17a1594e
VD		 192}
193
194static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
195 int src_port, u16 op)
196{
197 int err;
198
67d1ea8e
VD		 199 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT
200 * cleared, source device is 5-bit, source port is 4-bit.
17a1594e 201 */
67d1ea8e 202 op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
17a1594e
VD		 203 op |= (src_dev & 0x1f) << 4;
204 op |= (src_port & 0xf);
205
67d1ea8e 206 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
17a1594e
VD		 207 if (err)
208 return err;
209
210 return mv88e6xxx_g2_pvt_op_wait(chip);
211}
212
213int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
214 int src_port, u16 data)
215{
216 int err;
217
218 err = mv88e6xxx_g2_pvt_op_wait(chip);
219 if (err)
220 return err;
221
67d1ea8e 222 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
17a1594e
VD		 223 if (err)
224 return err;
225
226 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
67d1ea8e 227 MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
17a1594e
VD		 228}
229
ec561276
VD		 230/* Offset 0x0D: Switch MAC/WoL/WoF register */
231
232static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
233 unsigned int pointer, u8 data)
234{
235 u16 val = (pointer << 8) | data;
236
ed44152f 237 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SWITCH_MAC, val);
ec561276
VD		 238}
239
240int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
241{
242 int i, err;
243
244 for (i = 0; i < 6; i++) {
245 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
246 if (err)
247 break;
248 }
249
250 return err;
251}
252
253/* Offset 0x0F: Priority Override Table */
254
255static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
256 u8 data)
257{
258 u16 val = (pointer << 8) | (data & 0x7);
259
1d90016d 260 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_PRIO_OVERRIDE, val);
ec561276
VD		 261}
262
263static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
264{
265 int i, err;
266
267 /* Clear all sixteen possible Priority Override entries */
268 for (i = 0; i < 16; i++) {
269 err = mv88e6xxx_g2_pot_write(chip, i, 0);
270 if (err)
271 break;
272 }
273
274 return err;
275}
276
277/* Offset 0x14: EEPROM Command
98fc3c6f
VD		 278 * Offset 0x15: EEPROM Data (for 16-bit data access)
279 * Offset 0x15: EEPROM Addr (for 8-bit data access)
ec561276
VD		 280 */
281
282static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
283{
7fc8c9d5
VD		 284 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_EEPROM_CMD,
285 MV88E6XXX_G2_EEPROM_CMD_BUSY |
286 MV88E6XXX_G2_EEPROM_CMD_RUNNING);
ec561276
VD		 287}
288
289static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
290{
291 int err;
292
7fc8c9d5
VD		 293 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
294 MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
ec561276
VD		 295 if (err)
296 return err;
297
298 return mv88e6xxx_g2_eeprom_wait(chip);
299}
300
98fc3c6f
VD		 301static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
302 u16 addr, u8 *data)
303{
7fc8c9d5 304 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
98fc3c6f
VD		 305 int err;
306
307 err = mv88e6xxx_g2_eeprom_wait(chip);
308 if (err)
309 return err;
310
7fc8c9d5 311 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
98fc3c6f
VD		 312 if (err)
313 return err;
314
315 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
316 if (err)
317 return err;
318
7fc8c9d5 319 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
98fc3c6f
VD		 320 if (err)
321 return err;
322
323 *data = cmd & 0xff;
324
325 return 0;
326}
327
328static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
329 u16 addr, u8 data)
330{
7fc8c9d5
VD		 331 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
332 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
98fc3c6f
VD		 333 int err;
334
335 err = mv88e6xxx_g2_eeprom_wait(chip);
336 if (err)
337 return err;
338
7fc8c9d5 339 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
98fc3c6f
VD		 340 if (err)
341 return err;
342
343 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
344}
345
ec561276
VD		 346static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
347 u8 addr, u16 *data)
348{
7fc8c9d5 349 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
ec561276
VD		 350 int err;
351
352 err = mv88e6xxx_g2_eeprom_wait(chip);
353 if (err)
354 return err;
355
356 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
357 if (err)
358 return err;
359
7fc8c9d5 360 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
ec561276
VD		 361}
362
363static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
364 u8 addr, u16 data)
365{
7fc8c9d5 366 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
ec561276
VD		 367 int err;
368
369 err = mv88e6xxx_g2_eeprom_wait(chip);
370 if (err)
371 return err;
372
7fc8c9d5 373 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
ec561276
VD		 374 if (err)
375 return err;
376
377 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
378}
379
98fc3c6f
VD		 380int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
381 struct ethtool_eeprom *eeprom, u8 *data)
382{
383 unsigned int offset = eeprom->offset;
384 unsigned int len = eeprom->len;
385 int err;
386
387 eeprom->len = 0;
388
389 while (len) {
390 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
391 if (err)
392 return err;
393
394 eeprom->len++;
395 offset++;
396 data++;
397 len--;
398 }
399
400 return 0;
401}
402
403int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
404 struct ethtool_eeprom *eeprom, u8 *data)
405{
406 unsigned int offset = eeprom->offset;
407 unsigned int len = eeprom->len;
408 int err;
409
410 eeprom->len = 0;
411
412 while (len) {
413 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
414 if (err)
415 return err;
416
417 eeprom->len++;
418 offset++;
419 data++;
420 len--;
421 }
422
423 return 0;
424}
425
ec561276
VD		 426int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
427 struct ethtool_eeprom *eeprom, u8 *data)
428{
429 unsigned int offset = eeprom->offset;
430 unsigned int len = eeprom->len;
431 u16 val;
432 int err;
433
434 eeprom->len = 0;
435
436 if (offset & 1) {
437 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
438 if (err)
439 return err;
440
441 *data++ = (val >> 8) & 0xff;
442
443 offset++;
444 len--;
445 eeprom->len++;
446 }
447
448 while (len >= 2) {
449 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
450 if (err)
451 return err;
452
453 *data++ = val & 0xff;
454 *data++ = (val >> 8) & 0xff;
455
456 offset += 2;
457 len -= 2;
458 eeprom->len += 2;
459 }
460
461 if (len) {
462 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
463 if (err)
464 return err;
465
466 *data++ = val & 0xff;
467
468 offset++;
469 len--;
470 eeprom->len++;
471 }
472
473 return 0;
474}
475
476int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
477 struct ethtool_eeprom *eeprom, u8 *data)
478{
479 unsigned int offset = eeprom->offset;
480 unsigned int len = eeprom->len;
481 u16 val;
482 int err;
483
484 /* Ensure the RO WriteEn bit is set */
7fc8c9d5 485 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
ec561276
VD		 486 if (err)
487 return err;
488
7fc8c9d5 489 if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
ec561276
VD		 490 return -EROFS;
491
492 eeprom->len = 0;
493
494 if (offset & 1) {
495 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
496 if (err)
497 return err;
498
499 val = (*data++ << 8) | (val & 0xff);
500
501 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
502 if (err)
503 return err;
504
505 offset++;
506 len--;
507 eeprom->len++;
508 }
509
510 while (len >= 2) {
511 val = *data++;
512 val |= *data++ << 8;
513
514 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
515 if (err)
516 return err;
517
518 offset += 2;
519 len -= 2;
520 eeprom->len += 2;
521 }
522
523 if (len) {
524 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
525 if (err)
526 return err;
527
528 val = (val & 0xff00) | *data++;
529
530 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
531 if (err)
532 return err;
533
534 offset++;
535 len--;
536 eeprom->len++;
537 }
538
539 return 0;
540}
541
542/* Offset 0x18: SMI PHY Command Register
543 * Offset 0x19: SMI PHY Data Register
544 */
545
546static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
547{
e289ef0d
VD		 548 return mv88e6xxx_g2_wait(chip, MV88E6XXX_G2_SMI_PHY_CMD,
549 MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
ec561276
VD		 550}
551
552static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
553{
554 int err;
555
e289ef0d
VD		 556 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
557 MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
ec561276
VD		 558 if (err)
559 return err;
560
561 return mv88e6xxx_g2_smi_phy_wait(chip);
562}
563
e289ef0d
VD		 564static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
565 bool external, bool c45, u16 op, int dev,
566 int reg)
cf3e80df 567{
e289ef0d 568 u16 cmd = op;
cf3e80df
AL		 569
570 if (external)
e289ef0d
VD		 571 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
572 else
573 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL; /* empty mask */
cf3e80df 574
e289ef0d
VD		 575 if (c45)
576 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45; /* empty mask */
577 else
578 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
cf3e80df 579
e289ef0d
VD		 580 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
581 cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
582 cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
cf3e80df
AL		 583
584 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
585}
586
e289ef0d
VD		 587static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
588 bool external, u16 op, int dev,
589 int reg)
cf3e80df 590{
e289ef0d
VD		 591 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
592}
593
594/* IEEE 802.3 Clause 22 Read Data Register */
595static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
596 bool external, int dev, int reg,
597 u16 *data)
598{
599 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
cf3e80df 600 int err;
cf3e80df 601
e289ef0d 602 err = mv88e6xxx_g2_smi_phy_wait(chip);
cf3e80df
AL		 603 if (err)
604 return err;
605
e289ef0d
VD		 606 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
607 if (err)
608 return err;
cf3e80df 609
e289ef0d
VD		 610 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
611}
cf3e80df 612
e289ef0d
VD		 613/* IEEE 802.3 Clause 22 Write Data Register */
614static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
615 bool external, int dev, int reg,
616 u16 data)
617{
618 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
619 int err;
620
621 err = mv88e6xxx_g2_smi_phy_wait(chip);
cf3e80df
AL		 622 if (err)
623 return err;
624
e289ef0d 625 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
cf3e80df
AL		 626 if (err)
627 return err;
628
e289ef0d
VD		 629 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
630}
cf3e80df 631
e289ef0d
VD		 632static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
633 bool external, u16 op, int port,
634 int dev)
635{
636 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
cf3e80df
AL		 637}
638
e289ef0d
VD		 639/* IEEE 802.3 Clause 45 Write Address Register */
640static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
641 bool external, int port, int dev,
642 int addr)
cf3e80df 643{
e289ef0d 644 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
cf3e80df
AL		 645 int err;
646
cf3e80df
AL		 647 err = mv88e6xxx_g2_smi_phy_wait(chip);
648 if (err)
649 return err;
650
e289ef0d 651 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
cf3e80df
AL		 652 if (err)
653 return err;
654
e289ef0d 655 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
cf3e80df
AL		 656}
657
e289ef0d
VD		 658/* IEEE 802.3 Clause 45 Read Data Register */
659static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
660 bool external, int port, int dev,
661 u16 *data)
ec561276 662{
e289ef0d
VD		 663 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
664 int err;
cf3e80df 665
e289ef0d
VD		 666 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
667 if (err)
668 return err;
669
670 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
cf3e80df
AL		 671}
672
e289ef0d
VD		 673static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
674 bool external, int port, int reg,
675 u16 *data)
cf3e80df 676{
e289ef0d
VD		 677 int dev = (reg >> 16) & 0x1f;
678 int addr = reg & 0xffff;
ec561276
VD		 679 int err;
680
e289ef0d
VD		 681 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
682 addr);
cf3e80df
AL		 683 if (err)
684 return err;
685
e289ef0d
VD		 686 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
687 data);
688}
c61a6a71 689
e289ef0d
VD		 690/* IEEE 802.3 Clause 45 Write Data Register */
691static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
692 bool external, int port, int dev,
693 u16 data)
694{
695 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
696 int err;
ec561276 697
e289ef0d 698 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
ec561276
VD		 699 if (err)
700 return err;
701
e289ef0d 702 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
ec561276
VD		 703}
704
e289ef0d
VD		 705static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
706 bool external, int port, int reg,
707 u16 data)
ec561276 708{
e289ef0d
VD		 709 int dev = (reg >> 16) & 0x1f;
710 int addr = reg & 0xffff;
ec561276
VD		 711 int err;
712
e289ef0d
VD		 713 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
714 addr);
ec561276
VD		 715 if (err)
716 return err;
717
e289ef0d
VD		 718 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
719 data);
720}
ec561276 721
e289ef0d
VD		 722int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
723 int addr, int reg, u16 *val)
724{
725 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
726 bool external = mdio_bus->external;
727
728 if (reg & MII_ADDR_C45)
729 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
730 val);
731
732 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
733 val);
ec561276
VD		 734}
735
e289ef0d 736int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
cf3e80df
AL		 737 int addr, int reg, u16 val)
738{
739 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
740 bool external = mdio_bus->external;
741
742 if (reg & MII_ADDR_C45)
e289ef0d
VD		 743 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
744 val);
cf3e80df 745
e289ef0d
VD		 746 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
747 val);
cf3e80df
AL		 748}
749
fcd25166
AL		 750static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
751{
752 u16 reg;
753
3b19df73 754 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, &reg);
fcd25166
AL		 755
756 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
757
758 return IRQ_HANDLED;
759}
760
761static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
762{
763 u16 reg;
764
3b19df73 765 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, &reg);
fcd25166 766
3b19df73
VD		 767 reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
768 MV88E6352_G2_WDOG_CTL_QC_ENABLE);
fcd25166 769
3b19df73 770 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
fcd25166
AL		 771}
772
773static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
774{
3b19df73
VD		 775 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
776 MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
777 MV88E6352_G2_WDOG_CTL_QC_ENABLE |
778 MV88E6352_G2_WDOG_CTL_SWRESET);
fcd25166
AL		 779}
780
781const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
782 .irq_action = mv88e6097_watchdog_action,
783 .irq_setup = mv88e6097_watchdog_setup,
784 .irq_free = mv88e6097_watchdog_free,
785};
786
61303736
AL		 787static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
788{
3b19df73
VD		 789 return mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
790 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
791 MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
792 MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
793 MV88E6390_G2_WDOG_CTL_EGRESS |
794 MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
61303736
AL		 795}
796
797static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
798{
799 int err;
800 u16 reg;
801
3b19df73
VD		 802 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
803 MV88E6390_G2_WDOG_CTL_PTR_EVENT);
804 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, &reg);
61303736
AL		 805
806 dev_info(chip->dev, "Watchdog event: 0x%04x",
3b19df73 807 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
61303736 808
3b19df73
VD		 809 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
810 MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
811 err = mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, &reg);
61303736
AL		 812
813 dev_info(chip->dev, "Watchdog history: 0x%04x",
3b19df73 814 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
61303736
AL		 815
816 /* Trigger a software reset to try to recover the switch */
817 if (chip->info->ops->reset)
818 chip->info->ops->reset(chip);
819
820 mv88e6390_watchdog_setup(chip);
821
822 return IRQ_HANDLED;
823}
824
825static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
826{
3b19df73
VD		 827 mv88e6xxx_g2_update(chip, MV88E6390_G2_WDOG_CTL,
828 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
61303736
AL		 829}
830
831const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
832 .irq_action = mv88e6390_watchdog_action,
833 .irq_setup = mv88e6390_watchdog_setup,
834 .irq_free = mv88e6390_watchdog_free,
835};
836
fcd25166
AL		 837static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
838{
839 struct mv88e6xxx_chip *chip = dev_id;
840 irqreturn_t ret = IRQ_NONE;
841
842 mutex_lock(&chip->reg_lock);
843 if (chip->info->ops->watchdog_ops->irq_action)
844 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
845 mutex_unlock(&chip->reg_lock);
846
847 return ret;
848}
849
850static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
851{
852 mutex_lock(&chip->reg_lock);
853 if (chip->info->ops->watchdog_ops->irq_free)
854 chip->info->ops->watchdog_ops->irq_free(chip);
855 mutex_unlock(&chip->reg_lock);
856
857 free_irq(chip->watchdog_irq, chip);
858 irq_dispose_mapping(chip->watchdog_irq);
859}
860
861static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
862{
863 int err;
864
865 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
1d90016d 866 MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
fcd25166
AL		 867 if (chip->watchdog_irq < 0)
868 return chip->watchdog_irq;
869
870 err = request_threaded_irq(chip->watchdog_irq, NULL,
871 mv88e6xxx_g2_watchdog_thread_fn,
872 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
873 "mv88e6xxx-watchdog", chip);
874 if (err)
875 return err;
876
877 mutex_lock(&chip->reg_lock);
878 if (chip->info->ops->watchdog_ops->irq_setup)
879 err = chip->info->ops->watchdog_ops->irq_setup(chip);
880 mutex_unlock(&chip->reg_lock);
881
882 return err;
883}
884
81228996
VD		 885/* Offset 0x1D: Misc Register */
886
887static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
888 bool port_5_bit)
889{
890 u16 val;
891 int err;
892
1d90016d 893 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
81228996
VD		 894 if (err)
895 return err;
896
897 if (port_5_bit)
1d90016d 898 val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
81228996 899 else
1d90016d 900 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
81228996 901
1d90016d 902 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
81228996
VD		 903}
904
905int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
906{
907 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
908}
909
dc30c35b
AL		 910static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
911{
912 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
913 unsigned int n = d->hwirq;
914
915 chip->g2_irq.masked |= (1 << n);
916}
917
918static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
919{
920 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
921 unsigned int n = d->hwirq;
922
923 chip->g2_irq.masked &= ~(1 << n);
924}
925
926static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
927{
928 struct mv88e6xxx_chip *chip = dev_id;
929 unsigned int nhandled = 0;
930 unsigned int sub_irq;
931 unsigned int n;
932 int err;
933 u16 reg;
934
935 mutex_lock(&chip->reg_lock);
1d90016d 936 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SOURCE, &reg);
dc30c35b
AL		 937 mutex_unlock(&chip->reg_lock);
938 if (err)
939 goto out;
940
941 for (n = 0; n < 16; ++n) {
942 if (reg & (1 << n)) {
943 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
944 handle_nested_irq(sub_irq);
945 ++nhandled;
946 }
947 }
948out:
949 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
950}
951
952static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
953{
954 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
955
956 mutex_lock(&chip->reg_lock);
957}
958
959static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
960{
961 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
962
1d90016d 963 mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, ~chip->g2_irq.masked);
dc30c35b
AL		 964
965 mutex_unlock(&chip->reg_lock);
966}
967
968static struct irq_chip mv88e6xxx_g2_irq_chip = {
969 .name = "mv88e6xxx-g2",
970 .irq_mask = mv88e6xxx_g2_irq_mask,
971 .irq_unmask = mv88e6xxx_g2_irq_unmask,
972 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
973 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
974};
975
976static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
977 unsigned int irq,
978 irq_hw_number_t hwirq)
979{
980 struct mv88e6xxx_chip *chip = d->host_data;
981
982 irq_set_chip_data(irq, d->host_data);
983 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
984 irq_set_noprobe(irq);
985
986 return 0;
987}
988
989static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
990 .map = mv88e6xxx_g2_irq_domain_map,
991 .xlate = irq_domain_xlate_twocell,
992};
993
994void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
995{
996 int irq, virq;
997
fcd25166
AL		 998 mv88e6xxx_g2_watchdog_free(chip);
999
8e757eba
AL		 1000 free_irq(chip->device_irq, chip);
1001 irq_dispose_mapping(chip->device_irq);
1002
dc30c35b
AL		 1003 for (irq = 0; irq < 16; irq++) {
1004 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1005 irq_dispose_mapping(virq);
1006 }
1007
1008 irq_domain_remove(chip->g2_irq.domain);
1009}
1010
1011int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1012{
8e757eba 1013 int err, irq, virq;
dc30c35b
AL		 1014
1015 if (!chip->dev->of_node)
1016 return -EINVAL;
1017
1018 chip->g2_irq.domain = irq_domain_add_simple(
1019 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1020 if (!chip->g2_irq.domain)
1021 return -ENOMEM;
1022
1023 for (irq = 0; irq < 16; irq++)
1024 irq_create_mapping(chip->g2_irq.domain, irq);
1025
1026 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1027 chip->g2_irq.masked = ~0;
1028
8e757eba 1029 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
82466921 1030 MV88E6XXX_G1_STS_IRQ_DEVICE);
8e757eba
AL		 1031 if (chip->device_irq < 0) {
1032 err = chip->device_irq;
dc30c35b
AL		 1033 goto out;
1034 }
1035
8e757eba
AL		 1036 err = request_threaded_irq(chip->device_irq, NULL,
1037 mv88e6xxx_g2_irq_thread_fn,
1038 IRQF_ONESHOT, "mv88e6xxx-g1", chip);
dc30c35b
AL		 1039 if (err)
1040 goto out;
1041
fcd25166 1042 return mv88e6xxx_g2_watchdog_setup(chip);
8e757eba 1043
dc30c35b 1044out:
8e757eba
AL		 1045 for (irq = 0; irq < 16; irq++) {
1046 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1047 irq_dispose_mapping(virq);
1048 }
1049
1050 irq_domain_remove(chip->g2_irq.domain);
dc30c35b
AL		 1051
1052 return err;
1053}
1054
ec561276
VD		 1055int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
1056{
1057 u16 reg;
1058 int err;
1059
ec561276
VD		 1060 /* Ignore removed tag data on doubly tagged packets, disable
1061 * flow control messages, force flow control priority to the
1062 * highest, and send all special multicast frames to the CPU
1063 * port at the highest priority.
1064 */
6bff47be 1065 reg = MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI | (0x7 << 4);
ec561276
VD		 1066 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
1067 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
6bff47be
VD		 1068 reg |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU | 0x7;
1069 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, reg);
ec561276
VD		 1070 if (err)
1071 return err;
1072
1073 /* Program the DSA routing table. */
1074 err = mv88e6xxx_g2_set_device_mapping(chip);
1075 if (err)
1076 return err;
1077
1078 /* Clear all trunk masks and mapping. */
1079 err = mv88e6xxx_g2_clear_trunk(chip);
1080 if (err)
1081 return err;
1082
ec561276
VD		 1083 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
1084 /* Clear the priority override table. */
1085 err = mv88e6xxx_g2_clear_pot(chip);
1086 if (err)
1087 return err;
1088 }
1089
1090 return 0;
1091}
Empty description
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