[linux.git] / drivers / gpio / gpio-ath79.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Atheros AR71XX/AR724X/AR913X GPIO API support
 *
 *  Copyright (C) 2015 Alban Bedel <[email protected]>
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
 *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
 *  Copyright (C) 2008 Imre Kaloz <[email protected]>
 */

#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/platform_data/gpio-ath79.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>

#define AR71XX_GPIO_REG_OE		0x00
#define AR71XX_GPIO_REG_IN		0x04
#define AR71XX_GPIO_REG_SET		0x0c
#define AR71XX_GPIO_REG_CLEAR		0x10

#define AR71XX_GPIO_REG_INT_ENABLE	0x14
#define AR71XX_GPIO_REG_INT_TYPE	0x18
#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
#define AR71XX_GPIO_REG_INT_PENDING	0x20
#define AR71XX_GPIO_REG_INT_MASK	0x24

struct ath79_gpio_ctrl {
	struct gpio_chip gc;
	void __iomem *base;
	raw_spinlock_t lock;
	unsigned long both_edges;
};

static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);

	return container_of(gc, struct ath79_gpio_ctrl, gc);
}

static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
{
	return readl(ctrl->base + reg);
}

static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
			unsigned reg, u32 val)
{
	writel(val, ctrl->base + reg);
}

static bool ath79_gpio_update_bits(
	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
{
	u32 old_val, new_val;

	old_val = ath79_gpio_read(ctrl, reg);
	new_val = (old_val & ~mask) | (bits & mask);

	if (new_val != old_val)
		ath79_gpio_write(ctrl, reg, new_val);

	return new_val != old_val;
}

static void ath79_gpio_irq_unmask(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data));
	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static void ath79_gpio_irq_mask(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
	gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data));
}

static void ath79_gpio_irq_enable(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static void ath79_gpio_irq_disable(struct irq_data *data)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	unsigned long flags;

	raw_spin_lock_irqsave(&ctrl->lock, flags);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
}

static int ath79_gpio_irq_set_type(struct irq_data *data,
				unsigned int flow_type)
{
	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	u32 mask = BIT(irqd_to_hwirq(data));
	u32 type = 0, polarity = 0;
	unsigned long flags;
	bool disabled;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_RISING:
		polarity |= mask;
		fallthrough;
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_EDGE_BOTH:
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		polarity |= mask;
		fallthrough;
	case IRQ_TYPE_LEVEL_LOW:
		type |= mask;
		break;

	default:
		return -EINVAL;
	}

	raw_spin_lock_irqsave(&ctrl->lock, flags);

	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
		ctrl->both_edges |= mask;
		polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	} else {
		ctrl->both_edges &= ~mask;
	}

	/* As the IRQ configuration can't be loaded atomically we
	 * have to disable the interrupt while the configuration state
	 * is invalid.
	 */
	disabled = ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);

	ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
	ath79_gpio_update_bits(
		ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);

	if (disabled)
		ath79_gpio_update_bits(
			ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);

	raw_spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static const struct irq_chip ath79_gpio_irqchip = {
	.name = "gpio-ath79",
	.irq_enable = ath79_gpio_irq_enable,
	.irq_disable = ath79_gpio_irq_disable,
	.irq_mask = ath79_gpio_irq_mask,
	.irq_unmask = ath79_gpio_irq_unmask,
	.irq_set_type = ath79_gpio_irq_set_type,
	.flags = IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void ath79_gpio_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	struct ath79_gpio_ctrl *ctrl =
		container_of(gc, struct ath79_gpio_ctrl, gc);
	unsigned long flags, pending;
	u32 both_edges, state;
	int irq;

	chained_irq_enter(irqchip, desc);

	raw_spin_lock_irqsave(&ctrl->lock, flags);

	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);

	/* Update the polarity of the both edges irqs */
	both_edges = ctrl->both_edges & pending;
	if (both_edges) {
		state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
		ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
				both_edges, ~state);
	}

	raw_spin_unlock_irqrestore(&ctrl->lock, flags);

	for_each_set_bit(irq, &pending, gc->ngpio)
		generic_handle_domain_irq(gc->irq.domain, irq);

	chained_irq_exit(irqchip, desc);
}

static const struct of_device_id ath79_gpio_of_match[] = {
	{ .compatible = "qca,ar7100-gpio" },
	{ .compatible = "qca,ar9340-gpio" },
	{},
};
MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);

static int ath79_gpio_probe(struct platform_device *pdev)
{
	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct ath79_gpio_ctrl *ctrl;
	struct gpio_irq_chip *girq;
	u32 ath79_gpio_count;
	bool oe_inverted;
	int err;

	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl)
		return -ENOMEM;

	if (np) {
		err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
		if (err) {
			dev_err(dev, "ngpios property is not valid\n");
			return err;
		}
		oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	} else if (pdata) {
		ath79_gpio_count = pdata->ngpios;
		oe_inverted = pdata->oe_inverted;
	} else {
		dev_err(dev, "No DT node or platform data found\n");
		return -EINVAL;
	}

	if (ath79_gpio_count >= 32) {
		dev_err(dev, "ngpios must be less than 32\n");
		return -EINVAL;
	}

	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(ctrl->base))
		return PTR_ERR(ctrl->base);

	raw_spin_lock_init(&ctrl->lock);
	err = bgpio_init(&ctrl->gc, dev, 4,
			ctrl->base + AR71XX_GPIO_REG_IN,
			ctrl->base + AR71XX_GPIO_REG_SET,
			ctrl->base + AR71XX_GPIO_REG_CLEAR,
			oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
			oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
			0);
	if (err) {
		dev_err(dev, "bgpio_init failed\n");
		return err;
	}
	/* Use base 0 to stay compatible with legacy platforms */
	ctrl->gc.base = 0;

	/* Optional interrupt setup */
	if (!np || of_property_read_bool(np, "interrupt-controller")) {
		girq = &ctrl->gc.irq;
		gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip);
		girq->parent_handler = ath79_gpio_irq_handler;
		girq->num_parents = 1;
		girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
					     GFP_KERNEL);
		if (!girq->parents)
			return -ENOMEM;
		girq->parents[0] = platform_get_irq(pdev, 0);
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_simple_irq;
	}

	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
}

static struct platform_driver ath79_gpio_driver = {
	.driver = {
		.name = "ath79-gpio",
		.of_match_table	= ath79_gpio_of_match,
	},
	.probe = ath79_gpio_probe,
};

module_platform_driver(ath79_gpio_driver);

MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
6eae43c5 GJ	2	/*
	3	* Atheros AR71XX/AR724X/AR913X GPIO API support
	4	*
28be55df	5	* Copyright (C) 2015 Alban Bedel <[email protected]>
5b5b544e GJ	6	* Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
5b5b544e GJ	7	* Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
6eae43c5	8	* Copyright (C) 2008 Imre Kaloz <[email protected]>
6eae43c5 GJ	9	*/
6eae43c5 GJ	10
49a5bd88	11	#include <linux/gpio/driver.h>
e91d0f05	12	#include <linux/platform_device.h>
2ddf3a79	13	#include <linux/platform_data/gpio-ath79.h>
e91d0f05	14	#include <linux/of.h>
2b8f89e1	15	#include <linux/interrupt.h>
2034b9dc	16	#include <linux/module.h>
2b8f89e1	17	#include <linux/irq.h>
6eae43c5	18
409d8783 AB	19	#define AR71XX_GPIO_REG_OE 0x00
	20	#define AR71XX_GPIO_REG_IN 0x04
	21	#define AR71XX_GPIO_REG_SET 0x0c
	22	#define AR71XX_GPIO_REG_CLEAR 0x10
6eae43c5	23
2b8f89e1 AB	24	#define AR71XX_GPIO_REG_INT_ENABLE 0x14
	25	#define AR71XX_GPIO_REG_INT_TYPE 0x18
	26	#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
	27	#define AR71XX_GPIO_REG_INT_PENDING 0x20
	28	#define AR71XX_GPIO_REG_INT_MASK 0x24
	29
49a5bd88	30	struct ath79_gpio_ctrl {
ab32770e	31	struct gpio_chip gc;
49a5bd88	32	void __iomem *base;
a080ce53	33	raw_spinlock_t lock;
2b8f89e1 AB	34	unsigned long both_edges;
	35	};
	36
	37	static struct ath79_gpio_ctrl irq_data_to_ath79_gpio(struct irq_data data)
	38	{
	39	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
	40
	41	return container_of(gc, struct ath79_gpio_ctrl, gc);
	42	}
	43
	44	static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
	45	{
	46	return readl(ctrl->base + reg);
	47	}
	48
	49	static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
	50	unsigned reg, u32 val)
	51	{
23211b08	52	writel(val, ctrl->base + reg);
2b8f89e1 AB	53	}
	54
	55	static bool ath79_gpio_update_bits(
	56	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
	57	{
	58	u32 old_val, new_val;
	59
	60	old_val = ath79_gpio_read(ctrl, reg);
	61	new_val = (old_val & ~mask) \| (bits & mask);
	62
	63	if (new_val != old_val)
	64	ath79_gpio_write(ctrl, reg, new_val);
	65
	66	return new_val != old_val;
	67	}
	68
	69	static void ath79_gpio_irq_unmask(struct irq_data *data)
	70	{
	71	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	72	u32 mask = BIT(irqd_to_hwirq(data));
	73	unsigned long flags;
	74
b11ce7e4	75	gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data));
a080ce53	76	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1	77	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
a080ce53	78	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	79	}
	80
	81	static void ath79_gpio_irq_mask(struct irq_data *data)
	82	{
	83	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	84	u32 mask = BIT(irqd_to_hwirq(data));
	85	unsigned long flags;
	86
a080ce53	87	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1	88	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
a080ce53	89	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
b11ce7e4	90	gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data));
2b8f89e1 AB	91	}
	92
	93	static void ath79_gpio_irq_enable(struct irq_data *data)
	94	{
	95	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	96	u32 mask = BIT(irqd_to_hwirq(data));
	97	unsigned long flags;
	98
a080ce53	99	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	100	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
2b8f89e1 AB	101	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
a080ce53	102	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	103	}
	104
	105	static void ath79_gpio_irq_disable(struct irq_data *data)
	106	{
	107	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	108	u32 mask = BIT(irqd_to_hwirq(data));
	109	unsigned long flags;
	110
a080ce53	111	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	112	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
2b8f89e1 AB	113	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
a080ce53	114	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	115	}
	116
	117	static int ath79_gpio_irq_set_type(struct irq_data *data,
	118	unsigned int flow_type)
	119	{
	120	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
	121	u32 mask = BIT(irqd_to_hwirq(data));
	122	u32 type = 0, polarity = 0;
	123	unsigned long flags;
	124	bool disabled;
	125
	126	switch (flow_type) {
	127	case IRQ_TYPE_EDGE_RISING:
	128	polarity \|= mask;
d49ee562	129	fallthrough;
2b8f89e1 AB	130	case IRQ_TYPE_EDGE_FALLING:
	131	case IRQ_TYPE_EDGE_BOTH:
	132	break;
	133
	134	case IRQ_TYPE_LEVEL_HIGH:
	135	polarity \|= mask;
df561f66	136	fallthrough;
2b8f89e1 AB	137	case IRQ_TYPE_LEVEL_LOW:
	138	type \|= mask;
	139	break;
	140
	141	default:
	142	return -EINVAL;
	143	}
	144
a080ce53	145	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	146
	147	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
	148	ctrl->both_edges \|= mask;
	149	polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	150	} else {
	151	ctrl->both_edges &= ~mask;
	152	}
	153
	154	/* As the IRQ configuration can't be loaded atomically we
	155	* have to disable the interrupt while the configuration state
	156	* is invalid.
	157	*/
	158	disabled = ath79_gpio_update_bits(
	159	ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
	160
	161	ath79_gpio_update_bits(
	162	ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
	163	ath79_gpio_update_bits(
	164	ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
	165
	166	if (disabled)
	167	ath79_gpio_update_bits(
	168	ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
	169
a080ce53	170	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1 AB	171
	172	return 0;
	173	}
	174
b11ce7e4	175	static const struct irq_chip ath79_gpio_irqchip = {
2b8f89e1 AB	176	.name = "gpio-ath79",
	177	.irq_enable = ath79_gpio_irq_enable,
	178	.irq_disable = ath79_gpio_irq_disable,
	179	.irq_mask = ath79_gpio_irq_mask,
	180	.irq_unmask = ath79_gpio_irq_unmask,
	181	.irq_set_type = ath79_gpio_irq_set_type,
b11ce7e4 LW	182	.flags = IRQCHIP_IMMUTABLE,
b11ce7e4 LW	183	GPIOCHIP_IRQ_RESOURCE_HELPERS,
49a5bd88 AB	184	};
49a5bd88 AB	185
2b8f89e1 AB	186	static void ath79_gpio_irq_handler(struct irq_desc *desc)
	187	{
	188	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	189	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	190	struct ath79_gpio_ctrl *ctrl =
	191	container_of(gc, struct ath79_gpio_ctrl, gc);
	192	unsigned long flags, pending;
	193	u32 both_edges, state;
	194	int irq;
	195
	196	chained_irq_enter(irqchip, desc);
	197
a080ce53	198	raw_spin_lock_irqsave(&ctrl->lock, flags);
2b8f89e1 AB	199
	200	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
	201
	202	/* Update the polarity of the both edges irqs */
	203	both_edges = ctrl->both_edges & pending;
	204	if (both_edges) {
	205	state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
	206	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
	207	both_edges, ~state);
	208	}
	209
a080ce53	210	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
2b8f89e1	211
dbd1c54f MZ	212	for_each_set_bit(irq, &pending, gc->ngpio)
dbd1c54f MZ	213	generic_handle_domain_irq(gc->irq.domain, irq);
2b8f89e1 AB	214
	215	chained_irq_exit(irqchip, desc);
	216	}
	217
2ddf3a79 AB	218	static const struct of_device_id ath79_gpio_of_match[] = {
	219	{ .compatible = "qca,ar7100-gpio" },
	220	{ .compatible = "qca,ar9340-gpio" },
	221	{},
	222	};
6d8d271e	223	MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
2ddf3a79 AB	224
2ddf3a79 AB	225	static int ath79_gpio_probe(struct platform_device *pdev)
6eae43c5	226	{
ab128afc	227	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
aee5cec5 LW	228	struct device *dev = &pdev->dev;
aee5cec5 LW	229	struct device_node *np = dev->of_node;
49a5bd88	230	struct ath79_gpio_ctrl *ctrl;
aee5cec5	231	struct gpio_irq_chip *girq;
49a5bd88	232	u32 ath79_gpio_count;
2ddf3a79	233	bool oe_inverted;
6eae43c5 GJ	234	int err;
6eae43c5 GJ	235
aee5cec5	236	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
49a5bd88 AB	237	if (!ctrl)
	238	return -ENOMEM;
	239
2ddf3a79 AB	240	if (np) {
	241	err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
	242	if (err) {
aee5cec5	243	dev_err(dev, "ngpios property is not valid\n");
2ddf3a79 AB	244	return err;
2ddf3a79 AB	245	}
2ddf3a79 AB	246	oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	247	} else if (pdata) {
	248	ath79_gpio_count = pdata->ngpios;
	249	oe_inverted = pdata->oe_inverted;
	250	} else {
aee5cec5	251	dev_err(dev, "No DT node or platform data found\n");
2ddf3a79 AB	252	return -EINVAL;
	253	}
	254
f0d3c72c	255	if (ath79_gpio_count >= 32) {
aee5cec5	256	dev_err(dev, "ngpios must be less than 32\n");
f0d3c72c AL	257	return -EINVAL;
	258	}
	259
71b4da2b BG	260	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
	261	if (IS_ERR(ctrl->base))
	262	return PTR_ERR(ctrl->base);
6eae43c5	263
a080ce53	264	raw_spin_lock_init(&ctrl->lock);
aee5cec5	265	err = bgpio_init(&ctrl->gc, dev, 4,
ab32770e AB	266	ctrl->base + AR71XX_GPIO_REG_IN,
	267	ctrl->base + AR71XX_GPIO_REG_SET,
	268	ctrl->base + AR71XX_GPIO_REG_CLEAR,
	269	oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
	270	oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
	271	0);
	272	if (err) {
aee5cec5	273	dev_err(dev, "bgpio_init failed\n");
ab32770e	274	return err;
5b5b544e	275	}
ab32770e AB	276	/* Use base 0 to stay compatible with legacy platforms */
ab32770e AB	277	ctrl->gc.base = 0;
6eae43c5	278
aee5cec5 LW	279	/* Optional interrupt setup */
	280	if (!np \|\| of_property_read_bool(np, "interrupt-controller")) {
	281	girq = &ctrl->gc.irq;
b11ce7e4	282	gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip);
aee5cec5 LW	283	girq->parent_handler = ath79_gpio_irq_handler;
	284	girq->num_parents = 1;
	285	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	286	GFP_KERNEL);
	287	if (!girq->parents)
	288	return -ENOMEM;
	289	girq->parents[0] = platform_get_irq(pdev, 0);
	290	girq->default_type = IRQ_TYPE_NONE;
	291	girq->handler = handle_simple_irq;
2ddf3a79 AB	292	}
2ddf3a79 AB	293
cd440753	294	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
2f890cf0 AB	295	}
2f890cf0 AB	296
2ddf3a79 AB	297	static struct platform_driver ath79_gpio_driver = {
	298	.driver = {
	299	.name = "ath79-gpio",
	300	.of_match_table = ath79_gpio_of_match,
	301	},
	302	.probe = ath79_gpio_probe,
	303	};
	304
	305	module_platform_driver(ath79_gpio_driver);
539340f3 JC	306
	307	MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
	308	MODULE_LICENSE("GPL v2");