[linux.git] / drivers / spi / spi-mxs.c

/*
 * Freescale MXS SPI master driver
 *
 * Copyright 2012 DENX Software Engineering, GmbH.
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 *
 * Rework and transition to new API by:
 * Marek Vasut <[email protected]>
 *
 * Based on previous attempt by:
 * Fabio Estevam <[email protected]>
 *
 * Based on code from U-Boot bootloader by:
 * Marek Vasut <[email protected]>
 *
 * Based on spi-stmp.c, which is:
 * Author: Dmitry Pervushin <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/module.h>
#include <linux/stmp_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/mxs-spi.h>

#define DRIVER_NAME		"mxs-spi"

/* Use 10S timeout for very long transfers, it should suffice. */
#define SSP_TIMEOUT		10000

#define SG_MAXLEN		0xff00

/*
 * Flags for txrx functions.  More efficient that using an argument register for
 * each one.
 */
#define TXRX_WRITE		(1<<0)	/* This is a write */
#define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */

struct mxs_spi {
	struct mxs_ssp		ssp;
	struct completion	c;
	unsigned int		sck;	/* Rate requested (vs actual) */
};

static int mxs_spi_setup_transfer(struct spi_device *dev,
				  const struct spi_transfer *t)
{
	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	struct mxs_ssp *ssp = &spi->ssp;
	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);

	if (hz == 0) {
		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
		return -EINVAL;
	}

	if (hz != spi->sck) {
		mxs_ssp_set_clk_rate(ssp, hz);
		/*
		 * Save requested rate, hz, rather than the actual rate,
		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
		 * when the actual rate is not quite the same as requested rate.
		 */
		spi->sck = hz;
		/*
		 * Perhaps we should return an error if the actual clock is
		 * nowhere close to what was requested?
		 */
	}

	writel(BM_SSP_CTRL0_LOCK_CS,
		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
	       BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	       ssp->base + HW_SSP_CTRL1(ssp));

	writel(0x0, ssp->base + HW_SSP_CMD0);
	writel(0x0, ssp->base + HW_SSP_CMD1);

	return 0;
}

static u32 mxs_spi_cs_to_reg(unsigned cs)
{
	u32 select = 0;

	/*
	 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	 *
	 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
	 * the datasheet for further details. In SPI mode, they are used to
	 * toggle the chip-select lines (nCS pins).
	 */
	if (cs & 1)
		select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
	if (cs & 2)
		select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;

	return select;
}

static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
{
	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
	struct mxs_ssp *ssp = &spi->ssp;
	u32 reg;

	do {
		reg = readl_relaxed(ssp->base + offset);

		if (!set)
			reg = ~reg;

		reg &= mask;

		if (reg == mask)
			return 0;
	} while (time_before(jiffies, timeout));

	return -ETIMEDOUT;
}

static void mxs_ssp_dma_irq_callback(void *param)
{
	struct mxs_spi *spi = param;

	complete(&spi->c);
}

static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
{
	struct mxs_ssp *ssp = dev_id;

	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
		__func__, __LINE__,
		readl(ssp->base + HW_SSP_CTRL1(ssp)),
		readl(ssp->base + HW_SSP_STATUS(ssp)));
	return IRQ_HANDLED;
}

static int mxs_spi_txrx_dma(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;
	struct dma_async_tx_descriptor *desc = NULL;
	const bool vmalloced_buf = is_vmalloc_addr(buf);
	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	const int sgs = DIV_ROUND_UP(len, desc_len);
	int sg_count;
	int min, ret;
	u32 ctrl0;
	struct page *vm_page;
	struct {
		u32			pio[4];
		struct scatterlist	sg;
	} *dma_xfer;

	if (!len)
		return -EINVAL;

	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
	if (!dma_xfer)
		return -ENOMEM;

	reinit_completion(&spi->c);

	/* Chip select was already programmed into CTRL0 */
	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
		 BM_SSP_CTRL0_READ);
	ctrl0 |= BM_SSP_CTRL0_DATA_XFER;

	if (!(flags & TXRX_WRITE))
		ctrl0 |= BM_SSP_CTRL0_READ;

	/* Queue the DMA data transfer. */
	for (sg_count = 0; sg_count < sgs; sg_count++) {
		/* Prepare the transfer descriptor. */
		min = min(len, desc_len);

		/*
		 * De-assert CS on last segment if flag is set (i.e., no more
		 * transfers will follow)
		 */
		if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
			ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;

		if (ssp->devid == IMX23_SSP) {
			ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
			ctrl0 |= min;
		}

		dma_xfer[sg_count].pio[0] = ctrl0;
		dma_xfer[sg_count].pio[3] = min;

		if (vmalloced_buf) {
			vm_page = vmalloc_to_page(buf);
			if (!vm_page) {
				ret = -ENOMEM;
				goto err_vmalloc;
			}

			sg_init_table(&dma_xfer[sg_count].sg, 1);
			sg_set_page(&dma_xfer[sg_count].sg, vm_page,
				    min, offset_in_page(buf));
		} else {
			sg_init_one(&dma_xfer[sg_count].sg, buf, min);
		}

		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);

		len -= min;
		buf += min;

		/* Queue the PIO register write transfer. */
		desc = dmaengine_prep_slave_sg(ssp->dmach,
				(struct scatterlist *)dma_xfer[sg_count].pio,
				(ssp->devid == IMX23_SSP) ? 1 : 4,
				DMA_TRANS_NONE,
				sg_count ? DMA_PREP_INTERRUPT : 0);
		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get PIO reg. write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}

		desc = dmaengine_prep_slave_sg(ssp->dmach,
				&dma_xfer[sg_count].sg, 1,
				(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc) {
			dev_err(ssp->dev,
				"Failed to get DMA data write descriptor.\n");
			ret = -EINVAL;
			goto err_mapped;
		}
	}

	/*
	 * The last descriptor must have this callback,
	 * to finish the DMA transaction.
	 */
	desc->callback = mxs_ssp_dma_irq_callback;
	desc->callback_param = spi;

	/* Start the transfer. */
	dmaengine_submit(desc);
	dma_async_issue_pending(ssp->dmach);

	if (!wait_for_completion_timeout(&spi->c,
					 msecs_to_jiffies(SSP_TIMEOUT))) {
		dev_err(ssp->dev, "DMA transfer timeout\n");
		ret = -ETIMEDOUT;
		dmaengine_terminate_all(ssp->dmach);
		goto err_vmalloc;
	}

	ret = 0;

err_vmalloc:
	while (--sg_count >= 0) {
err_mapped:
		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
			(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
	}

	kfree(dma_xfer);

	return ret;
}

static int mxs_spi_txrx_pio(struct mxs_spi *spi,
			    unsigned char *buf, int len,
			    unsigned int flags)
{
	struct mxs_ssp *ssp = &spi->ssp;

	writel(BM_SSP_CTRL0_IGNORE_CRC,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);

	while (len--) {
		if (len == 0 && (flags & TXRX_DEASSERT_CS))
			writel(BM_SSP_CTRL0_IGNORE_CRC,
			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (ssp->devid == IMX23_SSP) {
			writel(BM_SSP_CTRL0_XFER_COUNT,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
			writel(1,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
		} else {
			writel(1, ssp->base + HW_SSP_XFER_SIZE);
		}

		if (flags & TXRX_WRITE)
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
		else
			writel(BM_SSP_CTRL0_READ,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		writel(BM_SSP_CTRL0_RUN,
				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
			return -ETIMEDOUT;

		if (flags & TXRX_WRITE)
			writel(*buf, ssp->base + HW_SSP_DATA(ssp));

		writel(BM_SSP_CTRL0_DATA_XFER,
			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

		if (!(flags & TXRX_WRITE)) {
			if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
						BM_SSP_STATUS_FIFO_EMPTY, 0))
				return -ETIMEDOUT;

			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
		}

		if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
			return -ETIMEDOUT;

		buf++;
	}

	if (len <= 0)
		return 0;

	return -ETIMEDOUT;
}

static int mxs_spi_transfer_one(struct spi_master *master,
				struct spi_message *m)
{
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	struct spi_transfer *t;
	unsigned int flag;
	int status = 0;

	/* Program CS register bits here, it will be used for all transfers. */
	writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);

	list_for_each_entry(t, &m->transfers, transfer_list) {

		status = mxs_spi_setup_transfer(m->spi, t);
		if (status)
			break;

		/* De-assert on last transfer, inverted by cs_change flag */
		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
		       TXRX_DEASSERT_CS : 0;

		/*
		 * Small blocks can be transfered via PIO.
		 * Measured by empiric means:
		 *
		 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
		 *
		 * DMA only: 2.164808 seconds, 473.0KB/s
		 * Combined: 1.676276 seconds, 610.9KB/s
		 */
		if (t->len < 32) {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_CLR);

			if (t->tx_buf)
				status = mxs_spi_txrx_pio(spi,
						(void *)t->tx_buf,
						t->len, flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_pio(spi,
						t->rx_buf, t->len,
						flag);
		} else {
			writel(BM_SSP_CTRL1_DMA_ENABLE,
				ssp->base + HW_SSP_CTRL1(ssp) +
				STMP_OFFSET_REG_SET);

			if (t->tx_buf)
				status = mxs_spi_txrx_dma(spi,
						(void *)t->tx_buf, t->len,
						flag | TXRX_WRITE);
			if (t->rx_buf)
				status = mxs_spi_txrx_dma(spi,
						t->rx_buf, t->len,
						flag);
		}

		if (status) {
			stmp_reset_block(ssp->base);
			break;
		}

		m->actual_length += t->len;
	}

	m->status = status;
	spi_finalize_current_message(master);

	return status;
}

static int mxs_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	clk_disable_unprepare(ssp->clk);

	ret = pinctrl_pm_select_idle_state(dev);
	if (ret) {
		int ret2 = clk_prepare_enable(ssp->clk);

		if (ret2)
			dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
				 ret, ret2);
	}

	return ret;
}

static int mxs_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct mxs_spi *spi = spi_master_get_devdata(master);
	struct mxs_ssp *ssp = &spi->ssp;
	int ret;

	ret = pinctrl_pm_select_default_state(dev);
	if (ret)
		return ret;

	ret = clk_prepare_enable(ssp->clk);
	if (ret)
		pinctrl_pm_select_idle_state(dev);

	return ret;
}

static int __maybe_unused mxs_spi_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	ret = spi_master_suspend(master);
	if (ret)
		return ret;

	if (!pm_runtime_suspended(dev))
		return mxs_spi_runtime_suspend(dev);
	else
		return 0;
}

static int __maybe_unused mxs_spi_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	int ret;

	if (!pm_runtime_suspended(dev))
		ret = mxs_spi_runtime_resume(dev);
	else
		ret = 0;
	if (ret)
		return ret;

	ret = spi_master_resume(master);
	if (ret < 0 && !pm_runtime_suspended(dev))
		mxs_spi_runtime_suspend(dev);

	return ret;
}

static const struct dev_pm_ops mxs_spi_pm = {
	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
			   mxs_spi_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
};

static const struct of_device_id mxs_spi_dt_ids[] = {
	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);

static int mxs_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_spi_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;
	struct resource *iores;
	struct clk *clk;
	void __iomem *base;
	int devid, clk_freq;
	int ret = 0, irq_err;

	/*
	 * Default clock speed for the SPI core. 160MHz seems to
	 * work reasonably well with most SPI flashes, so use this
	 * as a default. Override with "clock-frequency" DT prop.
	 */
	const int clk_freq_default = 160000000;

	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq_err = platform_get_irq(pdev, 0);
	if (irq_err < 0)
		return irq_err;

	base = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	devid = (enum mxs_ssp_id) of_id->data;
	ret = of_property_read_u32(np, "clock-frequency",
				   &clk_freq);
	if (ret)
		clk_freq = clk_freq_default;

	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	if (!master)
		return -ENOMEM;

	platform_set_drvdata(pdev, master);

	master->transfer_one_message = mxs_spi_transfer_one;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->mode_bits = SPI_CPOL | SPI_CPHA;
	master->num_chipselect = 3;
	master->dev.of_node = np;
	master->flags = SPI_MASTER_HALF_DUPLEX;
	master->auto_runtime_pm = true;

	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;
	ssp->dev = &pdev->dev;
	ssp->clk = clk;
	ssp->base = base;
	ssp->devid = devid;

	init_completion(&spi->c);

	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
			       dev_name(&pdev->dev), ssp);
	if (ret)
		goto out_master_free;

	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
	if (!ssp->dmach) {
		dev_err(ssp->dev, "Failed to request DMA\n");
		ret = -ENODEV;
		goto out_master_free;
	}

	pm_runtime_enable(ssp->dev);
	if (!pm_runtime_enabled(ssp->dev)) {
		ret = mxs_spi_runtime_resume(ssp->dev);
		if (ret < 0) {
			dev_err(ssp->dev, "runtime resume failed\n");
			goto out_dma_release;
		}
	}

	ret = pm_runtime_get_sync(ssp->dev);
	if (ret < 0) {
		dev_err(ssp->dev, "runtime_get_sync failed\n");
		goto out_pm_runtime_disable;
	}

	clk_set_rate(ssp->clk, clk_freq);

	ret = stmp_reset_block(ssp->base);
	if (ret)
		goto out_pm_runtime_put;

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
		goto out_pm_runtime_put;
	}

	pm_runtime_put(ssp->dev);

	return 0;

out_pm_runtime_put:
	pm_runtime_put(ssp->dev);
out_pm_runtime_disable:
	pm_runtime_disable(ssp->dev);
out_dma_release:
	dma_release_channel(ssp->dmach);
out_master_free:
	spi_master_put(master);
	return ret;
}

static int mxs_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mxs_spi *spi;
	struct mxs_ssp *ssp;

	master = platform_get_drvdata(pdev);
	spi = spi_master_get_devdata(master);
	ssp = &spi->ssp;

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		mxs_spi_runtime_suspend(&pdev->dev);

	dma_release_channel(ssp->dmach);

	return 0;
}

static struct platform_driver mxs_spi_driver = {
	.probe	= mxs_spi_probe,
	.remove	= mxs_spi_remove,
	.driver	= {
		.name	= DRIVER_NAME,
		.of_match_table = mxs_spi_dt_ids,
		.pm = &mxs_spi_pm,
	},
};

module_platform_driver(mxs_spi_driver);

MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("MXS SPI master driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:mxs-spi");
Commit	Line	Data
646781d3 MV	1	/*
	2	* Freescale MXS SPI master driver
	3	*
	4	* Copyright 2012 DENX Software Engineering, GmbH.
	5	* Copyright 2012 Freescale Semiconductor, Inc.
	6	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
	7	*
	8	* Rework and transition to new API by:
	9	* Marek Vasut <[email protected]>
	10	*
	11	* Based on previous attempt by:
	12	* Fabio Estevam <[email protected]>
	13	*
	14	* Based on code from U-Boot bootloader by:
	15	* Marek Vasut <[email protected]>
	16	*
	17	* Based on spi-stmp.c, which is:
	18	* Author: Dmitry Pervushin <[email protected]>
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2 of the License, or
	23	* (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*/
	30
	31	#include <linux/kernel.h>
646781d3 MV	32	#include <linux/ioport.h>
	33	#include <linux/of.h>
	34	#include <linux/of_device.h>
	35	#include <linux/of_gpio.h>
	36	#include <linux/platform_device.h>
	37	#include <linux/delay.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/dma-mapping.h>
	40	#include <linux/dmaengine.h>
	41	#include <linux/highmem.h>
	42	#include <linux/clk.h>
	43	#include <linux/err.h>
	44	#include <linux/completion.h>
	45	#include <linux/gpio.h>
	46	#include <linux/regulator/consumer.h>
b7969caf	47	#include <linux/pm_runtime.h>
646781d3	48	#include <linux/module.h>
646781d3 MV	49	#include <linux/stmp_device.h>
	50	#include <linux/spi/spi.h>
	51	#include <linux/spi/mxs-spi.h>
	52
	53	#define DRIVER_NAME "mxs-spi"
	54
010b4818 MV	55	/* Use 10S timeout for very long transfers, it should suffice. */
010b4818 MV	56	#define SSP_TIMEOUT 10000
646781d3	57
474afc04 MV	58	#define SG_MAXLEN 0xff00
474afc04 MV	59
28cad125 TP	60	/*
	61	* Flags for txrx functions. More efficient that using an argument register for
	62	* each one.
	63	*/
	64	#define TXRX_WRITE (1<<0) /* This is a write */
	65	#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
	66
646781d3 MV	67	struct mxs_spi {
646781d3 MV	68	struct mxs_ssp ssp;
474afc04	69	struct completion c;
a560943e	70	unsigned int sck; /* Rate requested (vs actual) */
646781d3 MV	71	};
	72
	73	static int mxs_spi_setup_transfer(struct spi_device *dev,
aa9e0c6f	74	const struct spi_transfer *t)
646781d3 MV	75	{
	76	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
	77	struct mxs_ssp *ssp = &spi->ssp;
aa9e0c6f	78	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
646781d3	79
646781d3	80	if (hz == 0) {
aa9e0c6f	81	dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
646781d3 MV	82	return -EINVAL;
	83	}
	84
a560943e TP	85	if (hz != spi->sck) {
	86	mxs_ssp_set_clk_rate(ssp, hz);
	87	/*
	88	* Save requested rate, hz, rather than the actual rate,
a44619c3	89	* ssp->clk_rate. Otherwise we would set the rate every transfer
a560943e TP	90	* when the actual rate is not quite the same as requested rate.
	91	*/
	92	spi->sck = hz;
	93	/*
	94	* Perhaps we should return an error if the actual clock is
	95	* nowhere close to what was requested?
	96	*/
	97	}
646781d3	98
58f46e41 TP	99	writel(BM_SSP_CTRL0_LOCK_CS,
58f46e41 TP	100	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	101
646781d3 MV	102	writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) \|
aa9e0c6f TP	103	BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) \|
	104	((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) \|
	105	((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
	106	ssp->base + HW_SSP_CTRL1(ssp));
646781d3 MV	107
	108	writel(0x0, ssp->base + HW_SSP_CMD0);
	109	writel(0x0, ssp->base + HW_SSP_CMD1);
	110
	111	return 0;
	112	}
	113
42e182f8	114	static u32 mxs_spi_cs_to_reg(unsigned cs)
646781d3	115	{
42e182f8	116	u32 select = 0;
646781d3 MV	117
	118	/*
	119	* i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
	120	*
	121	* The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
	122	* in HW_SSP_CTRL0 register do have multiple usage, please refer to
	123	* the datasheet for further details. In SPI mode, they are used to
	124	* toggle the chip-select lines (nCS pins).
	125	*/
	126	if (cs & 1)
	127	select \|= BM_SSP_CTRL0_WAIT_FOR_CMD;
	128	if (cs & 2)
	129	select \|= BM_SSP_CTRL0_WAIT_FOR_IRQ;
	130
	131	return select;
	132	}
	133
646781d3 MV	134	static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
646781d3 MV	135	{
f13639dc	136	const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
646781d3	137	struct mxs_ssp *ssp = &spi->ssp;
42e182f8	138	u32 reg;
646781d3	139
f13639dc	140	do {
646781d3 MV	141	reg = readl_relaxed(ssp->base + offset);
646781d3 MV	142
f13639dc MV	143	if (!set)
f13639dc MV	144	reg = ~reg;
646781d3	145
f13639dc	146	reg &= mask;
646781d3	147
f13639dc MV	148	if (reg == mask)
	149	return 0;
	150	} while (time_before(jiffies, timeout));
646781d3	151
f13639dc	152	return -ETIMEDOUT;
646781d3 MV	153	}
646781d3 MV	154
474afc04 MV	155	static void mxs_ssp_dma_irq_callback(void *param)
	156	{
	157	struct mxs_spi *spi = param;
a7fa3219	158
474afc04 MV	159	complete(&spi->c);
	160	}
	161
	162	static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
	163	{
	164	struct mxs_ssp *ssp = dev_id;
a7fa3219	165
474afc04 MV	166	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
	167	__func__, __LINE__,
	168	readl(ssp->base + HW_SSP_CTRL1(ssp)),
	169	readl(ssp->base + HW_SSP_STATUS(ssp)));
	170	return IRQ_HANDLED;
	171	}
	172
0b782f70	173	static int mxs_spi_txrx_dma(struct mxs_spi *spi,
474afc04	174	unsigned char *buf, int len,
28cad125	175	unsigned int flags)
474afc04 MV	176	{
474afc04 MV	177	struct mxs_ssp *ssp = &spi->ssp;
010b4818 MV	178	struct dma_async_tx_descriptor *desc = NULL;
	179	const bool vmalloced_buf = is_vmalloc_addr(buf);
	180	const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
	181	const int sgs = DIV_ROUND_UP(len, desc_len);
474afc04	182	int sg_count;
010b4818	183	int min, ret;
42e182f8	184	u32 ctrl0;
010b4818	185	struct page *vm_page;
010b4818	186	struct {
42e182f8	187	u32 pio[4];
010b4818 MV	188	struct scatterlist sg;
	189	} *dma_xfer;
	190
	191	if (!len)
474afc04	192	return -EINVAL;
010b4818	193
a7fa3219	194	dma_xfer = kcalloc(sgs, sizeof(*dma_xfer), GFP_KERNEL);
010b4818 MV	195	if (!dma_xfer)
010b4818 MV	196	return -ENOMEM;
474afc04	197
16735d02	198	reinit_completion(&spi->c);
474afc04	199
0b782f70	200	/* Chip select was already programmed into CTRL0 */
010b4818	201	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
df23286e TP	202	ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT \| BM_SSP_CTRL0_IGNORE_CRC \|
df23286e TP	203	BM_SSP_CTRL0_READ);
0b782f70	204	ctrl0 \|= BM_SSP_CTRL0_DATA_XFER;
010b4818	205
28cad125	206	if (!(flags & TXRX_WRITE))
010b4818	207	ctrl0 \|= BM_SSP_CTRL0_READ;
474afc04 MV	208
474afc04 MV	209	/* Queue the DMA data transfer. */
010b4818	210	for (sg_count = 0; sg_count < sgs; sg_count++) {
28cad125	211	/* Prepare the transfer descriptor. */
010b4818 MV	212	min = min(len, desc_len);
010b4818 MV	213
28cad125 TP	214	/*
	215	* De-assert CS on last segment if flag is set (i.e., no more
	216	* transfers will follow)
	217	*/
	218	if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
010b4818 MV	219	ctrl0 \|= BM_SSP_CTRL0_IGNORE_CRC;
010b4818 MV	220
ba486a2a JL	221	if (ssp->devid == IMX23_SSP) {
ba486a2a JL	222	ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
010b4818	223	ctrl0 \|= min;
ba486a2a	224	}
010b4818 MV	225
	226	dma_xfer[sg_count].pio[0] = ctrl0;
	227	dma_xfer[sg_count].pio[3] = min;
	228
	229	if (vmalloced_buf) {
	230	vm_page = vmalloc_to_page(buf);
	231	if (!vm_page) {
	232	ret = -ENOMEM;
	233	goto err_vmalloc;
	234	}
9e8987ac CK	235
	236	sg_init_table(&dma_xfer[sg_count].sg, 1);
	237	sg_set_page(&dma_xfer[sg_count].sg, vm_page,
	238	min, offset_in_page(buf));
010b4818	239	} else {
9e8987ac	240	sg_init_one(&dma_xfer[sg_count].sg, buf, min);
010b4818 MV	241	}
010b4818 MV	242
010b4818	243	ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	244	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
010b4818 MV	245
	246	len -= min;
	247	buf += min;
	248
	249	/* Queue the PIO register write transfer. */
	250	desc = dmaengine_prep_slave_sg(ssp->dmach,
	251	(struct scatterlist *)dma_xfer[sg_count].pio,
	252	(ssp->devid == IMX23_SSP) ? 1 : 4,
	253	DMA_TRANS_NONE,
	254	sg_count ? DMA_PREP_INTERRUPT : 0);
	255	if (!desc) {
	256	dev_err(ssp->dev,
	257	"Failed to get PIO reg. write descriptor.\n");
	258	ret = -EINVAL;
	259	goto err_mapped;
	260	}
	261
	262	desc = dmaengine_prep_slave_sg(ssp->dmach,
	263	&dma_xfer[sg_count].sg, 1,
28cad125	264	(flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
010b4818 MV	265	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	266
	267	if (!desc) {
	268	dev_err(ssp->dev,
	269	"Failed to get DMA data write descriptor.\n");
	270	ret = -EINVAL;
	271	goto err_mapped;
	272	}
474afc04 MV	273	}
	274
	275	/*
	276	* The last descriptor must have this callback,
	277	* to finish the DMA transaction.
	278	*/
	279	desc->callback = mxs_ssp_dma_irq_callback;
	280	desc->callback_param = spi;
	281
	282	/* Start the transfer. */
	283	dmaengine_submit(desc);
	284	dma_async_issue_pending(ssp->dmach);
	285
f2234691 NMG	286	if (!wait_for_completion_timeout(&spi->c,
f2234691 NMG	287	msecs_to_jiffies(SSP_TIMEOUT))) {
474afc04 MV	288	dev_err(ssp->dev, "DMA transfer timeout\n");
474afc04 MV	289	ret = -ETIMEDOUT;
44968466	290	dmaengine_terminate_all(ssp->dmach);
010b4818	291	goto err_vmalloc;
474afc04 MV	292	}
	293
	294	ret = 0;
	295
010b4818 MV	296	err_vmalloc:
	297	while (--sg_count >= 0) {
	298	err_mapped:
	299	dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
28cad125	300	(flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
474afc04 MV	301	}
474afc04 MV	302
010b4818 MV	303	kfree(dma_xfer);
010b4818 MV	304
474afc04 MV	305	return ret;
	306	}
	307
0b782f70	308	static int mxs_spi_txrx_pio(struct mxs_spi *spi,
646781d3	309	unsigned char *buf, int len,
28cad125	310	unsigned int flags)
646781d3 MV	311	{
	312	struct mxs_ssp *ssp = &spi->ssp;
	313
75e73fa2 TP	314	writel(BM_SSP_CTRL0_IGNORE_CRC,
75e73fa2 TP	315	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
646781d3 MV	316
646781d3 MV	317	while (len--) {
28cad125	318	if (len == 0 && (flags & TXRX_DEASSERT_CS))
f5bc7384 TP	319	writel(BM_SSP_CTRL0_IGNORE_CRC,
f5bc7384 TP	320	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3 MV	321
	322	if (ssp->devid == IMX23_SSP) {
	323	writel(BM_SSP_CTRL0_XFER_COUNT,
	324	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	325	writel(1,
	326	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	327	} else {
	328	writel(1, ssp->base + HW_SSP_XFER_SIZE);
	329	}
	330
28cad125	331	if (flags & TXRX_WRITE)
646781d3 MV	332	writel(BM_SSP_CTRL0_READ,
	333	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	334	else
	335	writel(BM_SSP_CTRL0_READ,
	336	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	337
	338	writel(BM_SSP_CTRL0_RUN,
	339	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	340
	341	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
	342	return -ETIMEDOUT;
	343
28cad125	344	if (flags & TXRX_WRITE)
646781d3 MV	345	writel(*buf, ssp->base + HW_SSP_DATA(ssp));
	346
	347	writel(BM_SSP_CTRL0_DATA_XFER,
	348	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
	349
28cad125	350	if (!(flags & TXRX_WRITE)) {
646781d3 MV	351	if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
	352	BM_SSP_STATUS_FIFO_EMPTY, 0))
	353	return -ETIMEDOUT;
	354
	355	*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
	356	}
	357
	358	if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
	359	return -ETIMEDOUT;
	360
	361	buf++;
	362	}
	363
	364	if (len <= 0)
	365	return 0;
	366
	367	return -ETIMEDOUT;
	368	}
	369
	370	static int mxs_spi_transfer_one(struct spi_master *master,
	371	struct spi_message *m)
	372	{
	373	struct mxs_spi *spi = spi_master_get_devdata(master);
	374	struct mxs_ssp *ssp = &spi->ssp;
9a7da6cc	375	struct spi_transfer *t;
28cad125	376	unsigned int flag;
646781d3	377	int status = 0;
646781d3	378
0b782f70 TP	379	/* Program CS register bits here, it will be used for all transfers. */
	380	writel(BM_SSP_CTRL0_WAIT_FOR_CMD \| BM_SSP_CTRL0_WAIT_FOR_IRQ,
	381	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
	382	writel(mxs_spi_cs_to_reg(m->spi->chip_select),
	383	ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
646781d3	384
9a7da6cc	385	list_for_each_entry(t, &m->transfers, transfer_list) {
646781d3 MV	386
	387	status = mxs_spi_setup_transfer(m->spi, t);
	388	if (status)
	389	break;
	390
28cad125 TP	391	/* De-assert on last transfer, inverted by cs_change flag */
	392	flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
	393	TXRX_DEASSERT_CS : 0;
646781d3	394
474afc04 MV	395	/*
	396	* Small blocks can be transfered via PIO.
	397	* Measured by empiric means:
	398	*
	399	* dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
	400	*
	401	* DMA only: 2.164808 seconds, 473.0KB/s
	402	* Combined: 1.676276 seconds, 610.9KB/s
	403	*/
727c10e3	404	if (t->len < 32) {
474afc04 MV	405	writel(BM_SSP_CTRL1_DMA_ENABLE,
	406	ssp->base + HW_SSP_CTRL1(ssp) +
	407	STMP_OFFSET_REG_CLR);
	408
	409	if (t->tx_buf)
0b782f70	410	status = mxs_spi_txrx_pio(spi,
474afc04	411	(void *)t->tx_buf,
28cad125	412	t->len, flag \| TXRX_WRITE);
474afc04	413	if (t->rx_buf)
0b782f70	414	status = mxs_spi_txrx_pio(spi,
474afc04	415	t->rx_buf, t->len,
28cad125	416	flag);
474afc04 MV	417	} else {
	418	writel(BM_SSP_CTRL1_DMA_ENABLE,
	419	ssp->base + HW_SSP_CTRL1(ssp) +
	420	STMP_OFFSET_REG_SET);
	421
	422	if (t->tx_buf)
0b782f70	423	status = mxs_spi_txrx_dma(spi,
474afc04	424	(void *)t->tx_buf, t->len,
28cad125	425	flag \| TXRX_WRITE);
474afc04	426	if (t->rx_buf)
0b782f70	427	status = mxs_spi_txrx_dma(spi,
474afc04	428	t->rx_buf, t->len,
28cad125	429	flag);
474afc04	430	}
646781d3	431
c895db0f MV	432	if (status) {
c895db0f MV	433	stmp_reset_block(ssp->base);
646781d3	434	break;
c895db0f	435	}
646781d3	436
204e706f	437	m->actual_length += t->len;
646781d3 MV	438	}
646781d3 MV	439
d856f1eb	440	m->status = status;
646781d3 MV	441	spi_finalize_current_message(master);
	442
	443	return status;
	444	}
	445
b7969caf UKK	446	static int mxs_spi_runtime_suspend(struct device *dev)
	447	{
	448	struct spi_master *master = dev_get_drvdata(dev);
	449	struct mxs_spi *spi = spi_master_get_devdata(master);
	450	struct mxs_ssp *ssp = &spi->ssp;
	451	int ret;
	452
	453	clk_disable_unprepare(ssp->clk);
	454
	455	ret = pinctrl_pm_select_idle_state(dev);
	456	if (ret) {
	457	int ret2 = clk_prepare_enable(ssp->clk);
	458
	459	if (ret2)
	460	dev_warn(dev, "Failed to reenable clock after failing pinctrl request (pinctrl: %d, clk: %d)\n",
	461	ret, ret2);
	462	}
	463
	464	return ret;
	465	}
	466
	467	static int mxs_spi_runtime_resume(struct device *dev)
	468	{
	469	struct spi_master *master = dev_get_drvdata(dev);
	470	struct mxs_spi *spi = spi_master_get_devdata(master);
	471	struct mxs_ssp *ssp = &spi->ssp;
	472	int ret;
	473
	474	ret = pinctrl_pm_select_default_state(dev);
	475	if (ret)
	476	return ret;
	477
	478	ret = clk_prepare_enable(ssp->clk);
	479	if (ret)
	480	pinctrl_pm_select_idle_state(dev);
	481
	482	return ret;
	483	}
	484
	485	static int __maybe_unused mxs_spi_suspend(struct device *dev)
	486	{
	487	struct spi_master *master = dev_get_drvdata(dev);
	488	int ret;
	489
	490	ret = spi_master_suspend(master);
	491	if (ret)
	492	return ret;
	493
	494	if (!pm_runtime_suspended(dev))
	495	return mxs_spi_runtime_suspend(dev);
	496	else
	497	return 0;
	498	}
	499
	500	static int __maybe_unused mxs_spi_resume(struct device *dev)
	501	{
	502	struct spi_master *master = dev_get_drvdata(dev);
	503	int ret;
	504
	505	if (!pm_runtime_suspended(dev))
	506	ret = mxs_spi_runtime_resume(dev);
	507	else
	508	ret = 0;
	509	if (ret)
510	return ret;
511
512	ret = spi_master_resume(master);
513	if (ret < 0 && !pm_runtime_suspended(dev))
514	mxs_spi_runtime_suspend(dev);
515
516	return ret;
517	}
518
519	static const struct dev_pm_ops mxs_spi_pm = {
520	SET_RUNTIME_PM_OPS(mxs_spi_runtime_suspend,
521	mxs_spi_runtime_resume, NULL)
522	SET_SYSTEM_SLEEP_PM_OPS(mxs_spi_suspend, mxs_spi_resume)
523	};
524
646781d3 MV	525	static const struct of_device_id mxs_spi_dt_ids[] = {
	526	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
	527	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
	528	{ /* sentinel */ }
	529	};
	530	MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
	531
fd4a319b	532	static int mxs_spi_probe(struct platform_device *pdev)
646781d3 MV	533	{
	534	const struct of_device_id *of_id =
	535	of_match_device(mxs_spi_dt_ids, &pdev->dev);
	536	struct device_node *np = pdev->dev.of_node;
	537	struct spi_master *master;
	538	struct mxs_spi *spi;
	539	struct mxs_ssp *ssp;
26aafa77	540	struct resource *iores;
646781d3 MV	541	struct clk *clk;
646781d3 MV	542	void __iomem *base;
26aafa77 SG	543	int devid, clk_freq;
26aafa77 SG	544	int ret = 0, irq_err;
646781d3	545
e64d07a2 MV	546	/*
	547	* Default clock speed for the SPI core. 160MHz seems to
	548	* work reasonably well with most SPI flashes, so use this
	549	* as a default. Override with "clock-frequency" DT prop.
	550	*/
	551	const int clk_freq_default = 160000000;
	552
646781d3	553	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
474afc04	554	irq_err = platform_get_irq(pdev, 0);
796305a2	555	if (irq_err < 0)
cdd1945b	556	return irq_err;
646781d3	557
b0ee5605 TR	558	base = devm_ioremap_resource(&pdev->dev, iores);
	559	if (IS_ERR(base))
	560	return PTR_ERR(base);
646781d3	561
646781d3 MV	562	clk = devm_clk_get(&pdev->dev, NULL);
	563	if (IS_ERR(clk))
	564	return PTR_ERR(clk);
	565
26aafa77 SG	566	devid = (enum mxs_ssp_id) of_id->data;
	567	ret = of_property_read_u32(np, "clock-frequency",
	568	&clk_freq);
	569	if (ret)
e64d07a2	570	clk_freq = clk_freq_default;
646781d3 MV	571
	572	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
	573	if (!master)
	574	return -ENOMEM;
	575
b7969caf UKK	576	platform_set_drvdata(pdev, master);
b7969caf UKK	577
646781d3	578	master->transfer_one_message = mxs_spi_transfer_one;
24778be2	579	master->bits_per_word_mask = SPI_BPW_MASK(8);
646781d3 MV	580	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	581	master->num_chipselect = 3;
	582	master->dev.of_node = np;
	583	master->flags = SPI_MASTER_HALF_DUPLEX;
b7969caf	584	master->auto_runtime_pm = true;
646781d3 MV	585
	586	spi = spi_master_get_devdata(master);
	587	ssp = &spi->ssp;
	588	ssp->dev = &pdev->dev;
	589	ssp->clk = clk;
	590	ssp->base = base;
	591	ssp->devid = devid;
474afc04	592
41682e03 MV	593	init_completion(&spi->c);
41682e03 MV	594
474afc04	595	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
617100c2	596	dev_name(&pdev->dev), ssp);
474afc04 MV	597	if (ret)
	598	goto out_master_free;
	599
26aafa77	600	ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
474afc04 MV	601	if (!ssp->dmach) {
474afc04 MV	602	dev_err(ssp->dev, "Failed to request DMA\n");
58ad60bb	603	ret = -ENODEV;
474afc04 MV	604	goto out_master_free;
474afc04 MV	605	}
646781d3	606
b7969caf UKK	607	pm_runtime_enable(ssp->dev);
	608	if (!pm_runtime_enabled(ssp->dev)) {
	609	ret = mxs_spi_runtime_resume(ssp->dev);
	610	if (ret < 0) {
	611	dev_err(ssp->dev, "runtime resume failed\n");
	612	goto out_dma_release;
	613	}
	614	}
	615
	616	ret = pm_runtime_get_sync(ssp->dev);
	617	if (ret < 0) {
	618	dev_err(ssp->dev, "runtime_get_sync failed\n");
	619	goto out_pm_runtime_disable;
	620	}
9c4a39af	621
e64d07a2	622	clk_set_rate(ssp->clk, clk_freq);
646781d3	623
8498bce9 FE	624	ret = stmp_reset_block(ssp->base);
8498bce9 FE	625	if (ret)
b7969caf	626	goto out_pm_runtime_put;
646781d3	627
33e195ac	628	ret = devm_spi_register_master(&pdev->dev, master);
646781d3 MV	629	if (ret) {
646781d3 MV	630	dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
b7969caf	631	goto out_pm_runtime_put;
646781d3 MV	632	}
646781d3 MV	633
b7969caf UKK	634	pm_runtime_put(ssp->dev);
b7969caf UKK	635
646781d3 MV	636	return 0;
646781d3 MV	637
b7969caf UKK	638	out_pm_runtime_put:
	639	pm_runtime_put(ssp->dev);
	640	out_pm_runtime_disable:
	641	pm_runtime_disable(ssp->dev);
9c4a39af	642	out_dma_release:
e11933f6	643	dma_release_channel(ssp->dmach);
474afc04	644	out_master_free:
646781d3 MV	645	spi_master_put(master);
	646	return ret;
	647	}
	648
fd4a319b	649	static int mxs_spi_remove(struct platform_device *pdev)
646781d3 MV	650	{
	651	struct spi_master *master;
	652	struct mxs_spi *spi;
	653	struct mxs_ssp *ssp;
	654
e322ce93	655	master = platform_get_drvdata(pdev);
646781d3 MV	656	spi = spi_master_get_devdata(master);
	657	ssp = &spi->ssp;
	658
b7969caf UKK	659	pm_runtime_disable(&pdev->dev);
	660	if (!pm_runtime_status_suspended(&pdev->dev))
	661	mxs_spi_runtime_suspend(&pdev->dev);
	662
e11933f6	663	dma_release_channel(ssp->dmach);
646781d3 MV	664
	665	return 0;
	666	}
	667
	668	static struct platform_driver mxs_spi_driver = {
	669	.probe = mxs_spi_probe,
fd4a319b	670	.remove = mxs_spi_remove,
646781d3 MV	671	.driver = {
646781d3 MV	672	.name = DRIVER_NAME,
646781d3	673	.of_match_table = mxs_spi_dt_ids,
b7969caf	674	.pm = &mxs_spi_pm,
646781d3 MV	675	},
	676	};
	677
	678	module_platform_driver(mxs_spi_driver);
	679
	680	MODULE_AUTHOR("Marek Vasut <[email protected]>");
	681	MODULE_DESCRIPTION("MXS SPI master driver");
	682	MODULE_LICENSE("GPL");
	683	MODULE_ALIAS("platform:mxs-spi");