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usb: dwc3: ep0: pass dep as argument to internal functions
[linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <[email protected]>,
7 * Sebastian Andrzej Siewior <[email protected]>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
8598bde7
FB		 142 return -ETIMEDOUT;
143}
144
dca0119c
JY		 145/**
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
148 *
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
152 */
153static void dwc3_ep_inc_trb(u8 *index)
457e84b6 154{
dca0119c
JY		 155 (*index)++;
156 if (*index == (DWC3_TRB_NUM - 1))
157 *index = 0;
ef966b9d 158}
457e84b6 159
dca0119c 160static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
ef966b9d 161{
dca0119c 162 dwc3_ep_inc_trb(&dep->trb_enqueue);
ef966b9d 163}
457e84b6 164
dca0119c 165static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
ef966b9d 166{
dca0119c 167 dwc3_ep_inc_trb(&dep->trb_dequeue);
457e84b6
FB		 168}
169
72246da4
FB		 170void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
171 int status)
172{
173 struct dwc3 *dwc = dep->dwc;
de288e36 174 unsigned int unmap_after_complete = false;
72246da4 175
737f1ae2 176 req->started = false;
72246da4 177 list_del(&req->list);
eeb720fb 178 req->trb = NULL;
e62c5bc5 179 req->remaining = 0;
72246da4
FB		 180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
de288e36
JD		 184 /*
185 * NOTICE we don't want to unmap before calling ->complete() if we're
186 * dealing with a bounced ep0 request. If we unmap it here, we would end
187 * up overwritting the contents of req->buf and this could confuse the
188 * gadget driver.
189 */
190 if (dwc->ep0_bounced && dep->number <= 1) {
0416e494 191 dwc->ep0_bounced = false;
de288e36
JD		 192 unmap_after_complete = true;
193 } else {
194 usb_gadget_unmap_request_by_dev(dwc->sysdev,
195 &req->request, req->direction);
196 }
72246da4 197
2c4cbe6e 198 trace_dwc3_gadget_giveback(req);
72246da4
FB		 199
200 spin_unlock(&dwc->lock);
304f7e5e 201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4 202 spin_lock(&dwc->lock);
fc8bb91b 203
de288e36
JD		 204 if (unmap_after_complete)
205 usb_gadget_unmap_request_by_dev(dwc->sysdev,
206 &req->request, req->direction);
207
fc8bb91b
FB		 208 if (dep->number > 1)
209 pm_runtime_put(dwc->dev);
72246da4
FB		 210}
211
3ece0ec4 212int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 213{
214 u32 timeout = 500;
71f7e702 215 int status = 0;
0fe886cd 216 int ret = 0;
b09bb642
FB		 217 u32 reg;
218
219 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
220 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
221
222 do {
223 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
224 if (!(reg & DWC3_DGCMD_CMDACT)) {
71f7e702
FB		 225 status = DWC3_DGCMD_STATUS(reg);
226 if (status)
0fe886cd
FB		 227 ret = -EINVAL;
228 break;
b09bb642 229 }
e3aee486 230 } while (--timeout);
0fe886cd
FB		 231
232 if (!timeout) {
0fe886cd 233 ret = -ETIMEDOUT;
71f7e702 234 status = -ETIMEDOUT;
0fe886cd
FB		 235 }
236
71f7e702
FB		 237 trace_dwc3_gadget_generic_cmd(cmd, param, status);
238
0fe886cd 239 return ret;
b09bb642
FB		 240}
241
c36d8e94
FB		 242static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
243
2cd4718d
FB		 244int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
245 struct dwc3_gadget_ep_cmd_params *params)
72246da4 246{
8897a761 247 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
2cd4718d 248 struct dwc3 *dwc = dep->dwc;
61d58242 249 u32 timeout = 500;
72246da4
FB		 250 u32 reg;
251
0933df15 252 int cmd_status = 0;
2b0f11df 253 int susphy = false;
c0ca324d 254 int ret = -EINVAL;
72246da4 255
2b0f11df
FB		 256 /*
257 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
258 * we're issuing an endpoint command, we must check if
259 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
260 *
261 * We will also set SUSPHY bit to what it was before returning as stated
262 * by the same section on Synopsys databook.
263 */
ab2a92e7
FB		 264 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
265 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
266 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
267 susphy = true;
268 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
269 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
270 }
2b0f11df
FB		 271 }
272
5999914f 273 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
c36d8e94
FB		 274 int needs_wakeup;
275
276 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
277 dwc->link_state == DWC3_LINK_STATE_U2 ||
278 dwc->link_state == DWC3_LINK_STATE_U3);
279
280 if (unlikely(needs_wakeup)) {
281 ret = __dwc3_gadget_wakeup(dwc);
282 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
283 ret);
284 }
285 }
286
2eb88016
FB		 287 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
288 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
289 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
72246da4 290
8897a761
FB		 291 /*
292 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
293 * not relying on XferNotReady, we can make use of a special "No
294 * Response Update Transfer" command where we should clear both CmdAct
295 * and CmdIOC bits.
296 *
297 * With this, we don't need to wait for command completion and can
298 * straight away issue further commands to the endpoint.
299 *
300 * NOTICE: We're making an assumption that control endpoints will never
301 * make use of Update Transfer command. This is a safe assumption
302 * because we can never have more than one request at a time with
303 * Control Endpoints. If anybody changes that assumption, this chunk
304 * needs to be updated accordingly.
305 */
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
307 !usb_endpoint_xfer_isoc(desc))
308 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
309 else
310 cmd |= DWC3_DEPCMD_CMDACT;
311
312 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
72246da4 313 do {
2eb88016 314 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
72246da4 315 if (!(reg & DWC3_DEPCMD_CMDACT)) {
0933df15 316 cmd_status = DWC3_DEPCMD_STATUS(reg);
7b9cc7a2 317
7b9cc7a2
KL		 318 switch (cmd_status) {
319 case 0:
320 ret = 0;
321 break;
322 case DEPEVT_TRANSFER_NO_RESOURCE:
7b9cc7a2 323 ret = -EINVAL;
c0ca324d 324 break;
7b9cc7a2
KL		 325 case DEPEVT_TRANSFER_BUS_EXPIRY:
326 /*
327 * SW issues START TRANSFER command to
328 * isochronous ep with future frame interval. If
329 * future interval time has already passed when
330 * core receives the command, it will respond
331 * with an error status of 'Bus Expiry'.
332 *
333 * Instead of always returning -EINVAL, let's
334 * give a hint to the gadget driver that this is
335 * the case by returning -EAGAIN.
336 */
7b9cc7a2
KL		 337 ret = -EAGAIN;
338 break;
339 default:
340 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
341 }
342
c0ca324d 343 break;
72246da4 344 }
f6bb225b 345 } while (--timeout);
72246da4 346
f6bb225b 347 if (timeout == 0) {
f6bb225b 348 ret = -ETIMEDOUT;
0933df15 349 cmd_status = -ETIMEDOUT;
f6bb225b 350 }
c0ca324d 351
0933df15
FB		 352 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
353
6cb2e4e3
FB		 354 if (ret == 0) {
355 switch (DWC3_DEPCMD_CMD(cmd)) {
356 case DWC3_DEPCMD_STARTTRANSFER:
357 dep->flags |= DWC3_EP_TRANSFER_STARTED;
358 break;
359 case DWC3_DEPCMD_ENDTRANSFER:
360 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
361 break;
362 default:
363 /* nothing */
364 break;
365 }
366 }
367
2b0f11df
FB		 368 if (unlikely(susphy)) {
369 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
370 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
371 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
372 }
373
c0ca324d 374 return ret;
72246da4
FB		 375}
376
50c763f8
JY		 377static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380 struct dwc3_gadget_ep_cmd_params params;
381 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
382
383 /*
384 * As of core revision 2.60a the recommended programming model
385 * is to set the ClearPendIN bit when issuing a Clear Stall EP
386 * command for IN endpoints. This is to prevent an issue where
387 * some (non-compliant) hosts may not send ACK TPs for pending
388 * IN transfers due to a mishandled error condition. Synopsys
389 * STAR 9000614252.
390 */
5e6c88d2
LB		 391 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
392 (dwc->gadget.speed >= USB_SPEED_SUPER))
50c763f8
JY		 393 cmd |= DWC3_DEPCMD_CLEARPENDIN;
394
395 memset(&params, 0, sizeof(params));
396
2cd4718d 397 return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
50c763f8
JY		 398}
399
72246da4 400static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 401 struct dwc3_trb *trb)
72246da4 402{
c439ef87 403 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 404
405 return dep->trb_pool_dma + offset;
406}
407
408static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
409{
410 struct dwc3 *dwc = dep->dwc;
411
412 if (dep->trb_pool)
413 return 0;
414
d64ff406 415 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
72246da4
FB		 416 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
417 &dep->trb_pool_dma, GFP_KERNEL);
418 if (!dep->trb_pool) {
419 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
420 dep->name);
421 return -ENOMEM;
422 }
423
424 return 0;
425}
426
427static void dwc3_free_trb_pool(struct dwc3_ep *dep)
428{
429 struct dwc3 *dwc = dep->dwc;
430
d64ff406 431 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
72246da4
FB		 432 dep->trb_pool, dep->trb_pool_dma);
433
434 dep->trb_pool = NULL;
435 dep->trb_pool_dma = 0;
436}
437
c4509601
JY		 438static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
439
440/**
441 * dwc3_gadget_start_config - Configure EP resources
442 * @dwc: pointer to our controller context structure
443 * @dep: endpoint that is being enabled
444 *
445 * The assignment of transfer resources cannot perfectly follow the
446 * data book due to the fact that the controller driver does not have
447 * all knowledge of the configuration in advance. It is given this
448 * information piecemeal by the composite gadget framework after every
449 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
450 * programming model in this scenario can cause errors. For two
451 * reasons:
452 *
453 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
454 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
455 * multiple interfaces.
456 *
457 * 2) The databook does not mention doing more DEPXFERCFG for new
458 * endpoint on alt setting (8.1.6).
459 *
460 * The following simplified method is used instead:
461 *
462 * All hardware endpoints can be assigned a transfer resource and this
463 * setting will stay persistent until either a core reset or
464 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
465 * do DEPXFERCFG for every hardware endpoint as well. We are
466 * guaranteed that there are as many transfer resources as endpoints.
467 *
468 * This function is called for each endpoint when it is being enabled
469 * but is triggered only when called for EP0-out, which always happens
470 * first, and which should only happen in one of the above conditions.
471 */
72246da4
FB		 472static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
473{
474 struct dwc3_gadget_ep_cmd_params params;
475 u32 cmd;
c4509601
JY		 476 int i;
477 int ret;
478
479 if (dep->number)
480 return 0;
72246da4
FB		 481
482 memset(&params, 0x00, sizeof(params));
c4509601 483 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 484
2cd4718d 485 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
c4509601
JY		 486 if (ret)
487 return ret;
488
489 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
490 struct dwc3_ep *dep = dwc->eps[i];
72246da4 491
c4509601
JY		 492 if (!dep)
493 continue;
494
495 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
496 if (ret)
497 return ret;
72246da4
FB		 498 }
499
500 return 0;
501}
502
503static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
21e64bf2 504 bool modify, bool restore)
72246da4 505{
39ebb05c
JY		 506 const struct usb_ss_ep_comp_descriptor *comp_desc;
507 const struct usb_endpoint_descriptor *desc;
72246da4
FB		 508 struct dwc3_gadget_ep_cmd_params params;
509
21e64bf2
FB		 510 if (dev_WARN_ONCE(dwc->dev, modify && restore,
511 "Can't modify and restore\n"))
512 return -EINVAL;
513
39ebb05c
JY		 514 comp_desc = dep->endpoint.comp_desc;
515 desc = dep->endpoint.desc;
516
72246da4
FB		 517 memset(&params, 0x00, sizeof(params));
518
dc1c70a7 519 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 520 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
521
522 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 523 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
676e3497 524 u32 burst = dep->endpoint.maxburst;
676e3497 525 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
d2e9a13a 526 }
72246da4 527
21e64bf2
FB		 528 if (modify) {
529 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
530 } else if (restore) {
265b70a7
PZ		 531 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
532 params.param2 |= dep->saved_state;
21e64bf2
FB		 533 } else {
534 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
265b70a7
PZ		 535 }
536
4bc48c97
FB		 537 if (usb_endpoint_xfer_control(desc))
538 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
13fa2e69
FB		 539
540 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
541 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 542
18b7ede5 543 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 544 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
545 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 546 dep->stream_capable = true;
547 }
548
0b93a4c8 549 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 550 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 551
552 /*
553 * We are doing 1:1 mapping for endpoints, meaning
554 * Physical Endpoints 2 maps to Logical Endpoint 2 and
555 * so on. We consider the direction bit as part of the physical
556 * endpoint number. So USB endpoint 0x81 is 0x03.
557 */
dc1c70a7 558 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 559
560 /*
561 * We must use the lower 16 TX FIFOs even though
562 * HW might have more
563 */
564 if (dep->direction)
dc1c70a7 565 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 566
567 if (desc->bInterval) {
dc1c70a7 568 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 569 dep->interval = 1 << (desc->bInterval - 1);
570 }
571
2cd4718d 572 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
72246da4
FB		 573}
574
575static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
576{
577 struct dwc3_gadget_ep_cmd_params params;
578
579 memset(&params, 0x00, sizeof(params));
580
dc1c70a7 581 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4 582
2cd4718d
FB		 583 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
584 &params);
72246da4
FB		 585}
586
587/**
588 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
589 * @dep: endpoint to be initialized
590 * @desc: USB Endpoint Descriptor
591 *
592 * Caller should take care of locking
593 */
594static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
21e64bf2 595 bool modify, bool restore)
72246da4 596{
39ebb05c 597 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
72246da4 598 struct dwc3 *dwc = dep->dwc;
39ebb05c 599
72246da4 600 u32 reg;
b09e99ee 601 int ret;
72246da4
FB		 602
603 if (!(dep->flags & DWC3_EP_ENABLED)) {
604 ret = dwc3_gadget_start_config(dwc, dep);
605 if (ret)
606 return ret;
607 }
608
39ebb05c 609 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
72246da4
FB		 610 if (ret)
611 return ret;
612
613 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 614 struct dwc3_trb *trb_st_hw;
615 struct dwc3_trb *trb_link;
72246da4 616
72246da4
FB		 617 dep->type = usb_endpoint_type(desc);
618 dep->flags |= DWC3_EP_ENABLED;
76a638f8 619 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
72246da4
FB		 620
621 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
622 reg |= DWC3_DALEPENA_EP(dep->number);
623 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
624
76a638f8
BW		 625 init_waitqueue_head(&dep->wait_end_transfer);
626
36b68aae 627 if (usb_endpoint_xfer_control(desc))
2870e501 628 goto out;
72246da4 629
0d25744a
JY		 630 /* Initialize the TRB ring */
631 dep->trb_dequeue = 0;
632 dep->trb_enqueue = 0;
633 memset(dep->trb_pool, 0,
634 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
635
36b68aae 636 /* Link TRB. The HWO bit is never reset */
72246da4
FB		 637 trb_st_hw = &dep->trb_pool[0];
638
f6bafc6a 639 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
f6bafc6a
FB		 640 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
641 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
642 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
643 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 644 }
645
a97ea994
FB		 646 /*
647 * Issue StartTransfer here with no-op TRB so we can always rely on No
648 * Response Update Transfer command.
649 */
650 if (usb_endpoint_xfer_bulk(desc)) {
651 struct dwc3_gadget_ep_cmd_params params;
652 struct dwc3_trb *trb;
653 dma_addr_t trb_dma;
654 u32 cmd;
655
656 memset(&params, 0, sizeof(params));
657 trb = &dep->trb_pool[0];
658 trb_dma = dwc3_trb_dma_offset(dep, trb);
659
660 params.param0 = upper_32_bits(trb_dma);
661 params.param1 = lower_32_bits(trb_dma);
662
663 cmd = DWC3_DEPCMD_STARTTRANSFER;
664
665 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
666 if (ret < 0)
667 return ret;
668
669 dep->flags |= DWC3_EP_BUSY;
670
671 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
672 WARN_ON_ONCE(!dep->resource_index);
673 }
674
2870e501
FB		 675
676out:
677 trace_dwc3_gadget_ep_enable(dep);
678
72246da4
FB		 679 return 0;
680}
681
b992e681 682static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 683static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 684{
685 struct dwc3_request *req;
686
0e146028 687 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 688
0e146028
FB		 689 /* - giveback all requests to gadget driver */
690 while (!list_empty(&dep->started_list)) {
691 req = next_request(&dep->started_list);
1591633e 692
0e146028 693 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
ea53b882
FB		 694 }
695
aa3342c8
FB		 696 while (!list_empty(&dep->pending_list)) {
697 req = next_request(&dep->pending_list);
72246da4 698
624407f9 699 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 700 }
72246da4
FB		 701}
702
703/**
704 * __dwc3_gadget_ep_disable - Disables a HW endpoint
705 * @dep: the endpoint to disable
706 *
624407f9
SAS		 707 * This function also removes requests which are currently processed ny the
708 * hardware and those which are not yet scheduled.
709 * Caller should take care of locking.
72246da4 710 */
72246da4
FB		 711static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
712{
713 struct dwc3 *dwc = dep->dwc;
714 u32 reg;
715
2870e501 716 trace_dwc3_gadget_ep_disable(dep);
7eaeac5c 717
624407f9 718 dwc3_remove_requests(dwc, dep);
72246da4 719
687ef981
FB		 720 /* make sure HW endpoint isn't stalled */
721 if (dep->flags & DWC3_EP_STALL)
7a608559 722 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 723
72246da4
FB		 724 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
725 reg &= ~DWC3_DALEPENA_EP(dep->number);
726 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
727
879631aa 728 dep->stream_capable = false;
72246da4 729 dep->type = 0;
76a638f8 730 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
72246da4 731
39ebb05c
JY		 732 /* Clear out the ep descriptors for non-ep0 */
733 if (dep->number > 1) {
734 dep->endpoint.comp_desc = NULL;
735 dep->endpoint.desc = NULL;
736 }
737
72246da4
FB		 738 return 0;
739}
740
741/* -------------------------------------------------------------------------- */
742
743static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
744 const struct usb_endpoint_descriptor *desc)
745{
746 return -EINVAL;
747}
748
749static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
750{
751 return -EINVAL;
752}
753
754/* -------------------------------------------------------------------------- */
755
756static int dwc3_gadget_ep_enable(struct usb_ep *ep,
757 const struct usb_endpoint_descriptor *desc)
758{
759 struct dwc3_ep *dep;
760 struct dwc3 *dwc;
761 unsigned long flags;
762 int ret;
763
764 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
765 pr_debug("dwc3: invalid parameters\n");
766 return -EINVAL;
767 }
768
769 if (!desc->wMaxPacketSize) {
770 pr_debug("dwc3: missing wMaxPacketSize\n");
771 return -EINVAL;
772 }
773
774 dep = to_dwc3_ep(ep);
775 dwc = dep->dwc;
776
95ca961c
FB		 777 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
778 "%s is already enabled\n",
779 dep->name))
c6f83f38 780 return 0;
c6f83f38 781
72246da4 782 spin_lock_irqsave(&dwc->lock, flags);
39ebb05c 783 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 784 spin_unlock_irqrestore(&dwc->lock, flags);
785
786 return ret;
787}
788
789static int dwc3_gadget_ep_disable(struct usb_ep *ep)
790{
791 struct dwc3_ep *dep;
792 struct dwc3 *dwc;
793 unsigned long flags;
794 int ret;
795
796 if (!ep) {
797 pr_debug("dwc3: invalid parameters\n");
798 return -EINVAL;
799 }
800
801 dep = to_dwc3_ep(ep);
802 dwc = dep->dwc;
803
95ca961c
FB		 804 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
805 "%s is already disabled\n",
806 dep->name))
72246da4 807 return 0;
72246da4 808
72246da4
FB		 809 spin_lock_irqsave(&dwc->lock, flags);
810 ret = __dwc3_gadget_ep_disable(dep);
811 spin_unlock_irqrestore(&dwc->lock, flags);
812
813 return ret;
814}
815
816static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
817 gfp_t gfp_flags)
818{
819 struct dwc3_request *req;
820 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 821
822 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 823 if (!req)
72246da4 824 return NULL;
72246da4
FB		 825
826 req->epnum = dep->number;
827 req->dep = dep;
72246da4 828
68d34c8a
FB		 829 dep->allocated_requests++;
830
2c4cbe6e
FB		 831 trace_dwc3_alloc_request(req);
832
72246da4
FB		 833 return &req->request;
834}
835
836static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
837 struct usb_request *request)
838{
839 struct dwc3_request *req = to_dwc3_request(request);
68d34c8a 840 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4 841
68d34c8a 842 dep->allocated_requests--;
2c4cbe6e 843 trace_dwc3_free_request(req);
72246da4
FB		 844 kfree(req);
845}
846
2c78c029
FB		 847static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
848
e49d3cf4
FB		 849static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
850 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
851 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
c71fc37c 852{
6b9018d4
FB		 853 struct dwc3 *dwc = dep->dwc;
854 struct usb_gadget *gadget = &dwc->gadget;
855 enum usb_device_speed speed = gadget->speed;
c71fc37c 856
ef966b9d 857 dwc3_ep_inc_enq(dep);
e5ba5ec8 858
f6bafc6a
FB		 859 trb->size = DWC3_TRB_SIZE_LENGTH(length);
860 trb->bpl = lower_32_bits(dma);
861 trb->bph = upper_32_bits(dma);
c71fc37c 862
16e78db7 863 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 864 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 865 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 866 break;
867
868 case USB_ENDPOINT_XFER_ISOC:
6b9018d4 869 if (!node) {
e5ba5ec8 870 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
6b9018d4
FB		 871
872 if (speed == USB_SPEED_HIGH) {
873 struct usb_ep *ep = &dep->endpoint;
874 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
875 }
876 } else {
e5ba5ec8 877 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
6b9018d4 878 }
ca4d44ea
FB		 879
880 /* always enable Interrupt on Missed ISOC */
881 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 882 break;
883
884 case USB_ENDPOINT_XFER_BULK:
885 case USB_ENDPOINT_XFER_INT:
f6bafc6a 886 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 887 break;
888 default:
889 /*
890 * This is only possible with faulty memory because we
891 * checked it already :)
892 */
0a695d4c
FB		 893 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
894 usb_endpoint_type(dep->endpoint.desc));
c71fc37c
FB		 895 }
896
ca4d44ea 897 /* always enable Continue on Short Packet */
c9508c8c 898 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
58f29034 899 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 900
e49d3cf4 901 if (short_not_ok)
c9508c8c
FB		 902 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
903 }
904
e49d3cf4 905 if ((!no_interrupt && !chain) ||
2c78c029 906 (dwc3_calc_trbs_left(dep) == 0))
c9508c8c 907 trb->ctrl |= DWC3_TRB_CTRL_IOC;
f3af3651 908
e5ba5ec8
PA		 909 if (chain)
910 trb->ctrl |= DWC3_TRB_CTRL_CHN;
911
16e78db7 912 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
e49d3cf4 913 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
c71fc37c 914
f6bafc6a 915 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 916
917 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 918}
919
e49d3cf4
FB		 920/**
921 * dwc3_prepare_one_trb - setup one TRB from one request
922 * @dep: endpoint for which this request is prepared
923 * @req: dwc3_request pointer
924 * @chain: should this TRB be chained to the next?
925 * @node: only for isochronous endpoints. First TRB needs different type.
926 */
927static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
928 struct dwc3_request *req, unsigned chain, unsigned node)
929{
930 struct dwc3_trb *trb;
931 unsigned length = req->request.length;
932 unsigned stream_id = req->request.stream_id;
933 unsigned short_not_ok = req->request.short_not_ok;
934 unsigned no_interrupt = req->request.no_interrupt;
935 dma_addr_t dma = req->request.dma;
936
937 trb = &dep->trb_pool[dep->trb_enqueue];
938
939 if (!req->trb) {
940 dwc3_gadget_move_started_request(req);
941 req->trb = trb;
942 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
943 dep->queued_requests++;
944 }
945
946 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
947 stream_id, short_not_ok, no_interrupt);
948}
949
361572b5
JY		 950/**
951 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
952 * @dep: The endpoint with the TRB ring
953 * @index: The index of the current TRB in the ring
954 *
955 * Returns the TRB prior to the one pointed to by the index. If the
956 * index is 0, we will wrap backwards, skip the link TRB, and return
957 * the one just before that.
958 */
959static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
960{
45438a0c 961 u8 tmp = index;
361572b5 962
45438a0c
FB		 963 if (!tmp)
964 tmp = DWC3_TRB_NUM - 1;
361572b5 965
45438a0c 966 return &dep->trb_pool[tmp - 1];
361572b5
JY		 967}
968
c4233573
FB		 969static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
970{
971 struct dwc3_trb *tmp;
f2694a93 972 struct dwc3 *dwc = dep->dwc;
32db3d94 973 u8 trbs_left;
c4233573
FB		 974
975 /*
976 * If enqueue & dequeue are equal than it is either full or empty.
977 *
978 * One way to know for sure is if the TRB right before us has HWO bit
979 * set or not. If it has, then we're definitely full and can't fit any
980 * more transfers in our ring.
981 */
982 if (dep->trb_enqueue == dep->trb_dequeue) {
361572b5 983 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
f2694a93
JD		 984 if (dev_WARN_ONCE(dwc->dev, tmp->ctrl & DWC3_TRB_CTRL_HWO,
985 "%s No TRBS left\n", dep->name))
361572b5 986 return 0;
c4233573
FB		 987
988 return DWC3_TRB_NUM - 1;
989 }
990
9d7aba77 991 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
3de2685f 992 trbs_left &= (DWC3_TRB_NUM - 1);
32db3d94 993
9d7aba77
JY		 994 if (dep->trb_dequeue < dep->trb_enqueue)
995 trbs_left--;
996
32db3d94 997 return trbs_left;
c4233573
FB		 998}
999
5ee85d89 1000static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
7ae7df49 1001 struct dwc3_request *req)
5ee85d89 1002{
1f512119 1003 struct scatterlist *sg = req->sg;
5ee85d89 1004 struct scatterlist *s;
5ee85d89
FB		 1005 int i;
1006
1f512119 1007 for_each_sg(sg, s, req->num_pending_sgs, i) {
c6267a51
FB		 1008 unsigned int length = req->request.length;
1009 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1010 unsigned int rem = length % maxp;
5ee85d89
FB		 1011 unsigned chain = true;
1012
4bc48c97 1013 if (sg_is_last(s))
5ee85d89
FB		 1014 chain = false;
1015
c6267a51
FB		 1016 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1017 struct dwc3 *dwc = dep->dwc;
1018 struct dwc3_trb *trb;
1019
1020 req->unaligned = true;
1021
1022 /* prepare normal TRB */
1023 dwc3_prepare_one_trb(dep, req, true, i);
1024
1025 /* Now prepare one extra TRB to align transfer size */
1026 trb = &dep->trb_pool[dep->trb_enqueue];
1027 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1028 maxp - rem, false, 0,
1029 req->request.stream_id,
1030 req->request.short_not_ok,
1031 req->request.no_interrupt);
1032 } else {
1033 dwc3_prepare_one_trb(dep, req, chain, i);
1034 }
5ee85d89 1035
7ae7df49 1036 if (!dwc3_calc_trbs_left(dep))
5ee85d89
FB		 1037 break;
1038 }
1039}
1040
1041static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
7ae7df49 1042 struct dwc3_request *req)
5ee85d89 1043{
c6267a51
FB		 1044 unsigned int length = req->request.length;
1045 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1046 unsigned int rem = length % maxp;
1047
1048 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1049 struct dwc3 *dwc = dep->dwc;
1050 struct dwc3_trb *trb;
1051
1052 req->unaligned = true;
1053
1054 /* prepare normal TRB */
1055 dwc3_prepare_one_trb(dep, req, true, 0);
1056
1057 /* Now prepare one extra TRB to align transfer size */
1058 trb = &dep->trb_pool[dep->trb_enqueue];
1059 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1060 false, 0, req->request.stream_id,
1061 req->request.short_not_ok,
1062 req->request.no_interrupt);
1063 } else {
1064 dwc3_prepare_one_trb(dep, req, false, 0);
1065 }
5ee85d89
FB		 1066}
1067
72246da4
FB		 1068/*
1069 * dwc3_prepare_trbs - setup TRBs from requests
1070 * @dep: endpoint for which requests are being prepared
72246da4 1071 *
1d046793
PZ		 1072 * The function goes through the requests list and sets up TRBs for the
1073 * transfers. The function returns once there are no more TRBs available or
1074 * it runs out of requests.
72246da4 1075 */
c4233573 1076static void dwc3_prepare_trbs(struct dwc3_ep *dep)
72246da4 1077{
68e823e2 1078 struct dwc3_request *req, *n;
72246da4
FB		 1079
1080 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1081
7ae7df49 1082 if (!dwc3_calc_trbs_left(dep))
89bc856e 1083 return;
72246da4 1084
d86c5a67
FB		 1085 /*
1086 * We can get in a situation where there's a request in the started list
1087 * but there weren't enough TRBs to fully kick it in the first time
1088 * around, so it has been waiting for more TRBs to be freed up.
1089 *
1090 * In that case, we should check if we have a request with pending_sgs
1091 * in the started list and prepare TRBs for that request first,
1092 * otherwise we will prepare TRBs completely out of order and that will
1093 * break things.
1094 */
1095 list_for_each_entry(req, &dep->started_list, list) {
1096 if (req->num_pending_sgs > 0)
1097 dwc3_prepare_one_trb_sg(dep, req);
1098
1099 if (!dwc3_calc_trbs_left(dep))
1100 return;
1101 }
1102
aa3342c8 1103 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1f512119 1104 if (req->num_pending_sgs > 0)
7ae7df49 1105 dwc3_prepare_one_trb_sg(dep, req);
5ee85d89 1106 else
7ae7df49 1107 dwc3_prepare_one_trb_linear(dep, req);
72246da4 1108
7ae7df49 1109 if (!dwc3_calc_trbs_left(dep))
5ee85d89 1110 return;
72246da4 1111 }
72246da4
FB		 1112}
1113
4fae2e3e 1114static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
72246da4
FB		 1115{
1116 struct dwc3_gadget_ep_cmd_params params;
1117 struct dwc3_request *req;
4fae2e3e 1118 int starting;
72246da4
FB		 1119 int ret;
1120 u32 cmd;
1121
4fae2e3e 1122 starting = !(dep->flags & DWC3_EP_BUSY);
72246da4 1123
4fae2e3e
FB		 1124 dwc3_prepare_trbs(dep);
1125 req = next_request(&dep->started_list);
72246da4
FB		 1126 if (!req) {
1127 dep->flags |= DWC3_EP_PENDING_REQUEST;
1128 return 0;
1129 }
1130
1131 memset(&params, 0, sizeof(params));
72246da4 1132
4fae2e3e 1133 if (starting) {
1877d6c9
PA		 1134 params.param0 = upper_32_bits(req->trb_dma);
1135 params.param1 = lower_32_bits(req->trb_dma);
b6b1c6db
FB		 1136 cmd = DWC3_DEPCMD_STARTTRANSFER |
1137 DWC3_DEPCMD_PARAM(cmd_param);
1877d6c9 1138 } else {
b6b1c6db
FB		 1139 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1140 DWC3_DEPCMD_PARAM(dep->resource_index);
1877d6c9 1141 }
72246da4 1142
2cd4718d 1143 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
72246da4 1144 if (ret < 0) {
72246da4
FB		 1145 /*
1146 * FIXME we need to iterate over the list of requests
1147 * here and stop, unmap, free and del each of the linked
1d046793 1148 * requests instead of what we do now.
72246da4 1149 */
ce3fc8b3
JD		 1150 if (req->trb)
1151 memset(req->trb, 0, sizeof(struct dwc3_trb));
8ab89da4 1152 dep->queued_requests--;
15b8d933 1153 dwc3_gadget_giveback(dep, req, ret);
72246da4
FB		 1154 return ret;
1155 }
1156
1157 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1158
4fae2e3e 1159 if (starting) {
2eb88016 1160 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
b4996a86 1161 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1162 }
25b8ff68 1163
72246da4
FB		 1164 return 0;
1165}
1166
6cb2e4e3
FB		 1167static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1168{
1169 u32 reg;
1170
1171 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1172 return DWC3_DSTS_SOFFN(reg);
1173}
1174
d6d6ec7b
PA		 1175static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1176 struct dwc3_ep *dep, u32 cur_uf)
1177{
1178 u32 uf;
1179
aa3342c8 1180 if (list_empty(&dep->pending_list)) {
5eb30ced 1181 dev_info(dwc->dev, "%s: ran out of requests\n",
73815280 1182 dep->name);
f4a53c55 1183 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1184 return;
1185 }
1186
af771d73
JY		 1187 /*
1188 * Schedule the first trb for one interval in the future or at
1189 * least 4 microframes.
1190 */
1191 uf = cur_uf + max_t(u32, 4, dep->interval);
d6d6ec7b 1192
4fae2e3e 1193 __dwc3_gadget_kick_transfer(dep, uf);
d6d6ec7b
PA		 1194}
1195
1196static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1197 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1198{
1199 u32 cur_uf, mask;
1200
1201 mask = ~(dep->interval - 1);
1202 cur_uf = event->parameters & mask;
1203
1204 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1205}
1206
72246da4
FB		 1207static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1208{
0fc9a1be
FB		 1209 struct dwc3 *dwc = dep->dwc;
1210 int ret;
1211
bb423984 1212 if (!dep->endpoint.desc) {
5eb30ced
FB		 1213 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1214 dep->name);
bb423984
FB		 1215 return -ESHUTDOWN;
1216 }
1217
1218 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1219 &req->request, req->dep->name)) {
5eb30ced
FB		 1220 dev_err(dwc->dev, "%s: request %p belongs to '%s'\n",
1221 dep->name, &req->request, req->dep->name);
bb423984
FB		 1222 return -EINVAL;
1223 }
1224
fc8bb91b
FB		 1225 pm_runtime_get(dwc->dev);
1226
72246da4
FB		 1227 req->request.actual = 0;
1228 req->request.status = -EINPROGRESS;
1229 req->direction = dep->direction;
1230 req->epnum = dep->number;
1231
fe84f522
FB		 1232 trace_dwc3_ep_queue(req);
1233
d64ff406
AB		 1234 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1235 dep->direction);
0fc9a1be
FB		 1236 if (ret)
1237 return ret;
1238
1f512119
FB		 1239 req->sg = req->request.sg;
1240 req->num_pending_sgs = req->request.num_mapped_sgs;
89185916 1241
aa3342c8 1242 list_add_tail(&req->list, &dep->pending_list);
72246da4 1243
d889c23c
FB		 1244 /*
1245 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1246 * wait for a XferNotReady event so we will know what's the current
1247 * (micro-)frame number.
1248 *
1249 * Without this trick, we are very, very likely gonna get Bus Expiry
1250 * errors which will force us issue EndTransfer command.
1251 */
1252 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
6cb2e4e3
FB		 1253 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1254 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1255 dwc3_stop_active_transfer(dwc, dep->number, true);
1256 dep->flags = DWC3_EP_ENABLED;
1257 } else {
1258 u32 cur_uf;
1259
1260 cur_uf = __dwc3_gadget_get_frame(dwc);
1261 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
87aba106 1262 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
6cb2e4e3 1263 }
08a36b54
FB		 1264 }
1265 return 0;
a0925324 1266 }
72246da4 1267
594e121f
FB		 1268 if (!dwc3_calc_trbs_left(dep))
1269 return 0;
b997ada5 1270
08a36b54 1271 ret = __dwc3_gadget_kick_transfer(dep, 0);
a8f32817
FB		 1272 if (ret == -EBUSY)
1273 ret = 0;
1274
1275 return ret;
72246da4
FB		 1276}
1277
04c03d10
FB		 1278static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1279 struct usb_request *request)
1280{
1281 dwc3_gadget_ep_free_request(ep, request);
1282}
1283
1284static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1285{
1286 struct dwc3_request *req;
1287 struct usb_request *request;
1288 struct usb_ep *ep = &dep->endpoint;
1289
04c03d10
FB		 1290 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1291 if (!request)
1292 return -ENOMEM;
1293
1294 request->length = 0;
1295 request->buf = dwc->zlp_buf;
1296 request->complete = __dwc3_gadget_ep_zlp_complete;
1297
1298 req = to_dwc3_request(request);
1299
1300 return __dwc3_gadget_ep_queue(dep, req);
1301}
1302
72246da4
FB		 1303static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1304 gfp_t gfp_flags)
1305{
1306 struct dwc3_request *req = to_dwc3_request(request);
1307 struct dwc3_ep *dep = to_dwc3_ep(ep);
1308 struct dwc3 *dwc = dep->dwc;
1309
1310 unsigned long flags;
1311
1312 int ret;
1313
fdee4eba 1314 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1315 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1316
1317 /*
1318 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1319 * setting request->zero, instead of doing magic, we will just queue an
1320 * extra usb_request ourselves so that it gets handled the same way as
1321 * any other request.
1322 */
d9261898
JY		 1323 if (ret == 0 && request->zero && request->length &&
1324 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1325 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1326
72246da4
FB		 1327 spin_unlock_irqrestore(&dwc->lock, flags);
1328
1329 return ret;
1330}
1331
1332static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1333 struct usb_request *request)
1334{
1335 struct dwc3_request *req = to_dwc3_request(request);
1336 struct dwc3_request *r = NULL;
1337
1338 struct dwc3_ep *dep = to_dwc3_ep(ep);
1339 struct dwc3 *dwc = dep->dwc;
1340
1341 unsigned long flags;
1342 int ret = 0;
1343
2c4cbe6e
FB		 1344 trace_dwc3_ep_dequeue(req);
1345
72246da4
FB		 1346 spin_lock_irqsave(&dwc->lock, flags);
1347
aa3342c8 1348 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1349 if (r == req)
1350 break;
1351 }
1352
1353 if (r != req) {
aa3342c8 1354 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1355 if (r == req)
1356 break;
1357 }
1358 if (r == req) {
1359 /* wait until it is processed */
b992e681 1360 dwc3_stop_active_transfer(dwc, dep->number, true);
cf3113d8
FB		 1361
1362 /*
1363 * If request was already started, this means we had to
1364 * stop the transfer. With that we also need to ignore
1365 * all TRBs used by the request, however TRBs can only
1366 * be modified after completion of END_TRANSFER
1367 * command. So what we do here is that we wait for
1368 * END_TRANSFER completion and only after that, we jump
1369 * over TRBs by clearing HWO and incrementing dequeue
1370 * pointer.
1371 *
1372 * Note that we have 2 possible types of transfers here:
1373 *
1374 * i) Linear buffer request
1375 * ii) SG-list based request
1376 *
1377 * SG-list based requests will have r->num_pending_sgs
1378 * set to a valid number (> 0). Linear requests,
1379 * normally use a single TRB.
1380 *
1381 * For each of these two cases, if r->unaligned flag is
1382 * set, one extra TRB has been used to align transfer
1383 * size to wMaxPacketSize.
1384 *
1385 * All of these cases need to be taken into
1386 * consideration so we don't mess up our TRB ring
1387 * pointers.
1388 */
1389 wait_event_lock_irq(dep->wait_end_transfer,
1390 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1391 dwc->lock);
1392
1393 if (!r->trb)
1394 goto out1;
1395
1396 if (r->num_pending_sgs) {
1397 struct dwc3_trb *trb;
1398 int i = 0;
1399
1400 for (i = 0; i < r->num_pending_sgs; i++) {
1401 trb = r->trb + i;
1402 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1403 dwc3_ep_inc_deq(dep);
1404 }
1405
1406 if (r->unaligned) {
1407 trb = r->trb + r->num_pending_sgs + 1;
1408 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1409 dwc3_ep_inc_deq(dep);
1410 }
1411 } else {
1412 struct dwc3_trb *trb = r->trb;
1413
1414 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1415 dwc3_ep_inc_deq(dep);
1416
1417 if (r->unaligned) {
1418 trb = r->trb + 1;
1419 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1420 dwc3_ep_inc_deq(dep);
1421 }
1422 }
e8d4e8be 1423 goto out1;
72246da4
FB		 1424 }
1425 dev_err(dwc->dev, "request %p was not queued to %s\n",
1426 request, ep->name);
1427 ret = -EINVAL;
1428 goto out0;
1429 }
1430
e8d4e8be 1431out1:
72246da4 1432 /* giveback the request */
cf3113d8 1433 dep->queued_requests--;
72246da4
FB		 1434 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1435
1436out0:
1437 spin_unlock_irqrestore(&dwc->lock, flags);
1438
1439 return ret;
1440}
1441
7a608559 1442int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1443{
1444 struct dwc3_gadget_ep_cmd_params params;
1445 struct dwc3 *dwc = dep->dwc;
1446 int ret;
1447
5ad02fb8
FB		 1448 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1449 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1450 return -EINVAL;
1451 }
1452
72246da4
FB		 1453 memset(&params, 0x00, sizeof(params));
1454
1455 if (value) {
69450c4d
FB		 1456 struct dwc3_trb *trb;
1457
1458 unsigned transfer_in_flight;
1459 unsigned started;
1460
ffb80fc6
FB		 1461 if (dep->flags & DWC3_EP_STALL)
1462 return 0;
1463
69450c4d
FB		 1464 if (dep->number > 1)
1465 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1466 else
1467 trb = &dwc->ep0_trb[dep->trb_enqueue];
1468
1469 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1470 started = !list_empty(&dep->started_list);
1471
1472 if (!protocol && ((dep->direction && transfer_in_flight) ||
1473 (!dep->direction && started))) {
7a608559
FB		 1474 return -EAGAIN;
1475 }
1476
2cd4718d
FB		 1477 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1478 &params);
72246da4 1479 if (ret)
3f89204b 1480 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1481 dep->name);
1482 else
1483 dep->flags |= DWC3_EP_STALL;
1484 } else {
ffb80fc6
FB		 1485 if (!(dep->flags & DWC3_EP_STALL))
1486 return 0;
2cd4718d 1487
50c763f8 1488 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4 1489 if (ret)
3f89204b 1490 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1491 dep->name);
1492 else
a535d81c 1493 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1494 }
5275455a 1495
72246da4
FB		 1496 return ret;
1497}
1498
1499static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1500{
1501 struct dwc3_ep *dep = to_dwc3_ep(ep);
1502 struct dwc3 *dwc = dep->dwc;
1503
1504 unsigned long flags;
1505
1506 int ret;
1507
1508 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1509 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1510 spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512 return ret;
1513}
1514
1515static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1516{
1517 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1518 struct dwc3 *dwc = dep->dwc;
1519 unsigned long flags;
95aa4e8d 1520 int ret;
72246da4 1521
249a4569 1522 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1523 dep->flags |= DWC3_EP_WEDGE;
1524
08f0d966 1525 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1526 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1527 else
7a608559 1528 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1529 spin_unlock_irqrestore(&dwc->lock, flags);
1530
1531 return ret;
72246da4
FB		 1532}
1533
1534/* -------------------------------------------------------------------------- */
1535
1536static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1537 .bLength = USB_DT_ENDPOINT_SIZE,
1538 .bDescriptorType = USB_DT_ENDPOINT,
1539 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1540};
1541
1542static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1543 .enable = dwc3_gadget_ep0_enable,
1544 .disable = dwc3_gadget_ep0_disable,
1545 .alloc_request = dwc3_gadget_ep_alloc_request,
1546 .free_request = dwc3_gadget_ep_free_request,
1547 .queue = dwc3_gadget_ep0_queue,
1548 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1549 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1550 .set_wedge = dwc3_gadget_ep_set_wedge,
1551};
1552
1553static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1554 .enable = dwc3_gadget_ep_enable,
1555 .disable = dwc3_gadget_ep_disable,
1556 .alloc_request = dwc3_gadget_ep_alloc_request,
1557 .free_request = dwc3_gadget_ep_free_request,
1558 .queue = dwc3_gadget_ep_queue,
1559 .dequeue = dwc3_gadget_ep_dequeue,
1560 .set_halt = dwc3_gadget_ep_set_halt,
1561 .set_wedge = dwc3_gadget_ep_set_wedge,
1562};
1563
1564/* -------------------------------------------------------------------------- */
1565
1566static int dwc3_gadget_get_frame(struct usb_gadget *g)
1567{
1568 struct dwc3 *dwc = gadget_to_dwc(g);
72246da4 1569
6cb2e4e3 1570 return __dwc3_gadget_get_frame(dwc);
72246da4
FB		 1571}
1572
218ef7b6 1573static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1574{
d6011f6f 1575 int retries;
72246da4 1576
218ef7b6 1577 int ret;
72246da4
FB		 1578 u32 reg;
1579
72246da4
FB		 1580 u8 link_state;
1581 u8 speed;
1582
72246da4
FB		 1583 /*
1584 * According to the Databook Remote wakeup request should
1585 * be issued only when the device is in early suspend state.
1586 *
1587 * We can check that via USB Link State bits in DSTS register.
1588 */
1589 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1590
1591 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c 1592 if ((speed == DWC3_DSTS_SUPERSPEED) ||
5eb30ced 1593 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
6b742899 1594 return 0;
72246da4
FB		 1595
1596 link_state = DWC3_DSTS_USBLNKST(reg);
1597
1598 switch (link_state) {
1599 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1600 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1601 break;
1602 default:
218ef7b6 1603 return -EINVAL;
72246da4
FB		 1604 }
1605
8598bde7
FB		 1606 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1607 if (ret < 0) {
1608 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1609 return ret;
8598bde7 1610 }
72246da4 1611
802fde98
PZ		 1612 /* Recent versions do this automatically */
1613 if (dwc->revision < DWC3_REVISION_194A) {
1614 /* write zeroes to Link Change Request */
fcc023c7 1615 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1616 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1617 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1618 }
72246da4 1619
1d046793 1620 /* poll until Link State changes to ON */
d6011f6f 1621 retries = 20000;
72246da4 1622
d6011f6f 1623 while (retries--) {
72246da4
FB		 1624 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1625
1626 /* in HS, means ON */
1627 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1628 break;
1629 }
1630
1631 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1632 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1633 return -EINVAL;
72246da4
FB		 1634 }
1635
218ef7b6
FB		 1636 return 0;
1637}
1638
1639static int dwc3_gadget_wakeup(struct usb_gadget *g)
1640{
1641 struct dwc3 *dwc = gadget_to_dwc(g);
1642 unsigned long flags;
1643 int ret;
1644
1645 spin_lock_irqsave(&dwc->lock, flags);
1646 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1647 spin_unlock_irqrestore(&dwc->lock, flags);
1648
1649 return ret;
1650}
1651
1652static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1653 int is_selfpowered)
1654{
1655 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1656 unsigned long flags;
72246da4 1657
249a4569 1658 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1659 g->is_selfpowered = !!is_selfpowered;
249a4569 1660 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1661
1662 return 0;
1663}
1664
7b2a0368 1665static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1666{
1667 u32 reg;
61d58242 1668 u32 timeout = 500;
72246da4 1669
fc8bb91b
FB		 1670 if (pm_runtime_suspended(dwc->dev))
1671 return 0;
1672
72246da4 1673 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1674 if (is_on) {
802fde98
PZ		 1675 if (dwc->revision <= DWC3_REVISION_187A) {
1676 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1677 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1678 }
1679
1680 if (dwc->revision >= DWC3_REVISION_194A)
1681 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1682 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1683
1684 if (dwc->has_hibernation)
1685 reg |= DWC3_DCTL_KEEP_CONNECT;
1686
9fcb3bd8 1687 dwc->pullups_connected = true;
8db7ed15 1688 } else {
72246da4 1689 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1690
1691 if (dwc->has_hibernation && !suspend)
1692 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1693
9fcb3bd8 1694 dwc->pullups_connected = false;
8db7ed15 1695 }
72246da4
FB		 1696
1697 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1698
1699 do {
1700 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
b6d4e16e
FB		 1701 reg &= DWC3_DSTS_DEVCTRLHLT;
1702 } while (--timeout && !(!is_on ^ !reg));
f2df679b
FB		 1703
1704 if (!timeout)
1705 return -ETIMEDOUT;
72246da4 1706
6f17f74b 1707 return 0;
72246da4
FB		 1708}
1709
1710static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1711{
1712 struct dwc3 *dwc = gadget_to_dwc(g);
1713 unsigned long flags;
6f17f74b 1714 int ret;
72246da4
FB		 1715
1716 is_on = !!is_on;
1717
bb014736
BW		 1718 /*
1719 * Per databook, when we want to stop the gadget, if a control transfer
1720 * is still in process, complete it and get the core into setup phase.
1721 */
1722 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1723 reinit_completion(&dwc->ep0_in_setup);
1724
1725 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1726 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1727 if (ret == 0) {
1728 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1729 return -ETIMEDOUT;
1730 }
1731 }
1732
72246da4 1733 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1734 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1735 spin_unlock_irqrestore(&dwc->lock, flags);
1736
6f17f74b 1737 return ret;
72246da4
FB		 1738}
1739
8698e2ac
FB		 1740static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1741{
1742 u32 reg;
1743
1744 /* Enable all but Start and End of Frame IRQs */
1745 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1746 DWC3_DEVTEN_EVNTOVERFLOWEN |
1747 DWC3_DEVTEN_CMDCMPLTEN |
1748 DWC3_DEVTEN_ERRTICERREN |
1749 DWC3_DEVTEN_WKUPEVTEN |
8698e2ac
FB		 1750 DWC3_DEVTEN_CONNECTDONEEN |
1751 DWC3_DEVTEN_USBRSTEN |
1752 DWC3_DEVTEN_DISCONNEVTEN);
1753
799e9dc8
FB		 1754 if (dwc->revision < DWC3_REVISION_250A)
1755 reg |= DWC3_DEVTEN_ULSTCNGEN;
1756
8698e2ac
FB		 1757 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1758}
1759
1760static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1761{
1762 /* mask all interrupts */
1763 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1764}
1765
1766static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1767static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1768
4e99472b
FB		 1769/**
1770 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1771 * dwc: pointer to our context structure
1772 *
1773 * The following looks like complex but it's actually very simple. In order to
1774 * calculate the number of packets we can burst at once on OUT transfers, we're
1775 * gonna use RxFIFO size.
1776 *
1777 * To calculate RxFIFO size we need two numbers:
1778 * MDWIDTH = size, in bits, of the internal memory bus
1779 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1780 *
1781 * Given these two numbers, the formula is simple:
1782 *
1783 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1784 *
1785 * 24 bytes is for 3x SETUP packets
1786 * 16 bytes is a clock domain crossing tolerance
1787 *
1788 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1789 */
1790static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1791{
1792 u32 ram2_depth;
1793 u32 mdwidth;
1794 u32 nump;
1795 u32 reg;
1796
1797 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1798 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1799
1800 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1801 nump = min_t(u32, nump, 16);
1802
1803 /* update NumP */
1804 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1805 reg &= ~DWC3_DCFG_NUMP_MASK;
1806 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1807 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1808}
1809
d7be2952 1810static int __dwc3_gadget_start(struct dwc3 *dwc)
72246da4 1811{
72246da4 1812 struct dwc3_ep *dep;
72246da4
FB		 1813 int ret = 0;
1814 u32 reg;
1815
cf40b86b
JY		 1816 /*
1817 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1818 * the core supports IMOD, disable it.
1819 */
1820 if (dwc->imod_interval) {
1821 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1822 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1823 } else if (dwc3_has_imod(dwc)) {
1824 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1825 }
1826
72246da4
FB		 1827 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1828 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1829
1830 /**
1831 * WORKAROUND: DWC3 revision < 2.20a have an issue
1832 * which would cause metastability state on Run/Stop
1833 * bit if we try to force the IP to USB2-only mode.
1834 *
1835 * Because of that, we cannot configure the IP to any
1836 * speed other than the SuperSpeed
1837 *
1838 * Refers to:
1839 *
1840 * STAR#9000525659: Clock Domain Crossing on DCTL in
1841 * USB 2.0 Mode
1842 */
f7e846f0 1843 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1844 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1845 } else {
1846 switch (dwc->maximum_speed) {
1847 case USB_SPEED_LOW:
2da9ad76 1848 reg |= DWC3_DCFG_LOWSPEED;
f7e846f0
FB		 1849 break;
1850 case USB_SPEED_FULL:
9418ee15 1851 reg |= DWC3_DCFG_FULLSPEED;
f7e846f0
FB		 1852 break;
1853 case USB_SPEED_HIGH:
2da9ad76 1854 reg |= DWC3_DCFG_HIGHSPEED;
f7e846f0 1855 break;
7580862b 1856 case USB_SPEED_SUPER_PLUS:
2da9ad76 1857 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
7580862b 1858 break;
f7e846f0 1859 default:
77966eb8
JY		 1860 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1861 dwc->maximum_speed);
1862 /* fall through */
1863 case USB_SPEED_SUPER:
1864 reg |= DWC3_DCFG_SUPERSPEED;
1865 break;
f7e846f0
FB		 1866 }
1867 }
72246da4
FB		 1868 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1869
2a58f9c1
FB		 1870 /*
1871 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1872 * field instead of letting dwc3 itself calculate that automatically.
1873 *
1874 * This way, we maximize the chances that we'll be able to get several
1875 * bursts of data without going through any sort of endpoint throttling.
1876 */
1877 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1878 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1879 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1880
4e99472b
FB		 1881 dwc3_gadget_setup_nump(dwc);
1882
72246da4
FB		 1883 /* Start with SuperSpeed Default */
1884 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1885
1886 dep = dwc->eps[0];
39ebb05c 1887 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1888 if (ret) {
1889 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1890 goto err0;
72246da4
FB		 1891 }
1892
1893 dep = dwc->eps[1];
39ebb05c 1894 ret = __dwc3_gadget_ep_enable(dep, false, false);
72246da4
FB		 1895 if (ret) {
1896 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
d7be2952 1897 goto err1;
72246da4
FB		 1898 }
1899
1900 /* begin to receive SETUP packets */
c7fcdeb2 1901 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1902 dwc3_ep0_out_start(dwc);
1903
8698e2ac
FB		 1904 dwc3_gadget_enable_irq(dwc);
1905
72246da4
FB		 1906 return 0;
1907
b0d7ffd4 1908err1:
d7be2952 1909 __dwc3_gadget_ep_disable(dwc->eps[0]);
b0d7ffd4
FB		 1910
1911err0:
72246da4
FB		 1912 return ret;
1913}
1914
d7be2952
FB		 1915static int dwc3_gadget_start(struct usb_gadget *g,
1916 struct usb_gadget_driver *driver)
72246da4
FB		 1917{
1918 struct dwc3 *dwc = gadget_to_dwc(g);
1919 unsigned long flags;
d7be2952 1920 int ret = 0;
8698e2ac 1921 int irq;
72246da4 1922
9522def4 1923 irq = dwc->irq_gadget;
d7be2952
FB		 1924 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1925 IRQF_SHARED, "dwc3", dwc->ev_buf);
1926 if (ret) {
1927 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1928 irq, ret);
1929 goto err0;
1930 }
1931
72246da4 1932 spin_lock_irqsave(&dwc->lock, flags);
d7be2952
FB		 1933 if (dwc->gadget_driver) {
1934 dev_err(dwc->dev, "%s is already bound to %s\n",
1935 dwc->gadget.name,
1936 dwc->gadget_driver->driver.name);
1937 ret = -EBUSY;
1938 goto err1;
1939 }
1940
1941 dwc->gadget_driver = driver;
1942
fc8bb91b
FB		 1943 if (pm_runtime_active(dwc->dev))
1944 __dwc3_gadget_start(dwc);
1945
d7be2952
FB		 1946 spin_unlock_irqrestore(&dwc->lock, flags);
1947
1948 return 0;
1949
1950err1:
1951 spin_unlock_irqrestore(&dwc->lock, flags);
1952 free_irq(irq, dwc);
1953
1954err0:
1955 return ret;
1956}
72246da4 1957
d7be2952
FB		 1958static void __dwc3_gadget_stop(struct dwc3 *dwc)
1959{
8698e2ac 1960 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1961 __dwc3_gadget_ep_disable(dwc->eps[0]);
1962 __dwc3_gadget_ep_disable(dwc->eps[1]);
d7be2952 1963}
72246da4 1964
d7be2952
FB		 1965static int dwc3_gadget_stop(struct usb_gadget *g)
1966{
1967 struct dwc3 *dwc = gadget_to_dwc(g);
1968 unsigned long flags;
76a638f8 1969 int epnum;
72246da4 1970
d7be2952 1971 spin_lock_irqsave(&dwc->lock, flags);
76a638f8
BW		 1972
1973 if (pm_runtime_suspended(dwc->dev))
1974 goto out;
1975
d7be2952 1976 __dwc3_gadget_stop(dwc);
76a638f8
BW		 1977
1978 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1979 struct dwc3_ep *dep = dwc->eps[epnum];
1980
1981 if (!dep)
1982 continue;
1983
1984 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1985 continue;
1986
1987 wait_event_lock_irq(dep->wait_end_transfer,
1988 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1989 dwc->lock);
1990 }
1991
1992out:
d7be2952 1993 dwc->gadget_driver = NULL;
72246da4
FB		 1994 spin_unlock_irqrestore(&dwc->lock, flags);
1995
3f308d17 1996 free_irq(dwc->irq_gadget, dwc->ev_buf);
b0d7ffd4 1997
72246da4
FB		 1998 return 0;
1999}
802fde98 2000
72246da4
FB		 2001static const struct usb_gadget_ops dwc3_gadget_ops = {
2002 .get_frame = dwc3_gadget_get_frame,
2003 .wakeup = dwc3_gadget_wakeup,
2004 .set_selfpowered = dwc3_gadget_set_selfpowered,
2005 .pullup = dwc3_gadget_pullup,
2006 .udc_start = dwc3_gadget_start,
2007 .udc_stop = dwc3_gadget_stop,
2008};
2009
2010/* -------------------------------------------------------------------------- */
2011
f3bcfc7e 2012static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 num)
72246da4
FB		 2013{
2014 struct dwc3_ep *dep;
47d3946e 2015 u8 epnum;
72246da4 2016
f3bcfc7e
BD		 2017 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2018
47d3946e
BD		 2019 for (epnum = 0; epnum < num; epnum++) {
2020 bool direction = epnum & 1;
72246da4 2021
72246da4 2022 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 2023 if (!dep)
72246da4 2024 return -ENOMEM;
72246da4
FB		 2025
2026 dep->dwc = dwc;
2027 dep->number = epnum;
47d3946e 2028 dep->direction = direction;
2eb88016 2029 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
72246da4
FB		 2030 dwc->eps[epnum] = dep;
2031
2032 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
47d3946e 2033 direction ? "in" : "out");
6a1e3ef4 2034
72246da4 2035 dep->endpoint.name = dep->name;
39ebb05c
JY		 2036
2037 if (!(dep->number > 1)) {
2038 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2039 dep->endpoint.comp_desc = NULL;
2040 }
2041
74674cbf 2042 spin_lock_init(&dep->lock);
72246da4
FB		 2043
2044 if (epnum == 0 || epnum == 1) {
e117e742 2045 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 2046 dep->endpoint.maxburst = 1;
72246da4
FB		 2047 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2048 if (!epnum)
2049 dwc->gadget.ep0 = &dep->endpoint;
28781789
FB		 2050 } else if (direction) {
2051 int mdwidth;
2052 int size;
2053 int ret;
2054 int num;
2055
2056 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2057 /* MDWIDTH is represented in bits, we need it in bytes */
2058 mdwidth /= 8;
2059
47d3946e 2060 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(epnum >> 1));
28781789
FB		 2061 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2062
2063 /* FIFO Depth is in MDWDITH bytes. Multiply */
2064 size *= mdwidth;
2065
2066 num = size / 1024;
2067 if (num == 0)
2068 num = 1;
2069
2070 /*
2071 * FIFO sizes account an extra MDWIDTH * (num + 1) bytes for
2072 * internal overhead. We don't really know how these are used,
2073 * but documentation say it exists.
2074 */
2075 size -= mdwidth * (num + 1);
2076 size /= num;
2077
2078 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2079
2080 dep->endpoint.max_streams = 15;
2081 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2082 list_add_tail(&dep->endpoint.ep_list,
2083 &dwc->gadget.ep_list);
2084
2085 ret = dwc3_alloc_trb_pool(dep);
2086 if (ret)
2087 return ret;
72246da4
FB		 2088 } else {
2089 int ret;
2090
e117e742 2091 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 2092 dep->endpoint.max_streams = 15;
72246da4
FB		 2093 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2094 list_add_tail(&dep->endpoint.ep_list,
2095 &dwc->gadget.ep_list);
2096
2097 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 2098 if (ret)
72246da4 2099 return ret;
72246da4 2100 }
25b8ff68 2101
a474d3b7
RB		 2102 if (epnum == 0 || epnum == 1) {
2103 dep->endpoint.caps.type_control = true;
2104 } else {
2105 dep->endpoint.caps.type_iso = true;
2106 dep->endpoint.caps.type_bulk = true;
2107 dep->endpoint.caps.type_int = true;
2108 }
2109
47d3946e 2110 dep->endpoint.caps.dir_in = direction;
a474d3b7
RB		 2111 dep->endpoint.caps.dir_out = !direction;
2112
aa3342c8
FB		 2113 INIT_LIST_HEAD(&dep->pending_list);
2114 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 2115 }
2116
2117 return 0;
2118}
2119
2120static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2121{
2122 struct dwc3_ep *dep;
2123 u8 epnum;
2124
2125 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2126 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2127 if (!dep)
2128 continue;
5bf8fae3
GC		 2129 /*
2130 * Physical endpoints 0 and 1 are special; they form the
2131 * bi-directional USB endpoint 0.
2132 *
2133 * For those two physical endpoints, we don't allocate a TRB
2134 * pool nor do we add them the endpoints list. Due to that, we
2135 * shouldn't do these two operations otherwise we would end up
2136 * with all sorts of bugs when removing dwc3.ko.
2137 */
2138 if (epnum != 0 && epnum != 1) {
2139 dwc3_free_trb_pool(dep);
72246da4 2140 list_del(&dep->endpoint.ep_list);
5bf8fae3 2141 }
72246da4
FB		 2142
2143 kfree(dep);
2144 }
2145}
2146
72246da4 2147/* -------------------------------------------------------------------------- */
e5caff68 2148
e5ba5ec8
PA		 2149static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2150 struct dwc3_request *req, struct dwc3_trb *trb,
e5b36ae2
FB		 2151 const struct dwc3_event_depevt *event, int status,
2152 int chain)
72246da4 2153{
72246da4
FB		 2154 unsigned int count;
2155 unsigned int s_pkt = 0;
d6d6ec7b 2156 unsigned int trb_status;
72246da4 2157
dc55c67e 2158 dwc3_ep_inc_deq(dep);
a9c3ca5f
FB		 2159
2160 if (req->trb == trb)
2161 dep->queued_requests--;
2162
2c4cbe6e
FB		 2163 trace_dwc3_complete_trb(dep, trb);
2164
e5b36ae2
FB		 2165 /*
2166 * If we're in the middle of series of chained TRBs and we
2167 * receive a short transfer along the way, DWC3 will skip
2168 * through all TRBs including the last TRB in the chain (the
2169 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2170 * bit and SW has to do it manually.
2171 *
2172 * We're going to do that here to avoid problems of HW trying
2173 * to use bogus TRBs for transfers.
2174 */
2175 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2176 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2177
c6267a51
FB		 2178 /*
2179 * If we're dealing with unaligned size OUT transfer, we will be left
2180 * with one TRB pending in the ring. We need to manually clear HWO bit
2181 * from that TRB.
2182 */
2183 if (req->unaligned && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2184 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2185 return 1;
2186 }
2187
e5ba5ec8 2188 count = trb->size & DWC3_TRB_SIZE_MASK;
e62c5bc5 2189 req->remaining += count;
e5ba5ec8 2190
35b2719e
FB		 2191 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2192 return 1;
2193
e5ba5ec8
PA		 2194 if (dep->direction) {
2195 if (count) {
2196 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2197 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
e5ba5ec8
PA		 2198 /*
2199 * If missed isoc occurred and there is
2200 * no request queued then issue END
2201 * TRANSFER, so that core generates
2202 * next xfernotready and we will issue
2203 * a fresh START TRANSFER.
2204 * If there are still queued request
2205 * then wait, do not issue either END
2206 * or UPDATE TRANSFER, just attach next
aa3342c8 2207 * request in pending_list during
e5ba5ec8
PA		 2208 * giveback.If any future queued request
2209 * is successfully transferred then we
2210 * will issue UPDATE TRANSFER for all
aa3342c8 2211 * request in the pending_list.
e5ba5ec8
PA		 2212 */
2213 dep->flags |= DWC3_EP_MISSED_ISOC;
2214 } else {
2215 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2216 dep->name);
2217 status = -ECONNRESET;
2218 }
2219 } else {
2220 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2221 }
2222 } else {
2223 if (count && (event->status & DEPEVT_STATUS_SHORT))
2224 s_pkt = 1;
2225 }
2226
7c705dfe 2227 if (s_pkt && !chain)
e5ba5ec8 2228 return 1;
f99f53f2 2229
e5ba5ec8
PA		 2230 if ((event->status & DEPEVT_STATUS_IOC) &&
2231 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2232 return 1;
f99f53f2 2233
e5ba5ec8
PA		 2234 return 0;
2235}
2236
2237static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2238 const struct dwc3_event_depevt *event, int status)
2239{
31162af4 2240 struct dwc3_request *req, *n;
e5ba5ec8 2241 struct dwc3_trb *trb;
d6e10bf2 2242 bool ioc = false;
e62c5bc5 2243 int ret = 0;
e5ba5ec8 2244
31162af4 2245 list_for_each_entry_safe(req, n, &dep->started_list, list) {
1f512119 2246 unsigned length;
e5b36ae2
FB		 2247 int chain;
2248
1f512119
FB		 2249 length = req->request.length;
2250 chain = req->num_pending_sgs > 0;
31162af4 2251 if (chain) {
1f512119 2252 struct scatterlist *sg = req->sg;
31162af4 2253 struct scatterlist *s;
1f512119 2254 unsigned int pending = req->num_pending_sgs;
31162af4 2255 unsigned int i;
c7de5734 2256
1f512119 2257 for_each_sg(sg, s, pending, i) {
31162af4 2258 trb = &dep->trb_pool[dep->trb_dequeue];
31162af4 2259
7282c4ef
FB		 2260 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2261 break;
2262
1f512119
FB		 2263 req->sg = sg_next(s);
2264 req->num_pending_sgs--;
2265
31162af4
FB		 2266 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2267 event, status, chain);
1f512119
FB		 2268 if (ret)
2269 break;
31162af4
FB		 2270 }
2271 } else {
737f1ae2 2272 trb = &dep->trb_pool[dep->trb_dequeue];
d115d705 2273 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
e5b36ae2 2274 event, status, chain);
31162af4 2275 }
d115d705 2276
c6267a51
FB		 2277 if (req->unaligned) {
2278 trb = &dep->trb_pool[dep->trb_dequeue];
2279 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2280 event, status, false);
2281 req->unaligned = false;
2282 }
2283
e62c5bc5 2284 req->request.actual = length - req->remaining;
1f512119 2285
ff377ae4 2286 if ((req->request.actual < length) && req->num_pending_sgs)
1f512119
FB		 2287 return __dwc3_gadget_kick_transfer(dep, 0);
2288
d115d705 2289 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8 2290
d6e10bf2
AB		 2291 if (ret) {
2292 if ((event->status & DEPEVT_STATUS_IOC) &&
2293 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2294 ioc = true;
72246da4 2295 break;
d6e10bf2 2296 }
31162af4 2297 }
72246da4 2298
4cb42217
FB		 2299 /*
2300 * Our endpoint might get disabled by another thread during
2301 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2302 * early on so DWC3_EP_BUSY flag gets cleared
2303 */
2304 if (!dep->endpoint.desc)
2305 return 1;
2306
cdc359dd 2307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 2308 list_empty(&dep->started_list)) {
2309 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 2310 /*
2311 * If there is no entry in request list then do
2312 * not issue END TRANSFER now. Just set PENDING
2313 * flag, so that END TRANSFER is issued when an
2314 * entry is added into request list.
2315 */
2316 dep->flags = DWC3_EP_PENDING_REQUEST;
2317 } else {
b992e681 2318 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 2319 dep->flags = DWC3_EP_ENABLED;
2320 }
7efea86c
PA		 2321 return 1;
2322 }
2323
d6e10bf2
AB		 2324 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2325 return 0;
2326
72246da4
FB		 2327 return 1;
2328}
2329
2330static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2331 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2332{
2333 unsigned status = 0;
2334 int clean_busy;
e18b7975
FB		 2335 u32 is_xfer_complete;
2336
2337 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2338
2339 if (event->status & DEPEVT_STATUS_BUSERR)
2340 status = -ECONNRESET;
2341
1d046793 2342 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
4cb42217 2343 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
e18b7975 2344 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2345 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2346
2347 /*
2348 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2349 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2350 */
2351 if (dwc->revision < DWC3_REVISION_183A) {
2352 u32 reg;
2353 int i;
2354
2355 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2356 dep = dwc->eps[i];
fae2b904
FB		 2357
2358 if (!(dep->flags & DWC3_EP_ENABLED))
2359 continue;
2360
aa3342c8 2361 if (!list_empty(&dep->started_list))
fae2b904
FB		 2362 return;
2363 }
2364
2365 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2366 reg |= dwc->u1u2;
2367 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2368
2369 dwc->u1u2 = 0;
2370 }
8a1a9c9e 2371
4cb42217
FB		 2372 /*
2373 * Our endpoint might get disabled by another thread during
2374 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2375 * early on so DWC3_EP_BUSY flag gets cleared
2376 */
2377 if (!dep->endpoint.desc)
2378 return;
2379
e6e709b7 2380 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2381 int ret;
2382
4fae2e3e 2383 ret = __dwc3_gadget_kick_transfer(dep, 0);
8a1a9c9e
FB		 2384 if (!ret || ret == -EBUSY)
2385 return;
2386 }
72246da4
FB		 2387}
2388
72246da4
FB		 2389static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2390 const struct dwc3_event_depevt *event)
2391{
2392 struct dwc3_ep *dep;
2393 u8 epnum = event->endpoint_number;
76a638f8 2394 u8 cmd;
72246da4
FB		 2395
2396 dep = dwc->eps[epnum];
2397
d7fd41c6
JD		 2398 if (!(dep->flags & DWC3_EP_ENABLED)) {
2399 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2400 return;
2401
2402 /* Handle only EPCMDCMPLT when EP disabled */
2403 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2404 return;
2405 }
3336abb5 2406
72246da4
FB		 2407 if (epnum == 0 || epnum == 1) {
2408 dwc3_ep0_interrupt(dwc, event);
2409 return;
2410 }
2411
2412 switch (event->endpoint_event) {
2413 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2414 dep->resource_index = 0;
c2df85ca 2415
16e78db7 2416 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8566cd1a 2417 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
72246da4
FB		 2418 return;
2419 }
2420
029d97ff 2421 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2422 break;
2423 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2424 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2425 break;
2426 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2427 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2428 dwc3_gadget_start_isoc(dwc, dep, event);
2429 } else {
2430 int ret;
2431
4fae2e3e 2432 ret = __dwc3_gadget_kick_transfer(dep, 0);
72246da4
FB		 2433 if (!ret || ret == -EBUSY)
2434 return;
72246da4
FB		 2435 }
2436
879631aa
FB		 2437 break;
2438 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2439 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2440 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2441 dep->name);
2442 return;
2443 }
72246da4 2444 break;
72246da4 2445 case DWC3_DEPEVT_EPCMDCMPLT:
76a638f8
BW		 2446 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2447
2448 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2449 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2450 wake_up(&dep->wait_end_transfer);
2451 }
2452 break;
2453 case DWC3_DEPEVT_RXTXFIFOEVT:
72246da4
FB		 2454 break;
2455 }
2456}
2457
2458static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2459{
2460 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2461 spin_unlock(&dwc->lock);
2462 dwc->gadget_driver->disconnect(&dwc->gadget);
2463 spin_lock(&dwc->lock);
2464 }
2465}
2466
bc5ba2e0
FB		 2467static void dwc3_suspend_gadget(struct dwc3 *dwc)
2468{
73a30bfc 2469 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2470 spin_unlock(&dwc->lock);
2471 dwc->gadget_driver->suspend(&dwc->gadget);
2472 spin_lock(&dwc->lock);
2473 }
2474}
2475
2476static void dwc3_resume_gadget(struct dwc3 *dwc)
2477{
73a30bfc 2478 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2479 spin_unlock(&dwc->lock);
2480 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2481 spin_lock(&dwc->lock);
8e74475b
FB		 2482 }
2483}
2484
2485static void dwc3_reset_gadget(struct dwc3 *dwc)
2486{
2487 if (!dwc->gadget_driver)
2488 return;
2489
2490 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2491 spin_unlock(&dwc->lock);
2492 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2493 spin_lock(&dwc->lock);
2494 }
2495}
2496
b992e681 2497static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2498{
2499 struct dwc3_ep *dep;
2500 struct dwc3_gadget_ep_cmd_params params;
2501 u32 cmd;
2502 int ret;
2503
2504 dep = dwc->eps[epnum];
2505
76a638f8
BW		 2506 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2507 !dep->resource_index)
3daf74d7
PA		 2508 return;
2509
57911504
PA		 2510 /*
2511 * NOTICE: We are violating what the Databook says about the
2512 * EndTransfer command. Ideally we would _always_ wait for the
2513 * EndTransfer Command Completion IRQ, but that's causing too
2514 * much trouble synchronizing between us and gadget driver.
2515 *
2516 * We have discussed this with the IP Provider and it was
2517 * suggested to giveback all requests here, but give HW some
2518 * extra time to synchronize with the interconnect. We're using
dc93b41a 2519 * an arbitrary 100us delay for that.
57911504
PA		 2520 *
2521 * Note also that a similar handling was tested by Synopsys
2522 * (thanks a lot Paul) and nothing bad has come out of it.
2523 * In short, what we're doing is:
2524 *
2525 * - Issue EndTransfer WITH CMDIOC bit set
2526 * - Wait 100us
06281d46
JY		 2527 *
2528 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2529 * supports a mode to work around the above limitation. The
2530 * software can poll the CMDACT bit in the DEPCMD register
2531 * after issuing a EndTransfer command. This mode is enabled
2532 * by writing GUCTL2[14]. This polling is already done in the
2533 * dwc3_send_gadget_ep_cmd() function so if the mode is
2534 * enabled, the EndTransfer command will have completed upon
2535 * returning from this function and we don't need to delay for
2536 * 100us.
2537 *
2538 * This mode is NOT available on the DWC_usb31 IP.
57911504
PA		 2539 */
2540
3daf74d7 2541 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2542 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2543 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2544 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7 2545 memset(&params, 0, sizeof(params));
2cd4718d 2546 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3daf74d7 2547 WARN_ON_ONCE(ret);
b4996a86 2548 dep->resource_index = 0;
041d81f4 2549 dep->flags &= ~DWC3_EP_BUSY;
06281d46 2550
76a638f8
BW		 2551 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2552 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
06281d46 2553 udelay(100);
76a638f8 2554 }
72246da4
FB		 2555}
2556
72246da4
FB		 2557static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2558{
2559 u32 epnum;
2560
2561 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2562 struct dwc3_ep *dep;
72246da4
FB		 2563 int ret;
2564
2565 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2566 if (!dep)
2567 continue;
72246da4
FB		 2568
2569 if (!(dep->flags & DWC3_EP_STALL))
2570 continue;
2571
2572 dep->flags &= ~DWC3_EP_STALL;
2573
50c763f8 2574 ret = dwc3_send_clear_stall_ep_cmd(dep);
72246da4
FB		 2575 WARN_ON_ONCE(ret);
2576 }
2577}
2578
2579static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2580{
c4430a26
FB		 2581 int reg;
2582
72246da4
FB		 2583 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2584 reg &= ~DWC3_DCTL_INITU1ENA;
2585 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2586
2587 reg &= ~DWC3_DCTL_INITU2ENA;
2588 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2589
72246da4
FB		 2590 dwc3_disconnect_gadget(dwc);
2591
2592 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2593 dwc->setup_packet_pending = false;
06a374ed 2594 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
fc8bb91b
FB		 2595
2596 dwc->connected = false;
72246da4
FB		 2597}
2598
72246da4
FB		 2599static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2600{
2601 u32 reg;
2602
fc8bb91b
FB		 2603 dwc->connected = true;
2604
df62df56
FB		 2605 /*
2606 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2607 * would cause a missing Disconnect Event if there's a
2608 * pending Setup Packet in the FIFO.
2609 *
2610 * There's no suggested workaround on the official Bug
2611 * report, which states that "unless the driver/application
2612 * is doing any special handling of a disconnect event,
2613 * there is no functional issue".
2614 *
2615 * Unfortunately, it turns out that we _do_ some special
2616 * handling of a disconnect event, namely complete all
2617 * pending transfers, notify gadget driver of the
2618 * disconnection, and so on.
2619 *
2620 * Our suggested workaround is to follow the Disconnect
2621 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2622 * flag. Such flag gets set whenever we have a SETUP_PENDING
2623 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2624 * same endpoint.
2625 *
2626 * Refers to:
2627 *
2628 * STAR#9000466709: RTL: Device : Disconnect event not
2629 * generated if setup packet pending in FIFO
2630 */
2631 if (dwc->revision < DWC3_REVISION_188A) {
2632 if (dwc->setup_packet_pending)
2633 dwc3_gadget_disconnect_interrupt(dwc);
2634 }
2635
8e74475b 2636 dwc3_reset_gadget(dwc);
72246da4
FB		 2637
2638 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2639 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2640 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2641 dwc->test_mode = false;
72246da4
FB		 2642 dwc3_clear_stall_all_ep(dwc);
2643
2644 /* Reset device address to zero */
2645 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2646 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2647 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2648}
2649
72246da4
FB		 2650static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2651{
72246da4
FB		 2652 struct dwc3_ep *dep;
2653 int ret;
2654 u32 reg;
2655 u8 speed;
2656
72246da4
FB		 2657 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2658 speed = reg & DWC3_DSTS_CONNECTSPD;
2659 dwc->speed = speed;
2660
5fb6fdaf
JY		 2661 /*
2662 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2663 * each time on Connect Done.
2664 *
2665 * Currently we always use the reset value. If any platform
2666 * wants to set this to a different value, we need to add a
2667 * setting and update GCTL.RAMCLKSEL here.
2668 */
72246da4
FB		 2669
2670 switch (speed) {
2da9ad76 2671 case DWC3_DSTS_SUPERSPEED_PLUS:
7580862b
JY		 2672 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2673 dwc->gadget.ep0->maxpacket = 512;
2674 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2675 break;
2da9ad76 2676 case DWC3_DSTS_SUPERSPEED:
05870c5b
FB		 2677 /*
2678 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2679 * would cause a missing USB3 Reset event.
2680 *
2681 * In such situations, we should force a USB3 Reset
2682 * event by calling our dwc3_gadget_reset_interrupt()
2683 * routine.
2684 *
2685 * Refers to:
2686 *
2687 * STAR#9000483510: RTL: SS : USB3 reset event may
2688 * not be generated always when the link enters poll
2689 */
2690 if (dwc->revision < DWC3_REVISION_190A)
2691 dwc3_gadget_reset_interrupt(dwc);
2692
72246da4
FB		 2693 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2694 dwc->gadget.ep0->maxpacket = 512;
2695 dwc->gadget.speed = USB_SPEED_SUPER;
2696 break;
2da9ad76 2697 case DWC3_DSTS_HIGHSPEED:
72246da4
FB		 2698 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2699 dwc->gadget.ep0->maxpacket = 64;
2700 dwc->gadget.speed = USB_SPEED_HIGH;
2701 break;
9418ee15 2702 case DWC3_DSTS_FULLSPEED:
72246da4
FB		 2703 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2704 dwc->gadget.ep0->maxpacket = 64;
2705 dwc->gadget.speed = USB_SPEED_FULL;
2706 break;
2da9ad76 2707 case DWC3_DSTS_LOWSPEED:
72246da4
FB		 2708 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2709 dwc->gadget.ep0->maxpacket = 8;
2710 dwc->gadget.speed = USB_SPEED_LOW;
2711 break;
2712 }
2713
2b758350
PA		 2714 /* Enable USB2 LPM Capability */
2715
ee5cd41c 2716 if ((dwc->revision > DWC3_REVISION_194A) &&
2da9ad76
JY		 2717 (speed != DWC3_DSTS_SUPERSPEED) &&
2718 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2b758350
PA		 2719 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2720 reg |= DWC3_DCFG_LPM_CAP;
2721 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2722
2723 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2724 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2725
460d098c 2726 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2727
80caf7d2
HR		 2728 /*
2729 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2730 * DCFG.LPMCap is set, core responses with an ACK and the
2731 * BESL value in the LPM token is less than or equal to LPM
2732 * NYET threshold.
2733 */
2734 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2735 && dwc->has_lpm_erratum,
9165dabb 2736 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
80caf7d2
HR		 2737
2738 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2739 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2740
356363bf
FB		 2741 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2742 } else {
2743 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2744 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2745 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2746 }
2747
72246da4 2748 dep = dwc->eps[0];
39ebb05c 2749 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2750 if (ret) {
2751 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2752 return;
2753 }
2754
2755 dep = dwc->eps[1];
39ebb05c 2756 ret = __dwc3_gadget_ep_enable(dep, true, false);
72246da4
FB		 2757 if (ret) {
2758 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2759 return;
2760 }
2761
2762 /*
2763 * Configure PHY via GUSB3PIPECTLn if required.
2764 *
2765 * Update GTXFIFOSIZn
2766 *
2767 * In both cases reset values should be sufficient.
2768 */
2769}
2770
2771static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2772{
72246da4
FB		 2773 /*
2774 * TODO take core out of low power mode when that's
2775 * implemented.
2776 */
2777
ad14d4e0
JL		 2778 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2779 spin_unlock(&dwc->lock);
2780 dwc->gadget_driver->resume(&dwc->gadget);
2781 spin_lock(&dwc->lock);
2782 }
72246da4
FB		 2783}
2784
2785static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2786 unsigned int evtinfo)
2787{
fae2b904 2788 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2789 unsigned int pwropt;
2790
2791 /*
2792 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2793 * Hibernation mode enabled which would show up when device detects
2794 * host-initiated U3 exit.
2795 *
2796 * In that case, device will generate a Link State Change Interrupt
2797 * from U3 to RESUME which is only necessary if Hibernation is
2798 * configured in.
2799 *
2800 * There are no functional changes due to such spurious event and we
2801 * just need to ignore it.
2802 *
2803 * Refers to:
2804 *
2805 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2806 * operational mode
2807 */
2808 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2809 if ((dwc->revision < DWC3_REVISION_250A) &&
2810 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2811 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2812 (next == DWC3_LINK_STATE_RESUME)) {
0b0cc1cd
FB		 2813 return;
2814 }
2815 }
fae2b904
FB		 2816
2817 /*
2818 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2819 * on the link partner, the USB session might do multiple entry/exit
2820 * of low power states before a transfer takes place.
2821 *
2822 * Due to this problem, we might experience lower throughput. The
2823 * suggested workaround is to disable DCTL[12:9] bits if we're
2824 * transitioning from U1/U2 to U0 and enable those bits again
2825 * after a transfer completes and there are no pending transfers
2826 * on any of the enabled endpoints.
2827 *
2828 * This is the first half of that workaround.
2829 *
2830 * Refers to:
2831 *
2832 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2833 * core send LGO_Ux entering U0
2834 */
2835 if (dwc->revision < DWC3_REVISION_183A) {
2836 if (next == DWC3_LINK_STATE_U0) {
2837 u32 u1u2;
2838 u32 reg;
2839
2840 switch (dwc->link_state) {
2841 case DWC3_LINK_STATE_U1:
2842 case DWC3_LINK_STATE_U2:
2843 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2844 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2845 | DWC3_DCTL_ACCEPTU2ENA
2846 | DWC3_DCTL_INITU1ENA
2847 | DWC3_DCTL_ACCEPTU1ENA);
2848
2849 if (!dwc->u1u2)
2850 dwc->u1u2 = reg & u1u2;
2851
2852 reg &= ~u1u2;
2853
2854 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2855 break;
2856 default:
2857 /* do nothing */
2858 break;
2859 }
2860 }
2861 }
2862
bc5ba2e0
FB		 2863 switch (next) {
2864 case DWC3_LINK_STATE_U1:
2865 if (dwc->speed == USB_SPEED_SUPER)
2866 dwc3_suspend_gadget(dwc);
2867 break;
2868 case DWC3_LINK_STATE_U2:
2869 case DWC3_LINK_STATE_U3:
2870 dwc3_suspend_gadget(dwc);
2871 break;
2872 case DWC3_LINK_STATE_RESUME:
2873 dwc3_resume_gadget(dwc);
2874 break;
2875 default:
2876 /* do nothing */
2877 break;
2878 }
2879
e57ebc1d 2880 dwc->link_state = next;
72246da4
FB		 2881}
2882
72704f87
BW		 2883static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2884 unsigned int evtinfo)
2885{
2886 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2887
2888 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2889 dwc3_suspend_gadget(dwc);
2890
2891 dwc->link_state = next;
2892}
2893
e1dadd3b
FB		 2894static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2895 unsigned int evtinfo)
2896{
2897 unsigned int is_ss = evtinfo & BIT(4);
2898
2899 /**
2900 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2901 * have a known issue which can cause USB CV TD.9.23 to fail
2902 * randomly.
2903 *
2904 * Because of this issue, core could generate bogus hibernation
2905 * events which SW needs to ignore.
2906 *
2907 * Refers to:
2908 *
2909 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2910 * Device Fallback from SuperSpeed
2911 */
2912 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2913 return;
2914
2915 /* enter hibernation here */
2916}
2917
72246da4
FB		 2918static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2919 const struct dwc3_event_devt *event)
2920{
2921 switch (event->type) {
2922 case DWC3_DEVICE_EVENT_DISCONNECT:
2923 dwc3_gadget_disconnect_interrupt(dwc);
2924 break;
2925 case DWC3_DEVICE_EVENT_RESET:
2926 dwc3_gadget_reset_interrupt(dwc);
2927 break;
2928 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2929 dwc3_gadget_conndone_interrupt(dwc);
2930 break;
2931 case DWC3_DEVICE_EVENT_WAKEUP:
2932 dwc3_gadget_wakeup_interrupt(dwc);
2933 break;
e1dadd3b
FB		 2934 case DWC3_DEVICE_EVENT_HIBER_REQ:
2935 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2936 "unexpected hibernation event\n"))
2937 break;
2938
2939 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2940 break;
72246da4
FB		 2941 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2942 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2943 break;
2944 case DWC3_DEVICE_EVENT_EOPF:
72704f87 2945 /* It changed to be suspend event for version 2.30a and above */
5eb30ced 2946 if (dwc->revision >= DWC3_REVISION_230A) {
72704f87
BW		 2947 /*
2948 * Ignore suspend event until the gadget enters into
2949 * USB_STATE_CONFIGURED state.
2950 */
2951 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2952 dwc3_gadget_suspend_interrupt(dwc,
2953 event->event_info);
2954 }
72246da4
FB		 2955 break;
2956 case DWC3_DEVICE_EVENT_SOF:
72246da4 2957 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
72246da4 2958 case DWC3_DEVICE_EVENT_CMD_CMPL:
72246da4 2959 case DWC3_DEVICE_EVENT_OVERFLOW:
72246da4
FB		 2960 break;
2961 default:
e9f2aa87 2962 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2963 }
2964}
2965
2966static void dwc3_process_event_entry(struct dwc3 *dwc,
2967 const union dwc3_event *event)
2968{
43c96be1 2969 trace_dwc3_event(event->raw, dwc);
2c4cbe6e 2970
72246da4
FB		 2971 /* Endpoint IRQ, handle it and return early */
2972 if (event->type.is_devspec == 0) {
2973 /* depevt */
2974 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2975 }
2976
2977 switch (event->type.type) {
2978 case DWC3_EVENT_TYPE_DEV:
2979 dwc3_gadget_interrupt(dwc, &event->devt);
2980 break;
2981 /* REVISIT what to do with Carkit and I2C events ? */
2982 default:
2983 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2984 }
2985}
2986
dea520a4 2987static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2988{
dea520a4 2989 struct dwc3 *dwc = evt->dwc;
b15a762f 2990 irqreturn_t ret = IRQ_NONE;
f42f2447 2991 int left;
e8adfc30 2992 u32 reg;
b15a762f 2993
f42f2447 2994 left = evt->count;
b15a762f 2995
f42f2447
FB		 2996 if (!(evt->flags & DWC3_EVENT_PENDING))
2997 return IRQ_NONE;
b15a762f 2998
f42f2447
FB		 2999 while (left > 0) {
3000 union dwc3_event event;
b15a762f 3001
ebbb2d59 3002 event.raw = *(u32 *) (evt->cache + evt->lpos);
b15a762f 3003
f42f2447 3004 dwc3_process_event_entry(dwc, &event);
b15a762f 3005
f42f2447
FB		 3006 /*
3007 * FIXME we wrap around correctly to the next entry as
3008 * almost all entries are 4 bytes in size. There is one
3009 * entry which has 12 bytes which is a regular entry
3010 * followed by 8 bytes data. ATM I don't know how
3011 * things are organized if we get next to the a
3012 * boundary so I worry about that once we try to handle
3013 * that.
3014 */
caefe6c7 3015 evt->lpos = (evt->lpos + 4) % evt->length;
f42f2447 3016 left -= 4;
f42f2447 3017 }
b15a762f 3018
f42f2447
FB		 3019 evt->count = 0;
3020 evt->flags &= ~DWC3_EVENT_PENDING;
3021 ret = IRQ_HANDLED;
b15a762f 3022
f42f2447 3023 /* Unmask interrupt */
660e9bde 3024 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 3025 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 3026 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 3027
cf40b86b
JY		 3028 if (dwc->imod_interval) {
3029 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3030 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3031 }
3032
f42f2447
FB		 3033 return ret;
3034}
e8adfc30 3035
dea520a4 3036static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 3037{
dea520a4
FB		 3038 struct dwc3_event_buffer *evt = _evt;
3039 struct dwc3 *dwc = evt->dwc;
e5f68b4a 3040 unsigned long flags;
f42f2447 3041 irqreturn_t ret = IRQ_NONE;
f42f2447 3042
e5f68b4a 3043 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 3044 ret = dwc3_process_event_buf(evt);
e5f68b4a 3045 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 3046
3047 return ret;
3048}
3049
dea520a4 3050static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 3051{
dea520a4 3052 struct dwc3 *dwc = evt->dwc;
ebbb2d59 3053 u32 amount;
72246da4 3054 u32 count;
e8adfc30 3055 u32 reg;
72246da4 3056
fc8bb91b
FB		 3057 if (pm_runtime_suspended(dwc->dev)) {
3058 pm_runtime_get(dwc->dev);
3059 disable_irq_nosync(dwc->irq_gadget);
3060 dwc->pending_events = true;
3061 return IRQ_HANDLED;
3062 }
3063
660e9bde 3064 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 3065 count &= DWC3_GEVNTCOUNT_MASK;
3066 if (!count)
3067 return IRQ_NONE;
3068
b15a762f
FB		 3069 evt->count = count;
3070 evt->flags |= DWC3_EVENT_PENDING;
72246da4 3071
e8adfc30 3072 /* Mask interrupt */
660e9bde 3073 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 3074 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 3075 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 3076
ebbb2d59
JY		 3077 amount = min(count, evt->length - evt->lpos);
3078 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3079
3080 if (amount < count)
3081 memcpy(evt->cache, evt->buf, count - amount);
3082
65aca320
JY		 3083 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3084
b15a762f 3085 return IRQ_WAKE_THREAD;
72246da4
FB		 3086}
3087
dea520a4 3088static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 3089{
dea520a4 3090 struct dwc3_event_buffer *evt = _evt;
72246da4 3091
dea520a4 3092 return dwc3_check_event_buf(evt);
72246da4
FB		 3093}
3094
6db3812e
FB		 3095static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3096{
3097 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3098 int irq;
3099
3100 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3101 if (irq > 0)
3102 goto out;
3103
3104 if (irq == -EPROBE_DEFER)
3105 goto out;
3106
3107 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3108 if (irq > 0)
3109 goto out;
3110
3111 if (irq == -EPROBE_DEFER)
3112 goto out;
3113
3114 irq = platform_get_irq(dwc3_pdev, 0);
3115 if (irq > 0)
3116 goto out;
3117
3118 if (irq != -EPROBE_DEFER)
3119 dev_err(dwc->dev, "missing peripheral IRQ\n");
3120
3121 if (!irq)
3122 irq = -EINVAL;
3123
3124out:
3125 return irq;
3126}
3127
72246da4
FB		 3128/**
3129 * dwc3_gadget_init - Initializes gadget related registers
1d046793 3130 * @dwc: pointer to our controller context structure
72246da4
FB		 3131 *
3132 * Returns 0 on success otherwise negative errno.
3133 */
41ac7b3a 3134int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 3135{
6db3812e
FB		 3136 int ret;
3137 int irq;
9522def4 3138
6db3812e
FB		 3139 irq = dwc3_gadget_get_irq(dwc);
3140 if (irq < 0) {
3141 ret = irq;
3142 goto err0;
9522def4
RQ		 3143 }
3144
3145 dwc->irq_gadget = irq;
72246da4 3146
d64ff406
AB		 3147 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3148 sizeof(*dwc->ep0_trb) * 2,
3149 &dwc->ep0_trb_addr, GFP_KERNEL);
72246da4
FB		 3150 if (!dwc->ep0_trb) {
3151 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3152 ret = -ENOMEM;
7d5e650a 3153 goto err0;
72246da4
FB		 3154 }
3155
3ef35faf 3156 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 3157 if (!dwc->setup_buf) {
72246da4 3158 ret = -ENOMEM;
7d5e650a 3159 goto err1;
72246da4
FB		 3160 }
3161
d64ff406 3162 dwc->ep0_bounce = dma_alloc_coherent(dwc->sysdev,
3ef35faf
FB		 3163 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3164 GFP_KERNEL);
5812b1c2
FB		 3165 if (!dwc->ep0_bounce) {
3166 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3167 ret = -ENOMEM;
7d5e650a 3168 goto err2;
5812b1c2
FB		 3169 }
3170
04c03d10
FB		 3171 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3172 if (!dwc->zlp_buf) {
3173 ret = -ENOMEM;
7d5e650a 3174 goto err3;
04c03d10
FB		 3175 }
3176
905dc04e
FB		 3177 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3178 &dwc->bounce_addr, GFP_KERNEL);
3179 if (!dwc->bounce) {
3180 ret = -ENOMEM;
7d5e650a 3181 goto err4;
905dc04e
FB		 3182 }
3183
bb014736
BW		 3184 init_completion(&dwc->ep0_in_setup);
3185
72246da4 3186 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 3187 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 3188 dwc->gadget.sg_supported = true;
72246da4 3189 dwc->gadget.name = "dwc3-gadget";
6a4290cc 3190 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 3191
b9e51b2b
BM		 3192 /*
3193 * FIXME We might be setting max_speed to <SUPER, however versions
3194 * <2.20a of dwc3 have an issue with metastability (documented
3195 * elsewhere in this driver) which tells us we can't set max speed to
3196 * anything lower than SUPER.
3197 *
3198 * Because gadget.max_speed is only used by composite.c and function
3199 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3200 * to happen so we avoid sending SuperSpeed Capability descriptor
3201 * together with our BOS descriptor as that could confuse host into
3202 * thinking we can handle super speed.
3203 *
3204 * Note that, in fact, we won't even support GetBOS requests when speed
3205 * is less than super speed because we don't have means, yet, to tell
3206 * composite.c that we are USB 2.0 + LPM ECN.
3207 */
3208 if (dwc->revision < DWC3_REVISION_220A)
5eb30ced 3209 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
b9e51b2b
BM		 3210 dwc->revision);
3211
3212 dwc->gadget.max_speed = dwc->maximum_speed;
3213
72246da4
FB		 3214 /*
3215 * REVISIT: Here we should clear all pending IRQs to be
3216 * sure we're starting from a well known location.
3217 */
3218
f3bcfc7e 3219 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
72246da4 3220 if (ret)
7d5e650a 3221 goto err5;
72246da4 3222
72246da4
FB		 3223 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3224 if (ret) {
3225 dev_err(dwc->dev, "failed to register udc\n");
7d5e650a 3226 goto err5;
72246da4
FB		 3227 }
3228
3229 return 0;
7d5e650a 3230err5:
905dc04e
FB		 3231 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3232 dwc->bounce_addr);
72246da4 3233
7d5e650a 3234err4:
04c03d10
FB		 3235 kfree(dwc->zlp_buf);
3236
7d5e650a 3237err3:
e1f80467 3238 dwc3_gadget_free_endpoints(dwc);
d64ff406 3239 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3240 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3241
7d5e650a 3242err2:
0fc9a1be 3243 kfree(dwc->setup_buf);
72246da4 3244
7d5e650a 3245err1:
d64ff406 3246 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 3247 dwc->ep0_trb, dwc->ep0_trb_addr);
3248
72246da4
FB		 3249err0:
3250 return ret;
3251}
3252
7415f17c
FB		 3253/* -------------------------------------------------------------------------- */
3254
72246da4
FB		 3255void dwc3_gadget_exit(struct dwc3 *dwc)
3256{
72246da4 3257 usb_del_gadget_udc(&dwc->gadget);
72246da4 3258
72246da4
FB		 3259 dwc3_gadget_free_endpoints(dwc);
3260
905dc04e
FB		 3261 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3262 dwc->bounce_addr);
d64ff406 3263 dma_free_coherent(dwc->sysdev, DWC3_EP0_BOUNCE_SIZE,
3ef35faf 3264 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 3265
0fc9a1be 3266 kfree(dwc->setup_buf);
04c03d10 3267 kfree(dwc->zlp_buf);
72246da4 3268
d64ff406 3269 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
72246da4 3270 dwc->ep0_trb, dwc->ep0_trb_addr);
72246da4 3271}
7415f17c 3272
0b0231aa 3273int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 3274{
9772b47a
RQ		 3275 if (!dwc->gadget_driver)
3276 return 0;
3277
1551e35e 3278 dwc3_gadget_run_stop(dwc, false, false);
9f8a67b6
FB		 3279 dwc3_disconnect_gadget(dwc);
3280 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3281
3282 return 0;
3283}
3284
3285int dwc3_gadget_resume(struct dwc3 *dwc)
3286{
7415f17c
FB		 3287 int ret;
3288
9772b47a
RQ		 3289 if (!dwc->gadget_driver)
3290 return 0;
3291
9f8a67b6
FB		 3292 ret = __dwc3_gadget_start(dwc);
3293 if (ret < 0)
7415f17c
FB		 3294 goto err0;
3295
9f8a67b6
FB		 3296 ret = dwc3_gadget_run_stop(dwc, true, false);
3297 if (ret < 0)
7415f17c
FB		 3298 goto err1;
3299
7415f17c
FB		 3300 return 0;
3301
3302err1:
9f8a67b6 3303 __dwc3_gadget_stop(dwc);
7415f17c
FB		 3304
3305err0:
3306 return ret;
3307}
fc8bb91b
FB		 3308
3309void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3310{
3311 if (dwc->pending_events) {
3312 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3313 dwc->pending_events = false;
3314 enable_irq(dwc->irq_gadget);
3315 }
3316}
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