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ASoC: wm_asdp: Validate sanity of algorithm count
[linux.git] / sound / soc / codecs / wm_adsp.c
CommitLineData
2159ad93
MB		 1/*
2 * wm_adsp.c -- Wolfson ADSP support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <[email protected]>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/firmware.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
973838a0 21#include <linux/regulator/consumer.h>
2159ad93
MB		 22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include <linux/mfd/arizona/registers.h>
32
33#include "wm_adsp.h"
34
35#define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
37#define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
39#define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
41#define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
43#define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
45
46#define ADSP1_CONTROL_1 0x00
47#define ADSP1_CONTROL_2 0x02
48#define ADSP1_CONTROL_3 0x03
49#define ADSP1_CONTROL_4 0x04
50#define ADSP1_CONTROL_5 0x06
51#define ADSP1_CONTROL_6 0x07
52#define ADSP1_CONTROL_7 0x08
53#define ADSP1_CONTROL_8 0x09
54#define ADSP1_CONTROL_9 0x0A
55#define ADSP1_CONTROL_10 0x0B
56#define ADSP1_CONTROL_11 0x0C
57#define ADSP1_CONTROL_12 0x0D
58#define ADSP1_CONTROL_13 0x0F
59#define ADSP1_CONTROL_14 0x10
60#define ADSP1_CONTROL_15 0x11
61#define ADSP1_CONTROL_16 0x12
62#define ADSP1_CONTROL_17 0x13
63#define ADSP1_CONTROL_18 0x14
64#define ADSP1_CONTROL_19 0x16
65#define ADSP1_CONTROL_20 0x17
66#define ADSP1_CONTROL_21 0x18
67#define ADSP1_CONTROL_22 0x1A
68#define ADSP1_CONTROL_23 0x1B
69#define ADSP1_CONTROL_24 0x1C
70#define ADSP1_CONTROL_25 0x1E
71#define ADSP1_CONTROL_26 0x20
72#define ADSP1_CONTROL_27 0x21
73#define ADSP1_CONTROL_28 0x22
74#define ADSP1_CONTROL_29 0x23
75#define ADSP1_CONTROL_30 0x24
76#define ADSP1_CONTROL_31 0x26
77
78/*
79 * ADSP1 Control 19
80 */
81#define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
82#define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
83#define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
84
85
86/*
87 * ADSP1 Control 30
88 */
89#define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
90#define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
91#define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
92#define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
93#define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
94#define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
95#define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
96#define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
97#define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
98#define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
99#define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
100#define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
101#define ADSP1_START 0x0001 /* DSP1_START */
102#define ADSP1_START_MASK 0x0001 /* DSP1_START */
103#define ADSP1_START_SHIFT 0 /* DSP1_START */
104#define ADSP1_START_WIDTH 1 /* DSP1_START */
105
973838a0
MB		 106#define ADSP2_CONTROL 0
107#define ADSP2_CLOCKING 1
108#define ADSP2_STATUS1 4
2159ad93
MB		 109
110/*
111 * ADSP2 Control
112 */
113
114#define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
115#define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
116#define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
117#define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
118#define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
119#define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
120#define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
121#define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
122#define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
123#define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
124#define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
125#define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
126#define ADSP2_START 0x0001 /* DSP1_START */
127#define ADSP2_START_MASK 0x0001 /* DSP1_START */
128#define ADSP2_START_SHIFT 0 /* DSP1_START */
129#define ADSP2_START_WIDTH 1 /* DSP1_START */
130
973838a0
MB		 131/*
132 * ADSP2 clocking
133 */
134#define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
135#define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
136#define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
137
2159ad93
MB		 138/*
139 * ADSP2 Status 1
140 */
141#define ADSP2_RAM_RDY 0x0001
142#define ADSP2_RAM_RDY_MASK 0x0001
143#define ADSP2_RAM_RDY_SHIFT 0
144#define ADSP2_RAM_RDY_WIDTH 1
145
146
147static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
148 int type)
149{
150 int i;
151
152 for (i = 0; i < dsp->num_mems; i++)
153 if (dsp->mem[i].type == type)
154 return &dsp->mem[i];
155
156 return NULL;
157}
158
45b9ee72
MB		 159static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
160 unsigned int offset)
161{
162 switch (region->type) {
163 case WMFW_ADSP1_PM:
164 return region->base + (offset * 3);
165 case WMFW_ADSP1_DM:
166 return region->base + (offset * 2);
167 case WMFW_ADSP2_XM:
168 return region->base + (offset * 2);
169 case WMFW_ADSP2_YM:
170 return region->base + (offset * 2);
171 case WMFW_ADSP1_ZM:
172 return region->base + (offset * 2);
173 default:
174 WARN_ON(NULL != "Unknown memory region type");
175 return offset;
176 }
177}
178
2159ad93
MB		 179static int wm_adsp_load(struct wm_adsp *dsp)
180{
181 const struct firmware *firmware;
182 struct regmap *regmap = dsp->regmap;
183 unsigned int pos = 0;
184 const struct wmfw_header *header;
185 const struct wmfw_adsp1_sizes *adsp1_sizes;
186 const struct wmfw_adsp2_sizes *adsp2_sizes;
187 const struct wmfw_footer *footer;
188 const struct wmfw_region *region;
189 const struct wm_adsp_region *mem;
190 const char *region_name;
191 char *file, *text;
192 unsigned int reg;
193 int regions = 0;
194 int ret, offset, type, sizes;
195
196 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
197 if (file == NULL)
198 return -ENOMEM;
199
200 snprintf(file, PAGE_SIZE, "%s-dsp%d.wmfw", dsp->part, dsp->num);
201 file[PAGE_SIZE - 1] = '\0';
202
203 ret = request_firmware(&firmware, file, dsp->dev);
204 if (ret != 0) {
205 adsp_err(dsp, "Failed to request '%s'\n", file);
206 goto out;
207 }
208 ret = -EINVAL;
209
210 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
211 if (pos >= firmware->size) {
212 adsp_err(dsp, "%s: file too short, %zu bytes\n",
213 file, firmware->size);
214 goto out_fw;
215 }
216
217 header = (void*)&firmware->data[0];
218
219 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
220 adsp_err(dsp, "%s: invalid magic\n", file);
221 goto out_fw;
222 }
223
224 if (header->ver != 0) {
225 adsp_err(dsp, "%s: unknown file format %d\n",
226 file, header->ver);
227 goto out_fw;
228 }
229
230 if (header->core != dsp->type) {
231 adsp_err(dsp, "%s: invalid core %d != %d\n",
232 file, header->core, dsp->type);
233 goto out_fw;
234 }
235
236 switch (dsp->type) {
237 case WMFW_ADSP1:
238 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
239 adsp1_sizes = (void *)&(header[1]);
240 footer = (void *)&(adsp1_sizes[1]);
241 sizes = sizeof(*adsp1_sizes);
242
243 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
244 file, le32_to_cpu(adsp1_sizes->dm),
245 le32_to_cpu(adsp1_sizes->pm),
246 le32_to_cpu(adsp1_sizes->zm));
247 break;
248
249 case WMFW_ADSP2:
250 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
251 adsp2_sizes = (void *)&(header[1]);
252 footer = (void *)&(adsp2_sizes[1]);
253 sizes = sizeof(*adsp2_sizes);
254
255 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
256 file, le32_to_cpu(adsp2_sizes->xm),
257 le32_to_cpu(adsp2_sizes->ym),
258 le32_to_cpu(adsp2_sizes->pm),
259 le32_to_cpu(adsp2_sizes->zm));
260 break;
261
262 default:
263 BUG_ON(NULL == "Unknown DSP type");
264 goto out_fw;
265 }
266
267 if (le32_to_cpu(header->len) != sizeof(*header) +
268 sizes + sizeof(*footer)) {
269 adsp_err(dsp, "%s: unexpected header length %d\n",
270 file, le32_to_cpu(header->len));
271 goto out_fw;
272 }
273
274 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
275 le64_to_cpu(footer->timestamp));
276
277 while (pos < firmware->size &&
278 pos - firmware->size > sizeof(*region)) {
279 region = (void *)&(firmware->data[pos]);
280 region_name = "Unknown";
281 reg = 0;
282 text = NULL;
283 offset = le32_to_cpu(region->offset) & 0xffffff;
284 type = be32_to_cpu(region->type) & 0xff;
285 mem = wm_adsp_find_region(dsp, type);
286
287 switch (type) {
288 case WMFW_NAME_TEXT:
289 region_name = "Firmware name";
290 text = kzalloc(le32_to_cpu(region->len) + 1,
291 GFP_KERNEL);
292 break;
293 case WMFW_INFO_TEXT:
294 region_name = "Information";
295 text = kzalloc(le32_to_cpu(region->len) + 1,
296 GFP_KERNEL);
297 break;
298 case WMFW_ABSOLUTE:
299 region_name = "Absolute";
300 reg = offset;
301 break;
302 case WMFW_ADSP1_PM:
303 BUG_ON(!mem);
304 region_name = "PM";
45b9ee72 305 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 306 break;
307 case WMFW_ADSP1_DM:
308 BUG_ON(!mem);
309 region_name = "DM";
45b9ee72 310 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 311 break;
312 case WMFW_ADSP2_XM:
313 BUG_ON(!mem);
314 region_name = "XM";
45b9ee72 315 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 316 break;
317 case WMFW_ADSP2_YM:
318 BUG_ON(!mem);
319 region_name = "YM";
45b9ee72 320 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 321 break;
322 case WMFW_ADSP1_ZM:
323 BUG_ON(!mem);
324 region_name = "ZM";
45b9ee72 325 reg = wm_adsp_region_to_reg(mem, offset);
2159ad93
MB		 326 break;
327 default:
328 adsp_warn(dsp,
329 "%s.%d: Unknown region type %x at %d(%x)\n",
330 file, regions, type, pos, pos);
331 break;
332 }
333
334 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
335 regions, le32_to_cpu(region->len), offset,
336 region_name);
337
338 if (text) {
339 memcpy(text, region->data, le32_to_cpu(region->len));
340 adsp_info(dsp, "%s: %s\n", file, text);
341 kfree(text);
342 }
343
344 if (reg) {
345 ret = regmap_raw_write(regmap, reg, region->data,
346 le32_to_cpu(region->len));
347 if (ret != 0) {
348 adsp_err(dsp,
349 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
350 file, regions,
351 le32_to_cpu(region->len), offset,
352 region_name, ret);
353 goto out_fw;
354 }
355 }
356
357 pos += le32_to_cpu(region->len) + sizeof(*region);
358 regions++;
359 }
360
361 if (pos > firmware->size)
362 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
363 file, regions, pos - firmware->size);
364
365out_fw:
366 release_firmware(firmware);
367out:
368 kfree(file);
369
370 return ret;
371}
372
db40517c
MB		 373static int wm_adsp_setup_algs(struct wm_adsp *dsp)
374{
375 struct regmap *regmap = dsp->regmap;
376 struct wmfw_adsp1_id_hdr adsp1_id;
377 struct wmfw_adsp2_id_hdr adsp2_id;
378 struct wmfw_adsp1_alg_hdr *adsp1_alg;
379 struct wmfw_adsp2_alg_hdr *adsp2_alg;
d62f4bc6 380 void *alg, *buf;
db40517c
MB		 381 const struct wm_adsp_region *mem;
382 unsigned int pos, term;
d62f4bc6 383 size_t algs, buf_size;
db40517c
MB		 384 __be32 val;
385 int i, ret;
386
387 switch (dsp->type) {
388 case WMFW_ADSP1:
389 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
390 break;
391 case WMFW_ADSP2:
392 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
393 break;
394 default:
395 mem = NULL;
396 break;
397 }
398
399 if (mem == NULL) {
400 BUG_ON(mem != NULL);
401 return -EINVAL;
402 }
403
404 switch (dsp->type) {
405 case WMFW_ADSP1:
406 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
407 sizeof(adsp1_id));
408 if (ret != 0) {
409 adsp_err(dsp, "Failed to read algorithm info: %d\n",
410 ret);
411 return ret;
412 }
413
d62f4bc6
MB		 414 buf = &adsp1_id;
415 buf_size = sizeof(adsp1_id);
416
db40517c
MB		 417 algs = be32_to_cpu(adsp1_id.algs);
418 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
419 be32_to_cpu(adsp1_id.fw.id),
420 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
421 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
422 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
423 algs);
424
425 pos = sizeof(adsp1_id) / 2;
426 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
427 break;
428
429 case WMFW_ADSP2:
430 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
431 sizeof(adsp2_id));
432 if (ret != 0) {
433 adsp_err(dsp, "Failed to read algorithm info: %d\n",
434 ret);
435 return ret;
436 }
437
d62f4bc6
MB		 438 buf = &adsp2_id;
439 buf_size = sizeof(adsp2_id);
440
db40517c
MB		 441 algs = be32_to_cpu(adsp2_id.algs);
442 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
443 be32_to_cpu(adsp2_id.fw.id),
444 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
445 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
446 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
447 algs);
448
449 pos = sizeof(adsp2_id) / 2;
450 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
451 break;
452
453 default:
454 BUG_ON(NULL == "Unknown DSP type");
455 return -EINVAL;
456 }
457
458 if (algs == 0) {
459 adsp_err(dsp, "No algorithms\n");
460 return -EINVAL;
461 }
462
d62f4bc6
MB		 463 if (algs > 1024) {
464 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
465 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
466 buf, buf_size);
467 return -EINVAL;
468 }
469
db40517c
MB		 470 /* Read the terminator first to validate the length */
471 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
472 if (ret != 0) {
473 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
474 ret);
475 return ret;
476 }
477
478 if (be32_to_cpu(val) != 0xbedead)
479 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
480 term, be32_to_cpu(val));
481
482 alg = kzalloc((term - pos) * 2, GFP_KERNEL);
483 if (!alg)
484 return -ENOMEM;
485
486 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
487 if (ret != 0) {
488 adsp_err(dsp, "Failed to read algorithm list: %d\n",
489 ret);
490 goto out;
491 }
492
493 adsp1_alg = alg;
494 adsp2_alg = alg;
495
496 for (i = 0; i < algs; i++) {
497 switch (dsp->type) {
498 case WMFW_ADSP1:
499 adsp_info(dsp, "%d: ID %x v%d.%d.%d\n",
500 i, be32_to_cpu(adsp1_alg[i].alg.id),
501 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
502 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
503 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff);
504 break;
505
506 case WMFW_ADSP2:
507 adsp_info(dsp, "%d: ID %x v%d.%d.%d\n",
508 i, be32_to_cpu(adsp2_alg[i].alg.id),
509 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
510 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
511 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff);
512 break;
513 }
514 }
515
516out:
517 kfree(alg);
518 return ret;
519}
520
2159ad93
MB		 521static int wm_adsp_load_coeff(struct wm_adsp *dsp)
522{
523 struct regmap *regmap = dsp->regmap;
524 struct wmfw_coeff_hdr *hdr;
525 struct wmfw_coeff_item *blk;
526 const struct firmware *firmware;
527 const char *region_name;
528 int ret, pos, blocks, type, offset, reg;
529 char *file;
530
531 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
532 if (file == NULL)
533 return -ENOMEM;
534
535 snprintf(file, PAGE_SIZE, "%s-dsp%d.bin", dsp->part, dsp->num);
536 file[PAGE_SIZE - 1] = '\0';
537
538 ret = request_firmware(&firmware, file, dsp->dev);
539 if (ret != 0) {
540 adsp_warn(dsp, "Failed to request '%s'\n", file);
541 ret = 0;
542 goto out;
543 }
544 ret = -EINVAL;
545
546 if (sizeof(*hdr) >= firmware->size) {
547 adsp_err(dsp, "%s: file too short, %zu bytes\n",
548 file, firmware->size);
549 goto out_fw;
550 }
551
552 hdr = (void*)&firmware->data[0];
553 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
554 adsp_err(dsp, "%s: invalid magic\n", file);
555 return -EINVAL;
556 }
557
558 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
559 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
560 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
561 le32_to_cpu(hdr->ver) & 0xff);
562
563 pos = le32_to_cpu(hdr->len);
564
565 blocks = 0;
566 while (pos < firmware->size &&
567 pos - firmware->size > sizeof(*blk)) {
568 blk = (void*)(&firmware->data[pos]);
569
570 type = be32_to_cpu(blk->type) & 0xff;
571 offset = le32_to_cpu(blk->offset) & 0xffffff;
572
573 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
574 file, blocks, le32_to_cpu(blk->id),
575 (le32_to_cpu(blk->ver) >> 16) & 0xff,
576 (le32_to_cpu(blk->ver) >> 8) & 0xff,
577 le32_to_cpu(blk->ver) & 0xff);
578 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
579 file, blocks, le32_to_cpu(blk->len), offset, type);
580
581 reg = 0;
582 region_name = "Unknown";
583 switch (type) {
584 case WMFW_NAME_TEXT:
585 case WMFW_INFO_TEXT:
586 break;
587 case WMFW_ABSOLUTE:
588 region_name = "register";
589 reg = offset;
590 break;
591 default:
592 adsp_err(dsp, "Unknown region type %x\n", type);
593 break;
594 }
595
596 if (reg) {
597 ret = regmap_raw_write(regmap, reg, blk->data,
598 le32_to_cpu(blk->len));
599 if (ret != 0) {
600 adsp_err(dsp,
601 "%s.%d: Failed to write to %x in %s\n",
602 file, blocks, reg, region_name);
603 }
604 }
605
606 pos += le32_to_cpu(blk->len) + sizeof(*blk);
607 blocks++;
608 }
609
610 if (pos > firmware->size)
611 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
612 file, blocks, pos - firmware->size);
613
614out_fw:
615 release_firmware(firmware);
616out:
617 kfree(file);
618 return 0;
619}
620
621int wm_adsp1_event(struct snd_soc_dapm_widget *w,
622 struct snd_kcontrol *kcontrol,
623 int event)
624{
625 struct snd_soc_codec *codec = w->codec;
626 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
627 struct wm_adsp *dsp = &dsps[w->shift];
628 int ret;
629
630 switch (event) {
631 case SND_SOC_DAPM_POST_PMU:
632 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
633 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
634
635 ret = wm_adsp_load(dsp);
636 if (ret != 0)
637 goto err;
638
db40517c
MB		 639 ret = wm_adsp_setup_algs(dsp);
640 if (ret != 0)
641 goto err;
642
2159ad93
MB		 643 ret = wm_adsp_load_coeff(dsp);
644 if (ret != 0)
645 goto err;
646
647 /* Start the core running */
648 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
649 ADSP1_CORE_ENA | ADSP1_START,
650 ADSP1_CORE_ENA | ADSP1_START);
651 break;
652
653 case SND_SOC_DAPM_PRE_PMD:
654 /* Halt the core */
655 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
656 ADSP1_CORE_ENA | ADSP1_START, 0);
657
658 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
659 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
660
661 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
662 ADSP1_SYS_ENA, 0);
663 break;
664
665 default:
666 break;
667 }
668
669 return 0;
670
671err:
672 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
673 ADSP1_SYS_ENA, 0);
674 return ret;
675}
676EXPORT_SYMBOL_GPL(wm_adsp1_event);
677
678static int wm_adsp2_ena(struct wm_adsp *dsp)
679{
680 unsigned int val;
681 int ret, count;
682
683 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
684 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
685 if (ret != 0)
686 return ret;
687
688 /* Wait for the RAM to start, should be near instantaneous */
689 count = 0;
690 do {
691 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
692 &val);
693 if (ret != 0)
694 return ret;
695 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
696
697 if (!(val & ADSP2_RAM_RDY)) {
698 adsp_err(dsp, "Failed to start DSP RAM\n");
699 return -EBUSY;
700 }
701
702 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
703 adsp_info(dsp, "RAM ready after %d polls\n", count);
704
705 return 0;
706}
707
708int wm_adsp2_event(struct snd_soc_dapm_widget *w,
709 struct snd_kcontrol *kcontrol, int event)
710{
711 struct snd_soc_codec *codec = w->codec;
712 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
713 struct wm_adsp *dsp = &dsps[w->shift];
973838a0 714 unsigned int val;
2159ad93
MB		 715 int ret;
716
717 switch (event) {
718 case SND_SOC_DAPM_POST_PMU:
dd49e2c8
MB		 719 /*
720 * For simplicity set the DSP clock rate to be the
721 * SYSCLK rate rather than making it configurable.
722 */
723 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
724 if (ret != 0) {
725 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
726 ret);
727 return ret;
728 }
729 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
730 >> ARIZONA_SYSCLK_FREQ_SHIFT;
731
732 ret = regmap_update_bits(dsp->regmap,
733 dsp->base + ADSP2_CLOCKING,
734 ADSP2_CLK_SEL_MASK, val);
735 if (ret != 0) {
736 adsp_err(dsp, "Failed to set clock rate: %d\n",
737 ret);
738 return ret;
739 }
740
973838a0
MB		 741 if (dsp->dvfs) {
742 ret = regmap_read(dsp->regmap,
743 dsp->base + ADSP2_CLOCKING, &val);
744 if (ret != 0) {
745 dev_err(dsp->dev,
746 "Failed to read clocking: %d\n", ret);
747 return ret;
748 }
749
25c6fdb0 750 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
973838a0
MB		 751 ret = regulator_enable(dsp->dvfs);
752 if (ret != 0) {
753 dev_err(dsp->dev,
754 "Failed to enable supply: %d\n",
755 ret);
756 return ret;
757 }
758
759 ret = regulator_set_voltage(dsp->dvfs,
760 1800000,
761 1800000);
762 if (ret != 0) {
763 dev_err(dsp->dev,
764 "Failed to raise supply: %d\n",
765 ret);
766 return ret;
767 }
768 }
769 }
770
2159ad93
MB		 771 ret = wm_adsp2_ena(dsp);
772 if (ret != 0)
773 return ret;
774
775 ret = wm_adsp_load(dsp);
776 if (ret != 0)
777 goto err;
778
db40517c
MB		 779 ret = wm_adsp_setup_algs(dsp);
780 if (ret != 0)
781 goto err;
782
2159ad93
MB		 783 ret = wm_adsp_load_coeff(dsp);
784 if (ret != 0)
785 goto err;
786
787 ret = regmap_update_bits(dsp->regmap,
788 dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 789 ADSP2_CORE_ENA | ADSP2_START,
790 ADSP2_CORE_ENA | ADSP2_START);
2159ad93
MB		 791 if (ret != 0)
792 goto err;
793 break;
794
795 case SND_SOC_DAPM_PRE_PMD:
796 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e
MB		 797 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
798 ADSP2_START, 0);
973838a0
MB		 799
800 if (dsp->dvfs) {
801 ret = regulator_set_voltage(dsp->dvfs, 1200000,
802 1800000);
803 if (ret != 0)
804 dev_warn(dsp->dev,
805 "Failed to lower supply: %d\n",
806 ret);
807
808 ret = regulator_disable(dsp->dvfs);
809 if (ret != 0)
810 dev_err(dsp->dev,
811 "Failed to enable supply: %d\n",
812 ret);
813 }
2159ad93
MB		 814 break;
815
816 default:
817 break;
818 }
819
820 return 0;
821err:
822 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
a7f9be7e 823 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2159ad93
MB		 824 return ret;
825}
826EXPORT_SYMBOL_GPL(wm_adsp2_event);
973838a0
MB		 827
828int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
829{
830 int ret;
831
10a2b662
MB		 832 /*
833 * Disable the DSP memory by default when in reset for a small
834 * power saving.
835 */
836 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
837 ADSP2_MEM_ENA, 0);
838 if (ret != 0) {
839 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
840 return ret;
841 }
842
973838a0
MB		 843 if (dvfs) {
844 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
845 if (IS_ERR(adsp->dvfs)) {
846 ret = PTR_ERR(adsp->dvfs);
847 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
848 return ret;
849 }
850
851 ret = regulator_enable(adsp->dvfs);
852 if (ret != 0) {
853 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
854 ret);
855 return ret;
856 }
857
858 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
859 if (ret != 0) {
860 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
861 ret);
862 return ret;
863 }
864
865 ret = regulator_disable(adsp->dvfs);
866 if (ret != 0) {
867 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
868 ret);
869 return ret;
870 }
871 }
872
873 return 0;
874}
875EXPORT_SYMBOL_GPL(wm_adsp2_init);
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