[linux.git] / drivers / nvmem / stm32-romem.c

// SPDX-License-Identifier: GPL-2.0
/*
 * STM32 Factory-programmed memory read access driver
 *
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author: Fabrice Gasnier <[email protected]> for STMicroelectronics.
 */

#include <linux/arm-smccc.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/tee_drv.h>

#include "stm32-bsec-optee-ta.h"

/* BSEC secure service access from non-secure */
#define STM32_SMC_BSEC			0x82001003
#define STM32_SMC_READ_SHADOW		0x01
#define STM32_SMC_PROG_OTP		0x02
#define STM32_SMC_WRITE_SHADOW		0x03
#define STM32_SMC_READ_OTP		0x04

/* shadow registers offset */
#define STM32MP15_BSEC_DATA0		0x200

struct stm32_romem_cfg {
	int size;
	u8 lower;
	bool ta;
};

struct stm32_romem_priv {
	void __iomem *base;
	struct nvmem_config cfg;
	u8 lower;
	struct tee_context *ctx;
};

static int stm32_romem_read(void *context, unsigned int offset, void *buf,
			    size_t bytes)
{
	struct stm32_romem_priv *priv = context;
	u8 *buf8 = buf;
	int i;

	for (i = offset; i < offset + bytes; i++)
		*buf8++ = readb_relaxed(priv->base + i);

	return 0;
}

static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
{
#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
	struct arm_smccc_res res;

	arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
	if (res.a0)
		return -EIO;

	if (result)
		*result = (u32)res.a1;

	return 0;
#else
	return -ENXIO;
#endif
}

static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
			   size_t bytes)
{
	struct stm32_romem_priv *priv = context;
	struct device *dev = priv->cfg.dev;
	u32 roffset, rbytes, val;
	u8 *buf8 = buf, *val8 = (u8 *)&val;
	int i, j = 0, ret, skip_bytes, size;

	/* Round unaligned access to 32-bits */
	roffset = rounddown(offset, 4);
	skip_bytes = offset & 0x3;
	rbytes = roundup(bytes + skip_bytes, 4);

	if (roffset + rbytes > priv->cfg.size)
		return -EINVAL;

	for (i = roffset; (i < roffset + rbytes); i += 4) {
		u32 otp = i >> 2;

		if (otp < priv->lower) {
			/* read lower data from shadow registers */
			val = readl_relaxed(
				priv->base + STM32MP15_BSEC_DATA0 + i);
		} else {
			ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
					     &val);
			if (ret) {
				dev_err(dev, "Can't read data%d (%d)\n", otp,
					ret);
				return ret;
			}
		}
		/* skip first bytes in case of unaligned read */
		if (skip_bytes)
			size = min(bytes, (size_t)(4 - skip_bytes));
		else
			size = min(bytes, (size_t)4);
		memcpy(&buf8[j], &val8[skip_bytes], size);
		bytes -= size;
		j += size;
		skip_bytes = 0;
	}

	return 0;
}

static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
			    size_t bytes)
{
	struct stm32_romem_priv *priv = context;
	struct device *dev = priv->cfg.dev;
	u32 *buf32 = buf;
	int ret, i;

	/* Allow only writing complete 32-bits aligned words */
	if ((bytes % 4) || (offset % 4))
		return -EINVAL;

	for (i = offset; i < offset + bytes; i += 4) {
		ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
				     NULL);
		if (ret) {
			dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
			return ret;
		}
	}

	if (offset + bytes >= priv->lower * 4)
		dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");

	return 0;
}

static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,
			       size_t bytes)
{
	struct stm32_romem_priv *priv = context;

	return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
}

static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,
				size_t bytes)
{
	struct stm32_romem_priv *priv = context;

	return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
}

static bool stm32_bsec_smc_check(void)
{
	u32 val;
	int ret;

	/* check that the OP-TEE support the BSEC SMC (legacy mode) */
	ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);

	return !ret;
}

static bool optee_presence_check(void)
{
	struct device_node *np;
	bool tee_detected = false;

	/* check that the OP-TEE node is present and available. */
	np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
	if (np && of_device_is_available(np))
		tee_detected = true;
	of_node_put(np);

	return tee_detected;
}

static int stm32_romem_probe(struct platform_device *pdev)
{
	const struct stm32_romem_cfg *cfg;
	struct device *dev = &pdev->dev;
	struct stm32_romem_priv *priv;
	struct resource *res;
	int rc;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->cfg.name = "stm32-romem";
	priv->cfg.word_size = 1;
	priv->cfg.stride = 1;
	priv->cfg.dev = dev;
	priv->cfg.priv = priv;
	priv->cfg.owner = THIS_MODULE;
	priv->cfg.type = NVMEM_TYPE_OTP;
	priv->cfg.add_legacy_fixed_of_cells = true;

	priv->lower = 0;

	cfg = device_get_match_data(dev);
	if (!cfg) {
		priv->cfg.read_only = true;
		priv->cfg.size = resource_size(res);
		priv->cfg.reg_read = stm32_romem_read;
	} else {
		priv->cfg.size = cfg->size;
		priv->lower = cfg->lower;
		if (cfg->ta || optee_presence_check()) {
			rc = stm32_bsec_optee_ta_open(&priv->ctx);
			if (rc) {
				/* wait for OP-TEE client driver to be up and ready */
				if (rc == -EPROBE_DEFER)
					return -EPROBE_DEFER;
				/* BSEC PTA is required or SMC not supported */
				if (cfg->ta || !stm32_bsec_smc_check())
					return rc;
			}
		}
		if (priv->ctx) {
			rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
			if (rc) {
				dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
				return rc;
			}
			priv->cfg.reg_read = stm32_bsec_pta_read;
			priv->cfg.reg_write = stm32_bsec_pta_write;
		} else {
			priv->cfg.reg_read = stm32_bsec_read;
			priv->cfg.reg_write = stm32_bsec_write;
		}
	}

	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
}

/*
 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
 * => 96 x 32-bits data words
 * - Lower: 1K bits, 2:1 redundancy, incremental bit programming
 *   => 32 (x 32-bits) lower shadow registers = words 0 to 31
 * - Upper: 2K bits, ECC protection, word programming only
 *   => 64 (x 32-bits) = words 32 to 95
 */
static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
	.size = 384,
	.lower = 32,
	.ta = false,
};

static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
	.size = 384,
	.lower = 32,
	.ta = true,
};

static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
	{ .compatible = "st,stm32f4-otp", }, {
		.compatible = "st,stm32mp15-bsec",
		.data = (void *)&stm32mp15_bsec_cfg,
	}, {
		.compatible = "st,stm32mp13-bsec",
		.data = (void *)&stm32mp13_bsec_cfg,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, stm32_romem_of_match);

static struct platform_driver stm32_romem_driver = {
	.probe = stm32_romem_probe,
	.driver = {
		.name = "stm32-romem",
		.of_match_table = of_match_ptr(stm32_romem_of_match),
	},
};
module_platform_driver(stm32_romem_driver);

MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
MODULE_ALIAS("platform:nvmem-stm32-romem");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ded1b7fc FG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* STM32 Factory-programmed memory read access driver
	4	*
	5	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
	6	* Author: Fabrice Gasnier <[email protected]> for STMicroelectronics.
	7	*/
	8
7c1cd8fd	9	#include <linux/arm-smccc.h>
ded1b7fc FG	10	#include <linux/io.h>
	11	#include <linux/module.h>
	12	#include <linux/nvmem-provider.h>
0720219f RH	13	#include <linux/of.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/property.h>
6a0bc352 PD	16	#include <linux/tee_drv.h>
	17
	18	#include "stm32-bsec-optee-ta.h"
ded1b7fc	19
7c1cd8fd FG	20	/* BSEC secure service access from non-secure */
	21	#define STM32_SMC_BSEC 0x82001003
	22	#define STM32_SMC_READ_SHADOW 0x01
	23	#define STM32_SMC_PROG_OTP 0x02
	24	#define STM32_SMC_WRITE_SHADOW 0x03
	25	#define STM32_SMC_READ_OTP 0x04
	26
06aac0e1	27	/* shadow registers offset */
7c1cd8fd FG	28	#define STM32MP15_BSEC_DATA0 0x200
7c1cd8fd FG	29
7c1cd8fd FG	30	struct stm32_romem_cfg {
7c1cd8fd FG	31	int size;
fbfc4ca4	32	u8 lower;
6a0bc352	33	bool ta;
7c1cd8fd FG	34	};
7c1cd8fd FG	35
ded1b7fc FG	36	struct stm32_romem_priv {
	37	void __iomem *base;
	38	struct nvmem_config cfg;
fbfc4ca4	39	u8 lower;
6a0bc352	40	struct tee_context *ctx;
ded1b7fc FG	41	};
	42
	43	static int stm32_romem_read(void context, unsigned int offset, void buf,
	44	size_t bytes)
	45	{
	46	struct stm32_romem_priv *priv = context;
	47	u8 *buf8 = buf;
	48	int i;
	49
	50	for (i = offset; i < offset + bytes; i++)
	51	*buf8++ = readb_relaxed(priv->base + i);
	52
	53	return 0;
	54	}
	55
7c1cd8fd FG	56	static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
	57	{
	58	#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
	59	struct arm_smccc_res res;
	60
	61	arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
	62	if (res.a0)
	63	return -EIO;
	64
	65	if (result)
	66	*result = (u32)res.a1;
	67
	68	return 0;
	69	#else
	70	return -ENXIO;
	71	#endif
	72	}
	73
	74	static int stm32_bsec_read(void context, unsigned int offset, void buf,
	75	size_t bytes)
	76	{
	77	struct stm32_romem_priv *priv = context;
	78	struct device *dev = priv->cfg.dev;
	79	u32 roffset, rbytes, val;
	80	u8 buf8 = buf, val8 = (u8 *)&val;
	81	int i, j = 0, ret, skip_bytes, size;
	82
	83	/* Round unaligned access to 32-bits */
	84	roffset = rounddown(offset, 4);
	85	skip_bytes = offset & 0x3;
	86	rbytes = roundup(bytes + skip_bytes, 4);
	87
	88	if (roffset + rbytes > priv->cfg.size)
	89	return -EINVAL;
	90
	91	for (i = roffset; (i < roffset + rbytes); i += 4) {
	92	u32 otp = i >> 2;
	93
fbfc4ca4	94	if (otp < priv->lower) {
7c1cd8fd FG	95	/* read lower data from shadow registers */
	96	val = readl_relaxed(
	97	priv->base + STM32MP15_BSEC_DATA0 + i);
	98	} else {
	99	ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
	100	&val);
	101	if (ret) {
	102	dev_err(dev, "Can't read data%d (%d)\n", otp,
	103	ret);
	104	return ret;
	105	}
	106	}
	107	/* skip first bytes in case of unaligned read */
	108	if (skip_bytes)
	109	size = min(bytes, (size_t)(4 - skip_bytes));
	110	else
	111	size = min(bytes, (size_t)4);
	112	memcpy(&buf8[j], &val8[skip_bytes], size);
	113	bytes -= size;
	114	j += size;
	115	skip_bytes = 0;
	116	}
	117
	118	return 0;
	119	}
	120
	121	static int stm32_bsec_write(void context, unsigned int offset, void buf,
	122	size_t bytes)
	123	{
	124	struct stm32_romem_priv *priv = context;
	125	struct device *dev = priv->cfg.dev;
	126	u32 *buf32 = buf;
	127	int ret, i;
	128
	129	/* Allow only writing complete 32-bits aligned words */
	130	if ((bytes % 4) \|\| (offset % 4))
	131	return -EINVAL;
	132
	133	for (i = offset; i < offset + bytes; i += 4) {
	134	ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
	135	NULL);
	136	if (ret) {
	137	dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
	138	return ret;
	139	}
	140	}
	141
d61784e6 PD	142	if (offset + bytes >= priv->lower * 4)
	143	dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");
	144
7c1cd8fd FG	145	return 0;
	146	}
	147
6a0bc352 PD	148	static int stm32_bsec_pta_read(void context, unsigned int offset, void buf,
	149	size_t bytes)
	150	{
	151	struct stm32_romem_priv *priv = context;
	152
	153	return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);
	154	}
	155
	156	static int stm32_bsec_pta_write(void context, unsigned int offset, void buf,
	157	size_t bytes)
	158	{
	159	struct stm32_romem_priv *priv = context;
	160
	161	return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);
	162	}
	163
df2f34ef PD	164	static bool stm32_bsec_smc_check(void)
	165	{
	166	u32 val;
	167	int ret;
	168
	169	/* check that the OP-TEE support the BSEC SMC (legacy mode) */
	170	ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);
	171
	172	return !ret;
	173	}
	174
	175	static bool optee_presence_check(void)
	176	{
	177	struct device_node *np;
	178	bool tee_detected = false;
	179
	180	/* check that the OP-TEE node is present and available. */
	181	np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
	182	if (np && of_device_is_available(np))
	183	tee_detected = true;
	184	of_node_put(np);
	185
	186	return tee_detected;
	187	}
	188
ded1b7fc FG	189	static int stm32_romem_probe(struct platform_device *pdev)
ded1b7fc FG	190	{
7c1cd8fd	191	const struct stm32_romem_cfg *cfg;
ded1b7fc FG	192	struct device *dev = &pdev->dev;
	193	struct stm32_romem_priv *priv;
	194	struct resource *res;
6a0bc352	195	int rc;
ded1b7fc FG	196
	197	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	198	if (!priv)
	199	return -ENOMEM;
	200
0a4a8c0d	201	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
ded1b7fc FG	202	if (IS_ERR(priv->base))
	203	return PTR_ERR(priv->base);
	204
	205	priv->cfg.name = "stm32-romem";
ded1b7fc FG	206	priv->cfg.word_size = 1;
ded1b7fc FG	207	priv->cfg.stride = 1;
ded1b7fc FG	208	priv->cfg.dev = dev;
	209	priv->cfg.priv = priv;
	210	priv->cfg.owner = THIS_MODULE;
a3816a7d	211	priv->cfg.type = NVMEM_TYPE_OTP;
2cc3b37f	212	priv->cfg.add_legacy_fixed_of_cells = true;
ded1b7fc	213
fbfc4ca4 PD	214	priv->lower = 0;
fbfc4ca4 PD	215
0720219f	216	cfg = device_get_match_data(dev);
7c1cd8fd FG	217	if (!cfg) {
	218	priv->cfg.read_only = true;
	219	priv->cfg.size = resource_size(res);
	220	priv->cfg.reg_read = stm32_romem_read;
	221	} else {
	222	priv->cfg.size = cfg->size;
fbfc4ca4	223	priv->lower = cfg->lower;
df2f34ef	224	if (cfg->ta \|\| optee_presence_check()) {
6a0bc352	225	rc = stm32_bsec_optee_ta_open(&priv->ctx);
df2f34ef PD	226	if (rc) {
	227	/* wait for OP-TEE client driver to be up and ready */
	228	if (rc == -EPROBE_DEFER)
	229	return -EPROBE_DEFER;
	230	/* BSEC PTA is required or SMC not supported */
	231	if (cfg->ta \|\| !stm32_bsec_smc_check())
	232	return rc;
	233	}
6a0bc352 PD	234	}
	235	if (priv->ctx) {
	236	rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);
	237	if (rc) {
	238	dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);
	239	return rc;
	240	}
	241	priv->cfg.reg_read = stm32_bsec_pta_read;
	242	priv->cfg.reg_write = stm32_bsec_pta_write;
	243	} else {
	244	priv->cfg.reg_read = stm32_bsec_read;
	245	priv->cfg.reg_write = stm32_bsec_write;
	246	}
7c1cd8fd FG	247	}
7c1cd8fd FG	248
ded1b7fc FG	249	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
	250	}
	251
fbfc4ca4	252	/*
6a0bc352	253	* STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)
fbfc4ca4 PD	254	* => 96 x 32-bits data words
	255	* - Lower: 1K bits, 2:1 redundancy, incremental bit programming
	256	* => 32 (x 32-bits) lower shadow registers = words 0 to 31
	257	* - Upper: 2K bits, ECC protection, word programming only
	258	* => 64 (x 32-bits) = words 32 to 95
	259	*/
7c1cd8fd	260	static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
fbfc4ca4 PD	261	.size = 384,
fbfc4ca4 PD	262	.lower = 32,
6a0bc352 PD	263	.ta = false,
	264	};
	265
	266	static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {
	267	.size = 384,
	268	.lower = 32,
	269	.ta = true,
7c1cd8fd FG	270	};
7c1cd8fd FG	271
a4fb434e	272	static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
7c1cd8fd FG	273	{ .compatible = "st,stm32f4-otp", }, {
	274	.compatible = "st,stm32mp15-bsec",
	275	.data = (void *)&stm32mp15_bsec_cfg,
	276	}, {
6a0bc352 PD	277	.compatible = "st,stm32mp13-bsec",
6a0bc352 PD	278	.data = (void *)&stm32mp13_bsec_cfg,
7c1cd8fd	279	},
6a0bc352	280	{ /* sentinel */ },
ded1b7fc FG	281	};
	282	MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
	283
	284	static struct platform_driver stm32_romem_driver = {
	285	.probe = stm32_romem_probe,
	286	.driver = {
	287	.name = "stm32-romem",
	288	.of_match_table = of_match_ptr(stm32_romem_of_match),
	289	},
	290	};
	291	module_platform_driver(stm32_romem_driver);
	292
	293	MODULE_AUTHOR("Fabrice Gasnier <[email protected]>");
	294	MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
	295	MODULE_ALIAS("platform:nvmem-stm32-romem");
	296	MODULE_LICENSE("GPL v2");