[linux.git] / drivers / irqchip / irq-tegra.c

/*
 * Driver code for Tegra's Legacy Interrupt Controller
 *
 * Author: Marc Zyngier <[email protected]>
 *
 * Heavily based on the original arch/arm/mach-tegra/irq.c code:
 * Copyright (C) 2011 Google, Inc.
 *
 * Author:
 *	Colin Cross <[email protected]>
 *
 * Copyright (C) 2010,2013, NVIDIA Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/syscore_ops.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define ICTLR_CPU_IEP_VFIQ	0x08
#define ICTLR_CPU_IEP_FIR	0x14
#define ICTLR_CPU_IEP_FIR_SET	0x18
#define ICTLR_CPU_IEP_FIR_CLR	0x1c

#define ICTLR_CPU_IER		0x20
#define ICTLR_CPU_IER_SET	0x24
#define ICTLR_CPU_IER_CLR	0x28
#define ICTLR_CPU_IEP_CLASS	0x2C

#define ICTLR_COP_IER		0x30
#define ICTLR_COP_IER_SET	0x34
#define ICTLR_COP_IER_CLR	0x38
#define ICTLR_COP_IEP_CLASS	0x3c

#define TEGRA_MAX_NUM_ICTLRS	6

static unsigned int num_ictlrs;

struct tegra_ictlr_soc {
	unsigned int num_ictlrs;
};

static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
	.num_ictlrs = 4,
};

static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
	.num_ictlrs = 5,
};

static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
	.num_ictlrs = 6,
};

static const struct of_device_id ictlr_matches[] = {
	{ .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
	{ .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
	{ .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
	{ }
};

struct tegra_ictlr_info {
	void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
#ifdef CONFIG_PM_SLEEP
	u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
	u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
	u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
	u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];

	u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
#endif
};

static struct tegra_ictlr_info *lic;

static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
{
	void __iomem *base = (void __iomem __force *)d->chip_data;
	u32 mask;

	mask = BIT(d->hwirq % 32);
	writel_relaxed(mask, base + reg);
}

static void tegra_mask(struct irq_data *d)
{
	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
	irq_chip_mask_parent(d);
}

static void tegra_unmask(struct irq_data *d)
{
	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
	irq_chip_unmask_parent(d);
}

static void tegra_eoi(struct irq_data *d)
{
	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
	irq_chip_eoi_parent(d);
}

static int tegra_retrigger(struct irq_data *d)
{
	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
	return irq_chip_retrigger_hierarchy(d);
}

#ifdef CONFIG_PM_SLEEP
static int tegra_set_wake(struct irq_data *d, unsigned int enable)
{
	u32 irq = d->hwirq;
	u32 index, mask;

	index = (irq / 32);
	mask = BIT(irq % 32);
	if (enable)
		lic->ictlr_wake_mask[index] |= mask;
	else
		lic->ictlr_wake_mask[index] &= ~mask;

	/*
	 * Do *not* call into the parent, as the GIC doesn't have any
	 * wake-up facility...
	 */
	return 0;
}

static int tegra_ictlr_suspend(void)
{
	unsigned long flags;
	unsigned int i;

	local_irq_save(flags);
	for (i = 0; i < num_ictlrs; i++) {
		void __iomem *ictlr = lic->base[i];

		/* Save interrupt state */
		lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
		lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
		lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
		lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);

		/* Disable COP interrupts */
		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);

		/* Disable CPU interrupts */
		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);

		/* Enable the wakeup sources of ictlr */
		writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
	}
	local_irq_restore(flags);

	return 0;
}

static void tegra_ictlr_resume(void)
{
	unsigned long flags;
	unsigned int i;

	local_irq_save(flags);
	for (i = 0; i < num_ictlrs; i++) {
		void __iomem *ictlr = lic->base[i];

		writel_relaxed(lic->cpu_iep[i],
			       ictlr + ICTLR_CPU_IEP_CLASS);
		writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
		writel_relaxed(lic->cpu_ier[i],
			       ictlr + ICTLR_CPU_IER_SET);
		writel_relaxed(lic->cop_iep[i],
			       ictlr + ICTLR_COP_IEP_CLASS);
		writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
		writel_relaxed(lic->cop_ier[i],
			       ictlr + ICTLR_COP_IER_SET);
	}
	local_irq_restore(flags);
}

static struct syscore_ops tegra_ictlr_syscore_ops = {
	.suspend	= tegra_ictlr_suspend,
	.resume		= tegra_ictlr_resume,
};

static void tegra_ictlr_syscore_init(void)
{
	register_syscore_ops(&tegra_ictlr_syscore_ops);
}
#else
#define tegra_set_wake	NULL
static inline void tegra_ictlr_syscore_init(void) {}
#endif

static struct irq_chip tegra_ictlr_chip = {
	.name			= "LIC",
	.irq_eoi		= tegra_eoi,
	.irq_mask		= tegra_mask,
	.irq_unmask		= tegra_unmask,
	.irq_retrigger		= tegra_retrigger,
	.irq_set_wake		= tegra_set_wake,
	.irq_set_type		= irq_chip_set_type_parent,
	.flags			= IRQCHIP_MASK_ON_SUSPEND,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int tegra_ictlr_domain_translate(struct irq_domain *d,
					struct irq_fwspec *fwspec,
					unsigned long *hwirq,
					unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
		return 0;
	}

	return -EINVAL;
}

static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
				    unsigned int virq,
				    unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	struct tegra_ictlr_info *info = domain->host_data;
	irq_hw_number_t hwirq;
	unsigned int i;

	if (fwspec->param_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (fwspec->param[0] != GIC_SPI)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = fwspec->param[1];
	if (hwirq >= (num_ictlrs * 32))
		return -EINVAL;

	for (i = 0; i < nr_irqs; i++) {
		int ictlr = (hwirq + i) / 32;

		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &tegra_ictlr_chip,
					      (void __force *)info->base[ictlr]);
	}

	parent_fwspec = *fwspec;
	parent_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops tegra_ictlr_domain_ops = {
	.translate	= tegra_ictlr_domain_translate,
	.alloc		= tegra_ictlr_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int __init tegra_ictlr_init(struct device_node *node,
				   struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	const struct of_device_id *match;
	const struct tegra_ictlr_soc *soc;
	unsigned int i;
	int err;

	if (!parent) {
		pr_err("%s: no parent, giving up\n", node->full_name);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%s: unable to obtain parent domain\n", node->full_name);
		return -ENXIO;
	}

	match = of_match_node(ictlr_matches, node);
	if (!match)		/* Should never happen... */
		return -ENODEV;

	soc = match->data;

	lic = kzalloc(sizeof(*lic), GFP_KERNEL);
	if (!lic)
		return -ENOMEM;

	for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
		void __iomem *base;

		base = of_iomap(node, i);
		if (!base)
			break;

		lic->base[i] = base;

		/* Disable all interrupts */
		writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
		/* All interrupts target IRQ */
		writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);

		num_ictlrs++;
	}

	if (!num_ictlrs) {
		pr_err("%s: no valid regions, giving up\n", node->full_name);
		err = -ENOMEM;
		goto out_free;
	}

	WARN(num_ictlrs != soc->num_ictlrs,
	     "%s: Found %u interrupt controllers in DT; expected %u.\n",
	     node->full_name, num_ictlrs, soc->num_ictlrs);


	domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
					  node, &tegra_ictlr_domain_ops,
					  lic);
	if (!domain) {
		pr_err("%s: failed to allocated domain\n", node->full_name);
		err = -ENOMEM;
		goto out_unmap;
	}

	tegra_ictlr_syscore_init();

	pr_info("%s: %d interrupts forwarded to %s\n",
		node->full_name, num_ictlrs * 32, parent->full_name);

	return 0;

out_unmap:
	for (i = 0; i < num_ictlrs; i++)
		iounmap(lic->base[i]);
out_free:
	kfree(lic);
	return err;
}

IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);
Commit	Line	Data
de3ce080 MZ	1	/*
	2	* Driver code for Tegra's Legacy Interrupt Controller
	3	*
	4	* Author: Marc Zyngier <[email protected]>
	5	*
	6	* Heavily based on the original arch/arm/mach-tegra/irq.c code:
	7	* Copyright (C) 2011 Google, Inc.
	8	*
	9	* Author:
	10	* Colin Cross <[email protected]>
	11	*
	12	* Copyright (C) 2010,2013, NVIDIA Corporation
	13	*
	14	* This software is licensed under the terms of the GNU General Public
	15	* License version 2, as published by the Free Software Foundation, and
	16	* may be copied, distributed, and modified under those terms.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	*/
	24
	25	#include <linux/io.h>
	26	#include <linux/irq.h>
41a83e06	27	#include <linux/irqchip.h>
de3ce080 MZ	28	#include <linux/irqdomain.h>
	29	#include <linux/of_address.h>
	30	#include <linux/slab.h>
	31	#include <linux/syscore_ops.h>
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
de3ce080 MZ	35	#define ICTLR_CPU_IEP_VFIQ 0x08
	36	#define ICTLR_CPU_IEP_FIR 0x14
	37	#define ICTLR_CPU_IEP_FIR_SET 0x18
	38	#define ICTLR_CPU_IEP_FIR_CLR 0x1c
	39
	40	#define ICTLR_CPU_IER 0x20
	41	#define ICTLR_CPU_IER_SET 0x24
	42	#define ICTLR_CPU_IER_CLR 0x28
	43	#define ICTLR_CPU_IEP_CLASS 0x2C
	44
	45	#define ICTLR_COP_IER 0x30
	46	#define ICTLR_COP_IER_SET 0x34
	47	#define ICTLR_COP_IER_CLR 0x38
	48	#define ICTLR_COP_IEP_CLASS 0x3c
	49
1eec5821	50	#define TEGRA_MAX_NUM_ICTLRS 6
de3ce080 MZ	51
	52	static unsigned int num_ictlrs;
	53
	54	struct tegra_ictlr_soc {
	55	unsigned int num_ictlrs;
	56	};
	57
	58	static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
	59	.num_ictlrs = 4,
	60	};
	61
	62	static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
	63	.num_ictlrs = 5,
	64	};
	65
1eec5821 TR	66	static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
	67	.num_ictlrs = 6,
	68	};
	69
de3ce080	70	static const struct of_device_id ictlr_matches[] = {
1eec5821	71	{ .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
de3ce080 MZ	72	{ .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
	73	{ .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
	74	{ }
	75	};
	76
	77	struct tegra_ictlr_info {
	78	void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
	79	#ifdef CONFIG_PM_SLEEP
	80	u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
	81	u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
	82	u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
	83	u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
	84
	85	u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
	86	#endif
	87	};
	88
	89	static struct tegra_ictlr_info *lic;
	90
	91	static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
	92	{
f6fbaaa4	93	void __iomem base = (void __iomem __force )d->chip_data;
de3ce080 MZ	94	u32 mask;
	95
	96	mask = BIT(d->hwirq % 32);
	97	writel_relaxed(mask, base + reg);
	98	}
	99
	100	static void tegra_mask(struct irq_data *d)
	101	{
	102	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
	103	irq_chip_mask_parent(d);
	104	}
	105
	106	static void tegra_unmask(struct irq_data *d)
	107	{
	108	tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
	109	irq_chip_unmask_parent(d);
	110	}
	111
	112	static void tegra_eoi(struct irq_data *d)
	113	{
	114	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
	115	irq_chip_eoi_parent(d);
	116	}
	117
	118	static int tegra_retrigger(struct irq_data *d)
	119	{
	120	tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
	121	return irq_chip_retrigger_hierarchy(d);
	122	}
	123
	124	#ifdef CONFIG_PM_SLEEP
	125	static int tegra_set_wake(struct irq_data *d, unsigned int enable)
	126	{
	127	u32 irq = d->hwirq;
	128	u32 index, mask;
	129
	130	index = (irq / 32);
	131	mask = BIT(irq % 32);
	132	if (enable)
	133	lic->ictlr_wake_mask[index] \|= mask;
	134	else
	135	lic->ictlr_wake_mask[index] &= ~mask;
	136
	137	/*
	138	* Do not call into the parent, as the GIC doesn't have any
	139	* wake-up facility...
	140	*/
	141	return 0;
	142	}
	143
	144	static int tegra_ictlr_suspend(void)
	145	{
	146	unsigned long flags;
	147	unsigned int i;
	148
	149	local_irq_save(flags);
	150	for (i = 0; i < num_ictlrs; i++) {
	151	void __iomem *ictlr = lic->base[i];
	152
	153	/* Save interrupt state */
	154	lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
	155	lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
	156	lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
	157	lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
158
159	/* Disable COP interrupts */
160	writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
161
162	/* Disable CPU interrupts */
163	writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
164
165	/* Enable the wakeup sources of ictlr */
166	writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
167	}
168	local_irq_restore(flags);
169
170	return 0;
171	}
172
173	static void tegra_ictlr_resume(void)
174	{
175	unsigned long flags;
176	unsigned int i;
177
178	local_irq_save(flags);
179	for (i = 0; i < num_ictlrs; i++) {
180	void __iomem *ictlr = lic->base[i];
181
182	writel_relaxed(lic->cpu_iep[i],
183	ictlr + ICTLR_CPU_IEP_CLASS);
184	writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
185	writel_relaxed(lic->cpu_ier[i],
186	ictlr + ICTLR_CPU_IER_SET);
187	writel_relaxed(lic->cop_iep[i],
188	ictlr + ICTLR_COP_IEP_CLASS);
189	writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
190	writel_relaxed(lic->cop_ier[i],
191	ictlr + ICTLR_COP_IER_SET);
192	}
193	local_irq_restore(flags);
194	}
195
196	static struct syscore_ops tegra_ictlr_syscore_ops = {
197	.suspend = tegra_ictlr_suspend,
198	.resume = tegra_ictlr_resume,
199	};
200
201	static void tegra_ictlr_syscore_init(void)
202	{
203	register_syscore_ops(&tegra_ictlr_syscore_ops);
204	}
205	#else
206	#define tegra_set_wake NULL
207	static inline void tegra_ictlr_syscore_init(void) {}
208	#endif
209
210	static struct irq_chip tegra_ictlr_chip = {
211	.name = "LIC",
212	.irq_eoi = tegra_eoi,
213	.irq_mask = tegra_mask,
214	.irq_unmask = tegra_unmask,
215	.irq_retrigger = tegra_retrigger,
216	.irq_set_wake = tegra_set_wake,
209da391	217	.irq_set_type = irq_chip_set_type_parent,
de3ce080 MZ	218	.flags = IRQCHIP_MASK_ON_SUSPEND,
	219	#ifdef CONFIG_SMP
	220	.irq_set_affinity = irq_chip_set_affinity_parent,
	221	#endif
	222	};
	223
f833f57f MZ	224	static int tegra_ictlr_domain_translate(struct irq_domain *d,
	225	struct irq_fwspec *fwspec,
	226	unsigned long *hwirq,
	227	unsigned int *type)
de3ce080	228	{
f833f57f MZ	229	if (is_of_node(fwspec->fwnode)) {
	230	if (fwspec->param_count != 3)
	231	return -EINVAL;
de3ce080	232
f833f57f MZ	233	/* No PPI should point to this domain */
	234	if (fwspec->param[0] != 0)
	235	return -EINVAL;
	236
	237	*hwirq = fwspec->param[1];
a2a8fa55	238	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
f833f57f MZ	239	return 0;
	240	}
	241
	242	return -EINVAL;
de3ce080 MZ	243	}
	244
	245	static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
	246	unsigned int virq,
	247	unsigned int nr_irqs, void *data)
	248	{
f833f57f MZ	249	struct irq_fwspec *fwspec = data;
f833f57f MZ	250	struct irq_fwspec parent_fwspec;
de3ce080 MZ	251	struct tegra_ictlr_info *info = domain->host_data;
	252	irq_hw_number_t hwirq;
	253	unsigned int i;
	254
f833f57f	255	if (fwspec->param_count != 3)
de3ce080	256	return -EINVAL; /* Not GIC compliant */
f833f57f	257	if (fwspec->param[0] != GIC_SPI)
de3ce080 MZ	258	return -EINVAL; /* No PPI should point to this domain */
de3ce080 MZ	259
f833f57f	260	hwirq = fwspec->param[1];
de3ce080 MZ	261	if (hwirq >= (num_ictlrs * 32))
	262	return -EINVAL;
	263
	264	for (i = 0; i < nr_irqs; i++) {
	265	int ictlr = (hwirq + i) / 32;
	266
	267	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	268	&tegra_ictlr_chip,
f6fbaaa4	269	(void __force *)info->base[ictlr]);
de3ce080 MZ	270	}
de3ce080 MZ	271
f833f57f MZ	272	parent_fwspec = *fwspec;
	273	parent_fwspec.fwnode = domain->parent->fwnode;
	274	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
	275	&parent_fwspec);
de3ce080 MZ	276	}
de3ce080 MZ	277
de3ce080	278	static const struct irq_domain_ops tegra_ictlr_domain_ops = {
f833f57f MZ	279	.translate = tegra_ictlr_domain_translate,
f833f57f MZ	280	.alloc = tegra_ictlr_domain_alloc,
46f920d8	281	.free = irq_domain_free_irqs_common,
de3ce080 MZ	282	};
	283
	284	static int __init tegra_ictlr_init(struct device_node *node,
	285	struct device_node *parent)
	286	{
	287	struct irq_domain parent_domain, domain;
	288	const struct of_device_id *match;
	289	const struct tegra_ictlr_soc *soc;
	290	unsigned int i;
	291	int err;
	292
	293	if (!parent) {
	294	pr_err("%s: no parent, giving up\n", node->full_name);
	295	return -ENODEV;
	296	}
	297
	298	parent_domain = irq_find_host(parent);
	299	if (!parent_domain) {
	300	pr_err("%s: unable to obtain parent domain\n", node->full_name);
	301	return -ENXIO;
	302	}
	303
	304	match = of_match_node(ictlr_matches, node);
	305	if (!match) /* Should never happen... */
	306	return -ENODEV;
	307
	308	soc = match->data;
	309
	310	lic = kzalloc(sizeof(*lic), GFP_KERNEL);
	311	if (!lic)
	312	return -ENOMEM;
	313
	314	for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
	315	void __iomem *base;
	316
	317	base = of_iomap(node, i);
	318	if (!base)
	319	break;
	320
	321	lic->base[i] = base;
	322
	323	/* Disable all interrupts */
	324	writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
	325	/* All interrupts target IRQ */
	326	writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
	327
	328	num_ictlrs++;
	329	}
	330
	331	if (!num_ictlrs) {
	332	pr_err("%s: no valid regions, giving up\n", node->full_name);
	333	err = -ENOMEM;
	334	goto out_free;
	335	}
	336
	337	WARN(num_ictlrs != soc->num_ictlrs,
	338	"%s: Found %u interrupt controllers in DT; expected %u.\n",
	339	node->full_name, num_ictlrs, soc->num_ictlrs);
	340
	341
	342	domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
	343	node, &tegra_ictlr_domain_ops,
	344	lic);
	345	if (!domain) {
346	pr_err("%s: failed to allocated domain\n", node->full_name);
347	err = -ENOMEM;
348	goto out_unmap;
349	}
350
351	tegra_ictlr_syscore_init();
352
353	pr_info("%s: %d interrupts forwarded to %s\n",
354	node->full_name, num_ictlrs * 32, parent->full_name);
355
356	return 0;
357
358	out_unmap:
359	for (i = 0; i < num_ictlrs; i++)
360	iounmap(lic->base[i]);
361	out_free:
362	kfree(lic);
363	return err;
364	}
365
366	IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
367	IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
1eec5821	368	IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);