[linux.git] / sound / soc / sunxi / sun8i-codec.c

/*
 * This driver supports the digital controls for the internal codec
 * found in Allwinner's A33 SoCs.
 *
 * (C) Copyright 2010-2016
 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
 * huangxin <[email protected]>
 * Mylène Josserand <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>

#define SUN8I_SYSCLK_CTL				0x00c
#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA			11
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL		9
#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC			8
#define SUN8I_SYSCLK_CTL_SYSCLK_ENA			3
#define SUN8I_SYSCLK_CTL_SYSCLK_SRC			0
#define SUN8I_MOD_CLK_ENA				0x010
#define SUN8I_MOD_CLK_ENA_AIF1				15
#define SUN8I_MOD_CLK_ENA_DAC				2
#define SUN8I_MOD_RST_CTL				0x014
#define SUN8I_MOD_RST_CTL_AIF1				15
#define SUN8I_MOD_RST_CTL_DAC				2
#define SUN8I_SYS_SR_CTRL				0x018
#define SUN8I_SYS_SR_CTRL_AIF1_FS			12
#define SUN8I_SYS_SR_CTRL_AIF2_FS			8
#define SUN8I_AIF1CLK_CTRL				0x040
#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD		15
#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV		14
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV		13
#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV		9
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV		6
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16		(1 << 6)
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ		4
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16		(1 << 4)
#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT		2
#define SUN8I_AIF1_DACDAT_CTRL				0x048
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA		15
#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA		14
#define SUN8I_DAC_DIG_CTRL				0x120
#define SUN8I_DAC_DIG_CTRL_ENDA			15
#define SUN8I_DAC_MXR_SRC				0x130
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L	15
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L	14
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL	13
#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL		12
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R	11
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R	10
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR	9
#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR		8

#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK		GENMASK(15, 12)
#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK		GENMASK(11, 8)
#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK	GENMASK(5, 4)
#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK	GENMASK(8, 6)

struct sun8i_codec {
	struct device	*dev;
	struct regmap	*regmap;
	struct clk	*clk_module;
	struct clk	*clk_bus;
};

static int sun8i_codec_runtime_resume(struct device *dev)
{
	struct sun8i_codec *scodec = dev_get_drvdata(dev);
	int ret;

	ret = clk_prepare_enable(scodec->clk_module);
	if (ret) {
		dev_err(dev, "Failed to enable the module clock\n");
		return ret;
	}

	ret = clk_prepare_enable(scodec->clk_bus);
	if (ret) {
		dev_err(dev, "Failed to enable the bus clock\n");
		goto err_disable_modclk;
	}

	regcache_cache_only(scodec->regmap, false);

	ret = regcache_sync(scodec->regmap);
	if (ret) {
		dev_err(dev, "Failed to sync regmap cache\n");
		goto err_disable_clk;
	}

	return 0;

err_disable_clk:
	clk_disable_unprepare(scodec->clk_bus);

err_disable_modclk:
	clk_disable_unprepare(scodec->clk_module);

	return ret;
}

static int sun8i_codec_runtime_suspend(struct device *dev)
{
	struct sun8i_codec *scodec = dev_get_drvdata(dev);

	regcache_cache_only(scodec->regmap, true);
	regcache_mark_dirty(scodec->regmap);

	clk_disable_unprepare(scodec->clk_module);
	clk_disable_unprepare(scodec->clk_bus);

	return 0;
}

static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
{
	unsigned int rate = params_rate(params);

	switch (rate) {
	case 8000:
	case 7350:
		return 0x0;
	case 11025:
		return 0x1;
	case 12000:
		return 0x2;
	case 16000:
		return 0x3;
	case 22050:
		return 0x4;
	case 24000:
		return 0x5;
	case 32000:
		return 0x6;
	case 44100:
		return 0x7;
	case 48000:
		return 0x8;
	case 96000:
		return 0x9;
	case 192000:
		return 0xa;
	default:
		return -EINVAL;
	}
}

static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
	u32 value;

	/* clock masters */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS: /* DAI Slave */
		value = 0x0; /* Codec Master */
		break;
	case SND_SOC_DAIFMT_CBM_CFM: /* DAI Master */
		value = 0x1; /* Codec Slave */
		break;
	default:
		return -EINVAL;
	}
	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
			   value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);

	/* clock inversion */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF: /* Normal */
		value = 0x0;
		break;
	case SND_SOC_DAIFMT_IB_IF: /* Inversion */
		value = 0x1;
		break;
	default:
		return -EINVAL;
	}
	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
			   value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
			   value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);

	/* DAI format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		value = 0x0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		value = 0x1;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		value = 0x2;
		break;
	case SND_SOC_DAIFMT_DSP_A:
	case SND_SOC_DAIFMT_DSP_B:
		value = 0x3;
		break;
	default:
		return -EINVAL;
	}
	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
			   value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);

	return 0;
}

static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
	int sample_rate;

	/*
	 * The CPU DAI handles only a sample of 16 bits. Configure the
	 * codec to handle this type of sample resolution.
	 */
	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
			   SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);

	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
			   SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
			   SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);

	sample_rate = sun8i_codec_get_hw_rate(params);
	if (sample_rate < 0)
		return sample_rate;

	regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
			   SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
			   sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
	regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
			   SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
			   sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);

	return 0;
}

static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
			SUN8I_DAC_MXR_SRC,
			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
	SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
			SUN8I_DAC_MXR_SRC,
			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
	SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
	SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
			SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
			SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
};

static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
	/* Digital parts of the DACs */
	SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
			    0, NULL, 0),

	/* Analog DAC AIF */
	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
			    SUN8I_AIF1_DACDAT_CTRL,
			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
			    SUN8I_AIF1_DACDAT_CTRL,
			    SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),

	/* DAC Mixers */
	SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
			sun8i_dac_mixer_controls),
	SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
			sun8i_dac_mixer_controls),

	/* Clocks */
	SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
			    SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
			    SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
			    SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),

	SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
			    SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
	/* Inversion as 0=AIF1, 1=AIF2 */
	SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
			    SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),

	/* Module reset */
	SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
			    SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
	SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
			    SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
};

static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
	/* Clock Routes */
	{ "AIF1", NULL, "SYSCLK AIF1" },
	{ "AIF1 PLL", NULL, "AIF1" },
	{ "RST AIF1", NULL, "AIF1 PLL" },
	{ "MODCLK AFI1", NULL, "RST AIF1" },
	{ "DAC", NULL, "MODCLK AFI1" },

	{ "RST DAC", NULL, "SYSCLK" },
	{ "MODCLK DAC", NULL, "RST DAC" },
	{ "DAC", NULL, "MODCLK DAC" },

	/* DAC Routes */
	{ "AIF1 Slot 0 Right", NULL, "DAC" },
	{ "AIF1 Slot 0 Left", NULL, "DAC" },

	/* DAC Mixer Routes */
	{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
	  "AIF1 Slot 0 Left"},
	{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
	  "AIF1 Slot 0 Right"},
};

static struct snd_soc_dai_ops sun8i_codec_dai_ops = {
	.hw_params = sun8i_codec_hw_params,
	.set_fmt = sun8i_set_fmt,
};

static struct snd_soc_dai_driver sun8i_codec_dai = {
	.name = "sun8i",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_192000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
	/* pcm operations */
	.ops = &sun8i_codec_dai_ops,
};

static struct snd_soc_codec_driver sun8i_soc_codec = {
	.component_driver = {
		.dapm_widgets		= sun8i_codec_dapm_widgets,
		.num_dapm_widgets	= ARRAY_SIZE(sun8i_codec_dapm_widgets),
		.dapm_routes		= sun8i_codec_dapm_routes,
		.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
	},
};

static const struct regmap_config sun8i_codec_regmap_config = {
	.reg_bits	= 32,
	.reg_stride	= 4,
	.val_bits	= 32,
	.max_register	= SUN8I_DAC_MXR_SRC,

	.cache_type	= REGCACHE_FLAT,
};

static int sun8i_codec_probe(struct platform_device *pdev)
{
	struct resource *res_base;
	struct sun8i_codec *scodec;
	void __iomem *base;
	int ret;

	scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
	if (!scodec)
		return -ENOMEM;

	scodec->dev = &pdev->dev;

	scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
	if (IS_ERR(scodec->clk_module)) {
		dev_err(&pdev->dev, "Failed to get the module clock\n");
		return PTR_ERR(scodec->clk_module);
	}

	scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
	if (IS_ERR(scodec->clk_bus)) {
		dev_err(&pdev->dev, "Failed to get the bus clock\n");
		return PTR_ERR(scodec->clk_bus);
	}

	res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res_base);
	if (IS_ERR(base)) {
		dev_err(&pdev->dev, "Failed to map the registers\n");
		return PTR_ERR(base);
	}

	scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
					       &sun8i_codec_regmap_config);
	if (IS_ERR(scodec->regmap)) {
		dev_err(&pdev->dev, "Failed to create our regmap\n");
		return PTR_ERR(scodec->regmap);
	}

	platform_set_drvdata(pdev, scodec);

	pm_runtime_enable(&pdev->dev);
	if (!pm_runtime_enabled(&pdev->dev)) {
		ret = sun8i_codec_runtime_resume(&pdev->dev);
		if (ret)
			goto err_pm_disable;
	}

	ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
				     &sun8i_codec_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Failed to register codec\n");
		goto err_suspend;
	}

	return ret;

err_suspend:
	if (!pm_runtime_status_suspended(&pdev->dev))
		sun8i_codec_runtime_suspend(&pdev->dev);

err_pm_disable:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int sun8i_codec_remove(struct platform_device *pdev)
{
	struct snd_soc_card *card = platform_get_drvdata(pdev);
	struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);

	pm_runtime_disable(&pdev->dev);
	if (!pm_runtime_status_suspended(&pdev->dev))
		sun8i_codec_runtime_suspend(&pdev->dev);

	snd_soc_unregister_codec(&pdev->dev);
	clk_disable_unprepare(scodec->clk_module);
	clk_disable_unprepare(scodec->clk_bus);

	return 0;
}

static const struct of_device_id sun8i_codec_of_match[] = {
	{ .compatible = "allwinner,sun8i-a33-codec" },
	{}
};
MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);

static const struct dev_pm_ops sun8i_codec_pm_ops = {
	SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
			   sun8i_codec_runtime_resume, NULL)
};

static struct platform_driver sun8i_codec_driver = {
	.driver = {
		.name = "sun8i-codec",
		.of_match_table = sun8i_codec_of_match,
		.pm = &sun8i_codec_pm_ops,
	},
	.probe = sun8i_codec_probe,
	.remove = sun8i_codec_remove,
};
module_platform_driver(sun8i_codec_driver);

MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
MODULE_AUTHOR("Mylène Josserand <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sun8i-codec");
Commit	Line	Data
36c68493 MJ	1	/*
	2	* This driver supports the digital controls for the internal codec
	3	* found in Allwinner's A33 SoCs.
	4	*
	5	* (C) Copyright 2010-2016
	6	* Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
	7	* huangxin <[email protected]>
	8	* Mylène Josserand <[email protected]>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
	24	#include <linux/io.h>
	25	#include <linux/pm_runtime.h>
	26	#include <linux/regmap.h>
	27
	28	#include <sound/pcm_params.h>
	29	#include <sound/soc.h>
	30	#include <sound/soc-dapm.h>
	31
	32	#define SUN8I_SYSCLK_CTL 0x00c
	33	#define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11
	34	#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL 9
	35	#define SUN8I_SYSCLK_CTL_AIF1CLK_SRC 8
	36	#define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3
	37	#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
	38	#define SUN8I_MOD_CLK_ENA 0x010
	39	#define SUN8I_MOD_CLK_ENA_AIF1 15
	40	#define SUN8I_MOD_CLK_ENA_DAC 2
	41	#define SUN8I_MOD_RST_CTL 0x014
	42	#define SUN8I_MOD_RST_CTL_AIF1 15
	43	#define SUN8I_MOD_RST_CTL_DAC 2
	44	#define SUN8I_SYS_SR_CTRL 0x018
	45	#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
	46	#define SUN8I_SYS_SR_CTRL_AIF2_FS 8
	47	#define SUN8I_AIF1CLK_CTRL 0x040
	48	#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
	49	#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV 14
	50	#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV 13
	51	#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
	52	#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
	53	#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16 (1 << 6)
	54	#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
	55	#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
	56	#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
	57	#define SUN8I_AIF1_DACDAT_CTRL 0x048
	58	#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
	59	#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
	60	#define SUN8I_DAC_DIG_CTRL 0x120
	61	#define SUN8I_DAC_DIG_CTRL_ENDA 15
	62	#define SUN8I_DAC_MXR_SRC 0x130
	63	#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15
	64	#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14
65	#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13
66	#define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12
67	#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11
68	#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
69	#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
70	#define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
71
72	#define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
73	#define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
74	#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
75	#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
76
77	struct sun8i_codec {
78	struct device *dev;
79	struct regmap *regmap;
80	struct clk *clk_module;
81	struct clk *clk_bus;
82	};
83
84	static int sun8i_codec_runtime_resume(struct device *dev)
85	{
86	struct sun8i_codec *scodec = dev_get_drvdata(dev);
87	int ret;
88
89	ret = clk_prepare_enable(scodec->clk_module);
90	if (ret) {
91	dev_err(dev, "Failed to enable the module clock\n");
92	return ret;
93	}
94
95	ret = clk_prepare_enable(scodec->clk_bus);
96	if (ret) {
97	dev_err(dev, "Failed to enable the bus clock\n");
98	goto err_disable_modclk;
99	}
100
101	regcache_cache_only(scodec->regmap, false);
102
103	ret = regcache_sync(scodec->regmap);
104	if (ret) {
105	dev_err(dev, "Failed to sync regmap cache\n");
106	goto err_disable_clk;
107	}
108
109	return 0;
110
111	err_disable_clk:
112	clk_disable_unprepare(scodec->clk_bus);
113
114	err_disable_modclk:
115	clk_disable_unprepare(scodec->clk_module);
116
117	return ret;
118	}
119
120	static int sun8i_codec_runtime_suspend(struct device *dev)
121	{
122	struct sun8i_codec *scodec = dev_get_drvdata(dev);
123
124	regcache_cache_only(scodec->regmap, true);
125	regcache_mark_dirty(scodec->regmap);
126
127	clk_disable_unprepare(scodec->clk_module);
128	clk_disable_unprepare(scodec->clk_bus);
129
130	return 0;
131	}
132
133	static int sun8i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
134	{
135	unsigned int rate = params_rate(params);
136
137	switch (rate) {
138	case 8000:
139	case 7350:
140	return 0x0;
141	case 11025:
142	return 0x1;
143	case 12000:
144	return 0x2;
145	case 16000:
146	return 0x3;
147	case 22050:
148	return 0x4;
149	case 24000:
150	return 0x5;
151	case 32000:
152	return 0x6;
153	case 44100:
154	return 0x7;
155	case 48000:
156	return 0x8;
157	case 96000:
158	return 0x9;
159	case 192000:
160	return 0xa;
161	default:
162	return -EINVAL;
163	}
164	}
165
166	static int sun8i_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
167	{
168	struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
169	u32 value;
170
171	/* clock masters */
172	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
173	case SND_SOC_DAIFMT_CBS_CFS: /* DAI Slave */
174	value = 0x0; /* Codec Master */
175	break;
176	case SND_SOC_DAIFMT_CBM_CFM: /* DAI Master */
177	value = 0x1; /* Codec Slave */
178	break;
179	default:
180	return -EINVAL;
181	}
182	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
183	BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
184	value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
185
186	/* clock inversion */
187	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
188	case SND_SOC_DAIFMT_NB_NF: /* Normal */
189	value = 0x0;
190	break;
191	case SND_SOC_DAIFMT_IB_IF: /* Inversion */
192	value = 0x1;
193	break;
194	default:
195	return -EINVAL;
196	}
197	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
198	BIT(SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV),
199	value << SUN8I_AIF1CLK_CTRL_AIF1_BCLK_INV);
200	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
201	BIT(SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV),
202	value << SUN8I_AIF1CLK_CTRL_AIF1_LRCK_INV);
203
204	/* DAI format */
205	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
206	case SND_SOC_DAIFMT_I2S:
207	value = 0x0;
208	break;
209	case SND_SOC_DAIFMT_LEFT_J:
210	value = 0x1;
211	break;
212	case SND_SOC_DAIFMT_RIGHT_J:
213	value = 0x2;
214	break;
215	case SND_SOC_DAIFMT_DSP_A:
216	case SND_SOC_DAIFMT_DSP_B:
217	value = 0x3;
218	break;
219	default:
220	return -EINVAL;
221	}
222	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
223	BIT(SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT),
224	value << SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT);
225
226	return 0;
227	}
228
229	static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
230	struct snd_pcm_hw_params *params,
231	struct snd_soc_dai *dai)
232	{
233	struct sun8i_codec *scodec = snd_soc_codec_get_drvdata(dai->codec);
234	int sample_rate;
235
236	/*
237	* The CPU DAI handles only a sample of 16 bits. Configure the
238	* codec to handle this type of sample resolution.
239	*/
240	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
241	SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK,
242	SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16);
243
244	regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
245	SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
246	SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
247
248	sample_rate = sun8i_codec_get_hw_rate(params);
249	if (sample_rate < 0)
250	return sample_rate;
251
252	regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
253	SUN8I_SYS_SR_CTRL_AIF1_FS_MASK,
254	sample_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
255	regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL,
256	SUN8I_SYS_SR_CTRL_AIF2_FS_MASK,
257	sample_rate << SUN8I_SYS_SR_CTRL_AIF2_FS);
258
259	return 0;
260	}
261
ca14da6e MJ	262	static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
	263	SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch",
	264	SUN8I_DAC_MXR_SRC,
	265	SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L,
36c68493	266	SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0),
ca14da6e MJ	267	SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch",
	268	SUN8I_DAC_MXR_SRC,
	269	SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L,
36c68493	270	SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0),
ca14da6e MJ	271	SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
ca14da6e MJ	272	SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL,
36c68493	273	SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0),
ca14da6e MJ	274	SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC,
ca14da6e MJ	275	SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL,
36c68493 MJ	276	SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
	277	};
	278
	279	static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
	280	/* Digital parts of the DACs */
	281	SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
	282	0, NULL, 0),
	283
9123aa86 MJ	284	/* Analog DAC AIF */
	285	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
	286	SUN8I_AIF1_DACDAT_CTRL,
	287	SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0),
	288	SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right", "Playback", 0,
	289	SUN8I_AIF1_DACDAT_CTRL,
	290	SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
36c68493 MJ	291
36c68493 MJ	292	/* DAC Mixers */
fa22ca4f MJ	293	SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
	294	sun8i_dac_mixer_controls),
	295	SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
	296	sun8i_dac_mixer_controls),
36c68493 MJ	297
	298	/* Clocks */
	299	SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
	300	SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
	301	SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
	302	SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
	303	SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
	304	SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
	305	SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
	306	SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0),
	307
	308	SND_SOC_DAPM_SUPPLY("AIF1 PLL", SUN8I_SYSCLK_CTL,
	309	SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL, 0, NULL, 0),
	310	/* Inversion as 0=AIF1, 1=AIF2 */
	311	SND_SOC_DAPM_SUPPLY("SYSCLK AIF1", SUN8I_SYSCLK_CTL,
	312	SUN8I_SYSCLK_CTL_SYSCLK_SRC, 1, NULL, 0),
	313
	314	/* Module reset */
	315	SND_SOC_DAPM_SUPPLY("RST AIF1", SUN8I_MOD_RST_CTL,
	316	SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
	317	SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
	318	SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
36c68493 MJ	319	};
	320
	321	static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
	322	/* Clock Routes */
	323	{ "AIF1", NULL, "SYSCLK AIF1" },
	324	{ "AIF1 PLL", NULL, "AIF1" },
	325	{ "RST AIF1", NULL, "AIF1 PLL" },
	326	{ "MODCLK AFI1", NULL, "RST AIF1" },
	327	{ "DAC", NULL, "MODCLK AFI1" },
	328
	329	{ "RST DAC", NULL, "SYSCLK" },
	330	{ "MODCLK DAC", NULL, "RST DAC" },
	331	{ "DAC", NULL, "MODCLK DAC" },
	332
	333	/* DAC Routes */
9123aa86 MJ	334	{ "AIF1 Slot 0 Right", NULL, "DAC" },
9123aa86 MJ	335	{ "AIF1 Slot 0 Left", NULL, "DAC" },
36c68493 MJ	336
36c68493 MJ	337	/* DAC Mixer Routes */
ca14da6e	338	{ "Left Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
9123aa86	339	"AIF1 Slot 0 Left"},
80405d44	340	{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
9123aa86	341	"AIF1 Slot 0 Right"},
36c68493 MJ	342	};
	343
	344	static struct snd_soc_dai_ops sun8i_codec_dai_ops = {
	345	.hw_params = sun8i_codec_hw_params,
	346	.set_fmt = sun8i_set_fmt,
	347	};
	348
	349	static struct snd_soc_dai_driver sun8i_codec_dai = {
	350	.name = "sun8i",
	351	/* playback capabilities */
	352	.playback = {
	353	.stream_name = "Playback",
	354	.channels_min = 1,
	355	.channels_max = 2,
	356	.rates = SNDRV_PCM_RATE_8000_192000,
	357	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	358	},
	359	/* pcm operations */
	360	.ops = &sun8i_codec_dai_ops,
	361	};
	362
	363	static struct snd_soc_codec_driver sun8i_soc_codec = {
	364	.component_driver = {
	365	.dapm_widgets = sun8i_codec_dapm_widgets,
	366	.num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets),
	367	.dapm_routes = sun8i_codec_dapm_routes,
	368	.num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes),
	369	},
	370	};
	371
	372	static const struct regmap_config sun8i_codec_regmap_config = {
	373	.reg_bits = 32,
	374	.reg_stride = 4,
	375	.val_bits = 32,
	376	.max_register = SUN8I_DAC_MXR_SRC,
	377
	378	.cache_type = REGCACHE_FLAT,
	379	};
	380
	381	static int sun8i_codec_probe(struct platform_device *pdev)
	382	{
	383	struct resource *res_base;
	384	struct sun8i_codec *scodec;
	385	void __iomem *base;
	386	int ret;
	387
	388	scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
	389	if (!scodec)
	390	return -ENOMEM;
	391
	392	scodec->dev = &pdev->dev;
	393
	394	scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
	395	if (IS_ERR(scodec->clk_module)) {
	396	dev_err(&pdev->dev, "Failed to get the module clock\n");
	397	return PTR_ERR(scodec->clk_module);
	398	}
	399
	400	scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
	401	if (IS_ERR(scodec->clk_bus)) {
	402	dev_err(&pdev->dev, "Failed to get the bus clock\n");
	403	return PTR_ERR(scodec->clk_bus);
	404	}
	405
406	res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
407	base = devm_ioremap_resource(&pdev->dev, res_base);
408	if (IS_ERR(base)) {
409	dev_err(&pdev->dev, "Failed to map the registers\n");
410	return PTR_ERR(base);
411	}
412
413	scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
414	&sun8i_codec_regmap_config);
415	if (IS_ERR(scodec->regmap)) {
416	dev_err(&pdev->dev, "Failed to create our regmap\n");
417	return PTR_ERR(scodec->regmap);
418	}
419
420	platform_set_drvdata(pdev, scodec);
421
422	pm_runtime_enable(&pdev->dev);
423	if (!pm_runtime_enabled(&pdev->dev)) {
424	ret = sun8i_codec_runtime_resume(&pdev->dev);
425	if (ret)
426	goto err_pm_disable;
427	}
428
429	ret = snd_soc_register_codec(&pdev->dev, &sun8i_soc_codec,
430	&sun8i_codec_dai, 1);
431	if (ret) {
432	dev_err(&pdev->dev, "Failed to register codec\n");
433	goto err_suspend;
434	}
435
436	return ret;
437
438	err_suspend:
439	if (!pm_runtime_status_suspended(&pdev->dev))
440	sun8i_codec_runtime_suspend(&pdev->dev);
441
442	err_pm_disable:
443	pm_runtime_disable(&pdev->dev);
444
445	return ret;
446	}
447
448	static int sun8i_codec_remove(struct platform_device *pdev)
449	{
450	struct snd_soc_card *card = platform_get_drvdata(pdev);
451	struct sun8i_codec *scodec = snd_soc_card_get_drvdata(card);
452
453	pm_runtime_disable(&pdev->dev);
454	if (!pm_runtime_status_suspended(&pdev->dev))
455	sun8i_codec_runtime_suspend(&pdev->dev);
456
457	snd_soc_unregister_codec(&pdev->dev);
458	clk_disable_unprepare(scodec->clk_module);
459	clk_disable_unprepare(scodec->clk_bus);
460
461	return 0;
462	}
463
464	static const struct of_device_id sun8i_codec_of_match[] = {
465	{ .compatible = "allwinner,sun8i-a33-codec" },
466	{}
467	};
468	MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
469
470	static const struct dev_pm_ops sun8i_codec_pm_ops = {
471	SET_RUNTIME_PM_OPS(sun8i_codec_runtime_suspend,
472	sun8i_codec_runtime_resume, NULL)
473	};
474
475	static struct platform_driver sun8i_codec_driver = {
476	.driver = {
477	.name = "sun8i-codec",
478	.of_match_table = sun8i_codec_of_match,
479	.pm = &sun8i_codec_pm_ops,
480	},
481	.probe = sun8i_codec_probe,
482	.remove = sun8i_codec_remove,
483	};
484	module_platform_driver(sun8i_codec_driver);
485
486	MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver");
487	MODULE_AUTHOR("Mylène Josserand <[email protected]>");
488	MODULE_LICENSE("GPL");
489	MODULE_ALIAS("platform:sun8i-codec");