[linux.git] / drivers / irqchip / irq-mtk-sysirq.c

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

struct mtk_sysirq_chip_data {
	spinlock_t lock;
	void __iomem *intpol_base;
};

static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
{
	irq_hw_number_t hwirq = data->hwirq;
	struct mtk_sysirq_chip_data *chip_data = data->chip_data;
	u32 offset, reg_index, value;
	unsigned long flags;
	int ret;

	offset = hwirq & 0x1f;
	reg_index = hwirq >> 5;

	spin_lock_irqsave(&chip_data->lock, flags);
	value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
		if (type == IRQ_TYPE_LEVEL_LOW)
			type = IRQ_TYPE_LEVEL_HIGH;
		else
			type = IRQ_TYPE_EDGE_RISING;
		value |= (1 << offset);
	} else {
		value &= ~(1 << offset);
	}
	writel(value, chip_data->intpol_base + reg_index * 4);

	data = data->parent_data;
	ret = data->chip->irq_set_type(data, type);
	spin_unlock_irqrestore(&chip_data->lock, flags);
	return ret;
}

static struct irq_chip mtk_sysirq_chip = {
	.name			= "MT_SYSIRQ",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_type		= mtk_sysirq_set_type,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
};

static int mtk_sysirq_domain_translate(struct irq_domain *d,
				       struct irq_fwspec *fwspec,
				       unsigned long *hwirq,
				       unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
		return 0;
	}

	return -EINVAL;
}

static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *arg)
{
	int i;
	irq_hw_number_t hwirq;
	struct irq_fwspec *fwspec = arg;
	struct irq_fwspec gic_fwspec = *fwspec;

	if (fwspec->param_count != 3)
		return -EINVAL;

	/* sysirq doesn't support PPI */
	if (fwspec->param[0])
		return -EINVAL;

	hwirq = fwspec->param[1];
	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &mtk_sysirq_chip,
					      domain->host_data);

	gic_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
}

static const struct irq_domain_ops sysirq_domain_ops = {
	.translate	= mtk_sysirq_domain_translate,
	.alloc		= mtk_sysirq_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

static int __init mtk_sysirq_of_init(struct device_node *node,
				     struct device_node *parent)
{
	struct irq_domain *domain, *domain_parent;
	struct mtk_sysirq_chip_data *chip_data;
	int ret, size, intpol_num;
	struct resource res;

	domain_parent = irq_find_host(parent);
	if (!domain_parent) {
		pr_err("mtk_sysirq: interrupt-parent not found\n");
		return -EINVAL;
	}

	ret = of_address_to_resource(node, 0, &res);
	if (ret)
		return ret;

	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
	if (!chip_data)
		return -ENOMEM;

	size = resource_size(&res);
	intpol_num = size * 8;
	chip_data->intpol_base = ioremap(res.start, size);
	if (!chip_data->intpol_base) {
		pr_err("mtk_sysirq: unable to map sysirq register\n");
		ret = -ENXIO;
		goto out_free;
	}

	domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
					  &sysirq_domain_ops, chip_data);
	if (!domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}
	spin_lock_init(&chip_data->lock);

	return 0;

out_unmap:
	iounmap(chip_data->intpol_base);
out_free:
	kfree(chip_data);
	return ret;
}
IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
Commit	Line	Data
5fe3bba3 YC	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Joe.C <[email protected]>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/irq.h>
41a83e06	16	#include <linux/irqchip.h>
5fe3bba3 YC	17	#include <linux/irqdomain.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
	21	#include <linux/io.h>
	22	#include <linux/slab.h>
	23	#include <linux/spinlock.h>
	24
5fe3bba3 YC	25	struct mtk_sysirq_chip_data {
	26	spinlock_t lock;
	27	void __iomem *intpol_base;
	28	};
	29
	30	static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
	31	{
	32	irq_hw_number_t hwirq = data->hwirq;
	33	struct mtk_sysirq_chip_data *chip_data = data->chip_data;
	34	u32 offset, reg_index, value;
	35	unsigned long flags;
	36	int ret;
	37
	38	offset = hwirq & 0x1f;
	39	reg_index = hwirq >> 5;
	40
	41	spin_lock_irqsave(&chip_data->lock, flags);
	42	value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
	43	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_EDGE_FALLING) {
	44	if (type == IRQ_TYPE_LEVEL_LOW)
	45	type = IRQ_TYPE_LEVEL_HIGH;
	46	else
	47	type = IRQ_TYPE_EDGE_RISING;
	48	value \|= (1 << offset);
	49	} else {
	50	value &= ~(1 << offset);
	51	}
	52	writel(value, chip_data->intpol_base + reg_index * 4);
	53
	54	data = data->parent_data;
	55	ret = data->chip->irq_set_type(data, type);
	56	spin_unlock_irqrestore(&chip_data->lock, flags);
	57	return ret;
	58	}
	59
	60	static struct irq_chip mtk_sysirq_chip = {
	61	.name = "MT_SYSIRQ",
	62	.irq_mask = irq_chip_mask_parent,
	63	.irq_unmask = irq_chip_unmask_parent,
	64	.irq_eoi = irq_chip_eoi_parent,
	65	.irq_set_type = mtk_sysirq_set_type,
	66	.irq_retrigger = irq_chip_retrigger_hierarchy,
	67	.irq_set_affinity = irq_chip_set_affinity_parent,
	68	};
	69
f833f57f MZ	70	static int mtk_sysirq_domain_translate(struct irq_domain *d,
	71	struct irq_fwspec *fwspec,
	72	unsigned long *hwirq,
	73	unsigned int *type)
5fe3bba3	74	{
f833f57f MZ	75	if (is_of_node(fwspec->fwnode)) {
	76	if (fwspec->param_count != 3)
	77	return -EINVAL;
5fe3bba3	78
f833f57f MZ	79	/* No PPI should point to this domain */
	80	if (fwspec->param[0] != 0)
	81	return -EINVAL;
	82
	83	*hwirq = fwspec->param[1];
	84	*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
	85	return 0;
	86	}
5fe3bba3	87
f833f57f	88	return -EINVAL;
5fe3bba3 YC	89	}
	90
	91	static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	92	unsigned int nr_irqs, void *arg)
	93	{
	94	int i;
	95	irq_hw_number_t hwirq;
f833f57f MZ	96	struct irq_fwspec *fwspec = arg;
f833f57f MZ	97	struct irq_fwspec gic_fwspec = *fwspec;
5fe3bba3	98
f833f57f	99	if (fwspec->param_count != 3)
5fe3bba3 YC	100	return -EINVAL;
	101
	102	/* sysirq doesn't support PPI */
f833f57f	103	if (fwspec->param[0])
5fe3bba3 YC	104	return -EINVAL;
5fe3bba3 YC	105
f833f57f	106	hwirq = fwspec->param[1];
5fe3bba3 YC	107	for (i = 0; i < nr_irqs; i++)
	108	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	109	&mtk_sysirq_chip,
	110	domain->host_data);
	111
f833f57f MZ	112	gic_fwspec.fwnode = domain->parent->fwnode;
f833f57f MZ	113	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
5fe3bba3 YC	114	}
5fe3bba3 YC	115
96009736	116	static const struct irq_domain_ops sysirq_domain_ops = {
f833f57f MZ	117	.translate = mtk_sysirq_domain_translate,
	118	.alloc = mtk_sysirq_domain_alloc,
	119	.free = irq_domain_free_irqs_common,
5fe3bba3 YC	120	};
	121
	122	static int __init mtk_sysirq_of_init(struct device_node *node,
	123	struct device_node *parent)
	124	{
	125	struct irq_domain domain, domain_parent;
	126	struct mtk_sysirq_chip_data *chip_data;
cdb647a7 YC	127	int ret, size, intpol_num;
cdb647a7 YC	128	struct resource res;
5fe3bba3 YC	129
	130	domain_parent = irq_find_host(parent);
	131	if (!domain_parent) {
	132	pr_err("mtk_sysirq: interrupt-parent not found\n");
	133	return -EINVAL;
	134	}
	135
cdb647a7 YC	136	ret = of_address_to_resource(node, 0, &res);
	137	if (ret)
	138	return ret;
	139
5fe3bba3 YC	140	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
	141	if (!chip_data)
	142	return -ENOMEM;
	143
cdb647a7 YC	144	size = resource_size(&res);
	145	intpol_num = size * 8;
	146	chip_data->intpol_base = ioremap(res.start, size);
	147	if (!chip_data->intpol_base) {
5fe3bba3	148	pr_err("mtk_sysirq: unable to map sysirq register\n");
e1a96fb8	149	ret = -ENXIO;
5fe3bba3 YC	150	goto out_free;
	151	}
	152
cdb647a7	153	domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
5fe3bba3 YC	154	&sysirq_domain_ops, chip_data);
	155	if (!domain) {
	156	ret = -ENOMEM;
	157	goto out_unmap;
	158	}
	159	spin_lock_init(&chip_data->lock);
	160
	161	return 0;
	162
	163	out_unmap:
	164	iounmap(chip_data->intpol_base);
	165	out_free:
	166	kfree(chip_data);
	167	return ret;
	168	}
	169	IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);