[linux.git] / drivers / ide / atiixp.c

/*
 *  Copyright (C) 2003 ATI Inc. <[email protected]>
 *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/init.h>

#define DRV_NAME "atiixp"

#define ATIIXP_IDE_PIO_TIMING		0x40
#define ATIIXP_IDE_MDMA_TIMING		0x44
#define ATIIXP_IDE_PIO_CONTROL		0x48
#define ATIIXP_IDE_PIO_MODE		0x4a
#define ATIIXP_IDE_UDMA_CONTROL		0x54
#define ATIIXP_IDE_UDMA_MODE		0x56

typedef struct {
	u8 command_width;
	u8 recover_width;
} atiixp_ide_timing;

static atiixp_ide_timing pio_timing[] = {
	{ 0x05, 0x0d },
	{ 0x04, 0x07 },
	{ 0x03, 0x04 },
	{ 0x02, 0x02 },
	{ 0x02, 0x00 },
};

static atiixp_ide_timing mdma_timing[] = {
	{ 0x07, 0x07 },
	{ 0x02, 0x01 },
	{ 0x02, 0x00 },
};

static DEFINE_SPINLOCK(atiixp_lock);

/**
 *	atiixp_set_pio_mode	-	set host controller for PIO mode
 *	@drive: drive
 *	@pio: PIO mode number
 *
 *	Set the interface PIO mode.
 */

static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn ^ 1) * 8;
	u32 pio_timing_data;
	u16 pio_mode_data;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	pio_mode_data |= (pio << (drive->dn * 4));
	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);

	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	pio_timing_data &= ~(0xff << timing_shift);
	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
		 (pio_timing[pio].command_width << (timing_shift + 4));
	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

/**
 *	atiixp_set_dma_mode	-	set host controller for DMA mode
 *	@drive: drive
 *	@speed: DMA mode
 *
 *	Set a ATIIXP host controller to the desired DMA mode.  This involves
 *	programming the right timing data into the PCI configuration space.
 */

static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
{
	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
	unsigned long flags;
	int timing_shift = (drive->dn ^ 1) * 8;
	u32 tmp32;
	u16 tmp16;
	u16 udma_ctl = 0;

	spin_lock_irqsave(&atiixp_lock, flags);

	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);

	if (speed >= XFER_UDMA_0) {
		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
		tmp16 &= ~(0x07 << (drive->dn * 4));
		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);

		udma_ctl |= (1 << drive->dn);
	} else if (speed >= XFER_MW_DMA_0) {
		u8 i = speed & 0x03;

		pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
		tmp32 &= ~(0xff << timing_shift);
		tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
			 (mdma_timing[i].command_width << (timing_shift + 4));
		pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);

		udma_ctl &= ~(1 << drive->dn);
	}

	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);

	spin_unlock_irqrestore(&atiixp_lock, flags);
}

static u8 atiixp_cable_detect(ide_hwif_t *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u8 udma_mode = 0, ch = hwif->channel;

	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);

	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static const struct ide_port_ops atiixp_port_ops = {
	.set_pio_mode		= atiixp_set_pio_mode,
	.set_dma_mode		= atiixp_set_dma_mode,
	.cable_detect		= atiixp_cable_detect,
};

static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
	{	/* 0: IXP200/300/400/700 */
		.name		= DRV_NAME,
		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
		.port_ops	= &atiixp_port_ops,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
	},
	{	/* 1: IXP600 */
		.name		= DRV_NAME,
		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
		.port_ops	= &atiixp_port_ops,
		.host_flags	= IDE_HFLAG_SINGLE,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA5,
 	},
};

/**
 *	atiixp_init_one	-	called when a ATIIXP is found
 *	@dev: the atiixp device
 *	@id: the matching pci id
 *
 *	Called when the PCI registration layer (or the IDE initialization)
 *	finds a device matching our IDE device tables.
 */

static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
}

static const struct pci_device_id atiixp_pci_tbl[] = {
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);

static struct pci_driver atiixp_pci_driver = {
	.name		= "ATIIXP_IDE",
	.id_table	= atiixp_pci_tbl,
	.probe		= atiixp_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init atiixp_ide_init(void)
{
	return ide_pci_register_driver(&atiixp_pci_driver);
}

static void __exit atiixp_ide_exit(void)
{
	pci_unregister_driver(&atiixp_pci_driver);
}

module_init(atiixp_ide_init);
module_exit(atiixp_ide_exit);

MODULE_AUTHOR("HUI YU");
MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 2003 ATI Inc. <[email protected]>
485efc6c	3	* Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
1da177e4 LT	4	*/
1da177e4 LT	5
1da177e4 LT	6	#include <linux/types.h>
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
1da177e4	9	#include <linux/pci.h>
1da177e4	10	#include <linux/ide.h>
1da177e4 LT	11	#include <linux/init.h>
1da177e4 LT	12
ced3ec8a BZ	13	#define DRV_NAME "atiixp"
ced3ec8a BZ	14
1da177e4 LT	15	#define ATIIXP_IDE_PIO_TIMING 0x40
	16	#define ATIIXP_IDE_MDMA_TIMING 0x44
	17	#define ATIIXP_IDE_PIO_CONTROL 0x48
	18	#define ATIIXP_IDE_PIO_MODE 0x4a
	19	#define ATIIXP_IDE_UDMA_CONTROL 0x54
	20	#define ATIIXP_IDE_UDMA_MODE 0x56
	21
	22	typedef struct {
	23	u8 command_width;
	24	u8 recover_width;
	25	} atiixp_ide_timing;
	26
	27	static atiixp_ide_timing pio_timing[] = {
	28	{ 0x05, 0x0d },
	29	{ 0x04, 0x07 },
	30	{ 0x03, 0x04 },
	31	{ 0x02, 0x02 },
	32	{ 0x02, 0x00 },
	33	};
	34
	35	static atiixp_ide_timing mdma_timing[] = {
	36	{ 0x07, 0x07 },
	37	{ 0x02, 0x01 },
	38	{ 0x02, 0x00 },
	39	};
	40
6c5f8cc3 AC	41	static DEFINE_SPINLOCK(atiixp_lock);
6c5f8cc3 AC	42
1da177e4	43	/**
88b2b32b BZ	44	* atiixp_set_pio_mode - set host controller for PIO mode
	45	* @drive: drive
	46	* @pio: PIO mode number
1da177e4 LT	47	*
	48	* Set the interface PIO mode.
	49	*/
	50
88b2b32b	51	static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
1da177e4	52	{
36501650	53	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4	54	unsigned long flags;
f76bee16	55	int timing_shift = (drive->dn ^ 1) * 8;
1da177e4 LT	56	u32 pio_timing_data;
	57	u16 pio_mode_data;
	58
6c5f8cc3	59	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4 LT	60
	61	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
	62	pio_mode_data &= ~(0x07 << (drive->dn * 4));
	63	pio_mode_data \|= (pio << (drive->dn * 4));
	64	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
	65
	66	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
	67	pio_timing_data &= ~(0xff << timing_shift);
	68	pio_timing_data \|= (pio_timing[pio].recover_width << timing_shift) \|
	69	(pio_timing[pio].command_width << (timing_shift + 4));
	70	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
	71
6c5f8cc3	72	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	73	}
	74
	75	/**
88b2b32b BZ	76	* atiixp_set_dma_mode - set host controller for DMA mode
	77	* @drive: drive
	78	* @speed: DMA mode
1da177e4	79	*
88b2b32b BZ	80	* Set a ATIIXP host controller to the desired DMA mode. This involves
88b2b32b BZ	81	* programming the right timing data into the PCI configuration space.
1da177e4 LT	82	*/
1da177e4 LT	83
88b2b32b	84	static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
1da177e4	85	{
36501650	86	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
1da177e4	87	unsigned long flags;
f76bee16	88	int timing_shift = (drive->dn ^ 1) * 8;
1da177e4 LT	89	u32 tmp32;
1da177e4 LT	90	u16 tmp16;
8ae60e34	91	u16 udma_ctl = 0;
94c7fa0f	92
6c5f8cc3	93	spin_lock_irqsave(&atiixp_lock, flags);
1da177e4	94
8ae60e34 BZ	95	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
8ae60e34 BZ	96
1da177e4 LT	97	if (speed >= XFER_UDMA_0) {
	98	pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
	99	tmp16 &= ~(0x07 << (drive->dn * 4));
	100	tmp16 \|= ((speed & 0x07) << (drive->dn * 4));
	101	pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
8ae60e34 BZ	102
	103	udma_ctl \|= (1 << drive->dn);
	104	} else if (speed >= XFER_MW_DMA_0) {
	105	u8 i = speed & 0x03;
	106
	107	pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
	108	tmp32 &= ~(0xff << timing_shift);
	109	tmp32 \|= (mdma_timing[i].recover_width << timing_shift) \|
	110	(mdma_timing[i].command_width << (timing_shift + 4));
	111	pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
	112
	113	udma_ctl &= ~(1 << drive->dn);
1da177e4 LT	114	}
1da177e4 LT	115
8ae60e34 BZ	116	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
8ae60e34 BZ	117
6c5f8cc3	118	spin_unlock_irqrestore(&atiixp_lock, flags);
1da177e4 LT	119	}
1da177e4 LT	120
f454cbe8	121	static u8 atiixp_cable_detect(ide_hwif_t *hwif)
b4d1c73d BZ	122	{
	123	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	124	u8 udma_mode = 0, ch = hwif->channel;
	125
	126	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
	127
	128	if ((udma_mode & 0x07) >= 0x04 \|\| (udma_mode & 0x70) >= 0x40)
	129	return ATA_CBL_PATA80;
	130	else
	131	return ATA_CBL_PATA40;
	132	}
	133
ac95beed BZ	134	static const struct ide_port_ops atiixp_port_ops = {
	135	.set_pio_mode = atiixp_set_pio_mode,
	136	.set_dma_mode = atiixp_set_dma_mode,
	137	.cable_detect = atiixp_cable_detect,
	138	};
1da177e4	139
85620436	140	static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
ced3ec8a BZ	141	{ /* 0: IXP200/300/400/700 */
ced3ec8a BZ	142	.name = DRV_NAME,
1da177e4	143	.enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
ac95beed	144	.port_ops = &atiixp_port_ops,
4099d143	145	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	146	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	147	.udma_mask = ATA_UDMA5,
ced3ec8a BZ	148	},
	149	{ /* 1: IXP600 */
	150	.name = DRV_NAME,
b25168df	151	.enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
ac95beed	152	.port_ops = &atiixp_port_ops,
2467922a	153	.host_flags = IDE_HFLAG_SINGLE,
4099d143	154	.pio_mask = ATA_PIO4,
5f8b6c34 BZ	155	.mwdma_mask = ATA_MWDMA2,
5f8b6c34 BZ	156	.udma_mask = ATA_UDMA5,
b25168df	157	},
1da177e4 LT	158	};
	159
	160	/**
	161	* atiixp_init_one - called when a ATIIXP is found
	162	* @dev: the atiixp device
	163	* @id: the matching pci id
	164	*
	165	* Called when the PCI registration layer (or the IDE initialization)
	166	* finds a device matching our IDE device tables.
	167	*/
	168
	169	static int __devinit atiixp_init_one(struct pci_dev dev, const struct pci_device_id id)
	170	{
6cdf6eb3	171	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
1da177e4 LT	172	}
1da177e4 LT	173
9cbcc5e3 BZ	174	static const struct pci_device_id atiixp_pci_tbl[] = {
	175	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
	176	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
	177	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
	178	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
	179	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
1da177e4 LT	180	{ 0, },
	181	};
	182	MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
	183
a9ab09e2	184	static struct pci_driver atiixp_pci_driver = {
1da177e4 LT	185	.name = "ATIIXP_IDE",
	186	.id_table = atiixp_pci_tbl,
	187	.probe = atiixp_init_one,
f354fbc4	188	.remove = ide_pci_remove,
feb22b7f BZ	189	.suspend = ide_pci_suspend,
feb22b7f BZ	190	.resume = ide_pci_resume,
1da177e4 LT	191	};
1da177e4 LT	192
82ab1eec	193	static int __init atiixp_ide_init(void)
1da177e4	194	{
a9ab09e2	195	return ide_pci_register_driver(&atiixp_pci_driver);
1da177e4 LT	196	}
1da177e4 LT	197
f354fbc4 BZ	198	static void __exit atiixp_ide_exit(void)
f354fbc4 BZ	199	{
a9ab09e2	200	pci_unregister_driver(&atiixp_pci_driver);
f354fbc4 BZ	201	}
f354fbc4 BZ	202
1da177e4	203	module_init(atiixp_ide_init);
f354fbc4	204	module_exit(atiixp_ide_exit);
1da177e4 LT	205
	206	MODULE_AUTHOR("HUI YU");
	207	MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
	208	MODULE_LICENSE("GPL");