[linux.git] / include / linux / mfd / max77843-private.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Common variables for the Maxim MAX77843 driver
 *
 * Copyright (C) 2015 Samsung Electronics
 * Author: Jaewon Kim <[email protected]>
 * Author: Beomho Seo <[email protected]>
 */

#ifndef __MAX77843_PRIVATE_H_
#define __MAX77843_PRIVATE_H_

#include <linux/i2c.h>
#include <linux/regmap.h>

#define I2C_ADDR_TOPSYS	(0xCC >> 1)
#define I2C_ADDR_CHG	(0xD2 >> 1)
#define I2C_ADDR_FG	(0x6C >> 1)
#define I2C_ADDR_MUIC	(0x4A >> 1)

/* Topsys, Haptic and LED registers */
enum max77843_sys_reg {
	MAX77843_SYS_REG_PMICID		= 0x00,
	MAX77843_SYS_REG_PMICREV	= 0x01,
	MAX77843_SYS_REG_MAINCTRL1	= 0x02,
	MAX77843_SYS_REG_INTSRC		= 0x22,
	MAX77843_SYS_REG_INTSRCMASK	= 0x23,
	MAX77843_SYS_REG_SYSINTSRC	= 0x24,
	MAX77843_SYS_REG_SYSINTMASK	= 0x26,
	MAX77843_SYS_REG_TOPSYS_STAT	= 0x28,
	MAX77843_SYS_REG_SAFEOUTCTRL	= 0xC6,

	MAX77843_SYS_REG_END,
};

enum max77843_haptic_reg {
	MAX77843_HAP_REG_MCONFIG	= 0x10,

	MAX77843_HAP_REG_END,
};

enum max77843_led_reg {
	MAX77843_LED_REG_LEDEN		= 0x30,
	MAX77843_LED_REG_LED0BRT	= 0x31,
	MAX77843_LED_REG_LED1BRT	= 0x32,
	MAX77843_LED_REG_LED2BRT	= 0x33,
	MAX77843_LED_REG_LED3BRT	= 0x34,
	MAX77843_LED_REG_LEDBLNK	= 0x38,
	MAX77843_LED_REG_LEDRAMP	= 0x36,

	MAX77843_LED_REG_END,
};

/* Charger registers */
enum max77843_charger_reg {
	MAX77843_CHG_REG_CHG_INT	= 0xB0,
	MAX77843_CHG_REG_CHG_INT_MASK	= 0xB1,
	MAX77843_CHG_REG_CHG_INT_OK	= 0xB2,
	MAX77843_CHG_REG_CHG_DTLS_00	= 0xB3,
	MAX77843_CHG_REG_CHG_DTLS_01	= 0xB4,
	MAX77843_CHG_REG_CHG_DTLS_02	= 0xB5,
	MAX77843_CHG_REG_CHG_CNFG_00	= 0xB7,
	MAX77843_CHG_REG_CHG_CNFG_01	= 0xB8,
	MAX77843_CHG_REG_CHG_CNFG_02	= 0xB9,
	MAX77843_CHG_REG_CHG_CNFG_03	= 0xBA,
	MAX77843_CHG_REG_CHG_CNFG_04	= 0xBB,
	MAX77843_CHG_REG_CHG_CNFG_06	= 0xBD,
	MAX77843_CHG_REG_CHG_CNFG_07	= 0xBE,
	MAX77843_CHG_REG_CHG_CNFG_09	= 0xC0,
	MAX77843_CHG_REG_CHG_CNFG_10	= 0xC1,
	MAX77843_CHG_REG_CHG_CNFG_11	= 0xC2,
	MAX77843_CHG_REG_CHG_CNFG_12	= 0xC3,

	MAX77843_CHG_REG_END,
};

/* Fuel gauge registers */
enum max77843_fuelgauge {
	MAX77843_FG_REG_STATUS		= 0x00,
	MAX77843_FG_REG_VALRT_TH	= 0x01,
	MAX77843_FG_REG_TALRT_TH	= 0x02,
	MAX77843_FG_REG_SALRT_TH	= 0x03,
	MAX77843_FG_RATE_AT_RATE	= 0x04,
	MAX77843_FG_REG_REMCAP_REP	= 0x05,
	MAX77843_FG_REG_SOCREP		= 0x06,
	MAX77843_FG_REG_AGE		= 0x07,
	MAX77843_FG_REG_TEMP		= 0x08,
	MAX77843_FG_REG_VCELL		= 0x09,
	MAX77843_FG_REG_CURRENT		= 0x0A,
	MAX77843_FG_REG_AVG_CURRENT	= 0x0B,
	MAX77843_FG_REG_SOCMIX		= 0x0D,
	MAX77843_FG_REG_SOCAV		= 0x0E,
	MAX77843_FG_REG_REMCAP_MIX	= 0x0F,
	MAX77843_FG_REG_FULLCAP		= 0x10,
	MAX77843_FG_REG_AVG_TEMP	= 0x16,
	MAX77843_FG_REG_CYCLES		= 0x17,
	MAX77843_FG_REG_AVG_VCELL	= 0x19,
	MAX77843_FG_REG_CONFIG		= 0x1D,
	MAX77843_FG_REG_REMCAP_AV	= 0x1F,
	MAX77843_FG_REG_FULLCAP_NOM	= 0x23,
	MAX77843_FG_REG_MISCCFG		= 0x2B,
	MAX77843_FG_REG_RCOMP		= 0x38,
	MAX77843_FG_REG_FSTAT		= 0x3D,
	MAX77843_FG_REG_DQACC		= 0x45,
	MAX77843_FG_REG_DPACC		= 0x46,
	MAX77843_FG_REG_OCV		= 0xEE,
	MAX77843_FG_REG_VFOCV		= 0xFB,
	MAX77843_FG_SOCVF		= 0xFF,

	MAX77843_FG_END,
};

/* MUIC registers */
enum max77843_muic_reg {
	MAX77843_MUIC_REG_ID		= 0x00,
	MAX77843_MUIC_REG_INT1		= 0x01,
	MAX77843_MUIC_REG_INT2		= 0x02,
	MAX77843_MUIC_REG_INT3		= 0x03,
	MAX77843_MUIC_REG_STATUS1	= 0x04,
	MAX77843_MUIC_REG_STATUS2	= 0x05,
	MAX77843_MUIC_REG_STATUS3	= 0x06,
	MAX77843_MUIC_REG_INTMASK1	= 0x07,
	MAX77843_MUIC_REG_INTMASK2	= 0x08,
	MAX77843_MUIC_REG_INTMASK3	= 0x09,
	MAX77843_MUIC_REG_CDETCTRL1	= 0x0A,
	MAX77843_MUIC_REG_CDETCTRL2	= 0x0B,
	MAX77843_MUIC_REG_CONTROL1	= 0x0C,
	MAX77843_MUIC_REG_CONTROL2	= 0x0D,
	MAX77843_MUIC_REG_CONTROL3	= 0x0E,
	MAX77843_MUIC_REG_CONTROL4	= 0x16,
	MAX77843_MUIC_REG_HVCONTROL1	= 0x17,
	MAX77843_MUIC_REG_HVCONTROL2	= 0x18,

	MAX77843_MUIC_REG_END,
};

enum max77843_irq {
	/* Topsys: SYSTEM */
	MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
	MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,

	/* Charger: CHG_INT */
	MAX77843_CHG_IRQ_CHG_INT_BYP_I,
	MAX77843_CHG_IRQ_CHG_INT_BATP_I,
	MAX77843_CHG_IRQ_CHG_INT_BAT_I,
	MAX77843_CHG_IRQ_CHG_INT_CHG_I,
	MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
	MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
	MAX77843_CHG_IRQ_CHG_INT_AICL_I,

	MAX77843_IRQ_NUM,
};

enum max77843_irq_muic {
	/* MUIC: INT1 */
	MAX77843_MUIC_IRQ_INT1_ADC,
	MAX77843_MUIC_IRQ_INT1_ADCERROR,
	MAX77843_MUIC_IRQ_INT1_ADC1K,

	/* MUIC: INT2 */
	MAX77843_MUIC_IRQ_INT2_CHGTYP,
	MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
	MAX77843_MUIC_IRQ_INT2_DCDTMR,
	MAX77843_MUIC_IRQ_INT2_DXOVP,
	MAX77843_MUIC_IRQ_INT2_VBVOLT,

	/* MUIC: INT3 */
	MAX77843_MUIC_IRQ_INT3_VBADC,
	MAX77843_MUIC_IRQ_INT3_VDNMON,
	MAX77843_MUIC_IRQ_INT3_DNRES,
	MAX77843_MUIC_IRQ_INT3_MPNACK,
	MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
	MAX77843_MUIC_IRQ_INT3_MRXTRF,
	MAX77843_MUIC_IRQ_INT3_MRXPERR,
	MAX77843_MUIC_IRQ_INT3_MRXRDY,

	MAX77843_MUIC_IRQ_NUM,
};

/* MAX77843 interrupts */
#define MAX77843_SYS_IRQ_SYSUVLO_INT		BIT(0)
#define MAX77843_SYS_IRQ_SYSOVLO_INT		BIT(1)
#define MAX77843_SYS_IRQ_TSHDN_INT		BIT(2)
#define MAX77843_SYS_IRQ_TM_INT			BIT(3)

/* MAX77843 MAINCTRL1 register */
#define MAINCTRL1_BIASEN_SHIFT			7
#define MAX77843_MAINCTRL1_BIASEN_MASK		BIT(MAINCTRL1_BIASEN_SHIFT)

/* MAX77843 MCONFIG register */
#define MCONFIG_MODE_SHIFT			7
#define MCONFIG_MEN_SHIFT			6
#define MCONFIG_PDIV_SHIFT			0

#define MAX77843_MCONFIG_MODE_MASK		BIT(MCONFIG_MODE_SHIFT)
#define MAX77843_MCONFIG_MEN_MASK		BIT(MCONFIG_MEN_SHIFT)
#define MAX77843_MCONFIG_PDIV_MASK		(0x3 << MCONFIG_PDIV_SHIFT)

/* Max77843 charger insterrupts */
#define MAX77843_CHG_BYP_I			BIT(0)
#define MAX77843_CHG_BATP_I			BIT(2)
#define MAX77843_CHG_BAT_I			BIT(3)
#define MAX77843_CHG_CHG_I			BIT(4)
#define MAX77843_CHG_WCIN_I			BIT(5)
#define MAX77843_CHG_CHGIN_I			BIT(6)
#define MAX77843_CHG_AICL_I			BIT(7)

/* MAX77843 CHG_INT_OK register */
#define MAX77843_CHG_BYP_OK			BIT(0)
#define MAX77843_CHG_BATP_OK			BIT(2)
#define MAX77843_CHG_BAT_OK			BIT(3)
#define MAX77843_CHG_CHG_OK			BIT(4)
#define MAX77843_CHG_WCIN_OK			BIT(5)
#define MAX77843_CHG_CHGIN_OK			BIT(6)
#define MAX77843_CHG_AICL_OK			BIT(7)

/* MAX77843 CHG_DETAILS_00 register */
#define MAX77843_CHG_BAT_DTLS			BIT(0)

/* MAX77843 CHG_DETAILS_01 register */
#define MAX77843_CHG_DTLS_MASK			0x0f
#define MAX77843_CHG_PQ_MODE			0x00
#define MAX77843_CHG_CC_MODE			0x01
#define MAX77843_CHG_CV_MODE			0x02
#define MAX77843_CHG_TO_MODE			0x03
#define MAX77843_CHG_DO_MODE			0x04
#define MAX77843_CHG_HT_MODE			0x05
#define MAX77843_CHG_TF_MODE			0x06
#define MAX77843_CHG_TS_MODE			0x07
#define MAX77843_CHG_OFF_MODE			0x08

#define MAX77843_CHG_BAT_DTLS_MASK		0xf0
#define MAX77843_CHG_NO_BAT			(0x00 << 4)
#define MAX77843_CHG_LOW_VOLT_BAT		(0x01 << 4)
#define MAX77843_CHG_LONG_BAT_TIME		(0x02 << 4)
#define MAX77843_CHG_OK_BAT			(0x03 << 4)
#define MAX77843_CHG_OK_LOW_VOLT_BAT		(0x04 << 4)
#define MAX77843_CHG_OVER_VOLT_BAT		(0x05 << 4)
#define MAX77843_CHG_OVER_CURRENT_BAT		(0x06 << 4)

/* MAX77843 CHG_CNFG_00 register */
#define MAX77843_CHG_MODE_MASK			0x0f
#define MAX77843_CHG_DISABLE			0x00
#define MAX77843_CHG_ENABLE			0x05
#define MAX77843_CHG_MASK			0x01
#define MAX77843_CHG_OTG_MASK			0x02
#define MAX77843_CHG_BUCK_MASK			0x04
#define MAX77843_CHG_BOOST_MASK			0x08

/* MAX77843 CHG_CNFG_01 register */
#define MAX77843_CHG_RESTART_THRESHOLD_100	0x00
#define MAX77843_CHG_RESTART_THRESHOLD_150	0x10
#define MAX77843_CHG_RESTART_THRESHOLD_200	0x20
#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE	0x30

/* MAX77843 CHG_CNFG_02 register */
#define MAX77843_CHG_FAST_CHG_CURRENT_MIN	100000
#define MAX77843_CHG_FAST_CHG_CURRENT_MAX	3150000
#define MAX77843_CHG_FAST_CHG_CURRENT_STEP	50000
#define MAX77843_CHG_FAST_CHG_CURRENT_MASK	0x3f
#define MAX77843_CHG_OTG_ILIMIT_500		(0x00 << 6)
#define MAX77843_CHG_OTG_ILIMIT_900		(0x01 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1200		(0x02 << 6)
#define MAX77843_CHG_OTG_ILIMIT_1500		(0x03 << 6)
#define MAX77843_CHG_OTG_ILIMIT_MASK		0xc0

/* MAX77843 CHG_CNFG_03 register */
#define MAX77843_CHG_TOP_OFF_CURRENT_MIN	125000
#define MAX77843_CHG_TOP_OFF_CURRENT_MAX	650000
#define MAX77843_CHG_TOP_OFF_CURRENT_STEP	75000
#define MAX77843_CHG_TOP_OFF_CURRENT_MASK	0x07

/* MAX77843 CHG_CNFG_06 register */
#define MAX77843_CHG_WRITE_CAP_BLOCK		0x10
#define MAX77843_CHG_WRITE_CAP_UNBLOCK		0x0C

/* MAX77843_CHG_CNFG_09_register */
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN	100000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX	4000000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF	3367000
#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP	33000

#define MAX77843_MUIC_ADC			BIT(0)
#define MAX77843_MUIC_ADCERROR			BIT(2)
#define MAX77843_MUIC_ADC1K			BIT(3)

#define MAX77843_MUIC_CHGTYP			BIT(0)
#define MAX77843_MUIC_CHGDETRUN			BIT(1)
#define MAX77843_MUIC_DCDTMR			BIT(2)
#define MAX77843_MUIC_DXOVP			BIT(3)
#define MAX77843_MUIC_VBVOLT			BIT(4)

#define MAX77843_MUIC_VBADC			BIT(0)
#define MAX77843_MUIC_VDNMON			BIT(1)
#define MAX77843_MUIC_DNRES			BIT(2)
#define MAX77843_MUIC_MPNACK			BIT(3)
#define MAX77843_MUIC_MRXBUFOW			BIT(4)
#define MAX77843_MUIC_MRXTRF			BIT(5)
#define MAX77843_MUIC_MRXPERR			BIT(6)
#define MAX77843_MUIC_MRXRDY			BIT(7)

/* MAX77843 INTSRCMASK register */
#define MAX77843_INTSRCMASK_CHGR		0
#define MAX77843_INTSRCMASK_SYS			1
#define MAX77843_INTSRCMASK_FG			2
#define MAX77843_INTSRCMASK_MUIC		3

#define MAX77843_INTSRCMASK_CHGR_MASK          BIT(MAX77843_INTSRCMASK_CHGR)
#define MAX77843_INTSRCMASK_SYS_MASK           BIT(MAX77843_INTSRCMASK_SYS)
#define MAX77843_INTSRCMASK_FG_MASK            BIT(MAX77843_INTSRCMASK_FG)
#define MAX77843_INTSRCMASK_MUIC_MASK          BIT(MAX77843_INTSRCMASK_MUIC)

#define MAX77843_INTSRC_MASK_MASK \
	(MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
	MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)

/* MAX77843 STATUS register*/
#define MAX77843_MUIC_STATUS1_ADC_SHIFT		0
#define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT	6
#define MAX77843_MUIC_STATUS1_ADC1K_SHIFT	7
#define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT	0
#define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT	3
#define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT	4
#define MAX77843_MUIC_STATUS2_DXOVP_SHIFT	5
#define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT	6
#define MAX77843_MUIC_STATUS3_VBADC_SHIFT	0
#define MAX77843_MUIC_STATUS3_VDNMON_SHIFT	4
#define MAX77843_MUIC_STATUS3_DNRES_SHIFT	5
#define MAX77843_MUIC_STATUS3_MPNACK_SHIFT	6

#define MAX77843_MUIC_STATUS1_ADC_MASK		(0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT)
#define MAX77843_MUIC_STATUS1_ADCERROR_MASK	BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT)
#define MAX77843_MUIC_STATUS1_ADC1K_MASK	BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGTYP_MASK	(0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT)
#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK	BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT)
#define MAX77843_MUIC_STATUS2_DCDTMR_MASK	BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT)
#define MAX77843_MUIC_STATUS2_DXOVP_MASK	BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT)
#define MAX77843_MUIC_STATUS2_VBVOLT_MASK	BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT)
#define MAX77843_MUIC_STATUS3_VBADC_MASK	(0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT)
#define MAX77843_MUIC_STATUS3_VDNMON_MASK	BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT)
#define MAX77843_MUIC_STATUS3_DNRES_MASK	BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT)
#define MAX77843_MUIC_STATUS3_MPNACK_MASK	BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT)

/* MAX77843 CONTROL register */
#define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT	0
#define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT	3
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT	6
#define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT	7
#define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT	0
#define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT	1
#define MAX77843_MUIC_CONTROL2_CPEN_SHIFT	2
#define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT	5
#define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT	6
#define MAX77843_MUIC_CONTROL2_RCPS_SHIFT	7
#define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT	0
#define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT	0
#define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT	4
#define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT	5
#define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT	6

#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK	(0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK	(0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)
#define MAX77843_MUIC_CONTROL1_IDBEN_MASK	BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT)
#define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK	BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT)
#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK	BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT)
#define MAX77843_MUIC_CONTROL2_ADCEN_MASK	BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_CPEN_MASK	BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT)
#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK	BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT)
#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK	BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT)
#define MAX77843_MUIC_CONTROL2_RCPS_MASK	BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT)
#define MAX77843_MUIC_CONTROL3_JIGSET_MASK	(0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK	(0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT)
#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK	BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK	BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)
#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK	(0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT)

/* MAX77843 switch port */
#define COM_OPEN				0
#define COM_USB					1
#define COM_AUDIO				2
#define COM_UART				3
#define COM_AUX_USB				4
#define COM_AUX_UART				5

#define MAX77843_MUIC_CONTROL1_COM_SW \
	((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
	 MAX77843_MUIC_CONTROL1_COMP2SW_MASK))

#define MAX77843_MUIC_CONTROL1_SW_OPEN \
	((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_USB \
	((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUDIO \
	((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_UART \
	((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_USB \
	((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
#define MAX77843_MUIC_CONTROL1_SW_AUX_UART \
	((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \
	 COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))

#define MAX77843_DISABLE			0
#define MAX77843_ENABLE				1

#define CONTROL4_AUTO_DISABLE \
	((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
	(MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
#define CONTROL4_AUTO_ENABLE \
	((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \
	(MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))

/* MAX77843 SAFEOUT LDO Control register */
#define SAFEOUTCTRL_SAFEOUT1_SHIFT		0
#define SAFEOUTCTRL_SAFEOUT2_SHIFT		2
#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT		6
#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT		7

#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
		BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
		BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
		(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
		(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)

#endif /* __MAX77843_H__ */
Commit	Line	Data
d7d8d7a2	1	/* SPDX-License-Identifier: GPL-2.0+ */
c7f585fe JK	2	/*
	3	* Common variables for the Maxim MAX77843 driver
	4	*
	5	* Copyright (C) 2015 Samsung Electronics
	6	* Author: Jaewon Kim <[email protected]>
	7	* Author: Beomho Seo <[email protected]>
c7f585fe JK	8	*/
	9
	10	#ifndef __MAX77843_PRIVATE_H_
	11	#define __MAX77843_PRIVATE_H_
	12
	13	#include <linux/i2c.h>
	14	#include <linux/regmap.h>
	15
	16	#define I2C_ADDR_TOPSYS (0xCC >> 1)
	17	#define I2C_ADDR_CHG (0xD2 >> 1)
	18	#define I2C_ADDR_FG (0x6C >> 1)
	19	#define I2C_ADDR_MUIC (0x4A >> 1)
	20
	21	/* Topsys, Haptic and LED registers */
	22	enum max77843_sys_reg {
	23	MAX77843_SYS_REG_PMICID = 0x00,
	24	MAX77843_SYS_REG_PMICREV = 0x01,
	25	MAX77843_SYS_REG_MAINCTRL1 = 0x02,
	26	MAX77843_SYS_REG_INTSRC = 0x22,
	27	MAX77843_SYS_REG_INTSRCMASK = 0x23,
	28	MAX77843_SYS_REG_SYSINTSRC = 0x24,
	29	MAX77843_SYS_REG_SYSINTMASK = 0x26,
	30	MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
	31	MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
	32
	33	MAX77843_SYS_REG_END,
	34	};
	35
	36	enum max77843_haptic_reg {
	37	MAX77843_HAP_REG_MCONFIG = 0x10,
	38
	39	MAX77843_HAP_REG_END,
	40	};
	41
	42	enum max77843_led_reg {
	43	MAX77843_LED_REG_LEDEN = 0x30,
	44	MAX77843_LED_REG_LED0BRT = 0x31,
	45	MAX77843_LED_REG_LED1BRT = 0x32,
	46	MAX77843_LED_REG_LED2BRT = 0x33,
	47	MAX77843_LED_REG_LED3BRT = 0x34,
	48	MAX77843_LED_REG_LEDBLNK = 0x38,
	49	MAX77843_LED_REG_LEDRAMP = 0x36,
	50
	51	MAX77843_LED_REG_END,
	52	};
	53
	54	/* Charger registers */
	55	enum max77843_charger_reg {
	56	MAX77843_CHG_REG_CHG_INT = 0xB0,
	57	MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
	58	MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
	59	MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
	60	MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
	61	MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
	62	MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
	63	MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
	64	MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
	65	MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
	66	MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
	67	MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
	68	MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
	69	MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
	70	MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
	71	MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
72	MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
73
74	MAX77843_CHG_REG_END,
75	};
76
77	/* Fuel gauge registers */
78	enum max77843_fuelgauge {
79	MAX77843_FG_REG_STATUS = 0x00,
80	MAX77843_FG_REG_VALRT_TH = 0x01,
81	MAX77843_FG_REG_TALRT_TH = 0x02,
82	MAX77843_FG_REG_SALRT_TH = 0x03,
83	MAX77843_FG_RATE_AT_RATE = 0x04,
84	MAX77843_FG_REG_REMCAP_REP = 0x05,
85	MAX77843_FG_REG_SOCREP = 0x06,
86	MAX77843_FG_REG_AGE = 0x07,
87	MAX77843_FG_REG_TEMP = 0x08,
88	MAX77843_FG_REG_VCELL = 0x09,
89	MAX77843_FG_REG_CURRENT = 0x0A,
90	MAX77843_FG_REG_AVG_CURRENT = 0x0B,
91	MAX77843_FG_REG_SOCMIX = 0x0D,
92	MAX77843_FG_REG_SOCAV = 0x0E,
93	MAX77843_FG_REG_REMCAP_MIX = 0x0F,
94	MAX77843_FG_REG_FULLCAP = 0x10,
95	MAX77843_FG_REG_AVG_TEMP = 0x16,
96	MAX77843_FG_REG_CYCLES = 0x17,
97	MAX77843_FG_REG_AVG_VCELL = 0x19,
98	MAX77843_FG_REG_CONFIG = 0x1D,
99	MAX77843_FG_REG_REMCAP_AV = 0x1F,
100	MAX77843_FG_REG_FULLCAP_NOM = 0x23,
101	MAX77843_FG_REG_MISCCFG = 0x2B,
102	MAX77843_FG_REG_RCOMP = 0x38,
103	MAX77843_FG_REG_FSTAT = 0x3D,
104	MAX77843_FG_REG_DQACC = 0x45,
105	MAX77843_FG_REG_DPACC = 0x46,
106	MAX77843_FG_REG_OCV = 0xEE,
107	MAX77843_FG_REG_VFOCV = 0xFB,
108	MAX77843_FG_SOCVF = 0xFF,
109
110	MAX77843_FG_END,
111	};
112
113	/* MUIC registers */
114	enum max77843_muic_reg {
115	MAX77843_MUIC_REG_ID = 0x00,
116	MAX77843_MUIC_REG_INT1 = 0x01,
117	MAX77843_MUIC_REG_INT2 = 0x02,
118	MAX77843_MUIC_REG_INT3 = 0x03,
119	MAX77843_MUIC_REG_STATUS1 = 0x04,
120	MAX77843_MUIC_REG_STATUS2 = 0x05,
121	MAX77843_MUIC_REG_STATUS3 = 0x06,
122	MAX77843_MUIC_REG_INTMASK1 = 0x07,
123	MAX77843_MUIC_REG_INTMASK2 = 0x08,
124	MAX77843_MUIC_REG_INTMASK3 = 0x09,
125	MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
126	MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
127	MAX77843_MUIC_REG_CONTROL1 = 0x0C,
128	MAX77843_MUIC_REG_CONTROL2 = 0x0D,
129	MAX77843_MUIC_REG_CONTROL3 = 0x0E,
130	MAX77843_MUIC_REG_CONTROL4 = 0x16,
131	MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
132	MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
133
134	MAX77843_MUIC_REG_END,
135	};
136
137	enum max77843_irq {
138	/* Topsys: SYSTEM */
139	MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
140	MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
141	MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
142	MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
143
144	/* Charger: CHG_INT */
145	MAX77843_CHG_IRQ_CHG_INT_BYP_I,
146	MAX77843_CHG_IRQ_CHG_INT_BATP_I,
147	MAX77843_CHG_IRQ_CHG_INT_BAT_I,
148	MAX77843_CHG_IRQ_CHG_INT_CHG_I,
149	MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
150	MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
151	MAX77843_CHG_IRQ_CHG_INT_AICL_I,
152
153	MAX77843_IRQ_NUM,
154	};
155
156	enum max77843_irq_muic {
157	/* MUIC: INT1 */
158	MAX77843_MUIC_IRQ_INT1_ADC,
159	MAX77843_MUIC_IRQ_INT1_ADCERROR,
160	MAX77843_MUIC_IRQ_INT1_ADC1K,
161
162	/* MUIC: INT2 */
163	MAX77843_MUIC_IRQ_INT2_CHGTYP,
164	MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
165	MAX77843_MUIC_IRQ_INT2_DCDTMR,
166	MAX77843_MUIC_IRQ_INT2_DXOVP,
167	MAX77843_MUIC_IRQ_INT2_VBVOLT,
168
169	/* MUIC: INT3 */
170	MAX77843_MUIC_IRQ_INT3_VBADC,
171	MAX77843_MUIC_IRQ_INT3_VDNMON,
172	MAX77843_MUIC_IRQ_INT3_DNRES,
173	MAX77843_MUIC_IRQ_INT3_MPNACK,
174	MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
175	MAX77843_MUIC_IRQ_INT3_MRXTRF,
176	MAX77843_MUIC_IRQ_INT3_MRXPERR,
177	MAX77843_MUIC_IRQ_INT3_MRXRDY,
178
179	MAX77843_MUIC_IRQ_NUM,
180	};
181
182	/* MAX77843 interrupts */
183	#define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
184	#define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
185	#define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
186	#define MAX77843_SYS_IRQ_TM_INT BIT(3)
187
188	/* MAX77843 MAINCTRL1 register */
189	#define MAINCTRL1_BIASEN_SHIFT 7
190	#define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
191
192	/* MAX77843 MCONFIG register */
193	#define MCONFIG_MODE_SHIFT 7
194	#define MCONFIG_MEN_SHIFT 6
195	#define MCONFIG_PDIV_SHIFT 0
196
197	#define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
198	#define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
199	#define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
200
201	/* Max77843 charger insterrupts */
202	#define MAX77843_CHG_BYP_I BIT(0)
203	#define MAX77843_CHG_BATP_I BIT(2)
204	#define MAX77843_CHG_BAT_I BIT(3)
205	#define MAX77843_CHG_CHG_I BIT(4)
206	#define MAX77843_CHG_WCIN_I BIT(5)
207	#define MAX77843_CHG_CHGIN_I BIT(6)
208	#define MAX77843_CHG_AICL_I BIT(7)
209
210	/* MAX77843 CHG_INT_OK register */
211	#define MAX77843_CHG_BYP_OK BIT(0)
212	#define MAX77843_CHG_BATP_OK BIT(2)
213	#define MAX77843_CHG_BAT_OK BIT(3)
214	#define MAX77843_CHG_CHG_OK BIT(4)
215	#define MAX77843_CHG_WCIN_OK BIT(5)
216	#define MAX77843_CHG_CHGIN_OK BIT(6)
217	#define MAX77843_CHG_AICL_OK BIT(7)
218
219	/* MAX77843 CHG_DETAILS_00 register */
220	#define MAX77843_CHG_BAT_DTLS BIT(0)
221
222	/* MAX77843 CHG_DETAILS_01 register */
223	#define MAX77843_CHG_DTLS_MASK 0x0f
224	#define MAX77843_CHG_PQ_MODE 0x00
225	#define MAX77843_CHG_CC_MODE 0x01
226	#define MAX77843_CHG_CV_MODE 0x02
227	#define MAX77843_CHG_TO_MODE 0x03
228	#define MAX77843_CHG_DO_MODE 0x04
229	#define MAX77843_CHG_HT_MODE 0x05
230	#define MAX77843_CHG_TF_MODE 0x06
231	#define MAX77843_CHG_TS_MODE 0x07
232	#define MAX77843_CHG_OFF_MODE 0x08
233
234	#define MAX77843_CHG_BAT_DTLS_MASK 0xf0
235	#define MAX77843_CHG_NO_BAT (0x00 << 4)
236	#define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
237	#define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
238	#define MAX77843_CHG_OK_BAT (0x03 << 4)
239	#define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
240	#define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
241	#define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
242
243	/* MAX77843 CHG_CNFG_00 register */
7b965110	244	#define MAX77843_CHG_MODE_MASK 0x0f
c7f585fe JK	245	#define MAX77843_CHG_DISABLE 0x00
	246	#define MAX77843_CHG_ENABLE 0x05
	247	#define MAX77843_CHG_MASK 0x01
7b965110	248	#define MAX77843_CHG_OTG_MASK 0x02
c7f585fe	249	#define MAX77843_CHG_BUCK_MASK 0x04
7b965110	250	#define MAX77843_CHG_BOOST_MASK 0x08
c7f585fe JK	251
	252	/* MAX77843 CHG_CNFG_01 register */
	253	#define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
	254	#define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
	255	#define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
	256	#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
	257
	258	/* MAX77843 CHG_CNFG_02 register */
	259	#define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
	260	#define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
	261	#define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
	262	#define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
	263	#define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
	264	#define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
	265	#define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
	266	#define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
	267	#define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
	268
	269	/* MAX77843 CHG_CNFG_03 register */
	270	#define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
	271	#define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
	272	#define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
	273	#define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
	274
	275	/* MAX77843 CHG_CNFG_06 register */
	276	#define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
	277	#define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
	278
	279	/* MAX77843_CHG_CNFG_09_register */
	280	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
	281	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
	282	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
	283	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
	284
	285	#define MAX77843_MUIC_ADC BIT(0)
	286	#define MAX77843_MUIC_ADCERROR BIT(2)
	287	#define MAX77843_MUIC_ADC1K BIT(3)
	288
	289	#define MAX77843_MUIC_CHGTYP BIT(0)
	290	#define MAX77843_MUIC_CHGDETRUN BIT(1)
	291	#define MAX77843_MUIC_DCDTMR BIT(2)
	292	#define MAX77843_MUIC_DXOVP BIT(3)
	293	#define MAX77843_MUIC_VBVOLT BIT(4)
	294
	295	#define MAX77843_MUIC_VBADC BIT(0)
	296	#define MAX77843_MUIC_VDNMON BIT(1)
	297	#define MAX77843_MUIC_DNRES BIT(2)
	298	#define MAX77843_MUIC_MPNACK BIT(3)
	299	#define MAX77843_MUIC_MRXBUFOW BIT(4)
	300	#define MAX77843_MUIC_MRXTRF BIT(5)
	301	#define MAX77843_MUIC_MRXPERR BIT(6)
	302	#define MAX77843_MUIC_MRXRDY BIT(7)
	303
	304	/* MAX77843 INTSRCMASK register */
	305	#define MAX77843_INTSRCMASK_CHGR 0
	306	#define MAX77843_INTSRCMASK_SYS 1
	307	#define MAX77843_INTSRCMASK_FG 2
	308	#define MAX77843_INTSRCMASK_MUIC 3
	309
	310	#define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
	311	#define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
	312	#define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
	313	#define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
	314
315	#define MAX77843_INTSRC_MASK_MASK \
316	(MAX77843_INTSRCMASK_MUIC_MASK \| MAX77843_INTSRCMASK_FG_MASK \| \
317	MAX77843_INTSRCMASK_SYS_MASK \| MAX77843_INTSRCMASK_CHGR_MASK)
318
319	/* MAX77843 STATUS register*/
309a3e00 KK	320	#define MAX77843_MUIC_STATUS1_ADC_SHIFT 0
	321	#define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6
	322	#define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7
	323	#define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0
	324	#define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3
	325	#define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4
	326	#define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5
	327	#define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6
	328	#define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0
	329	#define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4
	330	#define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5
	331	#define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6
	332
	333	#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT)
	334	#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT)
	335	#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT)
	336	#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT)
	337	#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT)
	338	#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT)
	339	#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT)
	340	#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT)
	341	#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT)
	342	#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT)
	343	#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT)
	344	#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT)
c7f585fe JK	345
c7f585fe JK	346	/* MAX77843 CONTROL register */
309a3e00 KK	347	#define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0
309a3e00 KK	348	#define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3
4a4a8714	349	#define MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT 6
309a3e00 KK	350	#define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7
	351	#define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0
	352	#define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1
	353	#define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2
	354	#define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5
	355	#define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6
	356	#define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7
	357	#define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0
	358	#define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0
	359	#define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4
	360	#define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5
	361	#define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6
	362
	363	#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT)
	364	#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)
	365	#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT)
4a4a8714	366	#define MAX77843_MUIC_CONTROL1_NOBCCOMP_MASK BIT(MAX77843_MUIC_CONTROL1_NOBCCOMP_SHIFT)
309a3e00 KK	367	#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT)
	368	#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT)
	369	#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT)
	370	#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT)
	371	#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT)
	372	#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT)
	373	#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT)
	374	#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT)
	375	#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT)
	376	#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)
	377	#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT)
c7f585fe JK	378
	379	/* MAX77843 switch port */
	380	#define COM_OPEN 0
	381	#define COM_USB 1
	382	#define COM_AUDIO 2
	383	#define COM_UART 3
	384	#define COM_AUX_USB 4
	385	#define COM_AUX_UART 5
	386
309a3e00	387	#define MAX77843_MUIC_CONTROL1_COM_SW \
c7f585fe JK	388	((MAX77843_MUIC_CONTROL1_COMP1SW_MASK \| \
	389	MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
	390
309a3e00 KK	391	#define MAX77843_MUIC_CONTROL1_SW_OPEN \
	392	((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	393	COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
	394	#define MAX77843_MUIC_CONTROL1_SW_USB \
	395	((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	396	COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
	397	#define MAX77843_MUIC_CONTROL1_SW_AUDIO \
	398	((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	399	COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
	400	#define MAX77843_MUIC_CONTROL1_SW_UART \
	401	((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	402	COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
	403	#define MAX77843_MUIC_CONTROL1_SW_AUX_USB \
	404	((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	405	COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
	406	#define MAX77843_MUIC_CONTROL1_SW_AUX_UART \
	407	((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT \| \
	408	COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT))
c7f585fe JK	409
	410	#define MAX77843_DISABLE 0
	411	#define MAX77843_ENABLE 1
	412
	413	#define CONTROL4_AUTO_DISABLE \
309a3e00 KK	414	((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) \| \
309a3e00 KK	415	(MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
c7f585fe	416	#define CONTROL4_AUTO_ENABLE \
309a3e00 KK	417	((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) \| \
309a3e00 KK	418	(MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT))
c7f585fe JK	419
	420	/* MAX77843 SAFEOUT LDO Control register */
	421	#define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
	422	#define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
	423	#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
	424	#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
	425
	426	#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
	427	BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
	428	#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
	429	BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
	430	#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
	431	(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
	432	#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
	433	(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
	434
c7f585fe	435	#endif /* __MAX77843_H__ */