[linux.git] / drivers / gpio / gpio-zx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ZTE ZX296702 GPIO driver
 *
 * Author: Jun Nie <[email protected]>
 *
 * Copyright (C) 2015 Linaro Ltd.
 */
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define ZX_GPIO_DIR	0x00
#define ZX_GPIO_IVE	0x04
#define ZX_GPIO_IV	0x08
#define ZX_GPIO_IEP	0x0C
#define ZX_GPIO_IEN	0x10
#define ZX_GPIO_DI	0x14
#define ZX_GPIO_DO1	0x18
#define ZX_GPIO_DO0	0x1C
#define ZX_GPIO_DO	0x20

#define ZX_GPIO_IM	0x28
#define ZX_GPIO_IE	0x2C

#define ZX_GPIO_MIS	0x30
#define ZX_GPIO_IC	0x34

#define ZX_GPIO_NR	16

struct zx_gpio {
	raw_spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
};

static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	u16 gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	raw_spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	gpiodir &= ~BIT(offset);
	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
	raw_spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	u16 gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	raw_spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	gpiodir |= BIT(offset);
	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);

	if (value)
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	else
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
	raw_spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int zx_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);

	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
}

static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct zx_gpio *chip = gpiochip_get_data(gc);

	if (value)
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	else
		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
}

static int zx_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
	u16 bit = BIT(offset);

	if (offset < 0 || offset >= ZX_GPIO_NR)
		return -EINVAL;

	raw_spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= bit;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
	} else
		gpiois &= ~bit;

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		gpioi_epos |= bit;
		gpioi_eneg |= bit;
	} else {
		if (trigger & IRQ_TYPE_EDGE_RISING) {
			gpioi_epos |= bit;
			gpioi_eneg &= ~bit;
		} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
			gpioi_eneg |= bit;
			gpioi_epos &= ~bit;
		}
	}

	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
	raw_spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void zx_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
	if (pending) {
		for_each_set_bit(offset, &pending, ZX_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void zx_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	u16 gpioie;

	raw_spin_lock(&chip->lock);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	raw_spin_unlock(&chip->lock);
}

static void zx_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct zx_gpio *chip = gpiochip_get_data(gc);
	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	u16 gpioie;

	raw_spin_lock(&chip->lock);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
	raw_spin_unlock(&chip->lock);
}

static struct irq_chip zx_irqchip = {
	.name		= "zx-gpio",
	.irq_mask	= zx_irq_mask,
	.irq_unmask	= zx_irq_unmask,
	.irq_set_type	= zx_irq_type,
};

static int zx_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct zx_gpio *chip;
	int irq, id, ret;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	chip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(chip->base))
		return PTR_ERR(chip->base);

	raw_spin_lock_init(&chip->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		chip->gc.request = gpiochip_generic_request;
		chip->gc.free = gpiochip_generic_free;
	}

	id = of_alias_get_id(dev->of_node, "gpio");
	chip->gc.direction_input = zx_direction_input;
	chip->gc.direction_output = zx_direction_output;
	chip->gc.get = zx_get_value;
	chip->gc.set = zx_set_value;
	chip->gc.base = ZX_GPIO_NR * id;
	chip->gc.ngpio = ZX_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.parent = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add_data(&chip->gc, chip);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
	writew_relaxed(0, chip->base + ZX_GPIO_IE);
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "invalid IRQ\n");
		gpiochip_remove(&chip->gc);
		return -ENODEV;
	}

	ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
				   0, handle_simple_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "could not add irqchip\n");
		gpiochip_remove(&chip->gc);
		return ret;
	}
	gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
				     irq, zx_irq_handler);

	platform_set_drvdata(pdev, chip);
	dev_info(dev, "ZX GPIO chip registered\n");

	return 0;
}

static const struct of_device_id zx_gpio_match[] = {
	{
		.compatible = "zte,zx296702-gpio",
	},
	{ },
};

static struct platform_driver zx_gpio_driver = {
	.probe		= zx_gpio_probe,
	.driver = {
		.name	= "zx_gpio",
		.of_match_table = of_match_ptr(zx_gpio_match),
	},
};
builtin_platform_driver(zx_gpio_driver)
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
e7aa6d8c	2	/*
18fb0a98 PG	3	* ZTE ZX296702 GPIO driver
	4	*
	5	* Author: Jun Nie <[email protected]>
	6	*
e7aa6d8c	7	* Copyright (C) 2015 Linaro Ltd.
e7aa6d8c JN	8	*/
	9	#include <linux/bitops.h>
	10	#include <linux/device.h>
	11	#include <linux/errno.h>
	12	#include <linux/gpio/driver.h>
	13	#include <linux/irqchip/chained_irq.h>
18fb0a98	14	#include <linux/init.h>
e7aa6d8c JN	15	#include <linux/of.h>
	16	#include <linux/pinctrl/consumer.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pm.h>
	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21
	22	#define ZX_GPIO_DIR 0x00
	23	#define ZX_GPIO_IVE 0x04
	24	#define ZX_GPIO_IV 0x08
	25	#define ZX_GPIO_IEP 0x0C
	26	#define ZX_GPIO_IEN 0x10
	27	#define ZX_GPIO_DI 0x14
	28	#define ZX_GPIO_DO1 0x18
	29	#define ZX_GPIO_DO0 0x1C
	30	#define ZX_GPIO_DO 0x20
	31
	32	#define ZX_GPIO_IM 0x28
	33	#define ZX_GPIO_IE 0x2C
	34
	35	#define ZX_GPIO_MIS 0x30
	36	#define ZX_GPIO_IC 0x34
	37
	38	#define ZX_GPIO_NR 16
	39
	40	struct zx_gpio {
8c41ab4f	41	raw_spinlock_t lock;
e7aa6d8c JN	42
	43	void __iomem *base;
	44	struct gpio_chip gc;
e7aa6d8c JN	45	};
e7aa6d8c JN	46
e7aa6d8c JN	47	static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
e7aa6d8c JN	48	{
17758b04	49	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	50	unsigned long flags;
	51	u16 gpiodir;
	52
	53	if (offset >= gc->ngpio)
	54	return -EINVAL;
	55
8c41ab4f	56	raw_spin_lock_irqsave(&chip->lock, flags);
e7aa6d8c JN	57	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	58	gpiodir &= ~BIT(offset);
	59	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
8c41ab4f	60	raw_spin_unlock_irqrestore(&chip->lock, flags);
e7aa6d8c JN	61
	62	return 0;
	63	}
	64
	65	static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
	66	int value)
	67	{
17758b04	68	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	69	unsigned long flags;
	70	u16 gpiodir;
	71
	72	if (offset >= gc->ngpio)
	73	return -EINVAL;
	74
8c41ab4f	75	raw_spin_lock_irqsave(&chip->lock, flags);
e7aa6d8c JN	76	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
	77	gpiodir \|= BIT(offset);
	78	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
	79
	80	if (value)
	81	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	82	else
	83	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
8c41ab4f	84	raw_spin_unlock_irqrestore(&chip->lock, flags);
e7aa6d8c JN	85
	86	return 0;
	87	}
	88
	89	static int zx_get_value(struct gpio_chip *gc, unsigned offset)
	90	{
17758b04	91	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	92
	93	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
	94	}
	95
	96	static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
	97	{
17758b04	98	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	99
	100	if (value)
	101	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
	102	else
	103	writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
	104	}
	105
	106	static int zx_irq_type(struct irq_data *d, unsigned trigger)
	107	{
	108	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	109	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	110	int offset = irqd_to_hwirq(d);
	111	unsigned long flags;
	112	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
	113	u16 bit = BIT(offset);
	114
	115	if (offset < 0 \|\| offset >= ZX_GPIO_NR)
	116	return -EINVAL;
	117
8c41ab4f	118	raw_spin_lock_irqsave(&chip->lock, flags);
e7aa6d8c JN	119
	120	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
	121	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
	122	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
	123	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
	124
	125	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
	126	gpiois \|= bit;
	127	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	128	gpioiev \|= bit;
	129	else
	130	gpioiev &= ~bit;
	131	} else
	132	gpiois &= ~bit;
	133
	134	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	135	gpioi_epos \|= bit;
	136	gpioi_eneg \|= bit;
	137	} else {
	138	if (trigger & IRQ_TYPE_EDGE_RISING) {
	139	gpioi_epos \|= bit;
	140	gpioi_eneg &= ~bit;
	141	} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
	142	gpioi_eneg \|= bit;
	143	gpioi_epos &= ~bit;
	144	}
	145	}
	146
	147	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
	148	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
	149	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
	150	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
8c41ab4f	151	raw_spin_unlock_irqrestore(&chip->lock, flags);
e7aa6d8c JN	152
	153	return 0;
	154	}
	155
bd0b9ac4	156	static void zx_irq_handler(struct irq_desc *desc)
e7aa6d8c JN	157	{
	158	unsigned long pending;
	159	int offset;
	160	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
17758b04	161	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	162	struct irq_chip *irqchip = irq_desc_get_chip(desc);
	163
	164	chained_irq_enter(irqchip, desc);
	165
	166	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
	167	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
	168	if (pending) {
	169	for_each_set_bit(offset, &pending, ZX_GPIO_NR)
f0fbe7bc	170	generic_handle_irq(irq_find_mapping(gc->irq.domain,
e7aa6d8c JN	171	offset));
	172	}
	173
	174	chained_irq_exit(irqchip, desc);
	175	}
	176
	177	static void zx_irq_mask(struct irq_data *d)
	178	{
	179	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	180	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	181	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	182	u16 gpioie;
	183
8c41ab4f	184	raw_spin_lock(&chip->lock);
e7aa6d8c JN	185	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) \| mask;
	186	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	187	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
	188	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
8c41ab4f	189	raw_spin_unlock(&chip->lock);
e7aa6d8c JN	190	}
	191
	192	static void zx_irq_unmask(struct irq_data *d)
	193	{
	194	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
17758b04	195	struct zx_gpio *chip = gpiochip_get_data(gc);
e7aa6d8c JN	196	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
	197	u16 gpioie;
	198
8c41ab4f	199	raw_spin_lock(&chip->lock);
e7aa6d8c JN	200	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
	201	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
	202	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) \| mask;
	203	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
8c41ab4f	204	raw_spin_unlock(&chip->lock);
e7aa6d8c JN	205	}
	206
	207	static struct irq_chip zx_irqchip = {
	208	.name = "zx-gpio",
	209	.irq_mask = zx_irq_mask,
	210	.irq_unmask = zx_irq_unmask,
	211	.irq_set_type = zx_irq_type,
	212	};
	213
	214	static int zx_gpio_probe(struct platform_device *pdev)
	215	{
	216	struct device *dev = &pdev->dev;
	217	struct zx_gpio *chip;
e7aa6d8c JN	218	int irq, id, ret;
	219
	220	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	221	if (!chip)
	222	return -ENOMEM;
	223
8d86f985	224	chip->base = devm_platform_ioremap_resource(pdev, 0);
e7aa6d8c JN	225	if (IS_ERR(chip->base))
	226	return PTR_ERR(chip->base);
	227
8c41ab4f	228	raw_spin_lock_init(&chip->lock);
da4002ee JG	229	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
	230	chip->gc.request = gpiochip_generic_request;
	231	chip->gc.free = gpiochip_generic_free;
	232	}
e7aa6d8c JN	233
e7aa6d8c JN	234	id = of_alias_get_id(dev->of_node, "gpio");
e7aa6d8c JN	235	chip->gc.direction_input = zx_direction_input;
	236	chip->gc.direction_output = zx_direction_output;
	237	chip->gc.get = zx_get_value;
	238	chip->gc.set = zx_set_value;
	239	chip->gc.base = ZX_GPIO_NR * id;
	240	chip->gc.ngpio = ZX_GPIO_NR;
	241	chip->gc.label = dev_name(dev);
58383c78	242	chip->gc.parent = dev;
e7aa6d8c JN	243	chip->gc.owner = THIS_MODULE;
e7aa6d8c JN	244
17758b04	245	ret = gpiochip_add_data(&chip->gc, chip);
e7aa6d8c JN	246	if (ret)
	247	return ret;
	248
	249	/*
	250	* irq_chip support
	251	*/
	252	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
	253	writew_relaxed(0, chip->base + ZX_GPIO_IE);
	254	irq = platform_get_irq(pdev, 0);
	255	if (irq < 0) {
	256	dev_err(dev, "invalid IRQ\n");
	257	gpiochip_remove(&chip->gc);
	258	return -ENODEV;
	259	}
	260
	261	ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
	262	0, handle_simple_irq,
	263	IRQ_TYPE_NONE);
	264	if (ret) {
	265	dev_err(dev, "could not add irqchip\n");
	266	gpiochip_remove(&chip->gc);
	267	return ret;
	268	}
	269	gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
	270	irq, zx_irq_handler);
	271
	272	platform_set_drvdata(pdev, chip);
	273	dev_info(dev, "ZX GPIO chip registered\n");
	274
	275	return 0;
	276	}
	277
	278	static const struct of_device_id zx_gpio_match[] = {
	279	{
	280	.compatible = "zte,zx296702-gpio",
	281	},
	282	{ },
	283	};
e7aa6d8c JN	284
	285	static struct platform_driver zx_gpio_driver = {
	286	.probe = zx_gpio_probe,
	287	.driver = {
	288	.name = "zx_gpio",
	289	.of_match_table = of_match_ptr(zx_gpio_match),
	290	},
	291	};
18fb0a98	292	builtin_platform_driver(zx_gpio_driver)