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mac80211: Add define for TX headroom reserved by mac80211 itself.
[linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <[email protected]>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
d43c36dc 33#include <linux/sched.h>
b481de9c
ZY		 34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
dbb6654c 42#include "iwl-fh.h"
bddadf86 43#include "iwl-3945-fh.h"
600c0e11 44#include "iwl-commands.h"
17f841cd 45#include "iwl-sta.h"
b481de9c 46#include "iwl-3945.h"
e6148917 47#include "iwl-eeprom.h"
5d08cd1d 48#include "iwl-helpers.h"
5747d47f 49#include "iwl-core.h"
e932a609
JB		 50#include "iwl-led.h"
51#include "iwl-3945-led.h"
b481de9c
ZY		 52
53#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 64
65/*
66 * Parameter order:
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
68 *
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
71 *
72 */
d9829a67 73const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 74 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 86};
87
bb8c093b 88/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 89#define IWL_EVT_DISABLE (0)
90#define IWL_EVT_DISABLE_SIZE (1532/32)
91
92/**
bb8c093b 93 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 94 *
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 101void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 102{
b481de9c
ZY		 103 int i;
104 u32 base; /* SRAM address of event log header */
105 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
106 u32 array_size; /* # of u32 entries in array */
107 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
155 };
156
157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 158 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 159 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 160 return;
161 }
162
5d49f498
AK		 163 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 165
166 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 167 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 168 disable_ptr);
b481de9c 169 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 170 iwl_write_targ_mem(priv,
af7cca2a
TW		 171 disable_ptr + (i * sizeof(u32)),
172 evt_disable[i]);
b481de9c 173
b481de9c 174 } else {
e1623446
TW		 175 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 178 disable_ptr, array_size);
179 }
180
181}
182
17744ff6
TW		 183static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184{
185 int idx;
186
187 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
188 if (iwl3945_rates[idx].plcp == plcp)
189 return idx;
190 return -1;
191}
192
d08853a3 193#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 194#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
195
196static const char *iwl3945_get_tx_fail_reason(u32 status)
197{
198 switch (status & TX_STATUS_MSK) {
199 case TX_STATUS_SUCCESS:
200 return "SUCCESS";
201 TX_STATUS_ENTRY(SHORT_LIMIT);
202 TX_STATUS_ENTRY(LONG_LIMIT);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204 TX_STATUS_ENTRY(MGMNT_ABORT);
205 TX_STATUS_ENTRY(NEXT_FRAG);
206 TX_STATUS_ENTRY(LIFE_EXPIRE);
207 TX_STATUS_ENTRY(DEST_PS);
208 TX_STATUS_ENTRY(ABORTED);
209 TX_STATUS_ENTRY(BT_RETRY);
210 TX_STATUS_ENTRY(STA_INVALID);
211 TX_STATUS_ENTRY(FRAG_DROPPED);
212 TX_STATUS_ENTRY(TID_DISABLE);
213 TX_STATUS_ENTRY(FRAME_FLUSHED);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215 TX_STATUS_ENTRY(TX_LOCKED);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217 }
218
219 return "UNKNOWN";
220}
221#else
222static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223{
224 return "";
225}
226#endif
227
e6a9854b
JB		 228/*
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
231 * value
232 */
4a8a4322 233int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 234{
235 int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237 switch (priv->band) {
238 case IEEE80211_BAND_5GHZ:
239 if (rate == IWL_RATE_12M_INDEX)
240 next_rate = IWL_RATE_9M_INDEX;
241 else if (rate == IWL_RATE_6M_INDEX)
242 next_rate = IWL_RATE_6M_INDEX;
243 break;
7262796a
AM		 244 case IEEE80211_BAND_2GHZ:
245 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 246 iwl_is_associated(priv)) {
7262796a
AM		 247 if (rate == IWL_RATE_11M_INDEX)
248 next_rate = IWL_RATE_5M_INDEX;
249 }
e6a9854b 250 break;
7262796a 251
e6a9854b
JB		 252 default:
253 break;
254 }
255
256 return next_rate;
257}
258
91c066f2
TW		 259
260/**
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262 *
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
266 */
4a8a4322 267static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 268 int txq_id, int index)
269{
188cf6c7 270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 271 struct iwl_queue *q = &txq->q;
dbb6654c 272 struct iwl_tx_info *tx_info;
91c066f2
TW		 273
274 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 280 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 281 tx_info->skb[0] = NULL;
7aaa1d79 282 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 283 }
284
d20b3c65 285 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 286 (txq_id != IWL_CMD_QUEUE_NUM) &&
287 priv->mac80211_registered)
e4e72fb4 288 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 289}
290
291/**
292 * iwl3945_rx_reply_tx - Handle Tx response
293 */
4a8a4322 294static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 295 struct iwl_rx_mem_buffer *rxb)
91c066f2 296{
2f301227 297 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 298 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299 int txq_id = SEQ_TO_QUEUE(sequence);
300 int index = SEQ_TO_INDEX(sequence);
188cf6c7 301 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 302 struct ieee80211_tx_info *info;
91c066f2
TW		 303 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304 u32 status = le32_to_cpu(tx_resp->status);
305 int rate_idx;
74221d07 306 int fail;
91c066f2 307
625a381a 308 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 309 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 310 "is out of range [0-%d] %d %d\n", txq_id,
311 index, txq->q.n_bd, txq->q.write_ptr,
312 txq->q.read_ptr);
313 return;
314 }
315
e039fa4a 316 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 317 ieee80211_tx_info_clear_status(info);
318
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321 if (info->band == IEEE80211_BAND_5GHZ)
322 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324 fail = tx_resp->failure_frame;
74221d07
AM		 325
326 info->status.rates[0].idx = rate_idx;
327 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 328
91c066f2 329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 330 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331 IEEE80211_TX_STAT_ACK : 0;
91c066f2 332
e1623446 333 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 334 txq_id, iwl3945_get_tx_fail_reason(status), status,
335 tx_resp->rate, tx_resp->failure_frame);
336
e1623446 337 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 341 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 342}
343
344
345
b481de9c
ZY		 346/*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
b481de9c
ZY		 352 *****************************************************************************/
353
396887a2
DH		 354void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355 struct iwl_rx_mem_buffer *rxb)
b481de9c 356{
2f301227 357 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e1623446 358 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 359 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 360 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 361
f2c7e521 362 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c
ZY		 363}
364
17744ff6
TW		 365/******************************************************************************
366 *
367 * Misc. internal state and helper functions
368 *
369 ******************************************************************************/
d08853a3 370#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 371
372/**
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
374 *
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
378 */
d08853a3 379static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 380 struct iwl_rx_packet *pkt,
17744ff6
TW		 381 struct ieee80211_hdr *header, int group100)
382{
383 u32 to_us;
384 u32 print_summary = 0;
385 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
386 u32 hundred = 0;
387 u32 dataframe = 0;
fd7c8a40 388 __le16 fc;
17744ff6
TW		 389 u16 seq_ctl;
390 u16 channel;
391 u16 phy_flags;
392 u16 length;
393 u16 status;
394 u16 bcn_tmr;
395 u32 tsf_low;
396 u64 tsf;
397 u8 rssi;
398 u8 agc;
399 u16 sig_avg;
400 u16 noise_diff;
401 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
402 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
403 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
404 u8 *data = IWL_RX_DATA(pkt);
405
406 /* MAC header */
fd7c8a40 407 fc = header->frame_control;
17744ff6
TW		 408 seq_ctl = le16_to_cpu(header->seq_ctrl);
409
410 /* metadata */
411 channel = le16_to_cpu(rx_hdr->channel);
412 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
413 length = le16_to_cpu(rx_hdr->len);
414
415 /* end-of-frame status and timestamp */
416 status = le32_to_cpu(rx_end->status);
417 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
418 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
419 tsf = le64_to_cpu(rx_end->timestamp);
420
421 /* signal statistics */
422 rssi = rx_stats->rssi;
423 agc = rx_stats->agc;
424 sig_avg = le16_to_cpu(rx_stats->sig_avg);
425 noise_diff = le16_to_cpu(rx_stats->noise_diff);
426
427 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
428
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 431 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 433 dataframe = 1;
434 if (!group100)
435 print_summary = 1; /* print each frame */
436 else if (priv->framecnt_to_us < 100) {
437 priv->framecnt_to_us++;
438 print_summary = 0;
439 } else {
440 priv->framecnt_to_us = 0;
441 print_summary = 1;
442 hundred = 1;
443 }
444 } else {
445 /* print summary for all other frames */
446 print_summary = 1;
447 }
448
449 if (print_summary) {
450 char *title;
0ff1cca0 451 int rate;
17744ff6
TW		 452
453 if (hundred)
454 title = "100Frames";
fd7c8a40 455 else if (ieee80211_has_retry(fc))
17744ff6 456 title = "Retry";
fd7c8a40 457 else if (ieee80211_is_assoc_resp(fc))
17744ff6 458 title = "AscRsp";
fd7c8a40 459 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 460 title = "RasRsp";
fd7c8a40 461 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 462 title = "PrbRsp";
463 print_dump = 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc)) {
465 title = "Beacon";
466 print_dump = 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc))
468 title = "ATIM";
469 else if (ieee80211_is_auth(fc))
470 title = "Auth";
471 else if (ieee80211_is_deauth(fc))
472 title = "DeAuth";
473 else if (ieee80211_is_disassoc(fc))
474 title = "DisAssoc";
475 else
476 title = "Frame";
477
478 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
479 if (rate == -1)
480 rate = 0;
481 else
482 rate = iwl3945_rates[rate].ieee / 2;
483
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
487 if (dataframe)
e1623446 488 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 489 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 490 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 491 length, rssi, channel, rate);
492 else {
493 /* src/dst addresses assume managed mode */
e1623446 494 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
fd7c8a40 497 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 498 header->addr3[5], rssi,
499 tsf_low - priv->scan_start_tsf,
500 phy_flags, channel);
501 }
502 }
503 if (print_dump)
3d816c77 504 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 505}
d08853a3
SO		 506
507static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
508 struct iwl_rx_packet *pkt,
509 struct ieee80211_hdr *header, int group100)
510{
3d816c77 511 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 512 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
513}
514
17744ff6 515#else
4a8a4322 516static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 517 struct iwl_rx_packet *pkt,
17744ff6
TW		 518 struct ieee80211_hdr *header, int group100)
519{
520}
521#endif
522
4bd9b4f3 523/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 524static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 525 struct ieee80211_hdr *header)
526{
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv->iw_mode) {
05c914fe 530 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 533 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header->addr2, priv->bssid);
536 default:
537 return 1;
538 }
539}
17744ff6 540
4a8a4322 541static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 542 struct iwl_rx_mem_buffer *rxb,
12342c47 543 struct ieee80211_rx_status *stats)
b481de9c 544{
2f301227 545 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 546 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 547 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
548 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 549 u16 len = le16_to_cpu(rx_hdr->len);
550 struct sk_buff *skb;
551 int ret;
29b1b268 552 __le16 fc = hdr->frame_control;
b481de9c
ZY		 553
554 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 555 if (unlikely(len + IWL39_RX_FRAME_SIZE >
556 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 557 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 558 return;
559 }
560
561 /* We only process data packets if the interface is open */
562 if (unlikely(!priv->is_open)) {
e1623446
TW		 563 IWL_DEBUG_DROP_LIMIT(priv,
564 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 565 return;
566 }
b481de9c 567
a3b6bd5b 568 skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
2f301227
ZY		 569 if (!skb) {
570 IWL_ERR(priv, "alloc_skb failed\n");
571 return;
572 }
b481de9c 573
9c74d9fb 574 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 575 iwl_set_decrypted_flag(priv,
2f301227 576 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 577 le32_to_cpu(rx_end->status), stats);
578
a3b6bd5b 579 skb_reserve(skb, IWL_LINK_HDR_MAX);
2f301227
ZY		 580 skb_add_rx_frag(skb, 0, rxb->page,
581 (void *)rx_hdr->payload - (void *)pkt, len);
582
583 /* mac80211 currently doesn't support paged SKB. Convert it to
584 * linear SKB for management frame and data frame requires
585 * software decryption or software defragementation. */
29b1b268
ZY		 586 if (ieee80211_is_mgmt(fc) ||
587 ieee80211_has_protected(fc) ||
588 ieee80211_has_morefrags(fc) ||
2f301227
ZY		 589 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
590 ret = skb_linearize(skb);
591 else
592 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
593 0 : -ENOMEM;
594
595 if (ret) {
596 kfree_skb(skb);
597 goto out;
598 }
599
29b1b268
ZY		 600 /*
601 * XXX: We cannot touch the page and its virtual memory (pkt) after
602 * here. It might have already been freed by the above skb change.
603 */
22fdf3c9 604
29b1b268 605 iwl_update_stats(priv, false, fc, len);
2f301227 606 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 607
29b1b268 608 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 609 out:
610 priv->alloc_rxb_page--;
611 rxb->page = NULL;
b481de9c
ZY		 612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
2f301227 621 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
9024adf5 641 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c 648 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 649 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
650 rx_stats->phy_count);
b481de9c
ZY		 651 return;
652 }
653
654 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
655 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 656 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 657 return;
658 }
659
56decd3c 660
b481de9c
ZY		 661
662 /* Convert 3945's rssi indicator to dBm */
250bdd21 663 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 664
665 /* Set default noise value to -127 */
666 if (priv->last_rx_noise == 0)
667 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
668
669 /* 3945 provides noise info for OFDM frames only.
670 * sig_avg and noise_diff are measured by the 3945's digital signal
671 * processor (DSP), and indicate linear levels of signal level and
672 * distortion/noise within the packet preamble after
673 * automatic gain control (AGC). sig_avg should stay fairly
674 * constant if the radio's AGC is working well.
675 * Since these values are linear (not dB or dBm), linear
676 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
677 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
678 * to obtain noise level in dBm.
17744ff6 679 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 680 if (rx_stats_noise_diff) {
681 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 682 rx_status.noise = rx_status.signal -
17744ff6 683 iwl3945_calc_db_from_ratio(snr);
566bfe5a 684 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 685 rx_status.noise);
b481de9c
ZY		 686
687 /* If noise info not available, calculate signal quality indicator (%)
688 * using just the dBm signal level. */
689 } else {
17744ff6 690 rx_status.noise = priv->last_rx_noise;
566bfe5a 691 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 692 }
693
694
e1623446 695 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 696 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 697 rx_stats_sig_avg, rx_stats_noise_diff);
698
b481de9c
ZY		 699 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
700
bb8c093b 701 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 702
e1623446 703 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 704 network_packet ? '*' : ' ',
705 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 706 rx_status.signal, rx_status.signal,
707 rx_status.noise, rx_status.rate_idx);
b481de9c 708
d08853a3
SO		 709 /* Set "1" to report good data frames in groups of 100 */
710 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 711 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 712
713 if (network_packet) {
714 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
715 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 716 priv->last_rx_rssi = rx_status.signal;
17744ff6 717 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 718 }
719
12e5e22d 720 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 721}
722
7aaa1d79
SO		 723int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
724 struct iwl_tx_queue *txq,
725 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 726{
727 int count;
7aaa1d79 728 struct iwl_queue *q;
59606ffa 729 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 730
731 q = &txq->q;
59606ffa
SO		 732 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
733 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 734
735 if (reset)
736 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 737
738 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 739
740 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 741 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 742 NUM_TFD_CHUNKS);
743 return -EINVAL;
744 }
745
dbb6654c
WT		 746 tfd->tbs[count].addr = cpu_to_le32(addr);
747 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 748
749 count++;
750
751 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
752 TFD_CTL_PAD_SET(pad));
753
754 return 0;
755}
756
757/**
bb8c093b 758 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 759 *
760 * Does NOT advance any indexes
761 */
7aaa1d79 762void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 763{
59606ffa 764 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 765 int index = txq->q.read_ptr;
766 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 767 struct pci_dev *dev = priv->pci_dev;
768 int i;
769 int counter;
770
b481de9c 771 /* sanity check */
dbb6654c 772 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 773 if (counter > NUM_TFD_CHUNKS) {
15b1687c 774 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 775 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 776 return;
b481de9c
ZY		 777 }
778
fd9377ee
RC		 779 /* Unmap tx_cmd */
780 if (counter)
781 pci_unmap_single(dev,
c2acea8e
JB		 782 pci_unmap_addr(&txq->meta[index], mapping),
783 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 784 PCI_DMA_TODEVICE);
785
b481de9c
ZY		 786 /* unmap chunks if any */
787
788 for (i = 1; i < counter; i++) {
dbb6654c
WT		 789 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
790 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 791 if (txq->txb[txq->q.read_ptr].skb[0]) {
792 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
793 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 794 /* Can be called from interrupt context */
795 dev_kfree_skb_any(skb);
fc4b6853 796 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 797 }
798 }
799 }
7aaa1d79 800 return ;
b481de9c
ZY		 801}
802
b481de9c 803/**
bb8c093b 804 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 805 *
806*/
c2acea8e
JB		 807void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
808 struct iwl_device_cmd *cmd,
809 struct ieee80211_tx_info *info,
810 struct ieee80211_hdr *hdr,
811 int sta_id, int tx_id)
b481de9c 812{
e039fa4a 813 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 814 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 815 u16 rate_mask;
816 int rate;
817 u8 rts_retry_limit;
818 u8 data_retry_limit;
819 __le32 tx_flags;
fd7c8a40 820 __le16 fc = hdr->frame_control;
9744c91f 821 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 822
bb8c093b 823 rate = iwl3945_rates[rate_index].plcp;
9744c91f 824 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 825
826 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 827 * in this running context */
b481de9c
ZY		 828 rate_mask = IWL_RATES_MASK;
829
768db982
AK		 830
831 /* Set retry limit on DATA packets and Probe Responses*/
832 if (ieee80211_is_probe_resp(fc))
833 data_retry_limit = 3;
834 else
835 data_retry_limit = IWL_DEFAULT_TX_RETRY;
836 tx_cmd->data_retry_limit = data_retry_limit;
837
b481de9c
ZY		 838 if (tx_id >= IWL_CMD_QUEUE_NUM)
839 rts_retry_limit = 3;
840 else
841 rts_retry_limit = 7;
842
768db982
AK		 843 if (data_retry_limit < rts_retry_limit)
844 rts_retry_limit = data_retry_limit;
845 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 846
fd7c8a40
HH		 847 if (ieee80211_is_mgmt(fc)) {
848 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
849 case cpu_to_le16(IEEE80211_STYPE_AUTH):
850 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
851 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
852 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 853 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
854 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
855 tx_flags |= TX_CMD_FLG_CTS_MSK;
856 }
857 break;
858 default:
859 break;
860 }
861 }
862
9744c91f
AK		 863 tx_cmd->rate = rate;
864 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 865
866 /* OFDM */
9744c91f 867 tx_cmd->supp_rates[0] =
14577f23 868 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 869
870 /* CCK */
9744c91f 871 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 872
e1623446 873 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 874 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 875 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
876 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 877}
878
4a8a4322 879u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 880{
881 unsigned long flags_spin;
c587de0b 882 struct iwl_station_entry *station;
b481de9c
ZY		 883
884 if (sta_id == IWL_INVALID_STATION)
885 return IWL_INVALID_STATION;
886
887 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 888 station = &priv->stations[sta_id];
b481de9c
ZY		 889
890 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
891 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 892 station->sta.mode = STA_CONTROL_MODIFY_MSK;
893
894 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
895
c587de0b 896 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 897 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 898 sta_id, tx_rate);
899 return sta_id;
900}
901
854682ed 902static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 903{
854682ed 904 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 905 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 906 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 907 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
908 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 909
5d49f498 910 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 911 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
912 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 913 }
b481de9c 914 } else {
5d49f498 915 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 916 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
917 ~APMG_PS_CTRL_MSK_PWR_SRC);
918
5d49f498 919 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 920 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
921 }
b481de9c 922
a8b50a0a 923 return 0;
b481de9c
ZY		 924}
925
4a8a4322 926static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 927{
5d49f498 928 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 929 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 930 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
931 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 932 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
933 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
934 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
935 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
936 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
937 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
938 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
939 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 940
941 /* fake read to flush all prev I/O */
5d49f498 942 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 943
b481de9c
ZY		 944 return 0;
945}
946
4a8a4322 947static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 948{
b481de9c
ZY		 949
950 /* bypass mode */
5d49f498 951 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 952
953 /* RA 0 is active */
5d49f498 954 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 955
956 /* all 6 fifo are active */
5d49f498 957 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 958
5d49f498
AK		 959 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
960 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
961 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
962 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 963
5d49f498 964 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 965 priv->shared_phys);
b481de9c 966
5d49f498 967 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
970 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
971 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
972 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
973 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
974 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 975
b481de9c
ZY		 976
977 return 0;
978}
979
980/**
981 * iwl3945_txq_ctx_reset - Reset TX queue context
982 *
983 * Destroys all DMA structures and initialize them again
984 */
4a8a4322 985static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 986{
987 int rc;
988 int txq_id, slots_num;
989
bb8c093b 990 iwl3945_hw_txq_ctx_free(priv);
b481de9c 991
88804e2b
WYG		 992 /* allocate tx queue structure */
993 rc = iwl_alloc_txq_mem(priv);
994 if (rc)
995 return rc;
996
b481de9c
ZY		 997 /* Tx CMD queue */
998 rc = iwl3945_tx_reset(priv);
999 if (rc)
1000 goto error;
1001
1002 /* Tx queue(s) */
5905a1aa 1003 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 1004 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1005 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1006 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1007 txq_id);
b481de9c 1008 if (rc) {
15b1687c 1009 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1010 goto error;
1011 }
1012 }
1013
1014 return rc;
1015
1016 error:
bb8c093b 1017 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1018 return rc;
1019}
1020
fadb3582 1021
f33269b8 1022/*
fadb3582
BC		 1023 * Start up 3945's basic functionality after it has been reset
1024 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 1025 * NOTE: This does not load uCode nor start the embedded processor
1026 */
01ec616d 1027static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1028{
fadb3582 1029 int ret = iwl_apm_init(priv);
01ec616d 1030
f33269b8
BC		 1031 /* Clear APMG (NIC's internal power management) interrupts */
1032 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1033 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1034
1035 /* Reset radio chip */
1036 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1037 udelay(5);
1038 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1039
01ec616d
KA		 1040 return ret;
1041}
b481de9c 1042
01ec616d
KA		 1043static void iwl3945_nic_config(struct iwl_priv *priv)
1044{
e6148917 1045 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1046 unsigned long flags;
1047 u8 rev_id = 0;
b481de9c 1048
b481de9c
ZY		 1049 spin_lock_irqsave(&priv->lock, flags);
1050
43121432
AK		 1051 /* Determine HW type */
1052 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1053
1054 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1055
b481de9c 1056 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1057 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1058 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1059 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1060 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1061 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1062 } else {
e1623446 1063 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1064 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1065 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1066 }
1067
e6148917 1068 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1069 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1070 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1071 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1072 } else
e1623446 1073 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1074
e6148917 1075 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1076 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1077 eeprom->board_revision);
5d49f498 1078 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1079 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1080 } else {
e1623446 1081 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1082 eeprom->board_revision);
5d49f498 1083 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1084 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1085 }
1086
e6148917 1087 if (eeprom->almgor_m_version <= 1) {
5d49f498 1088 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1089 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1090 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1091 eeprom->almgor_m_version);
b481de9c 1092 } else {
e1623446 1093 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1094 eeprom->almgor_m_version);
5d49f498 1095 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1096 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1097 }
1098 spin_unlock_irqrestore(&priv->lock, flags);
1099
e6148917 1100 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1101 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1102
e6148917 1103 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1104 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1105}
1106
1107int iwl3945_hw_nic_init(struct iwl_priv *priv)
1108{
01ec616d
KA		 1109 int rc;
1110 unsigned long flags;
1111 struct iwl_rx_queue *rxq = &priv->rxq;
1112
1113 spin_lock_irqsave(&priv->lock, flags);
1114 priv->cfg->ops->lib->apm_ops.init(priv);
1115 spin_unlock_irqrestore(&priv->lock, flags);
1116
854682ed 1117 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1118 if (rc)
854682ed
KA		 1119 return rc;
1120
01ec616d 1121 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1122
1123 /* Allocate the RX queue, or reset if it is already allocated */
1124 if (!rxq->bd) {
51af3d3f 1125 rc = iwl_rx_queue_alloc(priv);
b481de9c 1126 if (rc) {
15b1687c 1127 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1128 return -ENOMEM;
1129 }
1130 } else
df833b1d 1131 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1132
bb8c093b 1133 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1134
1135 iwl3945_rx_init(priv, rxq);
1136
b481de9c
ZY		 1137
1138 /* Look at using this instead:
1139 rxq->need_update = 1;
141c43a3 1140 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1141 */
1142
5d49f498 1143 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1144
1145 rc = iwl3945_txq_ctx_reset(priv);
1146 if (rc)
1147 return rc;
1148
1149 set_bit(STATUS_INIT, &priv->status);
1150
1151 return 0;
1152}
1153
1154/**
bb8c093b 1155 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1156 *
1157 * Destroy all TX DMA queues and structures
1158 */
4a8a4322 1159void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1160{
1161 int txq_id;
1162
1163 /* Tx queues */
88804e2b
WYG		 1164 if (priv->txq)
1165 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1166 txq_id++)
1167 if (txq_id == IWL_CMD_QUEUE_NUM)
1168 iwl_cmd_queue_free(priv);
1169 else
1170 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1171
88804e2b
WYG		 1172 /* free tx queue structure */
1173 iwl_free_txq_mem(priv);
b481de9c
ZY		 1174}
1175
4a8a4322 1176void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1177{
bddadf86 1178 int txq_id;
b481de9c
ZY		 1179
1180 /* stop SCD */
5d49f498 1181 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1182 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1183
1184 /* reset TFD queues */
5905a1aa 1185 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1186 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1187 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1188 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1189 1000);
1190 }
1191
bb8c093b 1192 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1193}
1194
b481de9c 1195/**
bb8c093b 1196 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1197 * return index delta into power gain settings table
1198*/
bb8c093b 1199static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1200{
1201 return (new_reading - old_reading) * (-11) / 100;
1202}
1203
1204/**
bb8c093b 1205 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1206 */
bb8c093b 1207static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1208{
3ac7f146 1209 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1210}
1211
4a8a4322 1212int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1213{
5d49f498 1214 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1215}
1216
1217/**
bb8c093b 1218 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1219 * get the current temperature by reading from NIC
1220*/
4a8a4322 1221static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1222{
e6148917 1223 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1224 int temperature;
1225
bb8c093b 1226 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1227
1228 /* driver's okay range is -260 to +25.
1229 * human readable okay range is 0 to +285 */
e1623446 1230 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1231
1232 /* handle insane temp reading */
bb8c093b 1233 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1234 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1235
1236 /* if really really hot(?),
1237 * substitute the 3rd band/group's temp measured at factory */
1238 if (priv->last_temperature > 100)
e6148917 1239 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1240 else /* else use most recent "sane" value from driver */
1241 temperature = priv->last_temperature;
1242 }
1243
1244 return temperature; /* raw, not "human readable" */
1245}
1246
1247/* Adjust Txpower only if temperature variance is greater than threshold.
1248 *
1249 * Both are lower than older versions' 9 degrees */
1250#define IWL_TEMPERATURE_LIMIT_TIMER 6
1251
1252/**
1253 * is_temp_calib_needed - determines if new calibration is needed
1254 *
1255 * records new temperature in tx_mgr->temperature.
1256 * replaces tx_mgr->last_temperature *only* if calib needed
1257 * (assumes caller will actually do the calibration!). */
4a8a4322 1258static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1259{
1260 int temp_diff;
1261
bb8c093b 1262 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1263 temp_diff = priv->temperature - priv->last_temperature;
1264
1265 /* get absolute value */
1266 if (temp_diff < 0) {
e1623446 1267 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1268 temp_diff = -temp_diff;
1269 } else if (temp_diff == 0)
e1623446 1270 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1271 else
e1623446 1272 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1273
1274 /* if we don't need calibration, *don't* update last_temperature */
1275 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1276 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1277 return 0;
1278 }
1279
e1623446 1280 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1281
1282 /* assume that caller will actually do calib ...
1283 * update the "last temperature" value */
1284 priv->last_temperature = priv->temperature;
1285 return 1;
1286}
1287
1288#define IWL_MAX_GAIN_ENTRIES 78
1289#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1290#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1291
1292/* radio and DSP power table, each step is 1/2 dB.
1293 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1294static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1295 {
1296 {251, 127}, /* 2.4 GHz, highest power */
1297 {251, 127},
1298 {251, 127},
1299 {251, 127},
1300 {251, 125},
1301 {251, 110},
1302 {251, 105},
1303 {251, 98},
1304 {187, 125},
1305 {187, 115},
1306 {187, 108},
1307 {187, 99},
1308 {243, 119},
1309 {243, 111},
1310 {243, 105},
1311 {243, 97},
1312 {243, 92},
1313 {211, 106},
1314 {211, 100},
1315 {179, 120},
1316 {179, 113},
1317 {179, 107},
1318 {147, 125},
1319 {147, 119},
1320 {147, 112},
1321 {147, 106},
1322 {147, 101},
1323 {147, 97},
1324 {147, 91},
1325 {115, 107},
1326 {235, 121},
1327 {235, 115},
1328 {235, 109},
1329 {203, 127},
1330 {203, 121},
1331 {203, 115},
1332 {203, 108},
1333 {203, 102},
1334 {203, 96},
1335 {203, 92},
1336 {171, 110},
1337 {171, 104},
1338 {171, 98},
1339 {139, 116},
1340 {227, 125},
1341 {227, 119},
1342 {227, 113},
1343 {227, 107},
1344 {227, 101},
1345 {227, 96},
1346 {195, 113},
1347 {195, 106},
1348 {195, 102},
1349 {195, 95},
1350 {163, 113},
1351 {163, 106},
1352 {163, 102},
1353 {163, 95},
1354 {131, 113},
1355 {131, 106},
1356 {131, 102},
1357 {131, 95},
1358 {99, 113},
1359 {99, 106},
1360 {99, 102},
1361 {99, 95},
1362 {67, 113},
1363 {67, 106},
1364 {67, 102},
1365 {67, 95},
1366 {35, 113},
1367 {35, 106},
1368 {35, 102},
1369 {35, 95},
1370 {3, 113},
1371 {3, 106},
1372 {3, 102},
1373 {3, 95} }, /* 2.4 GHz, lowest power */
1374 {
1375 {251, 127}, /* 5.x GHz, highest power */
1376 {251, 120},
1377 {251, 114},
1378 {219, 119},
1379 {219, 101},
1380 {187, 113},
1381 {187, 102},
1382 {155, 114},
1383 {155, 103},
1384 {123, 117},
1385 {123, 107},
1386 {123, 99},
1387 {123, 92},
1388 {91, 108},
1389 {59, 125},
1390 {59, 118},
1391 {59, 109},
1392 {59, 102},
1393 {59, 96},
1394 {59, 90},
1395 {27, 104},
1396 {27, 98},
1397 {27, 92},
1398 {115, 118},
1399 {115, 111},
1400 {115, 104},
1401 {83, 126},
1402 {83, 121},
1403 {83, 113},
1404 {83, 105},
1405 {83, 99},
1406 {51, 118},
1407 {51, 111},
1408 {51, 104},
1409 {51, 98},
1410 {19, 116},
1411 {19, 109},
1412 {19, 102},
1413 {19, 98},
1414 {19, 93},
1415 {171, 113},
1416 {171, 107},
1417 {171, 99},
1418 {139, 120},
1419 {139, 113},
1420 {139, 107},
1421 {139, 99},
1422 {107, 120},
1423 {107, 113},
1424 {107, 107},
1425 {107, 99},
1426 {75, 120},
1427 {75, 113},
1428 {75, 107},
1429 {75, 99},
1430 {43, 120},
1431 {43, 113},
1432 {43, 107},
1433 {43, 99},
1434 {11, 120},
1435 {11, 113},
1436 {11, 107},
1437 {11, 99},
1438 {131, 107},
1439 {131, 99},
1440 {99, 120},
1441 {99, 113},
1442 {99, 107},
1443 {99, 99},
1444 {67, 120},
1445 {67, 113},
1446 {67, 107},
1447 {67, 99},
1448 {35, 120},
1449 {35, 113},
1450 {35, 107},
1451 {35, 99},
1452 {3, 120} } /* 5.x GHz, lowest power */
1453};
1454
bb8c093b 1455static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1456{
1457 if (index < 0)
1458 return 0;
1459 if (index >= IWL_MAX_GAIN_ENTRIES)
1460 return IWL_MAX_GAIN_ENTRIES - 1;
1461 return (u8) index;
1462}
1463
1464/* Kick off thermal recalibration check every 60 seconds */
1465#define REG_RECALIB_PERIOD (60)
1466
1467/**
bb8c093b 1468 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1469 *
1470 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1471 * or 6 Mbit (OFDM) rates.
1472 */
4a8a4322 1473static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1474 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1475 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1476 int band_index)
1477{
bb8c093b 1478 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1479 s8 power;
1480 u8 power_index;
1481
1482 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1483
1484 /* use this channel group's 6Mbit clipping/saturation pwr,
1485 * but cap at regulatory scan power restriction (set during init
1486 * based on eeprom channel data) for this channel. */
14577f23 1487 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1488
1489 /* further limit to user's max power preference.
1490 * FIXME: Other spectrum management power limitations do not
1491 * seem to apply?? */
62ea9c5b 1492 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1493 scan_power_info->requested_power = power;
1494
1495 /* find difference between new scan *power* and current "normal"
1496 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1497 * current "normal" temperature-compensated Tx power *index* for
1498 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1499 * *index*. */
1500 power_index = ch_info->power_info[rate_index].power_table_index
1501 - (power - ch_info->power_info
14577f23 1502 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1503
1504 /* store reference index that we use when adjusting *all* scan
1505 * powers. So we can accommodate user (all channel) or spectrum
1506 * management (single channel) power changes "between" temperature
1507 * feedback compensation procedures.
1508 * don't force fit this reference index into gain table; it may be a
1509 * negative number. This will help avoid errors when we're at
1510 * the lower bounds (highest gains, for warmest temperatures)
1511 * of the table. */
1512
1513 /* don't exceed table bounds for "real" setting */
bb8c093b 1514 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1515
1516 scan_power_info->power_table_index = power_index;
1517 scan_power_info->tpc.tx_gain =
1518 power_gain_table[band_index][power_index].tx_gain;
1519 scan_power_info->tpc.dsp_atten =
1520 power_gain_table[band_index][power_index].dsp_atten;
1521}
1522
1523/**
75bcfae9 1524 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1525 *
1526 * Configures power settings for all rates for the current channel,
1527 * using values from channel info struct, and send to NIC
1528 */
dfb39e82 1529static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1530{
14577f23 1531 int rate_idx, i;
d20b3c65 1532 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1533 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1534 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1535 };
1536
8318d78a 1537 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1538 ch_info = iwl_get_channel_info(priv,
8318d78a 1539 priv->band,
8ccde88a 1540 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1541 if (!ch_info) {
15b1687c
WT		 1542 IWL_ERR(priv,
1543 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1544 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1545 return -EINVAL;
1546 }
1547
1548 if (!is_channel_valid(ch_info)) {
e1623446 1549 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1550 "non-Tx channel.\n");
1551 return 0;
1552 }
1553
1554 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1555 /* Fill OFDM rate */
1556 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1557 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1558
1559 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1560 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1561
e1623446 1562 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1563 le16_to_cpu(txpower.channel),
1564 txpower.band,
14577f23
MA		 1565 txpower.power[i].tpc.tx_gain,
1566 txpower.power[i].tpc.dsp_atten,
1567 txpower.power[i].rate);
1568 }
1569 /* Fill CCK rates */
1570 for (rate_idx = IWL_FIRST_CCK_RATE;
1571 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1572 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1573 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1574
e1623446 1575 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1576 le16_to_cpu(txpower.channel),
1577 txpower.band,
1578 txpower.power[i].tpc.tx_gain,
1579 txpower.power[i].tpc.dsp_atten,
1580 txpower.power[i].rate);
b481de9c
ZY		 1581 }
1582
518099a8
SO		 1583 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1584 sizeof(struct iwl3945_txpowertable_cmd),
1585 &txpower);
b481de9c
ZY		 1586
1587}
1588
1589/**
bb8c093b 1590 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1591 * @ch_info: Channel to update. Uses power_info.requested_power.
1592 *
1593 * Replace requested_power and base_power_index ch_info fields for
1594 * one channel.
1595 *
1596 * Called if user or spectrum management changes power preferences.
1597 * Takes into account h/w and modulation limitations (clip power).
1598 *
1599 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1600 *
1601 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1602 * properly fill out the scan powers, and actual h/w gain settings,
1603 * and send changes to NIC
1604 */
4a8a4322 1605static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1606 struct iwl_channel_info *ch_info)
b481de9c 1607{
bb8c093b 1608 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1609 int power_changed = 0;
1610 int i;
1611 const s8 *clip_pwrs;
1612 int power;
1613
1614 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1615 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1616
1617 /* Get this channel's rate-to-current-power settings table */
1618 power_info = ch_info->power_info;
1619
1620 /* update OFDM Txpower settings */
14577f23 1621 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1622 i++, ++power_info) {
1623 int delta_idx;
1624
1625 /* limit new power to be no more than h/w capability */
1626 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1627 if (power == power_info->requested_power)
1628 continue;
1629
1630 /* find difference between old and new requested powers,
1631 * update base (non-temp-compensated) power index */
1632 delta_idx = (power - power_info->requested_power) * 2;
1633 power_info->base_power_index -= delta_idx;
1634
1635 /* save new requested power value */
1636 power_info->requested_power = power;
1637
1638 power_changed = 1;
1639 }
1640
1641 /* update CCK Txpower settings, based on OFDM 12M setting ...
1642 * ... all CCK power settings for a given channel are the *same*. */
1643 if (power_changed) {
1644 power =
14577f23 1645 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1646 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1647
bb8c093b 1648 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1649 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1650 power_info->requested_power = power;
1651 power_info->base_power_index =
14577f23 1652 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1653 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1654 ++power_info;
1655 }
1656 }
1657
1658 return 0;
1659}
1660
1661/**
bb8c093b 1662 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1663 *
1664 * NOTE: Returned power limit may be less (but not more) than requested,
1665 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1666 * (no consideration for h/w clipping limitations).
1667 */
d20b3c65 1668static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1669{
1670 s8 max_power;
1671
1672#if 0
1673 /* if we're using TGd limits, use lower of TGd or EEPROM */
1674 if (ch_info->tgd_data.max_power != 0)
1675 max_power = min(ch_info->tgd_data.max_power,
1676 ch_info->eeprom.max_power_avg);
1677
1678 /* else just use EEPROM limits */
1679 else
1680#endif
1681 max_power = ch_info->eeprom.max_power_avg;
1682
1683 return min(max_power, ch_info->max_power_avg);
1684}
1685
1686/**
bb8c093b 1687 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1688 *
1689 * Compensate txpower settings of *all* channels for temperature.
1690 * This only accounts for the difference between current temperature
1691 * and the factory calibration temperatures, and bases the new settings
1692 * on the channel's base_power_index.
1693 *
1694 * If RxOn is "associated", this sends the new Txpower to NIC!
1695 */
4a8a4322 1696static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1697{
d20b3c65 1698 struct iwl_channel_info *ch_info = NULL;
e6148917 1699 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1700 int delta_index;
1701 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1702 u8 a_band;
1703 u8 rate_index;
1704 u8 scan_tbl_index;
1705 u8 i;
1706 int ref_temp;
1707 int temperature = priv->temperature;
1708
1709 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1710 for (i = 0; i < priv->channel_count; i++) {
1711 ch_info = &priv->channel_info[i];
1712 a_band = is_channel_a_band(ch_info);
1713
1714 /* Get this chnlgrp's factory calibration temperature */
e6148917 1715 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1716 temperature;
1717
a96a27f9 1718 /* get power index adjustment based on current and factory
b481de9c 1719 * temps */
bb8c093b 1720 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1721 ref_temp);
1722
1723 /* set tx power value for all rates, OFDM and CCK */
1724 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1725 rate_index++) {
1726 int power_idx =
1727 ch_info->power_info[rate_index].base_power_index;
1728
1729 /* temperature compensate */
1730 power_idx += delta_index;
1731
1732 /* stay within table range */
bb8c093b 1733 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1734 ch_info->power_info[rate_index].
1735 power_table_index = (u8) power_idx;
1736 ch_info->power_info[rate_index].tpc =
1737 power_gain_table[a_band][power_idx];
1738 }
1739
1740 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1741 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1742
1743 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1744 for (scan_tbl_index = 0;
1745 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1746 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1747 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1748 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1749 actual_index, clip_pwrs,
1750 ch_info, a_band);
1751 }
1752 }
1753
1754 /* send Txpower command for current channel to ucode */
75bcfae9 1755 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1756}
1757
4a8a4322 1758int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1759{
d20b3c65 1760 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1761 s8 max_power;
1762 u8 a_band;
1763 u8 i;
1764
62ea9c5b 1765 if (priv->tx_power_user_lmt == power) {
e1623446 1766 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1767 "limit: %ddBm.\n", power);
1768 return 0;
1769 }
1770
e1623446 1771 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1772 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1773
1774 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1775
1776 for (i = 0; i < priv->channel_count; i++) {
1777 ch_info = &priv->channel_info[i];
1778 a_band = is_channel_a_band(ch_info);
1779
1780 /* find minimum power of all user and regulatory constraints
1781 * (does not consider h/w clipping limitations) */
bb8c093b 1782 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1783 max_power = min(power, max_power);
1784 if (max_power != ch_info->curr_txpow) {
1785 ch_info->curr_txpow = max_power;
1786
1787 /* this considers the h/w clipping limitations */
bb8c093b 1788 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1789 }
1790 }
1791
1792 /* update txpower settings for all channels,
1793 * send to NIC if associated. */
1794 is_temp_calib_needed(priv);
bb8c093b 1795 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1796
1797 return 0;
1798}
1799
5bbe233b
AK		 1800static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1801{
1802 int rc = 0;
2f301227 1803 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1804 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1805 struct iwl_host_cmd cmd = {
1806 .id = REPLY_RXON_ASSOC,
1807 .len = sizeof(rxon_assoc),
c2acea8e 1808 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1809 .data = &rxon_assoc,
1810 };
1811 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1812 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1813
1814 if ((rxon1->flags == rxon2->flags) &&
1815 (rxon1->filter_flags == rxon2->filter_flags) &&
1816 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1817 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1818 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1819 return 0;
1820 }
1821
1822 rxon_assoc.flags = priv->staging_rxon.flags;
1823 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1824 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1825 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1826 rxon_assoc.reserved = 0;
1827
1828 rc = iwl_send_cmd_sync(priv, &cmd);
1829 if (rc)
1830 return rc;
1831
2f301227
ZY		 1832 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1833 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1834 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1835 rc = -EIO;
1836 }
1837
2f301227
ZY		 1838 priv->alloc_rxb_page--;
1839 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
5bbe233b
AK		 1840
1841 return rc;
1842}
1843
e0158e61
AK		 1844/**
1845 * iwl3945_commit_rxon - commit staging_rxon to hardware
1846 *
1847 * The RXON command in staging_rxon is committed to the hardware and
1848 * the active_rxon structure is updated with the new data. This
1849 * function correctly transitions out of the RXON_ASSOC_MSK state if
1850 * a HW tune is required based on the RXON structure changes.
1851 */
1852static int iwl3945_commit_rxon(struct iwl_priv *priv)
1853{
1854 /* cast away the const for active_rxon in this function */
1855 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1856 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1857 int rc = 0;
1858 bool new_assoc =
1859 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1860
1861 if (!iwl_is_alive(priv))
1862 return -1;
1863
1864 /* always get timestamp with Rx frame */
1865 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1866
1867 /* select antenna */
1868 staging_rxon->flags &=
1869 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1870 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1871
1872 rc = iwl_check_rxon_cmd(priv);
1873 if (rc) {
1874 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1875 return -EINVAL;
1876 }
1877
1878 /* If we don't need to send a full RXON, we can use
1879 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1880 * and other flags for the current radio configuration. */
1881 if (!iwl_full_rxon_required(priv)) {
1882 rc = iwl_send_rxon_assoc(priv);
1883 if (rc) {
1884 IWL_ERR(priv, "Error setting RXON_ASSOC "
1885 "configuration (%d).\n", rc);
1886 return rc;
1887 }
1888
1889 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1890
1891 return 0;
1892 }
1893
1894 /* If we are currently associated and the new config requires
1895 * an RXON_ASSOC and the new config wants the associated mask enabled,
1896 * we must clear the associated from the active configuration
1897 * before we apply the new config */
1898 if (iwl_is_associated(priv) && new_assoc) {
1899 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1900 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1901
1902 /*
1903 * reserved4 and 5 could have been filled by the iwlcore code.
1904 * Let's clear them before pushing to the 3945.
1905 */
1906 active_rxon->reserved4 = 0;
1907 active_rxon->reserved5 = 0;
1908 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1909 sizeof(struct iwl3945_rxon_cmd),
1910 &priv->active_rxon);
1911
1912 /* If the mask clearing failed then we set
1913 * active_rxon back to what it was previously */
1914 if (rc) {
1915 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1916 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1917 "configuration (%d).\n", rc);
1918 return rc;
1919 }
1920 }
1921
1922 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1923 "* with%s RXON_FILTER_ASSOC_MSK\n"
1924 "* channel = %d\n"
1925 "* bssid = %pM\n",
1926 (new_assoc ? "" : "out"),
1927 le16_to_cpu(staging_rxon->channel),
1928 staging_rxon->bssid_addr);
1929
1930 /*
1931 * reserved4 and 5 could have been filled by the iwlcore code.
1932 * Let's clear them before pushing to the 3945.
1933 */
1934 staging_rxon->reserved4 = 0;
1935 staging_rxon->reserved5 = 0;
1936
90e8e424 1937 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1938
1939 /* Apply the new configuration */
1940 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1941 sizeof(struct iwl3945_rxon_cmd),
1942 staging_rxon);
1943 if (rc) {
1944 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1945 return rc;
1946 }
1947
1948 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1949
c587de0b 1950 iwl_clear_stations_table(priv);
e0158e61
AK		 1951
1952 /* If we issue a new RXON command which required a tune then we must
1953 * send a new TXPOWER command or we won't be able to Tx any frames */
1954 rc = priv->cfg->ops->lib->send_tx_power(priv);
1955 if (rc) {
1956 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1957 return rc;
1958 }
1959
1960 /* Add the broadcast address so we can send broadcast frames */
c587de0b 1961 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 1962 IWL_INVALID_STATION) {
1963 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1964 return -EIO;
1965 }
1966
1967 /* If we have set the ASSOC_MSK and we are in BSS mode then
1968 * add the IWL_AP_ID to the station rate table */
1969 if (iwl_is_associated(priv) &&
1970 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 1971 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1972 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 1973 IWL_ERR(priv, "Error adding AP address for transmit\n");
1974 return -EIO;
1975 }
1976
1977 /* Init the hardware's rate fallback order based on the band */
1978 rc = iwl3945_init_hw_rate_table(priv);
1979 if (rc) {
1980 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1981 return -EIO;
1982 }
1983
1984 return 0;
1985}
1986
b481de9c
ZY		 1987/**
1988 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1989 *
1990 * -- reset periodic timer
1991 * -- see if temp has changed enough to warrant re-calibration ... if so:
1992 * -- correct coeffs for temp (can reset temp timer)
1993 * -- save this temp as "last",
1994 * -- send new set of gain settings to NIC
1995 * NOTE: This should continue working, even when we're not associated,
1996 * so we can keep our internal table of scan powers current. */
4a8a4322 1997void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1998{
1999 /* This will kick in the "brute force"
bb8c093b 2000 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2001 if (!is_temp_calib_needed(priv))
2002 goto reschedule;
2003
2004 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2005 * This is based *only* on current temperature,
2006 * ignoring any previous power measurements */
bb8c093b 2007 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2008
2009 reschedule:
2010 queue_delayed_work(priv->workqueue,
2011 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2012}
2013
416e1438 2014static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2015{
4a8a4322 2016 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2017 thermal_periodic.work);
2018
2019 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2020 return;
2021
2022 mutex_lock(&priv->mutex);
2023 iwl3945_reg_txpower_periodic(priv);
2024 mutex_unlock(&priv->mutex);
2025}
2026
2027/**
bb8c093b 2028 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2029 * for the channel.
2030 *
2031 * This function is used when initializing channel-info structs.
2032 *
2033 * NOTE: These channel groups do *NOT* match the bands above!
2034 * These channel groups are based on factory-tested channels;
2035 * on A-band, EEPROM's "group frequency" entries represent the top
2036 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2037 */
4a8a4322 2038static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2039 const struct iwl_channel_info *ch_info)
b481de9c 2040{
e6148917
SO		 2041 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2042 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2043 u8 group;
2044 u16 group_index = 0; /* based on factory calib frequencies */
2045 u8 grp_channel;
2046
2047 /* Find the group index for the channel ... don't use index 1(?) */
2048 if (is_channel_a_band(ch_info)) {
2049 for (group = 1; group < 5; group++) {
2050 grp_channel = ch_grp[group].group_channel;
2051 if (ch_info->channel <= grp_channel) {
2052 group_index = group;
2053 break;
2054 }
2055 }
2056 /* group 4 has a few channels *above* its factory cal freq */
2057 if (group == 5)
2058 group_index = 4;
2059 } else
2060 group_index = 0; /* 2.4 GHz, group 0 */
2061
e1623446 2062 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2063 group_index);
2064 return group_index;
2065}
2066
2067/**
bb8c093b 2068 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2069 *
2070 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2071 * into radio/DSP gain settings table for requested power.
2072 */
4a8a4322 2073static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2074 s8 requested_power,
2075 s32 setting_index, s32 *new_index)
2076{
bb8c093b 2077 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2078 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2079 s32 index0, index1;
2080 s32 power = 2 * requested_power;
2081 s32 i;
bb8c093b 2082 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2083 s32 gains0, gains1;
2084 s32 res;
2085 s32 denominator;
2086
e6148917 2087 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2088 samples = chnl_grp->samples;
2089 for (i = 0; i < 5; i++) {
2090 if (power == samples[i].power) {
2091 *new_index = samples[i].gain_index;
2092 return 0;
2093 }
2094 }
2095
2096 if (power > samples[1].power) {
2097 index0 = 0;
2098 index1 = 1;
2099 } else if (power > samples[2].power) {
2100 index0 = 1;
2101 index1 = 2;
2102 } else if (power > samples[3].power) {
2103 index0 = 2;
2104 index1 = 3;
2105 } else {
2106 index0 = 3;
2107 index1 = 4;
2108 }
2109
2110 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2111 if (denominator == 0)
2112 return -EINVAL;
2113 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2114 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2115 res = gains0 + (gains1 - gains0) *
2116 ((s32) power - (s32) samples[index0].power) / denominator +
2117 (1 << 18);
2118 *new_index = res >> 19;
2119 return 0;
2120}
2121
4a8a4322 2122static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2123{
2124 u32 i;
2125 s32 rate_index;
e6148917 2126 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2127 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2128
e1623446 2129 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2130
2131 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2132 s8 *clip_pwrs; /* table of power levels for each rate */
2133 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2134 group = &eeprom->groups[i];
b481de9c
ZY		 2135
2136 /* sanity check on factory saturation power value */
2137 if (group->saturation_power < 40) {
39aadf8c 2138 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2139 "less than minimum expected 40\n",
2140 group->saturation_power);
2141 return;
2142 }
2143
2144 /*
2145 * Derive requested power levels for each rate, based on
2146 * hardware capabilities (saturation power for band).
2147 * Basic value is 3dB down from saturation, with further
2148 * power reductions for highest 3 data rates. These
2149 * backoffs provide headroom for high rate modulation
2150 * power peaks, without too much distortion (clipping).
2151 */
2152 /* we'll fill in this array with h/w max power levels */
f2c7e521 2153 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2154
2155 /* divide factory saturation power by 2 to find -3dB level */
2156 satur_pwr = (s8) (group->saturation_power >> 1);
2157
2158 /* fill in channel group's nominal powers for each rate */
2159 for (rate_index = 0;
2160 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2161 switch (rate_index) {
14577f23 2162 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2163 if (i == 0) /* B/G */
2164 *clip_pwrs = satur_pwr;
2165 else /* A */
2166 *clip_pwrs = satur_pwr - 5;
2167 break;
14577f23 2168 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2169 if (i == 0)
2170 *clip_pwrs = satur_pwr - 7;
2171 else
2172 *clip_pwrs = satur_pwr - 10;
2173 break;
14577f23 2174 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2175 if (i == 0)
2176 *clip_pwrs = satur_pwr - 9;
2177 else
2178 *clip_pwrs = satur_pwr - 12;
2179 break;
2180 default:
2181 *clip_pwrs = satur_pwr;
2182 break;
2183 }
2184 }
2185 }
2186}
2187
2188/**
2189 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2190 *
2191 * Second pass (during init) to set up priv->channel_info
2192 *
2193 * Set up Tx-power settings in our channel info database for each VALID
2194 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2195 * and current temperature.
2196 *
2197 * Since this is based on current temperature (at init time), these values may
2198 * not be valid for very long, but it gives us a starting/default point,
2199 * and allows us to active (i.e. using Tx) scan.
2200 *
2201 * This does *not* write values to NIC, just sets up our internal table.
2202 */
4a8a4322 2203int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2204{
d20b3c65 2205 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2206 struct iwl3945_channel_power_info *pwr_info;
e6148917 2207 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2208 int delta_index;
2209 u8 rate_index;
2210 u8 scan_tbl_index;
2211 const s8 *clip_pwrs; /* array of power levels for each rate */
2212 u8 gain, dsp_atten;
2213 s8 power;
2214 u8 pwr_index, base_pwr_index, a_band;
2215 u8 i;
2216 int temperature;
2217
2218 /* save temperature reference,
2219 * so we can determine next time to calibrate */
bb8c093b 2220 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2221 priv->last_temperature = temperature;
2222
bb8c093b 2223 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2224
2225 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2226 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2227 i++, ch_info++) {
2228 a_band = is_channel_a_band(ch_info);
2229 if (!is_channel_valid(ch_info))
2230 continue;
2231
2232 /* find this channel's channel group (*not* "band") index */
2233 ch_info->group_index =
bb8c093b 2234 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2235
2236 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2237 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2238
2239 /* calculate power index *adjustment* value according to
2240 * diff between current temperature and factory temperature */
bb8c093b 2241 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2242 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2243 temperature);
2244
e1623446 2245 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2246 ch_info->channel, delta_index, temperature +
2247 IWL_TEMP_CONVERT);
2248
2249 /* set tx power value for all OFDM rates */
2250 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2251 rate_index++) {
25a4ccea 2252 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2253 int rc;
2254
2255 /* use channel group's clip-power table,
2256 * but don't exceed channel's max power */
2257 s8 pwr = min(ch_info->max_power_avg,
2258 clip_pwrs[rate_index]);
2259
2260 pwr_info = &ch_info->power_info[rate_index];
2261
2262 /* get base (i.e. at factory-measured temperature)
2263 * power table index for this rate's power */
bb8c093b 2264 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2265 ch_info->group_index,
2266 &power_idx);
2267 if (rc) {
15b1687c 2268 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2269 return rc;
2270 }
2271 pwr_info->base_power_index = (u8) power_idx;
2272
2273 /* temperature compensate */
2274 power_idx += delta_index;
2275
2276 /* stay within range of gain table */
bb8c093b 2277 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2278
bb8c093b 2279 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2280 pwr_info->requested_power = pwr;
2281 pwr_info->power_table_index = (u8) power_idx;
2282 pwr_info->tpc.tx_gain =
2283 power_gain_table[a_band][power_idx].tx_gain;
2284 pwr_info->tpc.dsp_atten =
2285 power_gain_table[a_band][power_idx].dsp_atten;
2286 }
2287
2288 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2289 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2290 power = pwr_info->requested_power +
2291 IWL_CCK_FROM_OFDM_POWER_DIFF;
2292 pwr_index = pwr_info->power_table_index +
2293 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2294 base_pwr_index = pwr_info->base_power_index +
2295 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2296
2297 /* stay within table range */
bb8c093b 2298 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2299 gain = power_gain_table[a_band][pwr_index].tx_gain;
2300 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2301
bb8c093b 2302 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2303 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2304 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2305 for (rate_index = 0;
2306 rate_index < IWL_CCK_RATES; rate_index++) {
2307 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2308 pwr_info->requested_power = power;
2309 pwr_info->power_table_index = pwr_index;
2310 pwr_info->base_power_index = base_pwr_index;
2311 pwr_info->tpc.tx_gain = gain;
2312 pwr_info->tpc.dsp_atten = dsp_atten;
2313 }
2314
2315 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2316 for (scan_tbl_index = 0;
2317 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2318 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2319 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2320 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2321 actual_index, clip_pwrs, ch_info, a_band);
2322 }
2323 }
2324
2325 return 0;
2326}
2327
4a8a4322 2328int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2329{
2330 int rc;
b481de9c 2331
5d49f498
AK		 2332 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2333 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2334 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2335 if (rc < 0)
15b1687c 2336 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2337
b481de9c
ZY		 2338 return 0;
2339}
2340
188cf6c7 2341int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2342{
b481de9c
ZY		 2343 int txq_id = txq->q.id;
2344
3832ec9d 2345 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2346
2347 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2348
5d49f498
AK		 2349 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2350 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2351
5d49f498 2352 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2353 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2357 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2358
2359 /* fake read to flush all prev. writes */
5d49f498 2360 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2361
2362 return 0;
2363}
2364
42427b4e
KA		 2365/*
2366 * HCMD utils
2367 */
2368static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2369{
2370 switch (cmd_id) {
2371 case REPLY_RXON:
d25aabb0
WT		 2372 return sizeof(struct iwl3945_rxon_cmd);
2373 case POWER_TABLE_CMD:
2374 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2375 default:
2376 return len;
2377 }
2378}
2379
c587de0b 2380
17f841cd
SO		 2381static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2382{
c587de0b
TW		 2383 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2384 addsta->mode = cmd->mode;
2385 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2386 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2387 addsta->station_flags = cmd->station_flags;
2388 addsta->station_flags_msk = cmd->station_flags_msk;
2389 addsta->tid_disable_tx = cpu_to_le16(0);
2390 addsta->rate_n_flags = cmd->rate_n_flags;
2391 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2392 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2393 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2394
2395 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2396}
2397
c587de0b 2398
b481de9c
ZY		 2399/**
2400 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2401 */
4a8a4322 2402int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2403{
14577f23 2404 int rc, i, index, prev_index;
bb8c093b 2405 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2406 .reserved = {0, 0, 0},
2407 };
bb8c093b 2408 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2409
bb8c093b
CH		 2410 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2411 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2412
2413 table[index].rate_n_flags =
bb8c093b 2414 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2415 table[index].try_cnt = priv->retry_rate;
bb8c093b 2416 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2417 table[index].next_rate_index =
2418 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2419 }
2420
8318d78a
JB		 2421 switch (priv->band) {
2422 case IEEE80211_BAND_5GHZ:
e1623446 2423 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2424 /* If one of the following CCK rates is used,
2425 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2426 for (i = IWL_RATE_1M_INDEX_TABLE;
2427 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2428 table[i].next_rate_index =
2429 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2430
2431 /* Don't fall back to CCK rates */
7262796a
AM		 2432 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2433 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2434
2435 /* Don't drop out of OFDM rates */
14577f23 2436 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2437 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2438 break;
2439
8318d78a 2440 case IEEE80211_BAND_2GHZ:
e1623446 2441 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2442 /* If an OFDM rate is used, have it fall back to the
2443 * 1M CCK rates */
b481de9c 2444
7262796a 2445 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2446 iwl_is_associated(priv)) {
7262796a
AM		 2447
2448 index = IWL_FIRST_CCK_RATE;
2449 for (i = IWL_RATE_6M_INDEX_TABLE;
2450 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2451 table[i].next_rate_index =
2452 iwl3945_rates[index].table_rs_index;
2453
2454 index = IWL_RATE_11M_INDEX_TABLE;
2455 /* CCK shouldn't fall back to OFDM... */
2456 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2457 }
b481de9c
ZY		 2458 break;
2459
2460 default:
8318d78a 2461 WARN_ON(1);
b481de9c
ZY		 2462 break;
2463 }
2464
2465 /* Update the rate scaling for control frame Tx */
2466 rate_cmd.table_id = 0;
518099a8 2467 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2468 &rate_cmd);
2469 if (rc)
2470 return rc;
2471
2472 /* Update the rate scaling for data frame Tx */
2473 rate_cmd.table_id = 1;
518099a8 2474 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2475 &rate_cmd);
2476}
2477
796083cb 2478/* Called when initializing driver */
4a8a4322 2479int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2480{
3832ec9d
AK		 2481 memset((void *)&priv->hw_params, 0,
2482 sizeof(struct iwl_hw_params));
b481de9c 2483
3832ec9d 2484 priv->shared_virt =
b481de9c 2485 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2486 sizeof(struct iwl3945_shared),
3832ec9d 2487 &priv->shared_phys);
b481de9c 2488
3832ec9d 2489 if (!priv->shared_virt) {
15b1687c 2490 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2491 mutex_unlock(&priv->mutex);
2492 return -ENOMEM;
2493 }
2494
21c02a1a 2495 /* Assign number of Usable TX queues */
88804e2b 2496 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2497
a8e74e27 2498 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2499 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2500 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2501 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2502 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2503 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2504
141c43a3 2505 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2506 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2507
b481de9c
ZY		 2508 return 0;
2509}
2510
4a8a4322 2511unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2512 struct iwl3945_frame *frame, u8 rate)
b481de9c 2513{
bb8c093b 2514 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2515 unsigned int frame_size;
2516
bb8c093b 2517 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2518 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2519
3832ec9d 2520 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2521 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2522
bb8c093b 2523 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2524 tx_beacon_cmd->frame,
b481de9c
ZY		 2525 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2526
2527 BUG_ON(frame_size > MAX_MPDU_SIZE);
2528 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2529
2530 tx_beacon_cmd->tx.rate = rate;
2531 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2532 TX_CMD_FLG_TSF_MSK);
2533
14577f23
MA		 2534 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2535 tx_beacon_cmd->tx.supp_rates[0] =
2536 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2537
b481de9c 2538 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2539 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2540
3ac7f146 2541 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2542}
2543
4a8a4322 2544void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2545{
91c066f2 2546 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2547 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2548}
2549
4a8a4322 2550void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2551{
2552 INIT_DELAYED_WORK(&priv->thermal_periodic,
2553 iwl3945_bg_reg_txpower_periodic);
2554}
2555
4a8a4322 2556void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2557{
2558 cancel_delayed_work(&priv->thermal_periodic);
2559}
2560
0164b9b4
KA		 2561/* check contents of special bootstrap uCode SRAM */
2562static int iwl3945_verify_bsm(struct iwl_priv *priv)
2563 {
2564 __le32 *image = priv->ucode_boot.v_addr;
2565 u32 len = priv->ucode_boot.len;
2566 u32 reg;
2567 u32 val;
2568
e1623446 2569 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2570
2571 /* verify BSM SRAM contents */
2572 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2573 for (reg = BSM_SRAM_LOWER_BOUND;
2574 reg < BSM_SRAM_LOWER_BOUND + len;
2575 reg += sizeof(u32), image++) {
2576 val = iwl_read_prph(priv, reg);
2577 if (val != le32_to_cpu(*image)) {
2578 IWL_ERR(priv, "BSM uCode verification failed at "
2579 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2580 BSM_SRAM_LOWER_BOUND,
2581 reg - BSM_SRAM_LOWER_BOUND, len,
2582 val, le32_to_cpu(*image));
2583 return -EIO;
2584 }
2585 }
2586
e1623446 2587 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2588
2589 return 0;
2590}
2591
e6148917
SO		 2592
2593/******************************************************************************
2594 *
2595 * EEPROM related functions
2596 *
2597 ******************************************************************************/
2598
2599/*
2600 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2601 * embedded controller) as EEPROM reader; each read is a series of pulses
2602 * to/from the EEPROM chip, not a single event, so even reads could conflict
2603 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2604 * simply claims ownership, which should be safe when this function is called
2605 * (i.e. before loading uCode!).
2606 */
2607static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2608{
2609 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2610 return 0;
2611}
2612
2613
2614static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2615{
2616 return;
2617}
2618
0164b9b4
KA		 2619 /**
2620 * iwl3945_load_bsm - Load bootstrap instructions
2621 *
2622 * BSM operation:
2623 *
2624 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2625 * in special SRAM that does not power down during RFKILL. When powering back
2626 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2627 * the bootstrap program into the on-board processor, and starts it.
2628 *
2629 * The bootstrap program loads (via DMA) instructions and data for a new
2630 * program from host DRAM locations indicated by the host driver in the
2631 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2632 * automatically.
2633 *
2634 * When initializing the NIC, the host driver points the BSM to the
2635 * "initialize" uCode image. This uCode sets up some internal data, then
2636 * notifies host via "initialize alive" that it is complete.
2637 *
2638 * The host then replaces the BSM_DRAM_* pointer values to point to the
2639 * normal runtime uCode instructions and a backup uCode data cache buffer
2640 * (filled initially with starting data values for the on-board processor),
2641 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2642 * which begins normal operation.
2643 *
2644 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2645 * the backup data cache in DRAM before SRAM is powered down.
2646 *
2647 * When powering back up, the BSM loads the bootstrap program. This reloads
2648 * the runtime uCode instructions and the backup data cache into SRAM,
2649 * and re-launches the runtime uCode from where it left off.
2650 */
2651static int iwl3945_load_bsm(struct iwl_priv *priv)
2652{
2653 __le32 *image = priv->ucode_boot.v_addr;
2654 u32 len = priv->ucode_boot.len;
2655 dma_addr_t pinst;
2656 dma_addr_t pdata;
2657 u32 inst_len;
2658 u32 data_len;
2659 int rc;
2660 int i;
2661 u32 done;
2662 u32 reg_offset;
2663
e1623446 2664 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2665
2666 /* make sure bootstrap program is no larger than BSM's SRAM size */
2667 if (len > IWL39_MAX_BSM_SIZE)
2668 return -EINVAL;
2669
2670 /* Tell bootstrap uCode where to find the "Initialize" uCode
2671 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2672 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2673 * after the "initialize" uCode has run, to point to
2674 * runtime/protocol instructions and backup data cache. */
2675 pinst = priv->ucode_init.p_addr;
2676 pdata = priv->ucode_init_data.p_addr;
2677 inst_len = priv->ucode_init.len;
2678 data_len = priv->ucode_init_data.len;
2679
0164b9b4
KA		 2680 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2681 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2682 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2683 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2684
2685 /* Fill BSM memory with bootstrap instructions */
2686 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2687 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2688 reg_offset += sizeof(u32), image++)
2689 _iwl_write_prph(priv, reg_offset,
2690 le32_to_cpu(*image));
2691
2692 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2693 if (rc)
0164b9b4 2694 return rc;
0164b9b4
KA		 2695
2696 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2697 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2698 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2699 IWL39_RTC_INST_LOWER_BOUND);
2700 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2701
2702 /* Load bootstrap code into instruction SRAM now,
2703 * to prepare to load "initialize" uCode */
2704 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2705 BSM_WR_CTRL_REG_BIT_START);
2706
2707 /* Wait for load of bootstrap uCode to finish */
2708 for (i = 0; i < 100; i++) {
2709 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2710 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2711 break;
2712 udelay(10);
2713 }
2714 if (i < 100)
e1623446 2715 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2716 else {
2717 IWL_ERR(priv, "BSM write did not complete!\n");
2718 return -EIO;
2719 }
2720
2721 /* Enable future boot loads whenever power management unit triggers it
2722 * (e.g. when powering back up after power-save shutdown) */
2723 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2724 BSM_WR_CTRL_REG_BIT_START_EN);
2725
0164b9b4
KA		 2726 return 0;
2727}
2728
cc0f555d
JS		 2729#define IWL3945_UCODE_GET(item) \
2730static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2731 u32 api_ver) \
2732{ \
2733 return le32_to_cpu(ucode->u.v1.item); \
2734}
2735
2736static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2737{
2738 return UCODE_HEADER_SIZE(1);
2739}
2740static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2741 u32 api_ver)
2742{
2743 return 0;
2744}
2745static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2746 u32 api_ver)
2747{
2748 return (u8 *) ucode->u.v1.data;
2749}
2750
2751IWL3945_UCODE_GET(inst_size);
2752IWL3945_UCODE_GET(data_size);
2753IWL3945_UCODE_GET(init_size);
2754IWL3945_UCODE_GET(init_data_size);
2755IWL3945_UCODE_GET(boot_size);
2756
5bbe233b
AK		 2757static struct iwl_hcmd_ops iwl3945_hcmd = {
2758 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2759 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2760};
2761
cc0f555d
JS		 2762static struct iwl_ucode_ops iwl3945_ucode = {
2763 .get_header_size = iwl3945_ucode_get_header_size,
2764 .get_build = iwl3945_ucode_get_build,
2765 .get_inst_size = iwl3945_ucode_get_inst_size,
2766 .get_data_size = iwl3945_ucode_get_data_size,
2767 .get_init_size = iwl3945_ucode_get_init_size,
2768 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2769 .get_boot_size = iwl3945_ucode_get_boot_size,
2770 .get_data = iwl3945_ucode_get_data,
2771};
2772
0164b9b4 2773static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2774 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2775 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2776 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2777 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2778 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2779 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2780 .apm_ops = {
2781 .init = iwl3945_apm_init,
d68b603c 2782 .stop = iwl_apm_stop,
01ec616d 2783 .config = iwl3945_nic_config,
854682ed 2784 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2785 },
e6148917
SO		 2786 .eeprom_ops = {
2787 .regulatory_bands = {
2788 EEPROM_REGULATORY_BAND_1_CHANNELS,
2789 EEPROM_REGULATORY_BAND_2_CHANNELS,
2790 EEPROM_REGULATORY_BAND_3_CHANNELS,
2791 EEPROM_REGULATORY_BAND_4_CHANNELS,
2792 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2793 EEPROM_REGULATORY_BAND_NO_HT40,
2794 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2795 },
2796 .verify_signature = iwlcore_eeprom_verify_signature,
2797 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2798 .release_semaphore = iwl3945_eeprom_release_semaphore,
2799 .query_addr = iwlcore_eeprom_query_addr,
2800 },
75bcfae9 2801 .send_tx_power = iwl3945_send_tx_power,
c2436980 2802 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2803 .post_associate = iwl3945_post_associate,
ef850d7c 2804 .isr = iwl_isr_legacy,
60690a6a 2805 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2806};
2807
42427b4e
KA		 2808static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2809 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2810 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2811 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
42427b4e
KA		 2812};
2813
0164b9b4 2814static struct iwl_ops iwl3945_ops = {
cc0f555d 2815 .ucode = &iwl3945_ucode,
0164b9b4 2816 .lib = &iwl3945_lib,
5bbe233b 2817 .hcmd = &iwl3945_hcmd,
42427b4e 2818 .utils = &iwl3945_hcmd_utils,
e932a609 2819 .led = &iwl3945_led_ops,
0164b9b4
KA		 2820};
2821
c0f20d91 2822static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2823 .name = "3945BG",
a0987a8d
RC		 2824 .fw_name_pre = IWL3945_FW_PRE,
2825 .ucode_api_max = IWL3945_UCODE_API_MAX,
2826 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2827 .sku = IWL_SKU_G,
e6148917
SO		 2828 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2829 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2830 .ops = &iwl3945_ops,
88804e2b 2831 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2832 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2833 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2834 .set_l0s = false,
2835 .use_bsm = true,
b261793d
DH		 2836 .use_isr_legacy = true,
2837 .ht_greenfield_support = false,
f2d0d0e2 2838 .led_compensation = 64,
82b9a121
TW		 2839};
2840
c0f20d91 2841static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2842 .name = "3945ABG",
a0987a8d
RC		 2843 .fw_name_pre = IWL3945_FW_PRE,
2844 .ucode_api_max = IWL3945_UCODE_API_MAX,
2845 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2846 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2847 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2848 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2849 .ops = &iwl3945_ops,
88804e2b 2850 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2851 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2852 .use_isr_legacy = true,
2853 .ht_greenfield_support = false,
f2d0d0e2 2854 .led_compensation = 64,
82b9a121
TW		 2855};
2856
bb8c093b 2857struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2858 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2859 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2860 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2861 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2862 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2863 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2864 {0}
2865};
2866
bb8c093b 2867MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
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