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atl1c: atl1c_resume() is only used when CONFIG_PM_SLEEP is defined.
[linux.git] / drivers / net / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <[email protected]>
5 * Copyright (c) 2003 - 2007 Francois Romieu <[email protected]>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
1da177e4 29
99f252b0 30#include <asm/system.h>
1da177e4
LT		 31#include <asm/io.h>
32#include <asm/irq.h>
33
865c652d 34#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 35#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 43
1da177e4
LT		 44#ifdef RTL8169_DEBUG
45#define assert(expr) \
5b0384f4
FR		 46 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 48 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 49 }
06fa7358
JP		 50#define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 52#else
53#define assert(expr) do {} while (0)
54#define dprintk(fmt, args...) do {} while (0)
55#endif /* RTL8169_DEBUG */
56
b57b7e5a 57#define R8169_MSG_DEFAULT \
f0e837d9 58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 59
1da177e4
LT		 60#define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 65static const int multicast_filter_limit = 32;
1da177e4
LT		 66
67/* MAC address length */
68#define MAC_ADDR_LEN 6
69
9c14ceaf 70#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 71#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
134 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 135};
136
2b7b4318
FR		 137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
85bffe6c
FR		 142#define _R(NAME,TD,FW) \
143 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 144
3c6bee1d 145static const struct {
1da177e4 146 const char *name;
2b7b4318 147 enum rtl_tx_desc_version txd_version;
953a12cc 148 const char *fw_name;
85bffe6c
FR		 149} rtl_chip_infos[] = {
150 /* PCI devices. */
151 [RTL_GIGA_MAC_VER_01] =
152 _R("RTL8169", RTL_TD_0, NULL),
153 [RTL_GIGA_MAC_VER_02] =
154 _R("RTL8169s", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_03] =
156 _R("RTL8110s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_04] =
158 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_05] =
160 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_06] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 /* PCI-E devices. */
164 [RTL_GIGA_MAC_VER_07] =
165 _R("RTL8102e", RTL_TD_1, NULL),
166 [RTL_GIGA_MAC_VER_08] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_09] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_10] =
171 _R("RTL8101e", RTL_TD_0, NULL),
172 [RTL_GIGA_MAC_VER_11] =
173 _R("RTL8168b/8111b", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_12] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_13] =
177 _R("RTL8101e", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_14] =
179 _R("RTL8100e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_15] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_16] =
183 _R("RTL8101e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_17] =
185 _R("RTL8168b/8111b", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_18] =
187 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
188 [RTL_GIGA_MAC_VER_19] =
189 _R("RTL8168c/8111c", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_20] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_21] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_22] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_23] =
197 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_24] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_25] =
201 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
202 [RTL_GIGA_MAC_VER_26] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
204 [RTL_GIGA_MAC_VER_27] =
205 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
206 [RTL_GIGA_MAC_VER_28] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_29] =
209 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
210 [RTL_GIGA_MAC_VER_30] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_31] =
213 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
214 [RTL_GIGA_MAC_VER_32] =
215 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
216 [RTL_GIGA_MAC_VER_33] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
953a12cc 218};
85bffe6c 219#undef _R
953a12cc 220
bcf0bf90
FR		 221enum cfg_version {
222 RTL_CFG_0 = 0x00,
223 RTL_CFG_1,
224 RTL_CFG_2
225};
226
07ce4064
FR		 227static void rtl_hw_start_8169(struct net_device *);
228static void rtl_hw_start_8168(struct net_device *);
229static void rtl_hw_start_8101(struct net_device *);
230
a3aa1884 231static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 232 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 238 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 239 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
240 { PCI_VENDOR_ID_LINKSYS, 0x1032,
241 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 242 { 0x0001, 0x8168,
243 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 244 {0,},
245};
246
247MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
248
6f0333b8 249static int rx_buf_sz = 16383;
4300e8c7 250static int use_dac;
b57b7e5a
SH		 251static struct {
252 u32 msg_enable;
253} debug = { -1 };
1da177e4 254
07d3f51f
FR		 255enum rtl_registers {
256 MAC0 = 0, /* Ethernet hardware address. */
773d2021 257 MAC4 = 4,
07d3f51f
FR		 258 MAR0 = 8, /* Multicast filter. */
259 CounterAddrLow = 0x10,
260 CounterAddrHigh = 0x14,
261 TxDescStartAddrLow = 0x20,
262 TxDescStartAddrHigh = 0x24,
263 TxHDescStartAddrLow = 0x28,
264 TxHDescStartAddrHigh = 0x2c,
265 FLASH = 0x30,
266 ERSR = 0x36,
267 ChipCmd = 0x37,
268 TxPoll = 0x38,
269 IntrMask = 0x3c,
270 IntrStatus = 0x3e,
271 TxConfig = 0x40,
272 RxConfig = 0x44,
2b7b4318
FR		 273
274#define RTL_RX_CONFIG_MASK 0xff7e1880u
275
07d3f51f
FR		 276 RxMissed = 0x4c,
277 Cfg9346 = 0x50,
278 Config0 = 0x51,
279 Config1 = 0x52,
280 Config2 = 0x53,
281 Config3 = 0x54,
282 Config4 = 0x55,
283 Config5 = 0x56,
284 MultiIntr = 0x5c,
285 PHYAR = 0x60,
07d3f51f
FR		 286 PHYstatus = 0x6c,
287 RxMaxSize = 0xda,
288 CPlusCmd = 0xe0,
289 IntrMitigate = 0xe2,
290 RxDescAddrLow = 0xe4,
291 RxDescAddrHigh = 0xe8,
f0298f81 292 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
293
294#define NoEarlyTx 0x3f /* Max value : no early transmit. */
295
296 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
297
298#define TxPacketMax (8064 >> 7)
299
07d3f51f
FR		 300 FuncEvent = 0xf0,
301 FuncEventMask = 0xf4,
302 FuncPresetState = 0xf8,
303 FuncForceEvent = 0xfc,
1da177e4
LT		 304};
305
f162a5d1
FR		 306enum rtl8110_registers {
307 TBICSR = 0x64,
308 TBI_ANAR = 0x68,
309 TBI_LPAR = 0x6a,
310};
311
312enum rtl8168_8101_registers {
313 CSIDR = 0x64,
314 CSIAR = 0x68,
315#define CSIAR_FLAG 0x80000000
316#define CSIAR_WRITE_CMD 0x80000000
317#define CSIAR_BYTE_ENABLE 0x0f
318#define CSIAR_BYTE_ENABLE_SHIFT 12
319#define CSIAR_ADDR_MASK 0x0fff
065c27c1 320 PMCH = 0x6f,
f162a5d1
FR		 321 EPHYAR = 0x80,
322#define EPHYAR_FLAG 0x80000000
323#define EPHYAR_WRITE_CMD 0x80000000
324#define EPHYAR_REG_MASK 0x1f
325#define EPHYAR_REG_SHIFT 16
326#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 327 DLLPR = 0xd0,
328#define PM_SWITCH (1 << 6)
f162a5d1
FR		 329 DBG_REG = 0xd1,
330#define FIX_NAK_1 (1 << 4)
331#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 332 TWSI = 0xd2,
333 MCU = 0xd3,
334#define EN_NDP (1 << 3)
335#define EN_OOB_RESET (1 << 2)
daf9df6d 336 EFUSEAR = 0xdc,
337#define EFUSEAR_FLAG 0x80000000
338#define EFUSEAR_WRITE_CMD 0x80000000
339#define EFUSEAR_READ_CMD 0x00000000
340#define EFUSEAR_REG_MASK 0x03ff
341#define EFUSEAR_REG_SHIFT 8
342#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 343};
344
c0e45c1c 345enum rtl8168_registers {
b646d900 346 ERIDR = 0x70,
347 ERIAR = 0x74,
348#define ERIAR_FLAG 0x80000000
349#define ERIAR_WRITE_CMD 0x80000000
350#define ERIAR_READ_CMD 0x00000000
351#define ERIAR_ADDR_BYTE_ALIGN 4
352#define ERIAR_EXGMAC 0
353#define ERIAR_MSIX 1
354#define ERIAR_ASF 2
355#define ERIAR_TYPE_SHIFT 16
356#define ERIAR_BYTEEN 0x0f
357#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 358 EPHY_RXER_NUM = 0x7c,
359 OCPDR = 0xb0, /* OCP GPHY access */
360#define OCPDR_WRITE_CMD 0x80000000
361#define OCPDR_READ_CMD 0x00000000
362#define OCPDR_REG_MASK 0x7f
363#define OCPDR_GPHY_REG_SHIFT 16
364#define OCPDR_DATA_MASK 0xffff
365 OCPAR = 0xb4,
366#define OCPAR_FLAG 0x80000000
367#define OCPAR_GPHY_WRITE_CMD 0x8000f060
368#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 369 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
370 MISC = 0xf0, /* 8168e only. */
cecb5fd7 371#define TXPLA_RST (1 << 29)
c0e45c1c 372};
373
07d3f51f 374enum rtl_register_content {
1da177e4 375 /* InterruptStatusBits */
07d3f51f
FR		 376 SYSErr = 0x8000,
377 PCSTimeout = 0x4000,
378 SWInt = 0x0100,
379 TxDescUnavail = 0x0080,
380 RxFIFOOver = 0x0040,
381 LinkChg = 0x0020,
382 RxOverflow = 0x0010,
383 TxErr = 0x0008,
384 TxOK = 0x0004,
385 RxErr = 0x0002,
386 RxOK = 0x0001,
1da177e4
LT		 387
388 /* RxStatusDesc */
9dccf611
FR		 389 RxFOVF = (1 << 23),
390 RxRWT = (1 << 22),
391 RxRES = (1 << 21),
392 RxRUNT = (1 << 20),
393 RxCRC = (1 << 19),
1da177e4
LT		 394
395 /* ChipCmdBits */
07d3f51f
FR		 396 CmdReset = 0x10,
397 CmdRxEnb = 0x08,
398 CmdTxEnb = 0x04,
399 RxBufEmpty = 0x01,
1da177e4 400
275391a4
FR		 401 /* TXPoll register p.5 */
402 HPQ = 0x80, /* Poll cmd on the high prio queue */
403 NPQ = 0x40, /* Poll cmd on the low prio queue */
404 FSWInt = 0x01, /* Forced software interrupt */
405
1da177e4 406 /* Cfg9346Bits */
07d3f51f
FR		 407 Cfg9346_Lock = 0x00,
408 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 409
410 /* rx_mode_bits */
07d3f51f
FR		 411 AcceptErr = 0x20,
412 AcceptRunt = 0x10,
413 AcceptBroadcast = 0x08,
414 AcceptMulticast = 0x04,
415 AcceptMyPhys = 0x02,
416 AcceptAllPhys = 0x01,
1da177e4
LT		 417
418 /* RxConfigBits */
07d3f51f
FR		 419 RxCfgFIFOShift = 13,
420 RxCfgDMAShift = 8,
1da177e4
LT		 421
422 /* TxConfigBits */
423 TxInterFrameGapShift = 24,
424 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
425
5d06a99f 426 /* Config1 register p.24 */
f162a5d1
FR		 427 LEDS1 = (1 << 7),
428 LEDS0 = (1 << 6),
fbac58fc 429 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 430 Speed_down = (1 << 4),
431 MEMMAP = (1 << 3),
432 IOMAP = (1 << 2),
433 VPD = (1 << 1),
5d06a99f
FR		 434 PMEnable = (1 << 0), /* Power Management Enable */
435
6dccd16b
FR		 436 /* Config2 register p. 25 */
437 PCI_Clock_66MHz = 0x01,
438 PCI_Clock_33MHz = 0x00,
439
61a4dcc2
FR		 440 /* Config3 register p.25 */
441 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
442 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 443 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 444
5d06a99f 445 /* Config5 register p.27 */
61a4dcc2
FR		 446 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
447 MWF = (1 << 5), /* Accept Multicast wakeup frame */
448 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 449 Spi_en = (1 << 3),
61a4dcc2 450 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 451 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
452
1da177e4
LT		 453 /* TBICSR p.28 */
454 TBIReset = 0x80000000,
455 TBILoopback = 0x40000000,
456 TBINwEnable = 0x20000000,
457 TBINwRestart = 0x10000000,
458 TBILinkOk = 0x02000000,
459 TBINwComplete = 0x01000000,
460
461 /* CPlusCmd p.31 */
f162a5d1
FR		 462 EnableBist = (1 << 15), // 8168 8101
463 Mac_dbgo_oe = (1 << 14), // 8168 8101
464 Normal_mode = (1 << 13), // unused
465 Force_half_dup = (1 << 12), // 8168 8101
466 Force_rxflow_en = (1 << 11), // 8168 8101
467 Force_txflow_en = (1 << 10), // 8168 8101
468 Cxpl_dbg_sel = (1 << 9), // 8168 8101
469 ASF = (1 << 8), // 8168 8101
470 PktCntrDisable = (1 << 7), // 8168 8101
471 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 472 RxVlan = (1 << 6),
473 RxChkSum = (1 << 5),
474 PCIDAC = (1 << 4),
475 PCIMulRW = (1 << 3),
0e485150
FR		 476 INTT_0 = 0x0000, // 8168
477 INTT_1 = 0x0001, // 8168
478 INTT_2 = 0x0002, // 8168
479 INTT_3 = 0x0003, // 8168
1da177e4
LT		 480
481 /* rtl8169_PHYstatus */
07d3f51f
FR		 482 TBI_Enable = 0x80,
483 TxFlowCtrl = 0x40,
484 RxFlowCtrl = 0x20,
485 _1000bpsF = 0x10,
486 _100bps = 0x08,
487 _10bps = 0x04,
488 LinkStatus = 0x02,
489 FullDup = 0x01,
1da177e4 490
1da177e4 491 /* _TBICSRBit */
07d3f51f 492 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 493
494 /* DumpCounterCommand */
07d3f51f 495 CounterDump = 0x8,
1da177e4
LT		 496};
497
2b7b4318
FR		 498enum rtl_desc_bit {
499 /* First doubleword. */
1da177e4
LT		 500 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
501 RingEnd = (1 << 30), /* End of descriptor ring */
502 FirstFrag = (1 << 29), /* First segment of a packet */
503 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 504};
505
506/* Generic case. */
507enum rtl_tx_desc_bit {
508 /* First doubleword. */
509 TD_LSO = (1 << 27), /* Large Send Offload */
510#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 511
2b7b4318
FR		 512 /* Second doubleword. */
513 TxVlanTag = (1 << 17), /* Add VLAN tag */
514};
515
516/* 8169, 8168b and 810x except 8102e. */
517enum rtl_tx_desc_bit_0 {
518 /* First doubleword. */
519#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
520 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
521 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
522 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
523};
524
525/* 8102e, 8168c and beyond. */
526enum rtl_tx_desc_bit_1 {
527 /* Second doubleword. */
528#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
529 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
530 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
531 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
532};
1da177e4 533
2b7b4318
FR		 534static const struct rtl_tx_desc_info {
535 struct {
536 u32 udp;
537 u32 tcp;
538 } checksum;
539 u16 mss_shift;
540 u16 opts_offset;
541} tx_desc_info [] = {
542 [RTL_TD_0] = {
543 .checksum = {
544 .udp = TD0_IP_CS | TD0_UDP_CS,
545 .tcp = TD0_IP_CS | TD0_TCP_CS
546 },
547 .mss_shift = TD0_MSS_SHIFT,
548 .opts_offset = 0
549 },
550 [RTL_TD_1] = {
551 .checksum = {
552 .udp = TD1_IP_CS | TD1_UDP_CS,
553 .tcp = TD1_IP_CS | TD1_TCP_CS
554 },
555 .mss_shift = TD1_MSS_SHIFT,
556 .opts_offset = 1
557 }
558};
559
560enum rtl_rx_desc_bit {
1da177e4
LT		 561 /* Rx private */
562 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
563 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
564
565#define RxProtoUDP (PID1)
566#define RxProtoTCP (PID0)
567#define RxProtoIP (PID1 | PID0)
568#define RxProtoMask RxProtoIP
569
570 IPFail = (1 << 16), /* IP checksum failed */
571 UDPFail = (1 << 15), /* UDP/IP checksum failed */
572 TCPFail = (1 << 14), /* TCP/IP checksum failed */
573 RxVlanTag = (1 << 16), /* VLAN tag available */
574};
575
576#define RsvdMask 0x3fffc000
577
578struct TxDesc {
6cccd6e7
REB		 579 __le32 opts1;
580 __le32 opts2;
581 __le64 addr;
1da177e4
LT		 582};
583
584struct RxDesc {
6cccd6e7
REB		 585 __le32 opts1;
586 __le32 opts2;
587 __le64 addr;
1da177e4
LT		 588};
589
590struct ring_info {
591 struct sk_buff *skb;
592 u32 len;
593 u8 __pad[sizeof(void *) - sizeof(u32)];
594};
595
f23e7fda 596enum features {
ccdffb9a
FR		 597 RTL_FEATURE_WOL = (1 << 0),
598 RTL_FEATURE_MSI = (1 << 1),
599 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 600};
601
355423d0
IV		 602struct rtl8169_counters {
603 __le64 tx_packets;
604 __le64 rx_packets;
605 __le64 tx_errors;
606 __le32 rx_errors;
607 __le16 rx_missed;
608 __le16 align_errors;
609 __le32 tx_one_collision;
610 __le32 tx_multi_collision;
611 __le64 rx_unicast;
612 __le64 rx_broadcast;
613 __le32 rx_multicast;
614 __le16 tx_aborted;
615 __le16 tx_underun;
616};
617
1da177e4
LT		 618struct rtl8169_private {
619 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 620 struct pci_dev *pci_dev;
c4028958 621 struct net_device *dev;
bea3348e 622 struct napi_struct napi;
cecb5fd7 623 spinlock_t lock;
b57b7e5a 624 u32 msg_enable;
2b7b4318
FR		 625 u16 txd_version;
626 u16 mac_version;
1da177e4
LT		 627 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
628 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
629 u32 dirty_rx;
630 u32 dirty_tx;
631 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
632 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
633 dma_addr_t TxPhyAddr;
634 dma_addr_t RxPhyAddr;
6f0333b8 635 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 636 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 637 struct timer_list timer;
638 u16 cp_cmd;
0e485150
FR		 639 u16 intr_event;
640 u16 napi_event;
1da177e4 641 u16 intr_mask;
c0e45c1c 642
643 struct mdio_ops {
644 void (*write)(void __iomem *, int, int);
645 int (*read)(void __iomem *, int);
646 } mdio_ops;
647
065c27c1 648 struct pll_power_ops {
649 void (*down)(struct rtl8169_private *);
650 void (*up)(struct rtl8169_private *);
651 } pll_power_ops;
652
54405cde 653 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 654 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 655 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 656 void (*hw_start)(struct net_device *);
4da19633 657 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 658 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 659 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 660 int pcie_cap;
c4028958 661 struct delayed_work task;
f23e7fda 662 unsigned features;
ccdffb9a
FR		 663
664 struct mii_if_info mii;
355423d0 665 struct rtl8169_counters counters;
e1759441 666 u32 saved_wolopts;
f1e02ed1 667
668 const struct firmware *fw;
953a12cc 669#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 670};
671
979b6c13 672MODULE_AUTHOR("Realtek and the Linux r8169 crew <[email protected]>");
1da177e4 673MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 674module_param(use_dac, int, 0);
4300e8c7 675MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 676module_param_named(debug, debug.msg_enable, int, 0);
677MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 678MODULE_LICENSE("GPL");
679MODULE_VERSION(RTL8169_VERSION);
bca03d5f 680MODULE_FIRMWARE(FIRMWARE_8168D_1);
681MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 682MODULE_FIRMWARE(FIRMWARE_8168E_1);
683MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 684MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 685
686static int rtl8169_open(struct net_device *dev);
61357325
SH		 687static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
688 struct net_device *dev);
7d12e780 689static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 690static int rtl8169_init_ring(struct net_device *dev);
07ce4064 691static void rtl_hw_start(struct net_device *dev);
1da177e4 692static int rtl8169_close(struct net_device *dev);
07ce4064 693static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 694static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 695static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 696static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 697 void __iomem *, u32 budget);
4dcb7d33 698static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 699static void rtl8169_down(struct net_device *dev);
99f252b0 700static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 701static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 702
1da177e4 703static const unsigned int rtl8169_rx_config =
5b0384f4 704 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 705
b646d900 706static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
707{
708 void __iomem *ioaddr = tp->mmio_addr;
709 int i;
710
711 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
712 for (i = 0; i < 20; i++) {
713 udelay(100);
714 if (RTL_R32(OCPAR) & OCPAR_FLAG)
715 break;
716 }
717 return RTL_R32(OCPDR);
718}
719
720static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
721{
722 void __iomem *ioaddr = tp->mmio_addr;
723 int i;
724
725 RTL_W32(OCPDR, data);
726 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
727 for (i = 0; i < 20; i++) {
728 udelay(100);
729 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
730 break;
731 }
732}
733
fac5b3ca 734static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 735{
fac5b3ca 736 void __iomem *ioaddr = tp->mmio_addr;
b646d900 737 int i;
738
739 RTL_W8(ERIDR, cmd);
740 RTL_W32(ERIAR, 0x800010e8);
741 msleep(2);
742 for (i = 0; i < 5; i++) {
743 udelay(100);
744 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
745 break;
746 }
747
fac5b3ca 748 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 749}
750
751#define OOB_CMD_RESET 0x00
752#define OOB_CMD_DRIVER_START 0x05
753#define OOB_CMD_DRIVER_STOP 0x06
754
cecb5fd7
FR		 755static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
756{
757 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
758}
759
b646d900 760static void rtl8168_driver_start(struct rtl8169_private *tp)
761{
cecb5fd7 762 u16 reg;
b646d900 763 int i;
764
765 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
766
cecb5fd7 767 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 768
b646d900 769 for (i = 0; i < 10; i++) {
770 msleep(10);
4804b3b3 771 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 772 break;
773 }
774}
775
776static void rtl8168_driver_stop(struct rtl8169_private *tp)
777{
cecb5fd7 778 u16 reg;
b646d900 779 int i;
780
781 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
782
cecb5fd7 783 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 784
b646d900 785 for (i = 0; i < 10; i++) {
786 msleep(10);
4804b3b3 787 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 788 break;
789 }
790}
791
4804b3b3 792static int r8168dp_check_dash(struct rtl8169_private *tp)
793{
cecb5fd7 794 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 795
cecb5fd7 796 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 797}
b646d900 798
4da19633 799static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 800{
801 int i;
802
a6baf3af 803 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 804
2371408c 805 for (i = 20; i > 0; i--) {
07d3f51f
FR		 806 /*
807 * Check if the RTL8169 has completed writing to the specified
808 * MII register.
809 */
5b0384f4 810 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 811 break;
2371408c 812 udelay(25);
1da177e4 813 }
024a07ba 814 /*
81a95f04
TT		 815 * According to hardware specs a 20us delay is required after write
816 * complete indication, but before sending next command.
024a07ba 817 */
81a95f04 818 udelay(20);
1da177e4
LT		 819}
820
4da19633 821static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 822{
823 int i, value = -1;
824
a6baf3af 825 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 826
2371408c 827 for (i = 20; i > 0; i--) {
07d3f51f
FR		 828 /*
829 * Check if the RTL8169 has completed retrieving data from
830 * the specified MII register.
831 */
1da177e4 832 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 833 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 834 break;
835 }
2371408c 836 udelay(25);
1da177e4 837 }
81a95f04
TT		 838 /*
839 * According to hardware specs a 20us delay is required after read
840 * complete indication, but before sending next command.
841 */
842 udelay(20);
843
1da177e4
LT		 844 return value;
845}
846
c0e45c1c 847static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
848{
849 int i;
850
851 RTL_W32(OCPDR, data |
852 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
853 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
854 RTL_W32(EPHY_RXER_NUM, 0);
855
856 for (i = 0; i < 100; i++) {
857 mdelay(1);
858 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
859 break;
860 }
861}
862
863static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
864{
865 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
866 (value & OCPDR_DATA_MASK));
867}
868
869static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
870{
871 int i;
872
873 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
874
875 mdelay(1);
876 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
877 RTL_W32(EPHY_RXER_NUM, 0);
878
879 for (i = 0; i < 100; i++) {
880 mdelay(1);
881 if (RTL_R32(OCPAR) & OCPAR_FLAG)
882 break;
883 }
884
885 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
886}
887
e6de30d6 888#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
889
890static void r8168dp_2_mdio_start(void __iomem *ioaddr)
891{
892 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
893}
894
895static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
896{
897 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
898}
899
900static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
901{
902 r8168dp_2_mdio_start(ioaddr);
903
904 r8169_mdio_write(ioaddr, reg_addr, value);
905
906 r8168dp_2_mdio_stop(ioaddr);
907}
908
909static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
910{
911 int value;
912
913 r8168dp_2_mdio_start(ioaddr);
914
915 value = r8169_mdio_read(ioaddr, reg_addr);
916
917 r8168dp_2_mdio_stop(ioaddr);
918
919 return value;
920}
921
4da19633 922static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 923{
c0e45c1c 924 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 925}
926
4da19633 927static int rtl_readphy(struct rtl8169_private *tp, int location)
928{
c0e45c1c 929 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 930}
931
932static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
933{
934 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
935}
936
937static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 938{
939 int val;
940
4da19633 941 val = rtl_readphy(tp, reg_addr);
942 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 943}
944
ccdffb9a
FR		 945static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
946 int val)
947{
948 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 949
4da19633 950 rtl_writephy(tp, location, val);
ccdffb9a
FR		 951}
952
953static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
954{
955 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 956
4da19633 957 return rtl_readphy(tp, location);
ccdffb9a
FR		 958}
959
dacf8154
FR		 960static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
961{
962 unsigned int i;
963
964 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
965 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
966
967 for (i = 0; i < 100; i++) {
968 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
969 break;
970 udelay(10);
971 }
972}
973
974static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
975{
976 u16 value = 0xffff;
977 unsigned int i;
978
979 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
980
981 for (i = 0; i < 100; i++) {
982 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
983 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
984 break;
985 }
986 udelay(10);
987 }
988
989 return value;
990}
991
992static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
993{
994 unsigned int i;
995
996 RTL_W32(CSIDR, value);
997 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
998 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
999
1000 for (i = 0; i < 100; i++) {
1001 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1002 break;
1003 udelay(10);
1004 }
1005}
1006
1007static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1008{
1009 u32 value = ~0x00;
1010 unsigned int i;
1011
1012 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1013 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1014
1015 for (i = 0; i < 100; i++) {
1016 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1017 value = RTL_R32(CSIDR);
1018 break;
1019 }
1020 udelay(10);
1021 }
1022
1023 return value;
1024}
1025
daf9df6d 1026static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1027{
1028 u8 value = 0xff;
1029 unsigned int i;
1030
1031 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1032
1033 for (i = 0; i < 300; i++) {
1034 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1035 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1036 break;
1037 }
1038 udelay(100);
1039 }
1040
1041 return value;
1042}
1043
1da177e4
LT		 1044static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1045{
1046 RTL_W16(IntrMask, 0x0000);
1047
1048 RTL_W16(IntrStatus, 0xffff);
1049}
1050
1051static void rtl8169_asic_down(void __iomem *ioaddr)
1052{
1053 RTL_W8(ChipCmd, 0x00);
1054 rtl8169_irq_mask_and_ack(ioaddr);
1055 RTL_R16(CPlusCmd);
1056}
1057
4da19633 1058static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1059{
4da19633 1060 void __iomem *ioaddr = tp->mmio_addr;
1061
1da177e4
LT		 1062 return RTL_R32(TBICSR) & TBIReset;
1063}
1064
4da19633 1065static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1066{
4da19633 1067 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1068}
1069
1070static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1071{
1072 return RTL_R32(TBICSR) & TBILinkOk;
1073}
1074
1075static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1076{
1077 return RTL_R8(PHYstatus) & LinkStatus;
1078}
1079
4da19633 1080static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1081{
4da19633 1082 void __iomem *ioaddr = tp->mmio_addr;
1083
1da177e4
LT		 1084 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1085}
1086
4da19633 1087static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1088{
1089 unsigned int val;
1090
4da19633 1091 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1092 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1093}
1094
e4fbce74 1095static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1096 struct rtl8169_private *tp,
1097 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1098{
1099 unsigned long flags;
1100
1101 spin_lock_irqsave(&tp->lock, flags);
1102 if (tp->link_ok(ioaddr)) {
e1759441 1103 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1104 if (pm)
1105 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1106 netif_carrier_on(dev);
1519e57f
FR		 1107 if (net_ratelimit())
1108 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1109 } else {
1da177e4 1110 netif_carrier_off(dev);
bf82c189 1111 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1112 if (pm)
1113 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1114 }
1da177e4
LT		 1115 spin_unlock_irqrestore(&tp->lock, flags);
1116}
1117
e4fbce74
RW		 1118static void rtl8169_check_link_status(struct net_device *dev,
1119 struct rtl8169_private *tp,
1120 void __iomem *ioaddr)
1121{
1122 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1123}
1124
e1759441
RW		 1125#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1126
1127static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1128{
61a4dcc2
FR		 1129 void __iomem *ioaddr = tp->mmio_addr;
1130 u8 options;
e1759441 1131 u32 wolopts = 0;
61a4dcc2
FR		 1132
1133 options = RTL_R8(Config1);
1134 if (!(options & PMEnable))
e1759441 1135 return 0;
61a4dcc2
FR		 1136
1137 options = RTL_R8(Config3);
1138 if (options & LinkUp)
e1759441 1139 wolopts |= WAKE_PHY;
61a4dcc2 1140 if (options & MagicPacket)
e1759441 1141 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1142
1143 options = RTL_R8(Config5);
1144 if (options & UWF)
e1759441 1145 wolopts |= WAKE_UCAST;
61a4dcc2 1146 if (options & BWF)
e1759441 1147 wolopts |= WAKE_BCAST;
61a4dcc2 1148 if (options & MWF)
e1759441 1149 wolopts |= WAKE_MCAST;
61a4dcc2 1150
e1759441 1151 return wolopts;
61a4dcc2
FR		 1152}
1153
e1759441 1154static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1155{
1156 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1157
1158 spin_lock_irq(&tp->lock);
1159
1160 wol->supported = WAKE_ANY;
1161 wol->wolopts = __rtl8169_get_wol(tp);
1162
1163 spin_unlock_irq(&tp->lock);
1164}
1165
1166static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1167{
61a4dcc2 1168 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1169 unsigned int i;
350f7596 1170 static const struct {
61a4dcc2
FR		 1171 u32 opt;
1172 u16 reg;
1173 u8 mask;
1174 } cfg[] = {
1175 { WAKE_ANY, Config1, PMEnable },
1176 { WAKE_PHY, Config3, LinkUp },
1177 { WAKE_MAGIC, Config3, MagicPacket },
1178 { WAKE_UCAST, Config5, UWF },
1179 { WAKE_BCAST, Config5, BWF },
1180 { WAKE_MCAST, Config5, MWF },
1181 { WAKE_ANY, Config5, LanWake }
1182 };
1183
61a4dcc2
FR		 1184 RTL_W8(Cfg9346, Cfg9346_Unlock);
1185
1186 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1187 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1188 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1189 options |= cfg[i].mask;
1190 RTL_W8(cfg[i].reg, options);
1191 }
1192
1193 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1194}
1195
1196static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1197{
1198 struct rtl8169_private *tp = netdev_priv(dev);
1199
1200 spin_lock_irq(&tp->lock);
61a4dcc2 1201
f23e7fda
FR		 1202 if (wol->wolopts)
1203 tp->features |= RTL_FEATURE_WOL;
1204 else
1205 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1206 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1207 spin_unlock_irq(&tp->lock);
1208
ea80907f 1209 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1210
61a4dcc2
FR		 1211 return 0;
1212}
1213
31bd204f
FR		 1214static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1215{
85bffe6c 1216 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1217}
1218
1da177e4
LT		 1219static void rtl8169_get_drvinfo(struct net_device *dev,
1220 struct ethtool_drvinfo *info)
1221{
1222 struct rtl8169_private *tp = netdev_priv(dev);
1223
1224 strcpy(info->driver, MODULENAME);
1225 strcpy(info->version, RTL8169_VERSION);
1226 strcpy(info->bus_info, pci_name(tp->pci_dev));
31bd204f
FR		 1227 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1228 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1da177e4
LT		 1229}
1230
1231static int rtl8169_get_regs_len(struct net_device *dev)
1232{
1233 return R8169_REGS_SIZE;
1234}
1235
1236static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1237 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1238{
1239 struct rtl8169_private *tp = netdev_priv(dev);
1240 void __iomem *ioaddr = tp->mmio_addr;
1241 int ret = 0;
1242 u32 reg;
1243
1244 reg = RTL_R32(TBICSR);
1245 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1246 (duplex == DUPLEX_FULL)) {
1247 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1248 } else if (autoneg == AUTONEG_ENABLE)
1249 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1250 else {
bf82c189
JP		 1251 netif_warn(tp, link, dev,
1252 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1253 ret = -EOPNOTSUPP;
1254 }
1255
1256 return ret;
1257}
1258
1259static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1260 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1261{
1262 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1263 int giga_ctrl, bmcr;
54405cde 1264 int rc = -EINVAL;
1da177e4 1265
716b50a3 1266 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1267
1268 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1269 int auto_nego;
1270
4da19633 1271 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1272 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1273 ADVERTISE_100HALF | ADVERTISE_100FULL);
1274
1275 if (adv & ADVERTISED_10baseT_Half)
1276 auto_nego |= ADVERTISE_10HALF;
1277 if (adv & ADVERTISED_10baseT_Full)
1278 auto_nego |= ADVERTISE_10FULL;
1279 if (adv & ADVERTISED_100baseT_Half)
1280 auto_nego |= ADVERTISE_100HALF;
1281 if (adv & ADVERTISED_100baseT_Full)
1282 auto_nego |= ADVERTISE_100FULL;
1283
3577aa1b 1284 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1285
4da19633 1286 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1287 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1288
3577aa1b 1289 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1290 if (tp->mii.supports_gmii) {
54405cde
ON		 1291 if (adv & ADVERTISED_1000baseT_Half)
1292 giga_ctrl |= ADVERTISE_1000HALF;
1293 if (adv & ADVERTISED_1000baseT_Full)
1294 giga_ctrl |= ADVERTISE_1000FULL;
1295 } else if (adv & (ADVERTISED_1000baseT_Half |
1296 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1297 netif_info(tp, link, dev,
1298 "PHY does not support 1000Mbps\n");
54405cde 1299 goto out;
bcf0bf90 1300 }
1da177e4 1301
3577aa1b 1302 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1303
4da19633 1304 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1305 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1306 } else {
1307 giga_ctrl = 0;
1308
1309 if (speed == SPEED_10)
1310 bmcr = 0;
1311 else if (speed == SPEED_100)
1312 bmcr = BMCR_SPEED100;
1313 else
54405cde 1314 goto out;
3577aa1b 1315
1316 if (duplex == DUPLEX_FULL)
1317 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1318 }
1319
4da19633 1320 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1321
cecb5fd7
FR		 1322 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1323 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1324 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1325 rtl_writephy(tp, 0x17, 0x2138);
1326 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1327 } else {
4da19633 1328 rtl_writephy(tp, 0x17, 0x2108);
1329 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1330 }
1331 }
1332
54405cde
ON		 1333 rc = 0;
1334out:
1335 return rc;
1da177e4
LT		 1336}
1337
1338static int rtl8169_set_speed(struct net_device *dev,
54405cde 1339 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1340{
1341 struct rtl8169_private *tp = netdev_priv(dev);
1342 int ret;
1343
54405cde 1344 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1345 if (ret < 0)
1346 goto out;
1da177e4 1347
4876cc1e
FR		 1348 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1349 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1350 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1351 }
1352out:
1da177e4
LT		 1353 return ret;
1354}
1355
1356static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1357{
1358 struct rtl8169_private *tp = netdev_priv(dev);
1359 unsigned long flags;
1360 int ret;
1361
4876cc1e
FR		 1362 del_timer_sync(&tp->timer);
1363
1da177e4 1364 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1365 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1366 cmd->duplex, cmd->advertising);
1da177e4 1367 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1368
1da177e4
LT		 1369 return ret;
1370}
1371
350fb32a 1372static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1373{
2b7b4318 1374 if (dev->mtu > TD_MSS_MAX)
350fb32a 1375 features &= ~NETIF_F_ALL_TSO;
1da177e4 1376
350fb32a 1377 return features;
1da177e4
LT		 1378}
1379
350fb32a 1380static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1381{
1382 struct rtl8169_private *tp = netdev_priv(dev);
1383 void __iomem *ioaddr = tp->mmio_addr;
1384 unsigned long flags;
1385
1386 spin_lock_irqsave(&tp->lock, flags);
1387
350fb32a 1388 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1389 tp->cp_cmd |= RxChkSum;
1390 else
1391 tp->cp_cmd &= ~RxChkSum;
1392
350fb32a
MM		 1393 if (dev->features & NETIF_F_HW_VLAN_RX)
1394 tp->cp_cmd |= RxVlan;
1395 else
1396 tp->cp_cmd &= ~RxVlan;
1397
1da177e4
LT		 1398 RTL_W16(CPlusCmd, tp->cp_cmd);
1399 RTL_R16(CPlusCmd);
1400
1401 spin_unlock_irqrestore(&tp->lock, flags);
1402
1403 return 0;
1404}
1405
1da177e4
LT		 1406static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1407 struct sk_buff *skb)
1408{
eab6d18d 1409 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1410 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1411}
1412
7a8fc77b 1413static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1414{
1415 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1416
7a8fc77b
FR		 1417 if (opts2 & RxVlanTag)
1418 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1419
1da177e4 1420 desc->opts2 = 0;
1da177e4
LT		 1421}
1422
ccdffb9a 1423static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1424{
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 void __iomem *ioaddr = tp->mmio_addr;
1427 u32 status;
1428
1429 cmd->supported =
1430 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1431 cmd->port = PORT_FIBRE;
1432 cmd->transceiver = XCVR_INTERNAL;
1433
1434 status = RTL_R32(TBICSR);
1435 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1436 cmd->autoneg = !!(status & TBINwEnable);
1437
70739497 1438 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1439 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1440
1441 return 0;
1da177e4
LT		 1442}
1443
ccdffb9a 1444static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1445{
1446 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1447
1448 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1449}
1450
1451static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1452{
1453 struct rtl8169_private *tp = netdev_priv(dev);
1454 unsigned long flags;
ccdffb9a 1455 int rc;
1da177e4
LT		 1456
1457 spin_lock_irqsave(&tp->lock, flags);
1458
ccdffb9a 1459 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1460
1461 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1462 return rc;
1da177e4
LT		 1463}
1464
1465static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1466 void *p)
1467{
5b0384f4
FR		 1468 struct rtl8169_private *tp = netdev_priv(dev);
1469 unsigned long flags;
1da177e4 1470
5b0384f4
FR		 1471 if (regs->len > R8169_REGS_SIZE)
1472 regs->len = R8169_REGS_SIZE;
1da177e4 1473
5b0384f4
FR		 1474 spin_lock_irqsave(&tp->lock, flags);
1475 memcpy_fromio(p, tp->mmio_addr, regs->len);
1476 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1477}
1478
b57b7e5a
SH		 1479static u32 rtl8169_get_msglevel(struct net_device *dev)
1480{
1481 struct rtl8169_private *tp = netdev_priv(dev);
1482
1483 return tp->msg_enable;
1484}
1485
1486static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1487{
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489
1490 tp->msg_enable = value;
1491}
1492
d4a3a0fc
SH		 1493static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1494 "tx_packets",
1495 "rx_packets",
1496 "tx_errors",
1497 "rx_errors",
1498 "rx_missed",
1499 "align_errors",
1500 "tx_single_collisions",
1501 "tx_multi_collisions",
1502 "unicast",
1503 "broadcast",
1504 "multicast",
1505 "tx_aborted",
1506 "tx_underrun",
1507};
1508
b9f2c044 1509static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1510{
b9f2c044
JG		 1511 switch (sset) {
1512 case ETH_SS_STATS:
1513 return ARRAY_SIZE(rtl8169_gstrings);
1514 default:
1515 return -EOPNOTSUPP;
1516 }
d4a3a0fc
SH		 1517}
1518
355423d0 1519static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1520{
1521 struct rtl8169_private *tp = netdev_priv(dev);
1522 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1523 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1524 struct rtl8169_counters *counters;
1525 dma_addr_t paddr;
1526 u32 cmd;
355423d0 1527 int wait = 1000;
d4a3a0fc 1528
355423d0
IV		 1529 /*
1530 * Some chips are unable to dump tally counters when the receiver
1531 * is disabled.
1532 */
1533 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1534 return;
d4a3a0fc 1535
48addcc9 1536 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1537 if (!counters)
1538 return;
1539
1540 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1541 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1542 RTL_W32(CounterAddrLow, cmd);
1543 RTL_W32(CounterAddrLow, cmd | CounterDump);
1544
355423d0
IV		 1545 while (wait--) {
1546 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1547 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1548 break;
355423d0
IV		 1549 }
1550 udelay(10);
d4a3a0fc
SH		 1551 }
1552
1553 RTL_W32(CounterAddrLow, 0);
1554 RTL_W32(CounterAddrHigh, 0);
1555
48addcc9 1556 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1557}
1558
355423d0
IV		 1559static void rtl8169_get_ethtool_stats(struct net_device *dev,
1560 struct ethtool_stats *stats, u64 *data)
1561{
1562 struct rtl8169_private *tp = netdev_priv(dev);
1563
1564 ASSERT_RTNL();
1565
1566 rtl8169_update_counters(dev);
1567
1568 data[0] = le64_to_cpu(tp->counters.tx_packets);
1569 data[1] = le64_to_cpu(tp->counters.rx_packets);
1570 data[2] = le64_to_cpu(tp->counters.tx_errors);
1571 data[3] = le32_to_cpu(tp->counters.rx_errors);
1572 data[4] = le16_to_cpu(tp->counters.rx_missed);
1573 data[5] = le16_to_cpu(tp->counters.align_errors);
1574 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1575 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1576 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1577 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1578 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1579 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1580 data[12] = le16_to_cpu(tp->counters.tx_underun);
1581}
1582
d4a3a0fc
SH		 1583static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1584{
1585 switch(stringset) {
1586 case ETH_SS_STATS:
1587 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1588 break;
1589 }
1590}
1591
7282d491 1592static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1593 .get_drvinfo = rtl8169_get_drvinfo,
1594 .get_regs_len = rtl8169_get_regs_len,
1595 .get_link = ethtool_op_get_link,
1596 .get_settings = rtl8169_get_settings,
1597 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1598 .get_msglevel = rtl8169_get_msglevel,
1599 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1600 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1601 .get_wol = rtl8169_get_wol,
1602 .set_wol = rtl8169_set_wol,
d4a3a0fc 1603 .get_strings = rtl8169_get_strings,
b9f2c044 1604 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1605 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1606};
1607
07d3f51f 1608static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1609 struct net_device *dev, u8 default_version)
1da177e4 1610{
5d320a20 1611 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1612 /*
1613 * The driver currently handles the 8168Bf and the 8168Be identically
1614 * but they can be identified more specifically through the test below
1615 * if needed:
1616 *
1617 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1618 *
1619 * Same thing for the 8101Eb and the 8101Ec:
1620 *
1621 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1622 */
350f7596 1623 static const struct {
1da177e4 1624 u32 mask;
e3cf0cc0 1625 u32 val;
1da177e4
LT		 1626 int mac_version;
1627 } mac_info[] = {
01dc7fec 1628 /* 8168E family. */
1629 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1630 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1631 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1632
5b538df9 1633 /* 8168D family. */
daf9df6d 1634 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1635 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1636 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1637
e6de30d6 1638 /* 8168DP family. */
1639 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1640 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1641 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1642
ef808d50 1643 /* 8168C family. */
17c99297 1644 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1645 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1646 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1647 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1648 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1649 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1650 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1651 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1652 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1653
1654 /* 8168B family. */
1655 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1656 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1657 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1658 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1659
1660 /* 8101 family. */
36a0e6c2 1661 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1662 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1663 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1664 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1665 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1666 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1667 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1668 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1669 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1670 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1671 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1672 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1673 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1674 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1675 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1676 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1677 /* FIXME: where did these entries come from ? -- FR */
1678 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1679 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1680
1681 /* 8110 family. */
1682 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1683 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1684 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1685 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1686 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1687 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1688
f21b75e9
JD		 1689 /* Catch-all */
1690 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1691 }, *p = mac_info;
1692 u32 reg;
1693
e3cf0cc0
FR		 1694 reg = RTL_R32(TxConfig);
1695 while ((reg & p->mask) != p->val)
1da177e4
LT		 1696 p++;
1697 tp->mac_version = p->mac_version;
5d320a20
FR		 1698
1699 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1700 netif_notice(tp, probe, dev,
1701 "unknown MAC, using family default\n");
1702 tp->mac_version = default_version;
1703 }
1da177e4
LT		 1704}
1705
1706static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1707{
bcf0bf90 1708 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1709}
1710
867763c1
FR		 1711struct phy_reg {
1712 u16 reg;
1713 u16 val;
1714};
1715
4da19633 1716static void rtl_writephy_batch(struct rtl8169_private *tp,
1717 const struct phy_reg *regs, int len)
867763c1
FR		 1718{
1719 while (len-- > 0) {
4da19633 1720 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1721 regs++;
1722 }
1723}
1724
bca03d5f 1725#define PHY_READ 0x00000000
1726#define PHY_DATA_OR 0x10000000
1727#define PHY_DATA_AND 0x20000000
1728#define PHY_BJMPN 0x30000000
1729#define PHY_READ_EFUSE 0x40000000
1730#define PHY_READ_MAC_BYTE 0x50000000
1731#define PHY_WRITE_MAC_BYTE 0x60000000
1732#define PHY_CLEAR_READCOUNT 0x70000000
1733#define PHY_WRITE 0x80000000
1734#define PHY_READCOUNT_EQ_SKIP 0x90000000
1735#define PHY_COMP_EQ_SKIPN 0xa0000000
1736#define PHY_COMP_NEQ_SKIPN 0xb0000000
1737#define PHY_WRITE_PREVIOUS 0xc0000000
1738#define PHY_SKIPN 0xd0000000
1739#define PHY_DELAY_MS 0xe0000000
1740#define PHY_WRITE_ERI_WORD 0xf0000000
1741
1742static void
1743rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1744{
bca03d5f 1745 __le32 *phytable = (__le32 *)fw->data;
1746 struct net_device *dev = tp->dev;
42b82dc1 1747 size_t index, fw_size = fw->size / sizeof(*phytable);
1748 u32 predata, count;
bca03d5f 1749
1750 if (fw->size % sizeof(*phytable)) {
1751 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1752 return;
1753 }
1754
42b82dc1 1755 for (index = 0; index < fw_size; index++) {
1756 u32 action = le32_to_cpu(phytable[index]);
1757 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1758
42b82dc1 1759 switch(action & 0xf0000000) {
1760 case PHY_READ:
1761 case PHY_DATA_OR:
1762 case PHY_DATA_AND:
1763 case PHY_READ_EFUSE:
1764 case PHY_CLEAR_READCOUNT:
1765 case PHY_WRITE:
1766 case PHY_WRITE_PREVIOUS:
1767 case PHY_DELAY_MS:
1768 break;
1769
1770 case PHY_BJMPN:
1771 if (regno > index) {
1772 netif_err(tp, probe, tp->dev,
cecb5fd7 1773 "Out of range of firmware\n");
42b82dc1 1774 return;
1775 }
1776 break;
1777 case PHY_READCOUNT_EQ_SKIP:
1778 if (index + 2 >= fw_size) {
1779 netif_err(tp, probe, tp->dev,
cecb5fd7 1780 "Out of range of firmware\n");
42b82dc1 1781 return;
1782 }
1783 break;
1784 case PHY_COMP_EQ_SKIPN:
1785 case PHY_COMP_NEQ_SKIPN:
1786 case PHY_SKIPN:
1787 if (index + 1 + regno >= fw_size) {
1788 netif_err(tp, probe, tp->dev,
cecb5fd7 1789 "Out of range of firmware\n");
42b82dc1 1790 return;
1791 }
bca03d5f 1792 break;
1793
42b82dc1 1794 case PHY_READ_MAC_BYTE:
1795 case PHY_WRITE_MAC_BYTE:
1796 case PHY_WRITE_ERI_WORD:
1797 default:
1798 netif_err(tp, probe, tp->dev,
1799 "Invalid action 0x%08x\n", action);
bca03d5f 1800 return;
1801 }
1802 }
1803
42b82dc1 1804 predata = 0;
1805 count = 0;
1806
1807 for (index = 0; index < fw_size; ) {
1808 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1809 u32 data = action & 0x0000ffff;
42b82dc1 1810 u32 regno = (action & 0x0fff0000) >> 16;
1811
1812 if (!action)
1813 break;
bca03d5f 1814
1815 switch(action & 0xf0000000) {
42b82dc1 1816 case PHY_READ:
1817 predata = rtl_readphy(tp, regno);
1818 count++;
1819 index++;
1820 break;
1821 case PHY_DATA_OR:
1822 predata |= data;
1823 index++;
1824 break;
1825 case PHY_DATA_AND:
1826 predata &= data;
1827 index++;
1828 break;
1829 case PHY_BJMPN:
1830 index -= regno;
1831 break;
1832 case PHY_READ_EFUSE:
1833 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1834 index++;
1835 break;
1836 case PHY_CLEAR_READCOUNT:
1837 count = 0;
1838 index++;
1839 break;
bca03d5f 1840 case PHY_WRITE:
42b82dc1 1841 rtl_writephy(tp, regno, data);
1842 index++;
1843 break;
1844 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1845 index += (count == data) ? 2 : 1;
bca03d5f 1846 break;
42b82dc1 1847 case PHY_COMP_EQ_SKIPN:
1848 if (predata == data)
1849 index += regno;
1850 index++;
1851 break;
1852 case PHY_COMP_NEQ_SKIPN:
1853 if (predata != data)
1854 index += regno;
1855 index++;
1856 break;
1857 case PHY_WRITE_PREVIOUS:
1858 rtl_writephy(tp, regno, predata);
1859 index++;
1860 break;
1861 case PHY_SKIPN:
1862 index += regno + 1;
1863 break;
1864 case PHY_DELAY_MS:
1865 mdelay(data);
1866 index++;
1867 break;
1868
1869 case PHY_READ_MAC_BYTE:
1870 case PHY_WRITE_MAC_BYTE:
1871 case PHY_WRITE_ERI_WORD:
bca03d5f 1872 default:
1873 BUG();
1874 }
1875 }
1876}
1877
f1e02ed1 1878static void rtl_release_firmware(struct rtl8169_private *tp)
1879{
953a12cc
FR		 1880 if (!IS_ERR_OR_NULL(tp->fw))
1881 release_firmware(tp->fw);
1882 tp->fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1883}
1884
953a12cc 1885static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1886{
953a12cc 1887 const struct firmware *fw = tp->fw;
f1e02ed1 1888
1889 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
953a12cc
FR		 1890 if (!IS_ERR_OR_NULL(fw))
1891 rtl_phy_write_fw(tp, fw);
1892}
1893
1894static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1895{
1896 if (rtl_readphy(tp, reg) != val)
1897 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1898 else
1899 rtl_apply_firmware(tp);
f1e02ed1 1900}
1901
4da19633 1902static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1903{
350f7596 1904 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1905 { 0x1f, 0x0001 },
1906 { 0x06, 0x006e },
1907 { 0x08, 0x0708 },
1908 { 0x15, 0x4000 },
1909 { 0x18, 0x65c7 },
1da177e4 1910
0b9b571d 1911 { 0x1f, 0x0001 },
1912 { 0x03, 0x00a1 },
1913 { 0x02, 0x0008 },
1914 { 0x01, 0x0120 },
1915 { 0x00, 0x1000 },
1916 { 0x04, 0x0800 },
1917 { 0x04, 0x0000 },
1da177e4 1918
0b9b571d 1919 { 0x03, 0xff41 },
1920 { 0x02, 0xdf60 },
1921 { 0x01, 0x0140 },
1922 { 0x00, 0x0077 },
1923 { 0x04, 0x7800 },
1924 { 0x04, 0x7000 },
1925
1926 { 0x03, 0x802f },
1927 { 0x02, 0x4f02 },
1928 { 0x01, 0x0409 },
1929 { 0x00, 0xf0f9 },
1930 { 0x04, 0x9800 },
1931 { 0x04, 0x9000 },
1932
1933 { 0x03, 0xdf01 },
1934 { 0x02, 0xdf20 },
1935 { 0x01, 0xff95 },
1936 { 0x00, 0xba00 },
1937 { 0x04, 0xa800 },
1938 { 0x04, 0xa000 },
1939
1940 { 0x03, 0xff41 },
1941 { 0x02, 0xdf20 },
1942 { 0x01, 0x0140 },
1943 { 0x00, 0x00bb },
1944 { 0x04, 0xb800 },
1945 { 0x04, 0xb000 },
1946
1947 { 0x03, 0xdf41 },
1948 { 0x02, 0xdc60 },
1949 { 0x01, 0x6340 },
1950 { 0x00, 0x007d },
1951 { 0x04, 0xd800 },
1952 { 0x04, 0xd000 },
1953
1954 { 0x03, 0xdf01 },
1955 { 0x02, 0xdf20 },
1956 { 0x01, 0x100a },
1957 { 0x00, 0xa0ff },
1958 { 0x04, 0xf800 },
1959 { 0x04, 0xf000 },
1960
1961 { 0x1f, 0x0000 },
1962 { 0x0b, 0x0000 },
1963 { 0x00, 0x9200 }
1964 };
1da177e4 1965
4da19633 1966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1967}
1968
4da19633 1969static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1970{
350f7596 1971 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1972 { 0x1f, 0x0002 },
1973 { 0x01, 0x90d0 },
1974 { 0x1f, 0x0000 }
1975 };
1976
4da19633 1977 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1978}
1979
4da19633 1980static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1981{
1982 struct pci_dev *pdev = tp->pci_dev;
1983 u16 vendor_id, device_id;
1984
1985 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1986 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1987
1988 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1989 return;
1990
4da19633 1991 rtl_writephy(tp, 0x1f, 0x0001);
1992 rtl_writephy(tp, 0x10, 0xf01b);
1993 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1994}
1995
4da19633 1996static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1997{
350f7596 1998 static const struct phy_reg phy_reg_init[] = {
2e955856 1999 { 0x1f, 0x0001 },
2000 { 0x04, 0x0000 },
2001 { 0x03, 0x00a1 },
2002 { 0x02, 0x0008 },
2003 { 0x01, 0x0120 },
2004 { 0x00, 0x1000 },
2005 { 0x04, 0x0800 },
2006 { 0x04, 0x9000 },
2007 { 0x03, 0x802f },
2008 { 0x02, 0x4f02 },
2009 { 0x01, 0x0409 },
2010 { 0x00, 0xf099 },
2011 { 0x04, 0x9800 },
2012 { 0x04, 0xa000 },
2013 { 0x03, 0xdf01 },
2014 { 0x02, 0xdf20 },
2015 { 0x01, 0xff95 },
2016 { 0x00, 0xba00 },
2017 { 0x04, 0xa800 },
2018 { 0x04, 0xf000 },
2019 { 0x03, 0xdf01 },
2020 { 0x02, 0xdf20 },
2021 { 0x01, 0x101a },
2022 { 0x00, 0xa0ff },
2023 { 0x04, 0xf800 },
2024 { 0x04, 0x0000 },
2025 { 0x1f, 0x0000 },
2026
2027 { 0x1f, 0x0001 },
2028 { 0x10, 0xf41b },
2029 { 0x14, 0xfb54 },
2030 { 0x18, 0xf5c7 },
2031 { 0x1f, 0x0000 },
2032
2033 { 0x1f, 0x0001 },
2034 { 0x17, 0x0cc0 },
2035 { 0x1f, 0x0000 }
2036 };
2037
4da19633 2038 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2039
4da19633 2040 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2041}
2042
4da19633 2043static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2044{
350f7596 2045 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2046 { 0x1f, 0x0001 },
2047 { 0x04, 0x0000 },
2048 { 0x03, 0x00a1 },
2049 { 0x02, 0x0008 },
2050 { 0x01, 0x0120 },
2051 { 0x00, 0x1000 },
2052 { 0x04, 0x0800 },
2053 { 0x04, 0x9000 },
2054 { 0x03, 0x802f },
2055 { 0x02, 0x4f02 },
2056 { 0x01, 0x0409 },
2057 { 0x00, 0xf099 },
2058 { 0x04, 0x9800 },
2059 { 0x04, 0xa000 },
2060 { 0x03, 0xdf01 },
2061 { 0x02, 0xdf20 },
2062 { 0x01, 0xff95 },
2063 { 0x00, 0xba00 },
2064 { 0x04, 0xa800 },
2065 { 0x04, 0xf000 },
2066 { 0x03, 0xdf01 },
2067 { 0x02, 0xdf20 },
2068 { 0x01, 0x101a },
2069 { 0x00, 0xa0ff },
2070 { 0x04, 0xf800 },
2071 { 0x04, 0x0000 },
2072 { 0x1f, 0x0000 },
2073
2074 { 0x1f, 0x0001 },
2075 { 0x0b, 0x8480 },
2076 { 0x1f, 0x0000 },
2077
2078 { 0x1f, 0x0001 },
2079 { 0x18, 0x67c7 },
2080 { 0x04, 0x2000 },
2081 { 0x03, 0x002f },
2082 { 0x02, 0x4360 },
2083 { 0x01, 0x0109 },
2084 { 0x00, 0x3022 },
2085 { 0x04, 0x2800 },
2086 { 0x1f, 0x0000 },
2087
2088 { 0x1f, 0x0001 },
2089 { 0x17, 0x0cc0 },
2090 { 0x1f, 0x0000 }
2091 };
2092
4da19633 2093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2094}
2095
4da19633 2096static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2097{
350f7596 2098 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2099 { 0x10, 0xf41b },
2100 { 0x1f, 0x0000 }
2101 };
2102
4da19633 2103 rtl_writephy(tp, 0x1f, 0x0001);
2104 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2105
4da19633 2106 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2107}
2108
4da19633 2109static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2110{
350f7596 2111 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2112 { 0x1f, 0x0001 },
2113 { 0x10, 0xf41b },
2114 { 0x1f, 0x0000 }
2115 };
2116
4da19633 2117 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2118}
2119
4da19633 2120static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2121{
350f7596 2122 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2123 { 0x1f, 0x0000 },
2124 { 0x1d, 0x0f00 },
2125 { 0x1f, 0x0002 },
2126 { 0x0c, 0x1ec8 },
2127 { 0x1f, 0x0000 }
2128 };
2129
4da19633 2130 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2131}
2132
4da19633 2133static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2134{
350f7596 2135 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2136 { 0x1f, 0x0001 },
2137 { 0x1d, 0x3d98 },
2138 { 0x1f, 0x0000 }
2139 };
2140
4da19633 2141 rtl_writephy(tp, 0x1f, 0x0000);
2142 rtl_patchphy(tp, 0x14, 1 << 5);
2143 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2144
4da19633 2145 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2146}
2147
4da19633 2148static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2149{
350f7596 2150 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2151 { 0x1f, 0x0001 },
2152 { 0x12, 0x2300 },
867763c1
FR		 2153 { 0x1f, 0x0002 },
2154 { 0x00, 0x88d4 },
2155 { 0x01, 0x82b1 },
2156 { 0x03, 0x7002 },
2157 { 0x08, 0x9e30 },
2158 { 0x09, 0x01f0 },
2159 { 0x0a, 0x5500 },
2160 { 0x0c, 0x00c8 },
2161 { 0x1f, 0x0003 },
2162 { 0x12, 0xc096 },
2163 { 0x16, 0x000a },
f50d4275
FR		 2164 { 0x1f, 0x0000 },
2165 { 0x1f, 0x0000 },
2166 { 0x09, 0x2000 },
2167 { 0x09, 0x0000 }
867763c1
FR		 2168 };
2169
4da19633 2170 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2171
4da19633 2172 rtl_patchphy(tp, 0x14, 1 << 5);
2173 rtl_patchphy(tp, 0x0d, 1 << 5);
2174 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2175}
2176
4da19633 2177static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2178{
350f7596 2179 static const struct phy_reg phy_reg_init[] = {
f50d4275 2180 { 0x1f, 0x0001 },
7da97ec9 2181 { 0x12, 0x2300 },
f50d4275
FR		 2182 { 0x03, 0x802f },
2183 { 0x02, 0x4f02 },
2184 { 0x01, 0x0409 },
2185 { 0x00, 0xf099 },
2186 { 0x04, 0x9800 },
2187 { 0x04, 0x9000 },
2188 { 0x1d, 0x3d98 },
7da97ec9
FR		 2189 { 0x1f, 0x0002 },
2190 { 0x0c, 0x7eb8 },
f50d4275
FR		 2191 { 0x06, 0x0761 },
2192 { 0x1f, 0x0003 },
2193 { 0x16, 0x0f0a },
7da97ec9
FR		 2194 { 0x1f, 0x0000 }
2195 };
2196
4da19633 2197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2198
4da19633 2199 rtl_patchphy(tp, 0x16, 1 << 0);
2200 rtl_patchphy(tp, 0x14, 1 << 5);
2201 rtl_patchphy(tp, 0x0d, 1 << 5);
2202 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2203}
2204
4da19633 2205static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2206{
350f7596 2207 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2208 { 0x1f, 0x0001 },
2209 { 0x12, 0x2300 },
2210 { 0x1d, 0x3d98 },
2211 { 0x1f, 0x0002 },
2212 { 0x0c, 0x7eb8 },
2213 { 0x06, 0x5461 },
2214 { 0x1f, 0x0003 },
2215 { 0x16, 0x0f0a },
2216 { 0x1f, 0x0000 }
2217 };
2218
4da19633 2219 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2220
4da19633 2221 rtl_patchphy(tp, 0x16, 1 << 0);
2222 rtl_patchphy(tp, 0x14, 1 << 5);
2223 rtl_patchphy(tp, 0x0d, 1 << 5);
2224 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2225}
2226
4da19633 2227static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2228{
4da19633 2229 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2230}
2231
bca03d5f 2232static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2233{
350f7596 2234 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2235 /* Channel Estimation */
5b538df9 2236 { 0x1f, 0x0001 },
daf9df6d 2237 { 0x06, 0x4064 },
2238 { 0x07, 0x2863 },
2239 { 0x08, 0x059c },
2240 { 0x09, 0x26b4 },
2241 { 0x0a, 0x6a19 },
2242 { 0x0b, 0xdcc8 },
2243 { 0x10, 0xf06d },
2244 { 0x14, 0x7f68 },
2245 { 0x18, 0x7fd9 },
2246 { 0x1c, 0xf0ff },
2247 { 0x1d, 0x3d9c },
5b538df9 2248 { 0x1f, 0x0003 },
daf9df6d 2249 { 0x12, 0xf49f },
2250 { 0x13, 0x070b },
2251 { 0x1a, 0x05ad },
bca03d5f 2252 { 0x14, 0x94c0 },
2253
2254 /*
2255 * Tx Error Issue
cecb5fd7 2256 * Enhance line driver power
bca03d5f 2257 */
5b538df9 2258 { 0x1f, 0x0002 },
daf9df6d 2259 { 0x06, 0x5561 },
2260 { 0x1f, 0x0005 },
2261 { 0x05, 0x8332 },
bca03d5f 2262 { 0x06, 0x5561 },
2263
2264 /*
2265 * Can not link to 1Gbps with bad cable
2266 * Decrease SNR threshold form 21.07dB to 19.04dB
2267 */
2268 { 0x1f, 0x0001 },
2269 { 0x17, 0x0cc0 },
daf9df6d 2270
5b538df9 2271 { 0x1f, 0x0000 },
bca03d5f 2272 { 0x0d, 0xf880 }
daf9df6d 2273 };
bca03d5f 2274 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2275
4da19633 2276 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2277
bca03d5f 2278 /*
2279 * Rx Error Issue
2280 * Fine Tune Switching regulator parameter
2281 */
4da19633 2282 rtl_writephy(tp, 0x1f, 0x0002);
2283 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2284 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2285
daf9df6d 2286 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2287 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2288 { 0x1f, 0x0002 },
2289 { 0x05, 0x669a },
2290 { 0x1f, 0x0005 },
2291 { 0x05, 0x8330 },
2292 { 0x06, 0x669a },
2293 { 0x1f, 0x0002 }
2294 };
2295 int val;
2296
4da19633 2297 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2298
4da19633 2299 val = rtl_readphy(tp, 0x0d);
daf9df6d 2300
2301 if ((val & 0x00ff) != 0x006c) {
350f7596 2302 static const u32 set[] = {
daf9df6d 2303 0x0065, 0x0066, 0x0067, 0x0068,
2304 0x0069, 0x006a, 0x006b, 0x006c
2305 };
2306 int i;
2307
4da19633 2308 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2309
2310 val &= 0xff00;
2311 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2312 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2313 }
2314 } else {
350f7596 2315 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2316 { 0x1f, 0x0002 },
2317 { 0x05, 0x6662 },
2318 { 0x1f, 0x0005 },
2319 { 0x05, 0x8330 },
2320 { 0x06, 0x6662 }
2321 };
2322
4da19633 2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2324 }
2325
bca03d5f 2326 /* RSET couple improve */
4da19633 2327 rtl_writephy(tp, 0x1f, 0x0002);
2328 rtl_patchphy(tp, 0x0d, 0x0300);
2329 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2330
bca03d5f 2331 /* Fine tune PLL performance */
4da19633 2332 rtl_writephy(tp, 0x1f, 0x0002);
2333 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2334 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2335
4da19633 2336 rtl_writephy(tp, 0x1f, 0x0005);
2337 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2338
2339 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2340
4da19633 2341 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2342}
2343
bca03d5f 2344static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2345{
350f7596 2346 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2347 /* Channel Estimation */
daf9df6d 2348 { 0x1f, 0x0001 },
2349 { 0x06, 0x4064 },
2350 { 0x07, 0x2863 },
2351 { 0x08, 0x059c },
2352 { 0x09, 0x26b4 },
2353 { 0x0a, 0x6a19 },
2354 { 0x0b, 0xdcc8 },
2355 { 0x10, 0xf06d },
2356 { 0x14, 0x7f68 },
2357 { 0x18, 0x7fd9 },
2358 { 0x1c, 0xf0ff },
2359 { 0x1d, 0x3d9c },
2360 { 0x1f, 0x0003 },
2361 { 0x12, 0xf49f },
2362 { 0x13, 0x070b },
2363 { 0x1a, 0x05ad },
2364 { 0x14, 0x94c0 },
2365
bca03d5f 2366 /*
2367 * Tx Error Issue
cecb5fd7 2368 * Enhance line driver power
bca03d5f 2369 */
daf9df6d 2370 { 0x1f, 0x0002 },
2371 { 0x06, 0x5561 },
2372 { 0x1f, 0x0005 },
2373 { 0x05, 0x8332 },
bca03d5f 2374 { 0x06, 0x5561 },
2375
2376 /*
2377 * Can not link to 1Gbps with bad cable
2378 * Decrease SNR threshold form 21.07dB to 19.04dB
2379 */
2380 { 0x1f, 0x0001 },
2381 { 0x17, 0x0cc0 },
daf9df6d 2382
2383 { 0x1f, 0x0000 },
bca03d5f 2384 { 0x0d, 0xf880 }
5b538df9 2385 };
bca03d5f 2386 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2387
4da19633 2388 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2389
daf9df6d 2390 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2391 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2392 { 0x1f, 0x0002 },
2393 { 0x05, 0x669a },
5b538df9 2394 { 0x1f, 0x0005 },
daf9df6d 2395 { 0x05, 0x8330 },
2396 { 0x06, 0x669a },
2397
2398 { 0x1f, 0x0002 }
2399 };
2400 int val;
2401
4da19633 2402 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2403
4da19633 2404 val = rtl_readphy(tp, 0x0d);
daf9df6d 2405 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2406 static const u32 set[] = {
daf9df6d 2407 0x0065, 0x0066, 0x0067, 0x0068,
2408 0x0069, 0x006a, 0x006b, 0x006c
2409 };
2410 int i;
2411
4da19633 2412 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2413
2414 val &= 0xff00;
2415 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2416 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2417 }
2418 } else {
350f7596 2419 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2420 { 0x1f, 0x0002 },
2421 { 0x05, 0x2642 },
5b538df9 2422 { 0x1f, 0x0005 },
daf9df6d 2423 { 0x05, 0x8330 },
2424 { 0x06, 0x2642 }
5b538df9
FR		 2425 };
2426
4da19633 2427 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2428 }
2429
bca03d5f 2430 /* Fine tune PLL performance */
4da19633 2431 rtl_writephy(tp, 0x1f, 0x0002);
2432 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2433 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2434
bca03d5f 2435 /* Switching regulator Slew rate */
4da19633 2436 rtl_writephy(tp, 0x1f, 0x0002);
2437 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2438
4da19633 2439 rtl_writephy(tp, 0x1f, 0x0005);
2440 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2441
2442 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2443
4da19633 2444 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2445}
2446
4da19633 2447static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2448{
350f7596 2449 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2450 { 0x1f, 0x0002 },
2451 { 0x10, 0x0008 },
2452 { 0x0d, 0x006c },
2453
2454 { 0x1f, 0x0000 },
2455 { 0x0d, 0xf880 },
2456
2457 { 0x1f, 0x0001 },
2458 { 0x17, 0x0cc0 },
2459
2460 { 0x1f, 0x0001 },
2461 { 0x0b, 0xa4d8 },
2462 { 0x09, 0x281c },
2463 { 0x07, 0x2883 },
2464 { 0x0a, 0x6b35 },
2465 { 0x1d, 0x3da4 },
2466 { 0x1c, 0xeffd },
2467 { 0x14, 0x7f52 },
2468 { 0x18, 0x7fc6 },
2469 { 0x08, 0x0601 },
2470 { 0x06, 0x4063 },
2471 { 0x10, 0xf074 },
2472 { 0x1f, 0x0003 },
2473 { 0x13, 0x0789 },
2474 { 0x12, 0xf4bd },
2475 { 0x1a, 0x04fd },
2476 { 0x14, 0x84b0 },
2477 { 0x1f, 0x0000 },
2478 { 0x00, 0x9200 },
2479
2480 { 0x1f, 0x0005 },
2481 { 0x01, 0x0340 },
2482 { 0x1f, 0x0001 },
2483 { 0x04, 0x4000 },
2484 { 0x03, 0x1d21 },
2485 { 0x02, 0x0c32 },
2486 { 0x01, 0x0200 },
2487 { 0x00, 0x5554 },
2488 { 0x04, 0x4800 },
2489 { 0x04, 0x4000 },
2490 { 0x04, 0xf000 },
2491 { 0x03, 0xdf01 },
2492 { 0x02, 0xdf20 },
2493 { 0x01, 0x101a },
2494 { 0x00, 0xa0ff },
2495 { 0x04, 0xf800 },
2496 { 0x04, 0xf000 },
2497 { 0x1f, 0x0000 },
2498
2499 { 0x1f, 0x0007 },
2500 { 0x1e, 0x0023 },
2501 { 0x16, 0x0000 },
2502 { 0x1f, 0x0000 }
2503 };
2504
4da19633 2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2506}
2507
e6de30d6 2508static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2509{
2510 static const struct phy_reg phy_reg_init[] = {
2511 { 0x1f, 0x0001 },
2512 { 0x17, 0x0cc0 },
2513
2514 { 0x1f, 0x0007 },
2515 { 0x1e, 0x002d },
2516 { 0x18, 0x0040 },
2517 { 0x1f, 0x0000 }
2518 };
2519
2520 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2521 rtl_patchphy(tp, 0x0d, 1 << 5);
2522}
2523
01dc7fec 2524static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2525{
2526 static const struct phy_reg phy_reg_init[] = {
2527 /* Enable Delay cap */
2528 { 0x1f, 0x0005 },
2529 { 0x05, 0x8b80 },
2530 { 0x06, 0xc896 },
2531 { 0x1f, 0x0000 },
2532
2533 /* Channel estimation fine tune */
2534 { 0x1f, 0x0001 },
2535 { 0x0b, 0x6c20 },
2536 { 0x07, 0x2872 },
2537 { 0x1c, 0xefff },
2538 { 0x1f, 0x0003 },
2539 { 0x14, 0x6420 },
2540 { 0x1f, 0x0000 },
2541
2542 /* Update PFM & 10M TX idle timer */
2543 { 0x1f, 0x0007 },
2544 { 0x1e, 0x002f },
2545 { 0x15, 0x1919 },
2546 { 0x1f, 0x0000 },
2547
2548 { 0x1f, 0x0007 },
2549 { 0x1e, 0x00ac },
2550 { 0x18, 0x0006 },
2551 { 0x1f, 0x0000 }
2552 };
2553
15ecd039
FR		 2554 rtl_apply_firmware(tp);
2555
01dc7fec 2556 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2557
2558 /* DCO enable for 10M IDLE Power */
2559 rtl_writephy(tp, 0x1f, 0x0007);
2560 rtl_writephy(tp, 0x1e, 0x0023);
2561 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2562 rtl_writephy(tp, 0x1f, 0x0000);
2563
2564 /* For impedance matching */
2565 rtl_writephy(tp, 0x1f, 0x0002);
2566 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2567 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2568
2569 /* PHY auto speed down */
2570 rtl_writephy(tp, 0x1f, 0x0007);
2571 rtl_writephy(tp, 0x1e, 0x002d);
2572 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2573 rtl_writephy(tp, 0x1f, 0x0000);
2574 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2575
2576 rtl_writephy(tp, 0x1f, 0x0005);
2577 rtl_writephy(tp, 0x05, 0x8b86);
2578 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2579 rtl_writephy(tp, 0x1f, 0x0000);
2580
2581 rtl_writephy(tp, 0x1f, 0x0005);
2582 rtl_writephy(tp, 0x05, 0x8b85);
2583 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2584 rtl_writephy(tp, 0x1f, 0x0007);
2585 rtl_writephy(tp, 0x1e, 0x0020);
2586 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2587 rtl_writephy(tp, 0x1f, 0x0006);
2588 rtl_writephy(tp, 0x00, 0x5a00);
2589 rtl_writephy(tp, 0x1f, 0x0000);
2590 rtl_writephy(tp, 0x0d, 0x0007);
2591 rtl_writephy(tp, 0x0e, 0x003c);
2592 rtl_writephy(tp, 0x0d, 0x4007);
2593 rtl_writephy(tp, 0x0e, 0x0000);
2594 rtl_writephy(tp, 0x0d, 0x0000);
2595}
2596
4da19633 2597static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2598{
350f7596 2599 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2600 { 0x1f, 0x0003 },
2601 { 0x08, 0x441d },
2602 { 0x01, 0x9100 },
2603 { 0x1f, 0x0000 }
2604 };
2605
4da19633 2606 rtl_writephy(tp, 0x1f, 0x0000);
2607 rtl_patchphy(tp, 0x11, 1 << 12);
2608 rtl_patchphy(tp, 0x19, 1 << 13);
2609 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2610
4da19633 2611 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2612}
2613
5a5e4443
HW		 2614static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2615{
2616 static const struct phy_reg phy_reg_init[] = {
2617 { 0x1f, 0x0005 },
2618 { 0x1a, 0x0000 },
2619 { 0x1f, 0x0000 },
2620
2621 { 0x1f, 0x0004 },
2622 { 0x1c, 0x0000 },
2623 { 0x1f, 0x0000 },
2624
2625 { 0x1f, 0x0001 },
2626 { 0x15, 0x7701 },
2627 { 0x1f, 0x0000 }
2628 };
2629
2630 /* Disable ALDPS before ram code */
2631 rtl_writephy(tp, 0x1f, 0x0000);
2632 rtl_writephy(tp, 0x18, 0x0310);
2633 msleep(100);
2634
953a12cc 2635 rtl_apply_firmware(tp);
5a5e4443
HW		 2636
2637 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2638}
2639
5615d9f1
FR		 2640static void rtl_hw_phy_config(struct net_device *dev)
2641{
2642 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2643
2644 rtl8169_print_mac_version(tp);
2645
2646 switch (tp->mac_version) {
2647 case RTL_GIGA_MAC_VER_01:
2648 break;
2649 case RTL_GIGA_MAC_VER_02:
2650 case RTL_GIGA_MAC_VER_03:
4da19633 2651 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2652 break;
2653 case RTL_GIGA_MAC_VER_04:
4da19633 2654 rtl8169sb_hw_phy_config(tp);
5615d9f1 2655 break;
2e955856 2656 case RTL_GIGA_MAC_VER_05:
4da19633 2657 rtl8169scd_hw_phy_config(tp);
2e955856 2658 break;
8c7006aa 2659 case RTL_GIGA_MAC_VER_06:
4da19633 2660 rtl8169sce_hw_phy_config(tp);
8c7006aa 2661 break;
2857ffb7
FR		 2662 case RTL_GIGA_MAC_VER_07:
2663 case RTL_GIGA_MAC_VER_08:
2664 case RTL_GIGA_MAC_VER_09:
4da19633 2665 rtl8102e_hw_phy_config(tp);
2857ffb7 2666 break;
236b8082 2667 case RTL_GIGA_MAC_VER_11:
4da19633 2668 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2669 break;
2670 case RTL_GIGA_MAC_VER_12:
4da19633 2671 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2672 break;
2673 case RTL_GIGA_MAC_VER_17:
4da19633 2674 rtl8168bef_hw_phy_config(tp);
236b8082 2675 break;
867763c1 2676 case RTL_GIGA_MAC_VER_18:
4da19633 2677 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2678 break;
2679 case RTL_GIGA_MAC_VER_19:
4da19633 2680 rtl8168c_1_hw_phy_config(tp);
867763c1 2681 break;
7da97ec9 2682 case RTL_GIGA_MAC_VER_20:
4da19633 2683 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2684 break;
197ff761 2685 case RTL_GIGA_MAC_VER_21:
4da19633 2686 rtl8168c_3_hw_phy_config(tp);
197ff761 2687 break;
6fb07058 2688 case RTL_GIGA_MAC_VER_22:
4da19633 2689 rtl8168c_4_hw_phy_config(tp);
6fb07058 2690 break;
ef3386f0 2691 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2692 case RTL_GIGA_MAC_VER_24:
4da19633 2693 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2694 break;
5b538df9 2695 case RTL_GIGA_MAC_VER_25:
bca03d5f 2696 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2697 break;
2698 case RTL_GIGA_MAC_VER_26:
bca03d5f 2699 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2700 break;
2701 case RTL_GIGA_MAC_VER_27:
4da19633 2702 rtl8168d_3_hw_phy_config(tp);
5b538df9 2703 break;
e6de30d6 2704 case RTL_GIGA_MAC_VER_28:
2705 rtl8168d_4_hw_phy_config(tp);
2706 break;
5a5e4443
HW		 2707 case RTL_GIGA_MAC_VER_29:
2708 case RTL_GIGA_MAC_VER_30:
2709 rtl8105e_hw_phy_config(tp);
2710 break;
cecb5fd7
FR		 2711 case RTL_GIGA_MAC_VER_31:
2712 /* None. */
2713 break;
01dc7fec 2714 case RTL_GIGA_MAC_VER_32:
01dc7fec 2715 case RTL_GIGA_MAC_VER_33:
15ecd039 2716 rtl8168e_hw_phy_config(tp);
01dc7fec 2717 break;
ef3386f0 2718
5615d9f1
FR		 2719 default:
2720 break;
2721 }
2722}
2723
1da177e4
LT		 2724static void rtl8169_phy_timer(unsigned long __opaque)
2725{
2726 struct net_device *dev = (struct net_device *)__opaque;
2727 struct rtl8169_private *tp = netdev_priv(dev);
2728 struct timer_list *timer = &tp->timer;
2729 void __iomem *ioaddr = tp->mmio_addr;
2730 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2731
bcf0bf90 2732 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2733
1da177e4
LT		 2734 spin_lock_irq(&tp->lock);
2735
4da19633 2736 if (tp->phy_reset_pending(tp)) {
5b0384f4 2737 /*
1da177e4
LT		 2738 * A busy loop could burn quite a few cycles on nowadays CPU.
2739 * Let's delay the execution of the timer for a few ticks.
2740 */
2741 timeout = HZ/10;
2742 goto out_mod_timer;
2743 }
2744
2745 if (tp->link_ok(ioaddr))
2746 goto out_unlock;
2747
bf82c189 2748 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2749
4da19633 2750 tp->phy_reset_enable(tp);
1da177e4
LT		 2751
2752out_mod_timer:
2753 mod_timer(timer, jiffies + timeout);
2754out_unlock:
2755 spin_unlock_irq(&tp->lock);
2756}
2757
1da177e4
LT		 2758#ifdef CONFIG_NET_POLL_CONTROLLER
2759/*
2760 * Polling 'interrupt' - used by things like netconsole to send skbs
2761 * without having to re-enable interrupts. It's not called while
2762 * the interrupt routine is executing.
2763 */
2764static void rtl8169_netpoll(struct net_device *dev)
2765{
2766 struct rtl8169_private *tp = netdev_priv(dev);
2767 struct pci_dev *pdev = tp->pci_dev;
2768
2769 disable_irq(pdev->irq);
7d12e780 2770 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2771 enable_irq(pdev->irq);
2772}
2773#endif
2774
2775static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2776 void __iomem *ioaddr)
2777{
2778 iounmap(ioaddr);
2779 pci_release_regions(pdev);
87aeec76 2780 pci_clear_mwi(pdev);
1da177e4
LT		 2781 pci_disable_device(pdev);
2782 free_netdev(dev);
2783}
2784
bf793295
FR		 2785static void rtl8169_phy_reset(struct net_device *dev,
2786 struct rtl8169_private *tp)
2787{
07d3f51f 2788 unsigned int i;
bf793295 2789
4da19633 2790 tp->phy_reset_enable(tp);
bf793295 2791 for (i = 0; i < 100; i++) {
4da19633 2792 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2793 return;
2794 msleep(1);
2795 }
bf82c189 2796 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2797}
2798
4ff96fa6
FR		 2799static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2800{
2801 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2802
5615d9f1 2803 rtl_hw_phy_config(dev);
4ff96fa6 2804
77332894
MS		 2805 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2806 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2807 RTL_W8(0x82, 0x01);
2808 }
4ff96fa6 2809
6dccd16b
FR		 2810 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2811
2812 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2813 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2814
bcf0bf90 2815 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2816 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2817 RTL_W8(0x82, 0x01);
2818 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2819 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2820 }
2821
bf793295
FR		 2822 rtl8169_phy_reset(dev, tp);
2823
54405cde 2824 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2825 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2826 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2827 (tp->mii.supports_gmii ?
2828 ADVERTISED_1000baseT_Half |
2829 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2830
bf82c189
JP		 2831 if (RTL_R8(PHYstatus) & TBI_Enable)
2832 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2833}
2834
773d2021
FR		 2835static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2836{
2837 void __iomem *ioaddr = tp->mmio_addr;
2838 u32 high;
2839 u32 low;
2840
2841 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2842 high = addr[4] | (addr[5] << 8);
2843
2844 spin_lock_irq(&tp->lock);
2845
2846 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2847
773d2021 2848 RTL_W32(MAC4, high);
908ba2bf 2849 RTL_R32(MAC4);
2850
78f1cd02 2851 RTL_W32(MAC0, low);
908ba2bf 2852 RTL_R32(MAC0);
2853
773d2021
FR		 2854 RTL_W8(Cfg9346, Cfg9346_Lock);
2855
2856 spin_unlock_irq(&tp->lock);
2857}
2858
2859static int rtl_set_mac_address(struct net_device *dev, void *p)
2860{
2861 struct rtl8169_private *tp = netdev_priv(dev);
2862 struct sockaddr *addr = p;
2863
2864 if (!is_valid_ether_addr(addr->sa_data))
2865 return -EADDRNOTAVAIL;
2866
2867 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2868
2869 rtl_rar_set(tp, dev->dev_addr);
2870
2871 return 0;
2872}
2873
5f787a1a
FR		 2874static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2875{
2876 struct rtl8169_private *tp = netdev_priv(dev);
2877 struct mii_ioctl_data *data = if_mii(ifr);
2878
8b4ab28d
FR		 2879 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2880}
5f787a1a 2881
cecb5fd7
FR		 2882static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2883 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2884{
5f787a1a
FR		 2885 switch (cmd) {
2886 case SIOCGMIIPHY:
2887 data->phy_id = 32; /* Internal PHY */
2888 return 0;
2889
2890 case SIOCGMIIREG:
4da19633 2891 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2892 return 0;
2893
2894 case SIOCSMIIREG:
4da19633 2895 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2896 return 0;
2897 }
2898 return -EOPNOTSUPP;
2899}
2900
8b4ab28d
FR		 2901static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2902{
2903 return -EOPNOTSUPP;
2904}
2905
0e485150
FR		 2906static const struct rtl_cfg_info {
2907 void (*hw_start)(struct net_device *);
2908 unsigned int region;
2909 unsigned int align;
2910 u16 intr_event;
2911 u16 napi_event;
ccdffb9a 2912 unsigned features;
f21b75e9 2913 u8 default_ver;
0e485150
FR		 2914} rtl_cfg_infos [] = {
2915 [RTL_CFG_0] = {
2916 .hw_start = rtl_hw_start_8169,
2917 .region = 1,
e9f63f30 2918 .align = 0,
0e485150
FR		 2919 .intr_event = SYSErr | LinkChg | RxOverflow |
2920 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2921 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2922 .features = RTL_FEATURE_GMII,
2923 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2924 },
2925 [RTL_CFG_1] = {
2926 .hw_start = rtl_hw_start_8168,
2927 .region = 2,
2928 .align = 8,
53f57357 2929 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2930 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2931 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2932 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2933 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2934 },
2935 [RTL_CFG_2] = {
2936 .hw_start = rtl_hw_start_8101,
2937 .region = 2,
2938 .align = 8,
2939 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2940 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2941 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2942 .features = RTL_FEATURE_MSI,
2943 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2944 }
2945};
2946
fbac58fc
FR		 2947/* Cfg9346_Unlock assumed. */
2948static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2949 const struct rtl_cfg_info *cfg)
2950{
2951 unsigned msi = 0;
2952 u8 cfg2;
2953
2954 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2955 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2956 if (pci_enable_msi(pdev)) {
2957 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2958 } else {
2959 cfg2 |= MSIEnable;
2960 msi = RTL_FEATURE_MSI;
2961 }
2962 }
2963 RTL_W8(Config2, cfg2);
2964 return msi;
2965}
2966
2967static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2968{
2969 if (tp->features & RTL_FEATURE_MSI) {
2970 pci_disable_msi(pdev);
2971 tp->features &= ~RTL_FEATURE_MSI;
2972 }
2973}
2974
8b4ab28d
FR		 2975static const struct net_device_ops rtl8169_netdev_ops = {
2976 .ndo_open = rtl8169_open,
2977 .ndo_stop = rtl8169_close,
2978 .ndo_get_stats = rtl8169_get_stats,
00829823 2979 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2980 .ndo_tx_timeout = rtl8169_tx_timeout,
2981 .ndo_validate_addr = eth_validate_addr,
2982 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2983 .ndo_fix_features = rtl8169_fix_features,
2984 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2985 .ndo_set_mac_address = rtl_set_mac_address,
2986 .ndo_do_ioctl = rtl8169_ioctl,
2987 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2988#ifdef CONFIG_NET_POLL_CONTROLLER
2989 .ndo_poll_controller = rtl8169_netpoll,
2990#endif
2991
2992};
2993
c0e45c1c 2994static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2995{
2996 struct mdio_ops *ops = &tp->mdio_ops;
2997
2998 switch (tp->mac_version) {
2999 case RTL_GIGA_MAC_VER_27:
3000 ops->write = r8168dp_1_mdio_write;
3001 ops->read = r8168dp_1_mdio_read;
3002 break;
e6de30d6 3003 case RTL_GIGA_MAC_VER_28:
4804b3b3 3004 case RTL_GIGA_MAC_VER_31:
e6de30d6 3005 ops->write = r8168dp_2_mdio_write;
3006 ops->read = r8168dp_2_mdio_read;
3007 break;
c0e45c1c 3008 default:
3009 ops->write = r8169_mdio_write;
3010 ops->read = r8169_mdio_read;
3011 break;
3012 }
3013}
3014
065c27c1 3015static void r810x_phy_power_down(struct rtl8169_private *tp)
3016{
3017 rtl_writephy(tp, 0x1f, 0x0000);
3018 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3019}
3020
3021static void r810x_phy_power_up(struct rtl8169_private *tp)
3022{
3023 rtl_writephy(tp, 0x1f, 0x0000);
3024 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3025}
3026
3027static void r810x_pll_power_down(struct rtl8169_private *tp)
3028{
3029 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3030 rtl_writephy(tp, 0x1f, 0x0000);
3031 rtl_writephy(tp, MII_BMCR, 0x0000);
3032 return;
3033 }
3034
3035 r810x_phy_power_down(tp);
3036}
3037
3038static void r810x_pll_power_up(struct rtl8169_private *tp)
3039{
3040 r810x_phy_power_up(tp);
3041}
3042
3043static void r8168_phy_power_up(struct rtl8169_private *tp)
3044{
3045 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3046 switch (tp->mac_version) {
3047 case RTL_GIGA_MAC_VER_11:
3048 case RTL_GIGA_MAC_VER_12:
3049 case RTL_GIGA_MAC_VER_17:
3050 case RTL_GIGA_MAC_VER_18:
3051 case RTL_GIGA_MAC_VER_19:
3052 case RTL_GIGA_MAC_VER_20:
3053 case RTL_GIGA_MAC_VER_21:
3054 case RTL_GIGA_MAC_VER_22:
3055 case RTL_GIGA_MAC_VER_23:
3056 case RTL_GIGA_MAC_VER_24:
3057 case RTL_GIGA_MAC_VER_25:
3058 case RTL_GIGA_MAC_VER_26:
3059 case RTL_GIGA_MAC_VER_27:
3060 case RTL_GIGA_MAC_VER_28:
3061 case RTL_GIGA_MAC_VER_31:
3062 rtl_writephy(tp, 0x0e, 0x0000);
3063 break;
3064 default:
3065 break;
3066 }
065c27c1 3067 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3068}
3069
3070static void r8168_phy_power_down(struct rtl8169_private *tp)
3071{
3072 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3073 switch (tp->mac_version) {
3074 case RTL_GIGA_MAC_VER_32:
3075 case RTL_GIGA_MAC_VER_33:
3076 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3077 break;
3078
3079 case RTL_GIGA_MAC_VER_11:
3080 case RTL_GIGA_MAC_VER_12:
3081 case RTL_GIGA_MAC_VER_17:
3082 case RTL_GIGA_MAC_VER_18:
3083 case RTL_GIGA_MAC_VER_19:
3084 case RTL_GIGA_MAC_VER_20:
3085 case RTL_GIGA_MAC_VER_21:
3086 case RTL_GIGA_MAC_VER_22:
3087 case RTL_GIGA_MAC_VER_23:
3088 case RTL_GIGA_MAC_VER_24:
3089 case RTL_GIGA_MAC_VER_25:
3090 case RTL_GIGA_MAC_VER_26:
3091 case RTL_GIGA_MAC_VER_27:
3092 case RTL_GIGA_MAC_VER_28:
3093 case RTL_GIGA_MAC_VER_31:
3094 rtl_writephy(tp, 0x0e, 0x0200);
3095 default:
3096 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3097 break;
3098 }
065c27c1 3099}
3100
3101static void r8168_pll_power_down(struct rtl8169_private *tp)
3102{
3103 void __iomem *ioaddr = tp->mmio_addr;
3104
cecb5fd7
FR		 3105 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3106 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3107 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3108 r8168dp_check_dash(tp)) {
065c27c1 3109 return;
5d2e1957 3110 }
065c27c1 3111
cecb5fd7
FR		 3112 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3113 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3114 (RTL_R16(CPlusCmd) & ASF)) {
3115 return;
3116 }
3117
01dc7fec 3118 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3119 tp->mac_version == RTL_GIGA_MAC_VER_33)
3120 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3121
065c27c1 3122 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3123 rtl_writephy(tp, 0x1f, 0x0000);
3124 rtl_writephy(tp, MII_BMCR, 0x0000);
3125
3126 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3127 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3128 return;
3129 }
3130
3131 r8168_phy_power_down(tp);
3132
3133 switch (tp->mac_version) {
3134 case RTL_GIGA_MAC_VER_25:
3135 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3136 case RTL_GIGA_MAC_VER_27:
3137 case RTL_GIGA_MAC_VER_28:
4804b3b3 3138 case RTL_GIGA_MAC_VER_31:
01dc7fec 3139 case RTL_GIGA_MAC_VER_32:
3140 case RTL_GIGA_MAC_VER_33:
065c27c1 3141 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3142 break;
3143 }
3144}
3145
3146static void r8168_pll_power_up(struct rtl8169_private *tp)
3147{
3148 void __iomem *ioaddr = tp->mmio_addr;
3149
cecb5fd7
FR		 3150 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3151 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3152 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3153 r8168dp_check_dash(tp)) {
065c27c1 3154 return;
5d2e1957 3155 }
065c27c1 3156
3157 switch (tp->mac_version) {
3158 case RTL_GIGA_MAC_VER_25:
3159 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3160 case RTL_GIGA_MAC_VER_27:
3161 case RTL_GIGA_MAC_VER_28:
4804b3b3 3162 case RTL_GIGA_MAC_VER_31:
01dc7fec 3163 case RTL_GIGA_MAC_VER_32:
3164 case RTL_GIGA_MAC_VER_33:
065c27c1 3165 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3166 break;
3167 }
3168
3169 r8168_phy_power_up(tp);
3170}
3171
3172static void rtl_pll_power_op(struct rtl8169_private *tp,
3173 void (*op)(struct rtl8169_private *))
3174{
3175 if (op)
3176 op(tp);
3177}
3178
3179static void rtl_pll_power_down(struct rtl8169_private *tp)
3180{
3181 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3182}
3183
3184static void rtl_pll_power_up(struct rtl8169_private *tp)
3185{
3186 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3187}
3188
3189static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3190{
3191 struct pll_power_ops *ops = &tp->pll_power_ops;
3192
3193 switch (tp->mac_version) {
3194 case RTL_GIGA_MAC_VER_07:
3195 case RTL_GIGA_MAC_VER_08:
3196 case RTL_GIGA_MAC_VER_09:
3197 case RTL_GIGA_MAC_VER_10:
3198 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3199 case RTL_GIGA_MAC_VER_29:
3200 case RTL_GIGA_MAC_VER_30:
065c27c1 3201 ops->down = r810x_pll_power_down;
3202 ops->up = r810x_pll_power_up;
3203 break;
3204
3205 case RTL_GIGA_MAC_VER_11:
3206 case RTL_GIGA_MAC_VER_12:
3207 case RTL_GIGA_MAC_VER_17:
3208 case RTL_GIGA_MAC_VER_18:
3209 case RTL_GIGA_MAC_VER_19:
3210 case RTL_GIGA_MAC_VER_20:
3211 case RTL_GIGA_MAC_VER_21:
3212 case RTL_GIGA_MAC_VER_22:
3213 case RTL_GIGA_MAC_VER_23:
3214 case RTL_GIGA_MAC_VER_24:
3215 case RTL_GIGA_MAC_VER_25:
3216 case RTL_GIGA_MAC_VER_26:
3217 case RTL_GIGA_MAC_VER_27:
e6de30d6 3218 case RTL_GIGA_MAC_VER_28:
4804b3b3 3219 case RTL_GIGA_MAC_VER_31:
01dc7fec 3220 case RTL_GIGA_MAC_VER_32:
3221 case RTL_GIGA_MAC_VER_33:
065c27c1 3222 ops->down = r8168_pll_power_down;
3223 ops->up = r8168_pll_power_up;
3224 break;
3225
3226 default:
3227 ops->down = NULL;
3228 ops->up = NULL;
3229 break;
3230 }
3231}
3232
6f43adc8
FR		 3233static void rtl_hw_reset(struct rtl8169_private *tp)
3234{
3235 void __iomem *ioaddr = tp->mmio_addr;
3236 int i;
3237
3238 /* Soft reset the chip. */
3239 RTL_W8(ChipCmd, CmdReset);
3240
3241 /* Check that the chip has finished the reset. */
3242 for (i = 0; i < 100; i++) {
3243 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3244 break;
3245 msleep_interruptible(1);
3246 }
3247}
3248
1da177e4 3249static int __devinit
4ff96fa6 3250rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3251{
0e485150
FR		 3252 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3253 const unsigned int region = cfg->region;
1da177e4 3254 struct rtl8169_private *tp;
ccdffb9a 3255 struct mii_if_info *mii;
4ff96fa6
FR		 3256 struct net_device *dev;
3257 void __iomem *ioaddr;
2b7b4318 3258 int chipset, i;
07d3f51f 3259 int rc;
1da177e4 3260
4ff96fa6
FR		 3261 if (netif_msg_drv(&debug)) {
3262 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3263 MODULENAME, RTL8169_VERSION);
3264 }
1da177e4 3265
1da177e4 3266 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3267 if (!dev) {
b57b7e5a 3268 if (netif_msg_drv(&debug))
9b91cf9d 3269 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3270 rc = -ENOMEM;
3271 goto out;
1da177e4
LT		 3272 }
3273
1da177e4 3274 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3275 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3276 tp = netdev_priv(dev);
c4028958 3277 tp->dev = dev;
21e197f2 3278 tp->pci_dev = pdev;
b57b7e5a 3279 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3280
ccdffb9a
FR		 3281 mii = &tp->mii;
3282 mii->dev = dev;
3283 mii->mdio_read = rtl_mdio_read;
3284 mii->mdio_write = rtl_mdio_write;
3285 mii->phy_id_mask = 0x1f;
3286 mii->reg_num_mask = 0x1f;
3287 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3288
ba04c7c9
SG		 3289 /* disable ASPM completely as that cause random device stop working
3290 * problems as well as full system hangs for some PCIe devices users */
3291 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3292 PCIE_LINK_STATE_CLKPM);
3293
1da177e4
LT		 3294 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3295 rc = pci_enable_device(pdev);
b57b7e5a 3296 if (rc < 0) {
bf82c189 3297 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3298 goto err_out_free_dev_1;
1da177e4
LT		 3299 }
3300
87aeec76 3301 if (pci_set_mwi(pdev) < 0)
3302 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3303
1da177e4 3304 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3305 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3306 netif_err(tp, probe, dev,
3307 "region #%d not an MMIO resource, aborting\n",
3308 region);
1da177e4 3309 rc = -ENODEV;
87aeec76 3310 goto err_out_mwi_2;
1da177e4 3311 }
4ff96fa6 3312
1da177e4 3313 /* check for weird/broken PCI region reporting */
bcf0bf90 3314 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3315 netif_err(tp, probe, dev,
3316 "Invalid PCI region size(s), aborting\n");
1da177e4 3317 rc = -ENODEV;
87aeec76 3318 goto err_out_mwi_2;
1da177e4
LT		 3319 }
3320
3321 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3322 if (rc < 0) {
bf82c189 3323 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3324 goto err_out_mwi_2;
1da177e4
LT		 3325 }
3326
d24e9aaf 3327 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3328
3329 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3330 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3331 tp->cp_cmd |= PCIDAC;
3332 dev->features |= NETIF_F_HIGHDMA;
3333 } else {
284901a9 3334 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3335 if (rc < 0) {
bf82c189 3336 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3337 goto err_out_free_res_3;
1da177e4
LT		 3338 }
3339 }
3340
1da177e4 3341 /* ioremap MMIO region */
bcf0bf90 3342 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3343 if (!ioaddr) {
bf82c189 3344 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3345 rc = -EIO;
87aeec76 3346 goto err_out_free_res_3;
1da177e4 3347 }
6f43adc8 3348 tp->mmio_addr = ioaddr;
1da177e4 3349
4300e8c7
DM		 3350 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3351 if (!tp->pcie_cap)
3352 netif_info(tp, probe, dev, "no PCI Express capability\n");
3353
d78ad8cb 3354 RTL_W16(IntrMask, 0x0000);
1da177e4 3355
6f43adc8 3356 rtl_hw_reset(tp);
1da177e4 3357
d78ad8cb
KW		 3358 RTL_W16(IntrStatus, 0xffff);
3359
ca52efd5 3360 pci_set_master(pdev);
3361
1da177e4 3362 /* Identify chip attached to board */
5d320a20 3363 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3364
7a8fc77b
FR		 3365 /*
3366 * Pretend we are using VLANs; This bypasses a nasty bug where
3367 * Interrupts stop flowing on high load on 8110SCd controllers.
3368 */
3369 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3370 tp->cp_cmd |= RxVlan;
3371
c0e45c1c 3372 rtl_init_mdio_ops(tp);
065c27c1 3373 rtl_init_pll_power_ops(tp);
c0e45c1c 3374
1da177e4 3375 rtl8169_print_mac_version(tp);
1da177e4 3376
85bffe6c
FR		 3377 chipset = tp->mac_version;
3378 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3379
5d06a99f
FR		 3380 RTL_W8(Cfg9346, Cfg9346_Unlock);
3381 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3382 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3383 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3384 tp->features |= RTL_FEATURE_WOL;
3385 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3386 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3387 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3388 RTL_W8(Cfg9346, Cfg9346_Lock);
3389
66ec5d4f
FR		 3390 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3391 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3392 tp->set_speed = rtl8169_set_speed_tbi;
3393 tp->get_settings = rtl8169_gset_tbi;
3394 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3395 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3396 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3397 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3398 } else {
3399 tp->set_speed = rtl8169_set_speed_xmii;
3400 tp->get_settings = rtl8169_gset_xmii;
3401 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3402 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3403 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3404 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3405 }
3406
df58ef51
FR		 3407 spin_lock_init(&tp->lock);
3408
7bf6bf48 3409 /* Get MAC address */
1da177e4
LT		 3410 for (i = 0; i < MAC_ADDR_LEN; i++)
3411 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3412 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3413
1da177e4 3414 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3415 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3416 dev->irq = pdev->irq;
3417 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3418
bea3348e 3419 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3420
350fb32a
MM		 3421 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3422 * properly for all devices */
3423 dev->features |= NETIF_F_RXCSUM |
3424 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3425
3426 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3427 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3428 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3429 NETIF_F_HIGHDMA;
3430
3431 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3432 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3433 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3434
3435 tp->intr_mask = 0xffff;
0e485150
FR		 3436 tp->hw_start = cfg->hw_start;
3437 tp->intr_event = cfg->intr_event;
3438 tp->napi_event = cfg->napi_event;
1da177e4 3439
2efa53f3
FR		 3440 init_timer(&tp->timer);
3441 tp->timer.data = (unsigned long) dev;
3442 tp->timer.function = rtl8169_phy_timer;
3443
953a12cc
FR		 3444 tp->fw = RTL_FIRMWARE_UNKNOWN;
3445
1da177e4 3446 rc = register_netdev(dev);
4ff96fa6 3447 if (rc < 0)
87aeec76 3448 goto err_out_msi_4;
1da177e4
LT		 3449
3450 pci_set_drvdata(pdev, dev);
3451
bf82c189 3452 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3453 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3454 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3455
cecb5fd7
FR		 3456 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3457 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3458 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3459 rtl8168_driver_start(tp);
e6de30d6 3460 }
b646d900 3461
8b76ab39 3462 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3463
f3ec4f87
AS		 3464 if (pci_dev_run_wake(pdev))
3465 pm_runtime_put_noidle(&pdev->dev);
e1759441 3466
0d672e9f
IV		 3467 netif_carrier_off(dev);
3468
4ff96fa6
FR		 3469out:
3470 return rc;
1da177e4 3471
87aeec76 3472err_out_msi_4:
fbac58fc 3473 rtl_disable_msi(pdev, tp);
4ff96fa6 3474 iounmap(ioaddr);
87aeec76 3475err_out_free_res_3:
4ff96fa6 3476 pci_release_regions(pdev);
87aeec76 3477err_out_mwi_2:
4ff96fa6 3478 pci_clear_mwi(pdev);
4ff96fa6
FR		 3479 pci_disable_device(pdev);
3480err_out_free_dev_1:
3481 free_netdev(dev);
3482 goto out;
1da177e4
LT		 3483}
3484
07d3f51f 3485static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3486{
3487 struct net_device *dev = pci_get_drvdata(pdev);
3488 struct rtl8169_private *tp = netdev_priv(dev);
3489
cecb5fd7
FR		 3490 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3491 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3492 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3493 rtl8168_driver_stop(tp);
e6de30d6 3494 }
b646d900 3495
23f333a2 3496 cancel_delayed_work_sync(&tp->task);
eb2a021c 3497
1da177e4 3498 unregister_netdev(dev);
cc098dc7 3499
953a12cc
FR		 3500 rtl_release_firmware(tp);
3501
f3ec4f87
AS		 3502 if (pci_dev_run_wake(pdev))
3503 pm_runtime_get_noresume(&pdev->dev);
e1759441 3504
cc098dc7
IV		 3505 /* restore original MAC address */
3506 rtl_rar_set(tp, dev->perm_addr);
3507
fbac58fc 3508 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3509 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3510 pci_set_drvdata(pdev, NULL);
3511}
3512
953a12cc
FR		 3513static void rtl_request_firmware(struct rtl8169_private *tp)
3514{
953a12cc 3515 /* Return early if the firmware is already loaded / cached. */
31bd204f
FR		 3516 if (IS_ERR(tp->fw)) {
3517 const char *name;
953a12cc 3518
31bd204f
FR		 3519 name = rtl_lookup_firmware_name(tp);
3520 if (name) {
953a12cc
FR		 3521 int rc;
3522
3523 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
31bd204f
FR		 3524 if (rc >= 0)
3525 return;
3526
3527 netif_warn(tp, ifup, tp->dev, "unable to load "
3528 "firmware patch %s (%d)\n", name, rc);
953a12cc 3529 }
31bd204f 3530 tp->fw = NULL;
953a12cc 3531 }
953a12cc
FR		 3532}
3533
1da177e4
LT		 3534static int rtl8169_open(struct net_device *dev)
3535{
3536 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3537 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3538 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3539 int retval = -ENOMEM;
1da177e4 3540
e1759441 3541 pm_runtime_get_sync(&pdev->dev);
1da177e4 3542
1da177e4
LT		 3543 /*
3544 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3545 * dma_alloc_coherent provides more.
1da177e4 3546 */
82553bb6
SG		 3547 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3548 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3549 if (!tp->TxDescArray)
e1759441 3550 goto err_pm_runtime_put;
1da177e4 3551
82553bb6
SG		 3552 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3553 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3554 if (!tp->RxDescArray)
99f252b0 3555 goto err_free_tx_0;
1da177e4
LT		 3556
3557 retval = rtl8169_init_ring(dev);
3558 if (retval < 0)
99f252b0 3559 goto err_free_rx_1;
1da177e4 3560
c4028958 3561 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3562
99f252b0
FR		 3563 smp_mb();
3564
953a12cc
FR		 3565 rtl_request_firmware(tp);
3566
fbac58fc
FR		 3567 retval = request_irq(dev->irq, rtl8169_interrupt,
3568 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3569 dev->name, dev);
3570 if (retval < 0)
953a12cc 3571 goto err_release_fw_2;
99f252b0 3572
bea3348e 3573 napi_enable(&tp->napi);
bea3348e 3574
eee3a96c 3575 rtl8169_init_phy(dev, tp);
3576
350fb32a 3577 rtl8169_set_features(dev, dev->features);
eee3a96c 3578
065c27c1 3579 rtl_pll_power_up(tp);
3580
07ce4064 3581 rtl_hw_start(dev);
1da177e4 3582
e1759441
RW		 3583 tp->saved_wolopts = 0;
3584 pm_runtime_put_noidle(&pdev->dev);
3585
eee3a96c 3586 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3587out:
3588 return retval;
3589
953a12cc
FR		 3590err_release_fw_2:
3591 rtl_release_firmware(tp);
99f252b0
FR		 3592 rtl8169_rx_clear(tp);
3593err_free_rx_1:
82553bb6
SG		 3594 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3595 tp->RxPhyAddr);
e1759441 3596 tp->RxDescArray = NULL;
99f252b0 3597err_free_tx_0:
82553bb6
SG		 3598 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3599 tp->TxPhyAddr);
e1759441
RW		 3600 tp->TxDescArray = NULL;
3601err_pm_runtime_put:
3602 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3603 goto out;
3604}
3605
e6de30d6 3606static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3607{
e6de30d6 3608 void __iomem *ioaddr = tp->mmio_addr;
3609
1da177e4
LT		 3610 /* Disable interrupts */
3611 rtl8169_irq_mask_and_ack(ioaddr);
3612
5d2e1957 3613 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3614 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3615 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3616 while (RTL_R8(TxPoll) & NPQ)
3617 udelay(20);
3618
3619 }
3620
1da177e4
LT		 3621 /* Reset the chipset */
3622 RTL_W8(ChipCmd, CmdReset);
3623
3624 /* PCI commit */
3625 RTL_R8(ChipCmd);
3626}
3627
7f796d83 3628static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3629{
3630 void __iomem *ioaddr = tp->mmio_addr;
3631 u32 cfg = rtl8169_rx_config;
3632
2b7b4318 3633 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3634 RTL_W32(RxConfig, cfg);
3635
3636 /* Set DMA burst size and Interframe Gap Time */
3637 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3638 (InterFrameGap << TxInterFrameGapShift));
3639}
3640
07ce4064 3641static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3642{
3643 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3644
6f43adc8 3645 rtl_hw_reset(tp);
1da177e4 3646
07ce4064
FR		 3647 tp->hw_start(dev);
3648
07ce4064
FR		 3649 netif_start_queue(dev);
3650}
3651
7f796d83
FR		 3652static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3653 void __iomem *ioaddr)
3654{
3655 /*
3656 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3657 * register to be written before TxDescAddrLow to work.
3658 * Switching from MMIO to I/O access fixes the issue as well.
3659 */
3660 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3661 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3662 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3663 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3664}
3665
3666static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3667{
3668 u16 cmd;
3669
3670 cmd = RTL_R16(CPlusCmd);
3671 RTL_W16(CPlusCmd, cmd);
3672 return cmd;
3673}
3674
fdd7b4c3 3675static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3676{
3677 /* Low hurts. Let's disable the filtering. */
207d6e87 3678 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3679}
3680
6dccd16b
FR		 3681static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3682{
350f7596 3683 static const struct {
6dccd16b
FR		 3684 u32 mac_version;
3685 u32 clk;
3686 u32 val;
3687 } cfg2_info [] = {
3688 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3689 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3690 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3691 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3692 }, *p = cfg2_info;
3693 unsigned int i;
3694 u32 clk;
3695
3696 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3697 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3698 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3699 RTL_W32(0x7c, p->val);
3700 break;
3701 }
3702 }
3703}
3704
07ce4064
FR		 3705static void rtl_hw_start_8169(struct net_device *dev)
3706{
3707 struct rtl8169_private *tp = netdev_priv(dev);
3708 void __iomem *ioaddr = tp->mmio_addr;
3709 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3710
9cb427b6
FR		 3711 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3712 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3713 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3714 }
3715
1da177e4 3716 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3717 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3718 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3719 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3720 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3721 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3722
f0298f81 3723 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3724
6f0333b8 3725 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3726
cecb5fd7
FR		 3727 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3728 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3729 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3730 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3731 rtl_set_rx_tx_config_registers(tp);
1da177e4 3732
7f796d83 3733 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3734
cecb5fd7
FR		 3735 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3736 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3737 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3738 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3739 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3740 }
3741
bcf0bf90
FR		 3742 RTL_W16(CPlusCmd, tp->cp_cmd);
3743
6dccd16b
FR		 3744 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3745
1da177e4
LT		 3746 /*
3747 * Undocumented corner. Supposedly:
3748 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3749 */
3750 RTL_W16(IntrMitigate, 0x0000);
3751
7f796d83 3752 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3753
cecb5fd7
FR		 3754 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3755 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3756 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3757 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3758 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3759 rtl_set_rx_tx_config_registers(tp);
3760 }
3761
1da177e4 3762 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3763
3764 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3765 RTL_R8(IntrMask);
1da177e4
LT		 3766
3767 RTL_W32(RxMissed, 0);
3768
07ce4064 3769 rtl_set_rx_mode(dev);
1da177e4
LT		 3770
3771 /* no early-rx interrupts */
3772 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3773
3774 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3775 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3776}
1da177e4 3777
9c14ceaf 3778static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3779{
9c14ceaf
FR		 3780 struct net_device *dev = pci_get_drvdata(pdev);
3781 struct rtl8169_private *tp = netdev_priv(dev);
3782 int cap = tp->pcie_cap;
3783
3784 if (cap) {
3785 u16 ctl;
458a9f61 3786
9c14ceaf
FR		 3787 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3788 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3789 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3790 }
458a9f61
FR		 3791}
3792
650e8d5d 3793static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3794{
3795 u32 csi;
3796
3797 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3798 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3799}
3800
e6de30d6 3801static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3802{
3803 rtl_csi_access_enable(ioaddr, 0x17000000);
3804}
3805
650e8d5d 3806static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3807{
3808 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3809}
3810
3811struct ephy_info {
3812 unsigned int offset;
3813 u16 mask;
3814 u16 bits;
3815};
3816
350f7596 3817static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3818{
3819 u16 w;
3820
3821 while (len-- > 0) {
3822 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3823 rtl_ephy_write(ioaddr, e->offset, w);
3824 e++;
3825 }
3826}
3827
b726e493
FR		 3828static void rtl_disable_clock_request(struct pci_dev *pdev)
3829{
3830 struct net_device *dev = pci_get_drvdata(pdev);
3831 struct rtl8169_private *tp = netdev_priv(dev);
3832 int cap = tp->pcie_cap;
3833
3834 if (cap) {
3835 u16 ctl;
3836
3837 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3838 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3839 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3840 }
3841}
3842
e6de30d6 3843static void rtl_enable_clock_request(struct pci_dev *pdev)
3844{
3845 struct net_device *dev = pci_get_drvdata(pdev);
3846 struct rtl8169_private *tp = netdev_priv(dev);
3847 int cap = tp->pcie_cap;
3848
3849 if (cap) {
3850 u16 ctl;
3851
3852 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3853 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3854 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3855 }
3856}
3857
b726e493
FR		 3858#define R8168_CPCMD_QUIRK_MASK (\
3859 EnableBist | \
3860 Mac_dbgo_oe | \
3861 Force_half_dup | \
3862 Force_rxflow_en | \
3863 Force_txflow_en | \
3864 Cxpl_dbg_sel | \
3865 ASF | \
3866 PktCntrDisable | \
3867 Mac_dbgo_sel)
3868
219a1e9d
FR		 3869static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3870{
b726e493
FR		 3871 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3872
3873 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3874
2e68ae44
FR		 3875 rtl_tx_performance_tweak(pdev,
3876 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3877}
3878
3879static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3880{
3881 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3882
f0298f81 3883 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3884
3885 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3886}
3887
3888static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3889{
b726e493
FR		 3890 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3891
3892 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3893
219a1e9d 3894 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3895
3896 rtl_disable_clock_request(pdev);
3897
3898 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3899}
3900
ef3386f0 3901static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3902{
350f7596 3903 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3904 { 0x01, 0, 0x0001 },
3905 { 0x02, 0x0800, 0x1000 },
3906 { 0x03, 0, 0x0042 },
3907 { 0x06, 0x0080, 0x0000 },
3908 { 0x07, 0, 0x2000 }
3909 };
3910
650e8d5d 3911 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3912
3913 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3914
219a1e9d
FR		 3915 __rtl_hw_start_8168cp(ioaddr, pdev);
3916}
3917
ef3386f0
FR		 3918static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3919{
650e8d5d 3920 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3921
3922 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3923
3924 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3925
3926 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3927}
3928
7f3e3d3a
FR		 3929static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3930{
650e8d5d 3931 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3932
3933 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3934
3935 /* Magic. */
3936 RTL_W8(DBG_REG, 0x20);
3937
f0298f81 3938 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3939
3940 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3941
3942 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3943}
3944
219a1e9d
FR		 3945static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3946{
350f7596 3947 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3948 { 0x02, 0x0800, 0x1000 },
3949 { 0x03, 0, 0x0002 },
3950 { 0x06, 0x0080, 0x0000 }
3951 };
3952
650e8d5d 3953 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3954
3955 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3956
3957 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3958
219a1e9d
FR		 3959 __rtl_hw_start_8168cp(ioaddr, pdev);
3960}
3961
3962static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3963{
350f7596 3964 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3965 { 0x01, 0, 0x0001 },
3966 { 0x03, 0x0400, 0x0220 }
3967 };
3968
650e8d5d 3969 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3970
3971 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3972
219a1e9d
FR		 3973 __rtl_hw_start_8168cp(ioaddr, pdev);
3974}
3975
197ff761
FR		 3976static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3977{
3978 rtl_hw_start_8168c_2(ioaddr, pdev);
3979}
3980
6fb07058
FR		 3981static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3982{
650e8d5d 3983 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3984
3985 __rtl_hw_start_8168cp(ioaddr, pdev);
3986}
3987
5b538df9
FR		 3988static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3989{
650e8d5d 3990 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3991
3992 rtl_disable_clock_request(pdev);
3993
f0298f81 3994 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3995
3996 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3997
3998 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3999}
4000
4804b3b3 4001static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4002{
4003 rtl_csi_access_enable_1(ioaddr);
4004
4005 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4006
4007 RTL_W8(MaxTxPacketSize, TxPacketMax);
4008
4009 rtl_disable_clock_request(pdev);
4010}
4011
e6de30d6 4012static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4013{
4014 static const struct ephy_info e_info_8168d_4[] = {
4015 { 0x0b, ~0, 0x48 },
4016 { 0x19, 0x20, 0x50 },
4017 { 0x0c, ~0, 0x20 }
4018 };
4019 int i;
4020
4021 rtl_csi_access_enable_1(ioaddr);
4022
4023 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4024
4025 RTL_W8(MaxTxPacketSize, TxPacketMax);
4026
4027 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4028 const struct ephy_info *e = e_info_8168d_4 + i;
4029 u16 w;
4030
4031 w = rtl_ephy_read(ioaddr, e->offset);
4032 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4033 }
4034
4035 rtl_enable_clock_request(pdev);
4036}
4037
01dc7fec 4038static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4039{
4040 static const struct ephy_info e_info_8168e[] = {
4041 { 0x00, 0x0200, 0x0100 },
4042 { 0x00, 0x0000, 0x0004 },
4043 { 0x06, 0x0002, 0x0001 },
4044 { 0x06, 0x0000, 0x0030 },
4045 { 0x07, 0x0000, 0x2000 },
4046 { 0x00, 0x0000, 0x0020 },
4047 { 0x03, 0x5800, 0x2000 },
4048 { 0x03, 0x0000, 0x0001 },
4049 { 0x01, 0x0800, 0x1000 },
4050 { 0x07, 0x0000, 0x4000 },
4051 { 0x1e, 0x0000, 0x2000 },
4052 { 0x19, 0xffff, 0xfe6c },
4053 { 0x0a, 0x0000, 0x0040 }
4054 };
4055
4056 rtl_csi_access_enable_2(ioaddr);
4057
4058 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4059
4060 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4061
4062 RTL_W8(MaxTxPacketSize, TxPacketMax);
4063
4064 rtl_disable_clock_request(pdev);
4065
4066 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4067 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4068 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4069
cecb5fd7 4070 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4071}
4072
07ce4064
FR		 4073static void rtl_hw_start_8168(struct net_device *dev)
4074{
2dd99530
FR		 4075 struct rtl8169_private *tp = netdev_priv(dev);
4076 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4077 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4078
4079 RTL_W8(Cfg9346, Cfg9346_Unlock);
4080
f0298f81 4081 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4082
6f0333b8 4083 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4084
0e485150 4085 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4086
4087 RTL_W16(CPlusCmd, tp->cp_cmd);
4088
0e485150 4089 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4090
0e485150 4091 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4092 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4093 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4094 tp->intr_event |= RxFIFOOver | PCSTimeout;
4095 tp->intr_event &= ~RxOverflow;
4096 }
4097
4098 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4099
b8363901
FR		 4100 rtl_set_rx_mode(dev);
4101
4102 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4103 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4104
4105 RTL_R8(IntrMask);
4106
219a1e9d
FR		 4107 switch (tp->mac_version) {
4108 case RTL_GIGA_MAC_VER_11:
4109 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4110 break;
219a1e9d
FR		 4111
4112 case RTL_GIGA_MAC_VER_12:
4113 case RTL_GIGA_MAC_VER_17:
4114 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4115 break;
219a1e9d
FR		 4116
4117 case RTL_GIGA_MAC_VER_18:
ef3386f0 4118 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4119 break;
219a1e9d
FR		 4120
4121 case RTL_GIGA_MAC_VER_19:
4122 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4123 break;
219a1e9d
FR		 4124
4125 case RTL_GIGA_MAC_VER_20:
4126 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4127 break;
219a1e9d 4128
197ff761
FR		 4129 case RTL_GIGA_MAC_VER_21:
4130 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4131 break;
197ff761 4132
6fb07058
FR		 4133 case RTL_GIGA_MAC_VER_22:
4134 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4135 break;
6fb07058 4136
ef3386f0
FR		 4137 case RTL_GIGA_MAC_VER_23:
4138 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4139 break;
ef3386f0 4140
7f3e3d3a
FR		 4141 case RTL_GIGA_MAC_VER_24:
4142 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4143 break;
7f3e3d3a 4144
5b538df9 4145 case RTL_GIGA_MAC_VER_25:
daf9df6d 4146 case RTL_GIGA_MAC_VER_26:
4147 case RTL_GIGA_MAC_VER_27:
5b538df9 4148 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4149 break;
5b538df9 4150
e6de30d6 4151 case RTL_GIGA_MAC_VER_28:
4152 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4153 break;
cecb5fd7 4154
4804b3b3 4155 case RTL_GIGA_MAC_VER_31:
4156 rtl_hw_start_8168dp(ioaddr, pdev);
4157 break;
4158
01dc7fec 4159 case RTL_GIGA_MAC_VER_32:
4160 case RTL_GIGA_MAC_VER_33:
4161 rtl_hw_start_8168e(ioaddr, pdev);
4162 break;
e6de30d6 4163
219a1e9d
FR		 4164 default:
4165 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4166 dev->name, tp->mac_version);
4804b3b3 4167 break;
219a1e9d 4168 }
2dd99530 4169
0e485150
FR		 4170 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4171
b8363901
FR		 4172 RTL_W8(Cfg9346, Cfg9346_Lock);
4173
2dd99530 4174 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4175
0e485150 4176 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4177}
1da177e4 4178
2857ffb7
FR		 4179#define R810X_CPCMD_QUIRK_MASK (\
4180 EnableBist | \
4181 Mac_dbgo_oe | \
4182 Force_half_dup | \
5edcc537 4183 Force_rxflow_en | \
2857ffb7
FR		 4184 Force_txflow_en | \
4185 Cxpl_dbg_sel | \
4186 ASF | \
4187 PktCntrDisable | \
d24e9aaf 4188 Mac_dbgo_sel)
2857ffb7
FR		 4189
4190static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4191{
350f7596 4192 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4193 { 0x01, 0, 0x6e65 },
4194 { 0x02, 0, 0x091f },
4195 { 0x03, 0, 0xc2f9 },
4196 { 0x06, 0, 0xafb5 },
4197 { 0x07, 0, 0x0e00 },
4198 { 0x19, 0, 0xec80 },
4199 { 0x01, 0, 0x2e65 },
4200 { 0x01, 0, 0x6e65 }
4201 };
4202 u8 cfg1;
4203
650e8d5d 4204 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4205
4206 RTL_W8(DBG_REG, FIX_NAK_1);
4207
4208 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4209
4210 RTL_W8(Config1,
4211 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4212 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4213
4214 cfg1 = RTL_R8(Config1);
4215 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4216 RTL_W8(Config1, cfg1 & ~LEDS0);
4217
2857ffb7
FR		 4218 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4219}
4220
4221static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4222{
650e8d5d 4223 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4224
4225 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4226
4227 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4228 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4229}
4230
4231static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4232{
4233 rtl_hw_start_8102e_2(ioaddr, pdev);
4234
4235 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4236}
4237
5a5e4443
HW		 4238static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4239{
4240 static const struct ephy_info e_info_8105e_1[] = {
4241 { 0x07, 0, 0x4000 },
4242 { 0x19, 0, 0x0200 },
4243 { 0x19, 0, 0x0020 },
4244 { 0x1e, 0, 0x2000 },
4245 { 0x03, 0, 0x0001 },
4246 { 0x19, 0, 0x0100 },
4247 { 0x19, 0, 0x0004 },
4248 { 0x0a, 0, 0x0020 }
4249 };
4250
cecb5fd7 4251 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4252 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4253
cecb5fd7 4254 /* Disable Early Tally Counter */
5a5e4443
HW		 4255 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4256
4257 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4258 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4259
4260 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4261}
4262
4263static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4264{
4265 rtl_hw_start_8105e_1(ioaddr, pdev);
4266 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4267}
4268
07ce4064
FR		 4269static void rtl_hw_start_8101(struct net_device *dev)
4270{
cdf1a608
FR		 4271 struct rtl8169_private *tp = netdev_priv(dev);
4272 void __iomem *ioaddr = tp->mmio_addr;
4273 struct pci_dev *pdev = tp->pci_dev;
4274
cecb5fd7
FR		 4275 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4276 tp->mac_version == RTL_GIGA_MAC_VER_16) {
9c14ceaf
FR		 4277 int cap = tp->pcie_cap;
4278
4279 if (cap) {
4280 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4281 PCI_EXP_DEVCTL_NOSNOOP_EN);
4282 }
cdf1a608
FR		 4283 }
4284
d24e9aaf
HW		 4285 RTL_W8(Cfg9346, Cfg9346_Unlock);
4286
2857ffb7
FR		 4287 switch (tp->mac_version) {
4288 case RTL_GIGA_MAC_VER_07:
4289 rtl_hw_start_8102e_1(ioaddr, pdev);
4290 break;
4291
4292 case RTL_GIGA_MAC_VER_08:
4293 rtl_hw_start_8102e_3(ioaddr, pdev);
4294 break;
4295
4296 case RTL_GIGA_MAC_VER_09:
4297 rtl_hw_start_8102e_2(ioaddr, pdev);
4298 break;
5a5e4443
HW		 4299
4300 case RTL_GIGA_MAC_VER_29:
4301 rtl_hw_start_8105e_1(ioaddr, pdev);
4302 break;
4303 case RTL_GIGA_MAC_VER_30:
4304 rtl_hw_start_8105e_2(ioaddr, pdev);
4305 break;
cdf1a608
FR		 4306 }
4307
d24e9aaf 4308 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4309
f0298f81 4310 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4311
6f0333b8 4312 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4313
d24e9aaf 4314 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4315 RTL_W16(CPlusCmd, tp->cp_cmd);
4316
4317 RTL_W16(IntrMitigate, 0x0000);
4318
4319 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4320
4321 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4322 rtl_set_rx_tx_config_registers(tp);
4323
cdf1a608
FR		 4324 RTL_R8(IntrMask);
4325
cdf1a608
FR		 4326 rtl_set_rx_mode(dev);
4327
4328 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4329
0e485150 4330 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4331}
4332
4333static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4334{
1da177e4
LT		 4335 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4336 return -EINVAL;
4337
4338 dev->mtu = new_mtu;
350fb32a
MM		 4339 netdev_update_features(dev);
4340
323bb685 4341 return 0;
1da177e4
LT		 4342}
4343
4344static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4345{
95e0918d 4346 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4347 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4348}
4349
6f0333b8
ED		 4350static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4351 void **data_buff, struct RxDesc *desc)
1da177e4 4352{
48addcc9 4353 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4354 DMA_FROM_DEVICE);
48addcc9 4355
6f0333b8
ED		 4356 kfree(*data_buff);
4357 *data_buff = NULL;
1da177e4
LT		 4358 rtl8169_make_unusable_by_asic(desc);
4359}
4360
4361static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4362{
4363 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4364
4365 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4366}
4367
4368static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4369 u32 rx_buf_sz)
4370{
4371 desc->addr = cpu_to_le64(mapping);
4372 wmb();
4373 rtl8169_mark_to_asic(desc, rx_buf_sz);
4374}
4375
6f0333b8
ED		 4376static inline void *rtl8169_align(void *data)
4377{
4378 return (void *)ALIGN((long)data, 16);
4379}
4380
0ecbe1ca
SG		 4381static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4382 struct RxDesc *desc)
1da177e4 4383{
6f0333b8 4384 void *data;
1da177e4 4385 dma_addr_t mapping;
48addcc9 4386 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4387 struct net_device *dev = tp->dev;
6f0333b8 4388 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4389
6f0333b8
ED		 4390 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4391 if (!data)
4392 return NULL;
e9f63f30 4393
6f0333b8
ED		 4394 if (rtl8169_align(data) != data) {
4395 kfree(data);
4396 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4397 if (!data)
4398 return NULL;
4399 }
3eafe507 4400
48addcc9 4401 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4402 DMA_FROM_DEVICE);
d827d86b
SG		 4403 if (unlikely(dma_mapping_error(d, mapping))) {
4404 if (net_ratelimit())
4405 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4406 goto err_out;
d827d86b 4407 }
1da177e4
LT		 4408
4409 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4410 return data;
3eafe507
SG		 4411
4412err_out:
4413 kfree(data);
4414 return NULL;
1da177e4
LT		 4415}
4416
4417static void rtl8169_rx_clear(struct rtl8169_private *tp)
4418{
07d3f51f 4419 unsigned int i;
1da177e4
LT		 4420
4421 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4422 if (tp->Rx_databuff[i]) {
4423 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4424 tp->RxDescArray + i);
4425 }
4426 }
4427}
4428
0ecbe1ca 4429static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4430{
0ecbe1ca
SG		 4431 desc->opts1 |= cpu_to_le32(RingEnd);
4432}
5b0384f4 4433
0ecbe1ca
SG		 4434static int rtl8169_rx_fill(struct rtl8169_private *tp)
4435{
4436 unsigned int i;
1da177e4 4437
0ecbe1ca
SG		 4438 for (i = 0; i < NUM_RX_DESC; i++) {
4439 void *data;
4ae47c2d 4440
6f0333b8 4441 if (tp->Rx_databuff[i])
1da177e4 4442 continue;
bcf0bf90 4443
0ecbe1ca 4444 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4445 if (!data) {
4446 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4447 goto err_out;
6f0333b8
ED		 4448 }
4449 tp->Rx_databuff[i] = data;
1da177e4 4450 }
1da177e4 4451
0ecbe1ca
SG		 4452 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4453 return 0;
4454
4455err_out:
4456 rtl8169_rx_clear(tp);
4457 return -ENOMEM;
1da177e4
LT		 4458}
4459
4460static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4461{
4462 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4463}
4464
4465static int rtl8169_init_ring(struct net_device *dev)
4466{
4467 struct rtl8169_private *tp = netdev_priv(dev);
4468
4469 rtl8169_init_ring_indexes(tp);
4470
4471 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4472 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4473
0ecbe1ca 4474 return rtl8169_rx_fill(tp);
1da177e4
LT		 4475}
4476
48addcc9 4477static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4478 struct TxDesc *desc)
4479{
4480 unsigned int len = tx_skb->len;
4481
48addcc9
SG		 4482 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4483
1da177e4
LT		 4484 desc->opts1 = 0x00;
4485 desc->opts2 = 0x00;
4486 desc->addr = 0x00;
4487 tx_skb->len = 0;
4488}
4489
3eafe507
SG		 4490static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4491 unsigned int n)
1da177e4
LT		 4492{
4493 unsigned int i;
4494
3eafe507
SG		 4495 for (i = 0; i < n; i++) {
4496 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4497 struct ring_info *tx_skb = tp->tx_skb + entry;
4498 unsigned int len = tx_skb->len;
4499
4500 if (len) {
4501 struct sk_buff *skb = tx_skb->skb;
4502
48addcc9 4503 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4504 tp->TxDescArray + entry);
4505 if (skb) {
cac4b22f 4506 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4507 dev_kfree_skb(skb);
4508 tx_skb->skb = NULL;
4509 }
1da177e4
LT		 4510 }
4511 }
3eafe507
SG		 4512}
4513
4514static void rtl8169_tx_clear(struct rtl8169_private *tp)
4515{
4516 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4517 tp->cur_tx = tp->dirty_tx = 0;
4518}
4519
c4028958 4520static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4521{
4522 struct rtl8169_private *tp = netdev_priv(dev);
4523
c4028958 4524 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4525 schedule_delayed_work(&tp->task, 4);
4526}
4527
4528static void rtl8169_wait_for_quiescence(struct net_device *dev)
4529{
4530 struct rtl8169_private *tp = netdev_priv(dev);
4531 void __iomem *ioaddr = tp->mmio_addr;
4532
4533 synchronize_irq(dev->irq);
4534
4535 /* Wait for any pending NAPI task to complete */
bea3348e 4536 napi_disable(&tp->napi);
1da177e4
LT		 4537
4538 rtl8169_irq_mask_and_ack(ioaddr);
4539
d1d08d12
DM		 4540 tp->intr_mask = 0xffff;
4541 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4542 napi_enable(&tp->napi);
1da177e4
LT		 4543}
4544
c4028958 4545static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4546{
c4028958
DH		 4547 struct rtl8169_private *tp =
4548 container_of(work, struct rtl8169_private, task.work);
4549 struct net_device *dev = tp->dev;
1da177e4
LT		 4550 int ret;
4551
eb2a021c
FR		 4552 rtnl_lock();
4553
4554 if (!netif_running(dev))
4555 goto out_unlock;
4556
4557 rtl8169_wait_for_quiescence(dev);
4558 rtl8169_close(dev);
1da177e4
LT		 4559
4560 ret = rtl8169_open(dev);
4561 if (unlikely(ret < 0)) {
bf82c189
JP		 4562 if (net_ratelimit())
4563 netif_err(tp, drv, dev,
4564 "reinit failure (status = %d). Rescheduling\n",
4565 ret);
1da177e4
LT		 4566 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4567 }
eb2a021c
FR		 4568
4569out_unlock:
4570 rtnl_unlock();
1da177e4
LT		 4571}
4572
c4028958 4573static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4574{
c4028958
DH		 4575 struct rtl8169_private *tp =
4576 container_of(work, struct rtl8169_private, task.work);
4577 struct net_device *dev = tp->dev;
56de414c 4578 int i;
1da177e4 4579
eb2a021c
FR		 4580 rtnl_lock();
4581
1da177e4 4582 if (!netif_running(dev))
eb2a021c 4583 goto out_unlock;
1da177e4
LT		 4584
4585 rtl8169_wait_for_quiescence(dev);
4586
56de414c
FR		 4587 for (i = 0; i < NUM_RX_DESC; i++)
4588 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4589
1da177e4
LT		 4590 rtl8169_tx_clear(tp);
4591
56de414c
FR		 4592 rtl8169_init_ring_indexes(tp);
4593 rtl_hw_start(dev);
4594 netif_wake_queue(dev);
4595 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4596
4597out_unlock:
4598 rtnl_unlock();
1da177e4
LT		 4599}
4600
4601static void rtl8169_tx_timeout(struct net_device *dev)
4602{
4603 struct rtl8169_private *tp = netdev_priv(dev);
4604
e6de30d6 4605 rtl8169_hw_reset(tp);
1da177e4
LT		 4606
4607 /* Let's wait a bit while any (async) irq lands on */
4608 rtl8169_schedule_work(dev, rtl8169_reset_task);
4609}
4610
4611static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4612 u32 *opts)
1da177e4
LT		 4613{
4614 struct skb_shared_info *info = skb_shinfo(skb);
4615 unsigned int cur_frag, entry;
a6343afb 4616 struct TxDesc * uninitialized_var(txd);
48addcc9 4617 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4618
4619 entry = tp->cur_tx;
4620 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4621 skb_frag_t *frag = info->frags + cur_frag;
4622 dma_addr_t mapping;
4623 u32 status, len;
4624 void *addr;
4625
4626 entry = (entry + 1) % NUM_TX_DESC;
4627
4628 txd = tp->TxDescArray + entry;
4629 len = frag->size;
4630 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4631 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4632 if (unlikely(dma_mapping_error(d, mapping))) {
4633 if (net_ratelimit())
4634 netif_err(tp, drv, tp->dev,
4635 "Failed to map TX fragments DMA!\n");
3eafe507 4636 goto err_out;
d827d86b 4637 }
1da177e4 4638
cecb5fd7 4639 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4640 status = opts[0] | len |
4641 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4642
4643 txd->opts1 = cpu_to_le32(status);
2b7b4318 4644 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4645 txd->addr = cpu_to_le64(mapping);
4646
4647 tp->tx_skb[entry].len = len;
4648 }
4649
4650 if (cur_frag) {
4651 tp->tx_skb[entry].skb = skb;
4652 txd->opts1 |= cpu_to_le32(LastFrag);
4653 }
4654
4655 return cur_frag;
3eafe507
SG		 4656
4657err_out:
4658 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4659 return -EIO;
1da177e4
LT		 4660}
4661
2b7b4318
FR		 4662static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4663 struct sk_buff *skb, u32 *opts)
1da177e4 4664{
2b7b4318 4665 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4666 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4667 int offset = info->opts_offset;
350fb32a 4668
2b7b4318
FR		 4669 if (mss) {
4670 opts[0] |= TD_LSO;
4671 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4672 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4673 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4674
4675 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4676 opts[offset] |= info->checksum.tcp;
1da177e4 4677 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4678 opts[offset] |= info->checksum.udp;
4679 else
4680 WARN_ON_ONCE(1);
1da177e4 4681 }
1da177e4
LT		 4682}
4683
61357325
SH		 4684static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4685 struct net_device *dev)
1da177e4
LT		 4686{
4687 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4688 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4689 struct TxDesc *txd = tp->TxDescArray + entry;
4690 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4691 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4692 dma_addr_t mapping;
4693 u32 status, len;
2b7b4318 4694 u32 opts[2];
3eafe507 4695 int frags;
5b0384f4 4696
1da177e4 4697 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4698 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4699 goto err_stop_0;
1da177e4
LT		 4700 }
4701
4702 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4703 goto err_stop_0;
4704
4705 len = skb_headlen(skb);
48addcc9 4706 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4707 if (unlikely(dma_mapping_error(d, mapping))) {
4708 if (net_ratelimit())
4709 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4710 goto err_dma_0;
d827d86b 4711 }
3eafe507
SG		 4712
4713 tp->tx_skb[entry].len = len;
4714 txd->addr = cpu_to_le64(mapping);
1da177e4 4715
2b7b4318
FR		 4716 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4717 opts[0] = DescOwn;
1da177e4 4718
2b7b4318
FR		 4719 rtl8169_tso_csum(tp, skb, opts);
4720
4721 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4722 if (frags < 0)
4723 goto err_dma_1;
4724 else if (frags)
2b7b4318 4725 opts[0] |= FirstFrag;
3eafe507 4726 else {
2b7b4318 4727 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4728 tp->tx_skb[entry].skb = skb;
4729 }
4730
2b7b4318
FR		 4731 txd->opts2 = cpu_to_le32(opts[1]);
4732
1da177e4
LT		 4733 wmb();
4734
cecb5fd7 4735 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4736 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4737 txd->opts1 = cpu_to_le32(status);
4738
1da177e4
LT		 4739 tp->cur_tx += frags + 1;
4740
4c020a96 4741 wmb();
1da177e4 4742
cecb5fd7 4743 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4744
4745 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4746 netif_stop_queue(dev);
4747 smp_rmb();
4748 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4749 netif_wake_queue(dev);
4750 }
4751
61357325 4752 return NETDEV_TX_OK;
1da177e4 4753
3eafe507 4754err_dma_1:
48addcc9 4755 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4756err_dma_0:
4757 dev_kfree_skb(skb);
4758 dev->stats.tx_dropped++;
4759 return NETDEV_TX_OK;
4760
4761err_stop_0:
1da177e4 4762 netif_stop_queue(dev);
cebf8cc7 4763 dev->stats.tx_dropped++;
61357325 4764 return NETDEV_TX_BUSY;
1da177e4
LT		 4765}
4766
4767static void rtl8169_pcierr_interrupt(struct net_device *dev)
4768{
4769 struct rtl8169_private *tp = netdev_priv(dev);
4770 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4771 u16 pci_status, pci_cmd;
4772
4773 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4774 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4775
bf82c189
JP		 4776 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4777 pci_cmd, pci_status);
1da177e4
LT		 4778
4779 /*
4780 * The recovery sequence below admits a very elaborated explanation:
4781 * - it seems to work;
d03902b8
FR		 4782 * - I did not see what else could be done;
4783 * - it makes iop3xx happy.
1da177e4
LT		 4784 *
4785 * Feel free to adjust to your needs.
4786 */
a27993f3 4787 if (pdev->broken_parity_status)
d03902b8
FR		 4788 pci_cmd &= ~PCI_COMMAND_PARITY;
4789 else
4790 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4791
4792 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4793
4794 pci_write_config_word(pdev, PCI_STATUS,
4795 pci_status & (PCI_STATUS_DETECTED_PARITY |
4796 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4797 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4798
4799 /* The infamous DAC f*ckup only happens at boot time */
4800 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4801 void __iomem *ioaddr = tp->mmio_addr;
4802
bf82c189 4803 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4804 tp->cp_cmd &= ~PCIDAC;
4805 RTL_W16(CPlusCmd, tp->cp_cmd);
4806 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4807 }
4808
e6de30d6 4809 rtl8169_hw_reset(tp);
d03902b8
FR		 4810
4811 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4812}
4813
07d3f51f
FR		 4814static void rtl8169_tx_interrupt(struct net_device *dev,
4815 struct rtl8169_private *tp,
4816 void __iomem *ioaddr)
1da177e4
LT		 4817{
4818 unsigned int dirty_tx, tx_left;
4819
1da177e4
LT		 4820 dirty_tx = tp->dirty_tx;
4821 smp_rmb();
4822 tx_left = tp->cur_tx - dirty_tx;
4823
4824 while (tx_left > 0) {
4825 unsigned int entry = dirty_tx % NUM_TX_DESC;
4826 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4827 u32 status;
4828
4829 rmb();
4830 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4831 if (status & DescOwn)
4832 break;
4833
48addcc9
SG		 4834 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4835 tp->TxDescArray + entry);
1da177e4 4836 if (status & LastFrag) {
cac4b22f
SG		 4837 dev->stats.tx_packets++;
4838 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4839 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4840 tx_skb->skb = NULL;
4841 }
4842 dirty_tx++;
4843 tx_left--;
4844 }
4845
4846 if (tp->dirty_tx != dirty_tx) {
4847 tp->dirty_tx = dirty_tx;
4848 smp_wmb();
4849 if (netif_queue_stopped(dev) &&
4850 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4851 netif_wake_queue(dev);
4852 }
d78ae2dc
FR		 4853 /*
4854 * 8168 hack: TxPoll requests are lost when the Tx packets are
4855 * too close. Let's kick an extra TxPoll request when a burst
4856 * of start_xmit activity is detected (if it is not detected,
4857 * it is slow enough). -- FR
4858 */
4859 smp_rmb();
4860 if (tp->cur_tx != dirty_tx)
4861 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4862 }
4863}
4864
126fa4b9
FR		 4865static inline int rtl8169_fragmented_frame(u32 status)
4866{
4867 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4868}
4869
adea1ac7 4870static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4871{
1da177e4
LT		 4872 u32 status = opts1 & RxProtoMask;
4873
4874 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4875 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4876 skb->ip_summed = CHECKSUM_UNNECESSARY;
4877 else
bc8acf2c 4878 skb_checksum_none_assert(skb);
1da177e4
LT		 4879}
4880
6f0333b8
ED		 4881static struct sk_buff *rtl8169_try_rx_copy(void *data,
4882 struct rtl8169_private *tp,
4883 int pkt_size,
4884 dma_addr_t addr)
1da177e4 4885{
b449655f 4886 struct sk_buff *skb;
48addcc9 4887 struct device *d = &tp->pci_dev->dev;
b449655f 4888
6f0333b8 4889 data = rtl8169_align(data);
48addcc9 4890 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4891 prefetch(data);
4892 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4893 if (skb)
4894 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4895 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4896
6f0333b8 4897 return skb;
1da177e4
LT		 4898}
4899
07d3f51f
FR		 4900static int rtl8169_rx_interrupt(struct net_device *dev,
4901 struct rtl8169_private *tp,
bea3348e 4902 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4903{
4904 unsigned int cur_rx, rx_left;
6f0333b8 4905 unsigned int count;
1da177e4 4906
1da177e4
LT		 4907 cur_rx = tp->cur_rx;
4908 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4909 rx_left = min(rx_left, budget);
1da177e4 4910
4dcb7d33 4911 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4912 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4913 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4914 u32 status;
4915
4916 rmb();
126fa4b9 4917 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4918
4919 if (status & DescOwn)
4920 break;
4dcb7d33 4921 if (unlikely(status & RxRES)) {
bf82c189
JP		 4922 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4923 status);
cebf8cc7 4924 dev->stats.rx_errors++;
1da177e4 4925 if (status & (RxRWT | RxRUNT))
cebf8cc7 4926 dev->stats.rx_length_errors++;
1da177e4 4927 if (status & RxCRC)
cebf8cc7 4928 dev->stats.rx_crc_errors++;
9dccf611
FR		 4929 if (status & RxFOVF) {
4930 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4931 dev->stats.rx_fifo_errors++;
9dccf611 4932 }
6f0333b8 4933 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4934 } else {
6f0333b8 4935 struct sk_buff *skb;
b449655f 4936 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4937 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4938
126fa4b9
FR		 4939 /*
4940 * The driver does not support incoming fragmented
4941 * frames. They are seen as a symptom of over-mtu
4942 * sized frames.
4943 */
4944 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4945 dev->stats.rx_dropped++;
4946 dev->stats.rx_length_errors++;
6f0333b8 4947 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4948 continue;
126fa4b9
FR		 4949 }
4950
6f0333b8
ED		 4951 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4952 tp, pkt_size, addr);
4953 rtl8169_mark_to_asic(desc, rx_buf_sz);
4954 if (!skb) {
4955 dev->stats.rx_dropped++;
4956 continue;
1da177e4
LT		 4957 }
4958
adea1ac7 4959 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4960 skb_put(skb, pkt_size);
4961 skb->protocol = eth_type_trans(skb, dev);
4962
7a8fc77b
FR		 4963 rtl8169_rx_vlan_tag(desc, skb);
4964
56de414c 4965 napi_gro_receive(&tp->napi, skb);
1da177e4 4966
cebf8cc7
FR		 4967 dev->stats.rx_bytes += pkt_size;
4968 dev->stats.rx_packets++;
1da177e4 4969 }
6dccd16b
FR		 4970
4971 /* Work around for AMD plateform. */
95e0918d 4972 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4973 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4974 desc->opts2 = 0;
4975 cur_rx++;
4976 }
1da177e4
LT		 4977 }
4978
4979 count = cur_rx - tp->cur_rx;
4980 tp->cur_rx = cur_rx;
4981
6f0333b8 4982 tp->dirty_rx += count;
1da177e4
LT		 4983
4984 return count;
4985}
4986
07d3f51f 4987static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4988{
07d3f51f 4989 struct net_device *dev = dev_instance;
1da177e4 4990 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4991 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4992 int handled = 0;
865c652d 4993 int status;
1da177e4 4994
f11a377b
DD		 4995 /* loop handling interrupts until we have no new ones or
4996 * we hit a invalid/hotplug case.
4997 */
865c652d 4998 status = RTL_R16(IntrStatus);
f11a377b
DD		 4999 while (status && status != 0xffff) {
5000 handled = 1;
1da177e4 5001
f11a377b
DD		 5002 /* Handle all of the error cases first. These will reset
5003 * the chip, so just exit the loop.
5004 */
5005 if (unlikely(!netif_running(dev))) {
5006 rtl8169_asic_down(ioaddr);
5007 break;
5008 }
1da177e4 5009
1519e57f
FR		 5010 if (unlikely(status & RxFIFOOver)) {
5011 switch (tp->mac_version) {
5012 /* Work around for rx fifo overflow */
5013 case RTL_GIGA_MAC_VER_11:
5014 case RTL_GIGA_MAC_VER_22:
5015 case RTL_GIGA_MAC_VER_26:
5016 netif_stop_queue(dev);
5017 rtl8169_tx_timeout(dev);
5018 goto done;
f60ac8e7
FR		 5019 /* Testers needed. */
5020 case RTL_GIGA_MAC_VER_17:
5021 case RTL_GIGA_MAC_VER_19:
5022 case RTL_GIGA_MAC_VER_20:
5023 case RTL_GIGA_MAC_VER_21:
5024 case RTL_GIGA_MAC_VER_23:
5025 case RTL_GIGA_MAC_VER_24:
5026 case RTL_GIGA_MAC_VER_27:
5027 case RTL_GIGA_MAC_VER_28:
4804b3b3 5028 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5029 /* Experimental science. Pktgen proof. */
5030 case RTL_GIGA_MAC_VER_12:
5031 case RTL_GIGA_MAC_VER_25:
5032 if (status == RxFIFOOver)
5033 goto done;
5034 break;
5035 default:
5036 break;
5037 }
f11a377b 5038 }
1da177e4 5039
f11a377b
DD		 5040 if (unlikely(status & SYSErr)) {
5041 rtl8169_pcierr_interrupt(dev);
5042 break;
5043 }
1da177e4 5044
f11a377b 5045 if (status & LinkChg)
e4fbce74 5046 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5047
f11a377b
DD		 5048 /* We need to see the lastest version of tp->intr_mask to
5049 * avoid ignoring an MSI interrupt and having to wait for
5050 * another event which may never come.
5051 */
5052 smp_rmb();
5053 if (status & tp->intr_mask & tp->napi_event) {
5054 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5055 tp->intr_mask = ~tp->napi_event;
5056
5057 if (likely(napi_schedule_prep(&tp->napi)))
5058 __napi_schedule(&tp->napi);
bf82c189
JP		 5059 else
5060 netif_info(tp, intr, dev,
5061 "interrupt %04x in poll\n", status);
f11a377b 5062 }
1da177e4 5063
f11a377b
DD		 5064 /* We only get a new MSI interrupt when all active irq
5065 * sources on the chip have been acknowledged. So, ack
5066 * everything we've seen and check if new sources have become
5067 * active to avoid blocking all interrupts from the chip.
5068 */
5069 RTL_W16(IntrStatus,
5070 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5071 status = RTL_R16(IntrStatus);
865c652d 5072 }
1519e57f 5073done:
1da177e4
LT		 5074 return IRQ_RETVAL(handled);
5075}
5076
bea3348e 5077static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5078{
bea3348e
SH		 5079 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5080 struct net_device *dev = tp->dev;
1da177e4 5081 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5082 int work_done;
1da177e4 5083
bea3348e 5084 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5085 rtl8169_tx_interrupt(dev, tp, ioaddr);
5086
bea3348e 5087 if (work_done < budget) {
288379f0 5088 napi_complete(napi);
f11a377b
DD		 5089
5090 /* We need for force the visibility of tp->intr_mask
5091 * for other CPUs, as we can loose an MSI interrupt
5092 * and potentially wait for a retransmit timeout if we don't.
5093 * The posted write to IntrMask is safe, as it will
5094 * eventually make it to the chip and we won't loose anything
5095 * until it does.
1da177e4 5096 */
f11a377b 5097 tp->intr_mask = 0xffff;
4c020a96 5098 wmb();
0e485150 5099 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5100 }
5101
bea3348e 5102 return work_done;
1da177e4 5103}
1da177e4 5104
523a6094
FR		 5105static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5106{
5107 struct rtl8169_private *tp = netdev_priv(dev);
5108
5109 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5110 return;
5111
5112 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5113 RTL_W32(RxMissed, 0);
5114}
5115
1da177e4
LT		 5116static void rtl8169_down(struct net_device *dev)
5117{
5118 struct rtl8169_private *tp = netdev_priv(dev);
5119 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5120
4876cc1e 5121 del_timer_sync(&tp->timer);
1da177e4
LT		 5122
5123 netif_stop_queue(dev);
5124
93dd79e8 5125 napi_disable(&tp->napi);
93dd79e8 5126
1da177e4
LT		 5127 spin_lock_irq(&tp->lock);
5128
5129 rtl8169_asic_down(ioaddr);
323bb685
SG		 5130 /*
5131 * At this point device interrupts can not be enabled in any function,
5132 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5133 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5134 */
523a6094 5135 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5136
5137 spin_unlock_irq(&tp->lock);
5138
5139 synchronize_irq(dev->irq);
5140
1da177e4 5141 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5142 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5143
1da177e4
LT		 5144 rtl8169_tx_clear(tp);
5145
5146 rtl8169_rx_clear(tp);
065c27c1 5147
5148 rtl_pll_power_down(tp);
1da177e4
LT		 5149}
5150
5151static int rtl8169_close(struct net_device *dev)
5152{
5153 struct rtl8169_private *tp = netdev_priv(dev);
5154 struct pci_dev *pdev = tp->pci_dev;
5155
e1759441
RW		 5156 pm_runtime_get_sync(&pdev->dev);
5157
cecb5fd7 5158 /* Update counters before going down */
355423d0
IV		 5159 rtl8169_update_counters(dev);
5160
1da177e4
LT		 5161 rtl8169_down(dev);
5162
5163 free_irq(dev->irq, dev);
5164
82553bb6
SG		 5165 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5166 tp->RxPhyAddr);
5167 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5168 tp->TxPhyAddr);
1da177e4
LT		 5169 tp->TxDescArray = NULL;
5170 tp->RxDescArray = NULL;
5171
e1759441
RW		 5172 pm_runtime_put_sync(&pdev->dev);
5173
1da177e4
LT		 5174 return 0;
5175}
5176
07ce4064 5177static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5178{
5179 struct rtl8169_private *tp = netdev_priv(dev);
5180 void __iomem *ioaddr = tp->mmio_addr;
5181 unsigned long flags;
5182 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5183 int rx_mode;
1da177e4
LT		 5184 u32 tmp = 0;
5185
5186 if (dev->flags & IFF_PROMISC) {
5187 /* Unconditionally log net taps. */
bf82c189 5188 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5189 rx_mode =
5190 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5191 AcceptAllPhys;
5192 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5193 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5194 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5195 /* Too many to filter perfectly -- accept all multicasts. */
5196 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5197 mc_filter[1] = mc_filter[0] = 0xffffffff;
5198 } else {
22bedad3 5199 struct netdev_hw_addr *ha;
07d3f51f 5200
1da177e4
LT		 5201 rx_mode = AcceptBroadcast | AcceptMyPhys;
5202 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5203 netdev_for_each_mc_addr(ha, dev) {
5204 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5205 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5206 rx_mode |= AcceptMulticast;
5207 }
5208 }
5209
5210 spin_lock_irqsave(&tp->lock, flags);
5211
5212 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5213 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5214
f887cce8 5215 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5216 u32 data = mc_filter[0];
5217
5218 mc_filter[0] = swab32(mc_filter[1]);
5219 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5220 }
5221
1da177e4 5222 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5223 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5224
57a9f236
FR		 5225 RTL_W32(RxConfig, tmp);
5226
1da177e4
LT		 5227 spin_unlock_irqrestore(&tp->lock, flags);
5228}
5229
5230/**
5231 * rtl8169_get_stats - Get rtl8169 read/write statistics
5232 * @dev: The Ethernet Device to get statistics for
5233 *
5234 * Get TX/RX statistics for rtl8169
5235 */
5236static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5237{
5238 struct rtl8169_private *tp = netdev_priv(dev);
5239 void __iomem *ioaddr = tp->mmio_addr;
5240 unsigned long flags;
5241
5242 if (netif_running(dev)) {
5243 spin_lock_irqsave(&tp->lock, flags);
523a6094 5244 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5245 spin_unlock_irqrestore(&tp->lock, flags);
5246 }
5b0384f4 5247
cebf8cc7 5248 return &dev->stats;
1da177e4
LT		 5249}
5250
861ab440 5251static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5252{
065c27c1 5253 struct rtl8169_private *tp = netdev_priv(dev);
5254
5d06a99f 5255 if (!netif_running(dev))
861ab440 5256 return;
5d06a99f 5257
065c27c1 5258 rtl_pll_power_down(tp);
5259
5d06a99f
FR		 5260 netif_device_detach(dev);
5261 netif_stop_queue(dev);
861ab440
RW		 5262}
5263
5264#ifdef CONFIG_PM
5265
5266static int rtl8169_suspend(struct device *device)
5267{
5268 struct pci_dev *pdev = to_pci_dev(device);
5269 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5270
861ab440 5271 rtl8169_net_suspend(dev);
1371fa6d 5272
5d06a99f
FR		 5273 return 0;
5274}
5275
e1759441
RW		 5276static void __rtl8169_resume(struct net_device *dev)
5277{
065c27c1 5278 struct rtl8169_private *tp = netdev_priv(dev);
5279
e1759441 5280 netif_device_attach(dev);
065c27c1 5281
5282 rtl_pll_power_up(tp);
5283
e1759441
RW		 5284 rtl8169_schedule_work(dev, rtl8169_reset_task);
5285}
5286
861ab440 5287static int rtl8169_resume(struct device *device)
5d06a99f 5288{
861ab440 5289 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5290 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5291 struct rtl8169_private *tp = netdev_priv(dev);
5292
5293 rtl8169_init_phy(dev, tp);
5d06a99f 5294
e1759441
RW		 5295 if (netif_running(dev))
5296 __rtl8169_resume(dev);
5d06a99f 5297
e1759441
RW		 5298 return 0;
5299}
5300
5301static int rtl8169_runtime_suspend(struct device *device)
5302{
5303 struct pci_dev *pdev = to_pci_dev(device);
5304 struct net_device *dev = pci_get_drvdata(pdev);
5305 struct rtl8169_private *tp = netdev_priv(dev);
5306
5307 if (!tp->TxDescArray)
5308 return 0;
5309
5310 spin_lock_irq(&tp->lock);
5311 tp->saved_wolopts = __rtl8169_get_wol(tp);
5312 __rtl8169_set_wol(tp, WAKE_ANY);
5313 spin_unlock_irq(&tp->lock);
5314
5315 rtl8169_net_suspend(dev);
5316
5317 return 0;
5318}
5319
5320static int rtl8169_runtime_resume(struct device *device)
5321{
5322 struct pci_dev *pdev = to_pci_dev(device);
5323 struct net_device *dev = pci_get_drvdata(pdev);
5324 struct rtl8169_private *tp = netdev_priv(dev);
5325
5326 if (!tp->TxDescArray)
5327 return 0;
5328
5329 spin_lock_irq(&tp->lock);
5330 __rtl8169_set_wol(tp, tp->saved_wolopts);
5331 tp->saved_wolopts = 0;
5332 spin_unlock_irq(&tp->lock);
5333
fccec10b
SG		 5334 rtl8169_init_phy(dev, tp);
5335
e1759441 5336 __rtl8169_resume(dev);
5d06a99f 5337
5d06a99f
FR		 5338 return 0;
5339}
5340
e1759441
RW		 5341static int rtl8169_runtime_idle(struct device *device)
5342{
5343 struct pci_dev *pdev = to_pci_dev(device);
5344 struct net_device *dev = pci_get_drvdata(pdev);
5345 struct rtl8169_private *tp = netdev_priv(dev);
5346
e4fbce74 5347 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5348}
5349
47145210 5350static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5351 .suspend = rtl8169_suspend,
5352 .resume = rtl8169_resume,
5353 .freeze = rtl8169_suspend,
5354 .thaw = rtl8169_resume,
5355 .poweroff = rtl8169_suspend,
5356 .restore = rtl8169_resume,
5357 .runtime_suspend = rtl8169_runtime_suspend,
5358 .runtime_resume = rtl8169_runtime_resume,
5359 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5360};
5361
5362#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5363
5364#else /* !CONFIG_PM */
5365
5366#define RTL8169_PM_OPS NULL
5367
5368#endif /* !CONFIG_PM */
5369
1765f95d
FR		 5370static void rtl_shutdown(struct pci_dev *pdev)
5371{
861ab440 5372 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5373 struct rtl8169_private *tp = netdev_priv(dev);
5374 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5375
5376 rtl8169_net_suspend(dev);
1765f95d 5377
cecb5fd7 5378 /* Restore original MAC address */
cc098dc7
IV		 5379 rtl_rar_set(tp, dev->perm_addr);
5380
4bb3f522 5381 spin_lock_irq(&tp->lock);
5382
5383 rtl8169_asic_down(ioaddr);
5384
5385 spin_unlock_irq(&tp->lock);
5386
861ab440 5387 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5388 /* WoL fails with some 8168 when the receiver is disabled. */
5389 if (tp->features & RTL_FEATURE_WOL) {
5390 pci_clear_master(pdev);
5391
5392 RTL_W8(ChipCmd, CmdRxEnb);
5393 /* PCI commit */
5394 RTL_R8(ChipCmd);
5395 }
5396
861ab440
RW		 5397 pci_wake_from_d3(pdev, true);
5398 pci_set_power_state(pdev, PCI_D3hot);
5399 }
5400}
5d06a99f 5401
1da177e4
LT		 5402static struct pci_driver rtl8169_pci_driver = {
5403 .name = MODULENAME,
5404 .id_table = rtl8169_pci_tbl,
5405 .probe = rtl8169_init_one,
5406 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5407 .shutdown = rtl_shutdown,
861ab440 5408 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5409};
5410
07d3f51f 5411static int __init rtl8169_init_module(void)
1da177e4 5412{
29917620 5413 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5414}
5415
07d3f51f 5416static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5417{
5418 pci_unregister_driver(&rtl8169_pci_driver);
5419}
5420
5421module_init(rtl8169_init_module);
5422module_exit(rtl8169_cleanup_module);
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