[linux.git] / drivers / phy / phy-omap-control.c

/*
 * omap-control-phy.c - The PHY part of control module.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <[email protected]>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/phy/omap_control_phy.h>

/**
 * omap_control_pcie_pcs - set the PCS delay count
 * @dev: the control module device
 * @delay: 8 bit delay value
 */
void omap_control_pcie_pcs(struct device *dev, u8 delay)
{
	u32 val;
	struct omap_control_phy	*control_phy;

	if (IS_ERR(dev) || !dev) {
		pr_err("%s: invalid device\n", __func__);
		return;
	}

	control_phy = dev_get_drvdata(dev);
	if (!control_phy) {
		dev_err(dev, "%s: invalid control phy device\n", __func__);
		return;
	}

	if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
		dev_err(dev, "%s: unsupported operation\n", __func__);
		return;
	}

	val = readl(control_phy->pcie_pcs);
	val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
		OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
	val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
	writel(val, control_phy->pcie_pcs);
}
EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);

/**
 * omap_control_phy_power - power on/off the phy using control module reg
 * @dev: the control module device
 * @on: 0 or 1, based on powering on or off the PHY
 */
void omap_control_phy_power(struct device *dev, int on)
{
	u32 val;
	unsigned long rate;
	struct omap_control_phy	*control_phy;

	if (IS_ERR(dev) || !dev) {
		pr_err("%s: invalid device\n", __func__);
		return;
	}

	control_phy = dev_get_drvdata(dev);
	if (!control_phy) {
		dev_err(dev, "%s: invalid control phy device\n", __func__);
		return;
	}

	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
		return;

	val = readl(control_phy->power);

	switch (control_phy->type) {
	case OMAP_CTRL_TYPE_USB2:
		if (on)
			val &= ~OMAP_CTRL_DEV_PHY_PD;
		else
			val |= OMAP_CTRL_DEV_PHY_PD;
		break;

	case OMAP_CTRL_TYPE_PCIE:
	case OMAP_CTRL_TYPE_PIPE3:
		rate = clk_get_rate(control_phy->sys_clk);
		rate = rate/1000000;

		if (on) {
			val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
			val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
			val |= rate <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
		} else {
			val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
			val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
		}
		break;

	case OMAP_CTRL_TYPE_DRA7USB2:
		if (on)
			val &= ~OMAP_CTRL_USB2_PHY_PD;
		else
			val |= OMAP_CTRL_USB2_PHY_PD;
		break;

	case OMAP_CTRL_TYPE_AM437USB2:
		if (on) {
			val &= ~(AM437X_CTRL_USB2_PHY_PD |
					AM437X_CTRL_USB2_OTG_PD);
			val |= (AM437X_CTRL_USB2_OTGVDET_EN |
					AM437X_CTRL_USB2_OTGSESSEND_EN);
		} else {
			val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
					AM437X_CTRL_USB2_OTGSESSEND_EN);
			val |= (AM437X_CTRL_USB2_PHY_PD |
					 AM437X_CTRL_USB2_OTG_PD);
		}
		break;
	default:
		dev_err(dev, "%s: type %d not recognized\n",
			__func__, control_phy->type);
		break;
	}

	writel(val, control_phy->power);
}
EXPORT_SYMBOL_GPL(omap_control_phy_power);

/**
 * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core that a usb
 * device has been connected.
 */
static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
	val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
 * impedance
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core that it has been
 * connected to a usb host.
 */
static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~OMAP_CTRL_DEV_SESSEND;
	val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
		OMAP_CTRL_DEV_VBUSVALID;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
 * impedance
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core it's now in
 * disconnected state.
 */
static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
	val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
 * or device mode or to denote disconnected state
 * @dev: the control module device
 * @mode: The mode to which usb should be configured
 *
 * This is an API to write to the mailbox register to notify the usb core that
 * a usb device has been connected.
 */
void omap_control_usb_set_mode(struct device *dev,
	enum omap_control_usb_mode mode)
{
	struct omap_control_phy	*ctrl_phy;

	if (IS_ERR(dev) || !dev)
		return;

	ctrl_phy = dev_get_drvdata(dev);
	if (!ctrl_phy) {
		dev_err(dev, "Invalid control phy device\n");
		return;
	}

	if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
		return;

	switch (mode) {
	case USB_MODE_HOST:
		omap_control_usb_host_mode(ctrl_phy);
		break;
	case USB_MODE_DEVICE:
		omap_control_usb_device_mode(ctrl_phy);
		break;
	case USB_MODE_DISCONNECT:
		omap_control_usb_set_sessionend(ctrl_phy);
		break;
	default:
		dev_vdbg(dev, "invalid omap control usb mode\n");
	}
}
EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);

static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;

static const struct of_device_id omap_control_phy_id_table[] = {
	{
		.compatible = "ti,control-phy-otghs",
		.data = &otghs_data,
	},
	{
		.compatible = "ti,control-phy-usb2",
		.data = &usb2_data,
	},
	{
		.compatible = "ti,control-phy-pipe3",
		.data = &pipe3_data,
	},
	{
		.compatible = "ti,control-phy-pcie",
		.data = &pcie_data,
	},
	{
		.compatible = "ti,control-phy-usb2-dra7",
		.data = &dra7usb2_data,
	},
	{
		.compatible = "ti,control-phy-usb2-am437",
		.data = &am437usb2_data,
	},
	{},
};
MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);

static int omap_control_phy_probe(struct platform_device *pdev)
{
	struct resource	*res;
	const struct of_device_id *of_id;
	struct omap_control_phy *control_phy;

	of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
	if (!of_id)
		return -EINVAL;

	control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
		GFP_KERNEL);
	if (!control_phy)
		return -ENOMEM;

	control_phy->dev = &pdev->dev;
	control_phy->type = *(enum omap_control_phy_type *)of_id->data;

	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
			"otghs_control");
		control_phy->otghs_control = devm_ioremap_resource(
			&pdev->dev, res);
		if (IS_ERR(control_phy->otghs_control))
			return PTR_ERR(control_phy->otghs_control);
	} else {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
				"power");
		control_phy->power = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(control_phy->power)) {
			dev_err(&pdev->dev, "Couldn't get power register\n");
			return PTR_ERR(control_phy->power);
		}
	}

	if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
	    control_phy->type == OMAP_CTRL_TYPE_PCIE) {
		control_phy->sys_clk = devm_clk_get(control_phy->dev,
			"sys_clkin");
		if (IS_ERR(control_phy->sys_clk)) {
			pr_err("%s: unable to get sys_clkin\n", __func__);
			return -EINVAL;
		}
	}

	if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						   "pcie_pcs");
		control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(control_phy->pcie_pcs))
			return PTR_ERR(control_phy->pcie_pcs);
	}

	dev_set_drvdata(control_phy->dev, control_phy);

	return 0;
}

static struct platform_driver omap_control_phy_driver = {
	.probe		= omap_control_phy_probe,
	.driver		= {
		.name	= "omap-control-phy",
		.of_match_table = omap_control_phy_id_table,
	},
};

static int __init omap_control_phy_init(void)
{
	return platform_driver_register(&omap_control_phy_driver);
}
subsys_initcall(omap_control_phy_init);

static void __exit omap_control_phy_exit(void)
{
	platform_driver_unregister(&omap_control_phy_driver);
}
module_exit(omap_control_phy_exit);

MODULE_ALIAS("platform:omap_control_phy");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
01658f0f	1	/*
14da699b	2	* omap-control-phy.c - The PHY part of control module.
01658f0f KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <[email protected]>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
	22	#include <linux/of.h>
6cb9310a	23	#include <linux/of_device.h>
01658f0f KVA	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/clk.h>
14da699b	27	#include <linux/phy/omap_control_phy.h>
01658f0f	28
f0e2cf7b KVA	29	/**
	30	* omap_control_pcie_pcs - set the PCS delay count
	31	* @dev: the control module device
f0e2cf7b KVA	32	* @delay: 8 bit delay value
f0e2cf7b KVA	33	*/
0bc09f9c	34	void omap_control_pcie_pcs(struct device *dev, u8 delay)
f0e2cf7b KVA	35	{
	36	u32 val;
	37	struct omap_control_phy *control_phy;
	38
	39	if (IS_ERR(dev) \|\| !dev) {
	40	pr_err("%s: invalid device\n", __func__);
	41	return;
	42	}
	43
	44	control_phy = dev_get_drvdata(dev);
	45	if (!control_phy) {
	46	dev_err(dev, "%s: invalid control phy device\n", __func__);
	47	return;
	48	}
	49
	50	if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
	51	dev_err(dev, "%s: unsupported operation\n", __func__);
	52	return;
	53	}
	54
	55	val = readl(control_phy->pcie_pcs);
	56	val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
0bc09f9c V	57	OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
0bc09f9c V	58	val \|= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
f0e2cf7b KVA	59	writel(val, control_phy->pcie_pcs);
	60	}
	61	EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
	62
01658f0f	63	/**
14da699b	64	* omap_control_phy_power - power on/off the phy using control module reg
01658f0f	65	* @dev: the control module device
6cb9310a	66	* @on: 0 or 1, based on powering on or off the PHY
01658f0f	67	*/
14da699b	68	void omap_control_phy_power(struct device *dev, int on)
01658f0f KVA	69	{
	70	u32 val;
	71	unsigned long rate;
14da699b	72	struct omap_control_phy *control_phy;
01658f0f	73
6cb9310a RQ	74	if (IS_ERR(dev) \|\| !dev) {
6cb9310a RQ	75	pr_err("%s: invalid device\n", __func__);
01658f0f	76	return;
6cb9310a	77	}
01658f0f	78
14da699b KVA	79	control_phy = dev_get_drvdata(dev);
	80	if (!control_phy) {
	81	dev_err(dev, "%s: invalid control phy device\n", __func__);
6cb9310a	82	return;
01658f0f KVA	83	}
01658f0f KVA	84
14da699b	85	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
6cb9310a	86	return;
01658f0f	87
14da699b	88	val = readl(control_phy->power);
6cb9310a	89
14da699b	90	switch (control_phy->type) {
6cb9310a RQ	91	case OMAP_CTRL_TYPE_USB2:
	92	if (on)
	93	val &= ~OMAP_CTRL_DEV_PHY_PD;
	94	else
	95	val \|= OMAP_CTRL_DEV_PHY_PD;
	96	break;
01658f0f	97
f0e2cf7b	98	case OMAP_CTRL_TYPE_PCIE:
6cb9310a	99	case OMAP_CTRL_TYPE_PIPE3:
14da699b	100	rate = clk_get_rate(control_phy->sys_clk);
6cb9310a RQ	101	rate = rate/1000000;
	102
	103	if (on) {
14da699b KVA	104	val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK \|
	105	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
	106	val \|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
	107	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
	108	val \|= rate <<
	109	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
6cb9310a	110	} else {
14da699b KVA	111	val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
	112	val \|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
	113	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
6cb9310a RQ	114	}
6cb9310a RQ	115	break;
01658f0f	116
6cb9310a RQ	117	case OMAP_CTRL_TYPE_DRA7USB2:
	118	if (on)
	119	val &= ~OMAP_CTRL_USB2_PHY_PD;
	120	else
	121	val \|= OMAP_CTRL_USB2_PHY_PD;
	122	break;
c4b34a3b GC	123
	124	case OMAP_CTRL_TYPE_AM437USB2:
	125	if (on) {
	126	val &= ~(AM437X_CTRL_USB2_PHY_PD \|
	127	AM437X_CTRL_USB2_OTG_PD);
	128	val \|= (AM437X_CTRL_USB2_OTGVDET_EN \|
	129	AM437X_CTRL_USB2_OTGSESSEND_EN);
	130	} else {
	131	val &= ~(AM437X_CTRL_USB2_OTGVDET_EN \|
	132	AM437X_CTRL_USB2_OTGSESSEND_EN);
	133	val \|= (AM437X_CTRL_USB2_PHY_PD \|
	134	AM437X_CTRL_USB2_OTG_PD);
	135	}
	136	break;
6cb9310a RQ	137	default:
6cb9310a RQ	138	dev_err(dev, "%s: type %d not recognized\n",
14da699b	139	__func__, control_phy->type);
6cb9310a RQ	140	break;
6cb9310a RQ	141	}
01658f0f	142
14da699b	143	writel(val, control_phy->power);
01658f0f	144	}
14da699b	145	EXPORT_SYMBOL_GPL(omap_control_phy_power);
01658f0f KVA	146
	147	/**
	148	* omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
14da699b	149	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	150	*
	151	* Writes to the mailbox register to notify the usb core that a usb
	152	* device has been connected.
	153	*/
14da699b	154	static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
01658f0f KVA	155	{
	156	u32 val;
	157
14da699b	158	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	159	val &= ~(OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_SESSEND);
01658f0f KVA	160	val \|= OMAP_CTRL_DEV_AVALID \| OMAP_CTRL_DEV_VBUSVALID;
14da699b	161	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	162	}
	163
	164	/**
	165	* omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
	166	* impedance
14da699b	167	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	168	*
	169	* Writes to the mailbox register to notify the usb core that it has been
	170	* connected to a usb host.
	171	*/
14da699b	172	static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
01658f0f KVA	173	{
	174	u32 val;
	175
14da699b	176	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	177	val &= ~OMAP_CTRL_DEV_SESSEND;
	178	val \|= OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_AVALID \|
	179	OMAP_CTRL_DEV_VBUSVALID;
14da699b	180	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	181	}
	182
	183	/**
	184	* omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
	185	* impedance
14da699b	186	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	187	*
	188	* Writes to the mailbox register to notify the usb core it's now in
	189	* disconnected state.
	190	*/
14da699b	191	static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
01658f0f KVA	192	{
	193	u32 val;
	194
14da699b	195	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	196	val &= ~(OMAP_CTRL_DEV_AVALID \| OMAP_CTRL_DEV_VBUSVALID);
01658f0f KVA	197	val \|= OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_SESSEND;
14da699b	198	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	199	}
	200
	201	/**
	202	* omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
	203	* or device mode or to denote disconnected state
	204	* @dev: the control module device
	205	* @mode: The mode to which usb should be configured
	206	*
	207	* This is an API to write to the mailbox register to notify the usb core that
	208	* a usb device has been connected.
	209	*/
	210	void omap_control_usb_set_mode(struct device *dev,
	211	enum omap_control_usb_mode mode)
	212	{
14da699b	213	struct omap_control_phy *ctrl_phy;
01658f0f	214
0bb85dc2	215	if (IS_ERR(dev) \|\| !dev)
01658f0f KVA	216	return;
01658f0f KVA	217
14da699b	218	ctrl_phy = dev_get_drvdata(dev);
14da699b KVA	219	if (!ctrl_phy) {
14da699b KVA	220	dev_err(dev, "Invalid control phy device\n");
0bb85dc2 RQ	221	return;
	222	}
	223
14da699b	224	if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
0bb85dc2 RQ	225	return;
0bb85dc2 RQ	226
01658f0f KVA	227	switch (mode) {
01658f0f KVA	228	case USB_MODE_HOST:
14da699b	229	omap_control_usb_host_mode(ctrl_phy);
01658f0f KVA	230	break;
01658f0f KVA	231	case USB_MODE_DEVICE:
14da699b	232	omap_control_usb_device_mode(ctrl_phy);
01658f0f KVA	233	break;
01658f0f KVA	234	case USB_MODE_DISCONNECT:
14da699b	235	omap_control_usb_set_sessionend(ctrl_phy);
01658f0f KVA	236	break;
	237	default:
	238	dev_vdbg(dev, "invalid omap control usb mode\n");
	239	}
	240	}
	241	EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
	242
14da699b KVA	243	static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
	244	static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
	245	static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
f0e2cf7b	246	static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
14da699b KVA	247	static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
14da699b KVA	248	static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
6cb9310a	249
14da699b	250	static const struct of_device_id omap_control_phy_id_table[] = {
6cb9310a RQ	251	{
	252	.compatible = "ti,control-phy-otghs",
	253	.data = &otghs_data,
	254	},
	255	{
	256	.compatible = "ti,control-phy-usb2",
	257	.data = &usb2_data,
	258	},
	259	{
	260	.compatible = "ti,control-phy-pipe3",
	261	.data = &pipe3_data,
	262	},
f0e2cf7b KVA	263	{
	264	.compatible = "ti,control-phy-pcie",
	265	.data = &pcie_data,
	266	},
6cb9310a	267	{
51c9f4ad	268	.compatible = "ti,control-phy-usb2-dra7",
6cb9310a RQ	269	.data = &dra7usb2_data,
6cb9310a RQ	270	},
c4b34a3b	271	{
51c9f4ad	272	.compatible = "ti,control-phy-usb2-am437",
c4b34a3b GC	273	.data = &am437usb2_data,
c4b34a3b GC	274	},
6cb9310a RQ	275	{},
6cb9310a RQ	276	};
14da699b	277	MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
6cb9310a	278
14da699b	279	static int omap_control_phy_probe(struct platform_device *pdev)
01658f0f KVA	280	{
01658f0f KVA	281	struct resource *res;
6cb9310a	282	const struct of_device_id *of_id;
14da699b	283	struct omap_control_phy *control_phy;
6cb9310a	284
1f9ba767	285	of_id = of_match_device(omap_control_phy_id_table, &pdev->dev);
6cb9310a RQ	286	if (!of_id)
6cb9310a RQ	287	return -EINVAL;
01658f0f	288
14da699b	289	control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
01658f0f	290	GFP_KERNEL);
437a6bc4	291	if (!control_phy)
01658f0f	292	return -ENOMEM;
01658f0f	293
14da699b KVA	294	control_phy->dev = &pdev->dev;
14da699b KVA	295	control_phy->type = (enum omap_control_phy_type )of_id->data;
01658f0f	296
14da699b	297	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
01658f0f KVA	298	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
01658f0f KVA	299	"otghs_control");
14da699b	300	control_phy->otghs_control = devm_ioremap_resource(
01658f0f	301	&pdev->dev, res);
14da699b KVA	302	if (IS_ERR(control_phy->otghs_control))
14da699b KVA	303	return PTR_ERR(control_phy->otghs_control);
6cb9310a	304	} else {
01658f0f	305	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
6cb9310a	306	"power");
14da699b KVA	307	control_phy->power = devm_ioremap_resource(&pdev->dev, res);
14da699b KVA	308	if (IS_ERR(control_phy->power)) {
6cb9310a	309	dev_err(&pdev->dev, "Couldn't get power register\n");
14da699b	310	return PTR_ERR(control_phy->power);
6cb9310a RQ	311	}
6cb9310a RQ	312	}
01658f0f	313
f0e2cf7b KVA	314	if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 \|\|
f0e2cf7b KVA	315	control_phy->type == OMAP_CTRL_TYPE_PCIE) {
14da699b	316	control_phy->sys_clk = devm_clk_get(control_phy->dev,
01658f0f	317	"sys_clkin");
14da699b	318	if (IS_ERR(control_phy->sys_clk)) {
01658f0f KVA	319	pr_err("%s: unable to get sys_clkin\n", __func__);
	320	return -EINVAL;
	321	}
	322	}
	323
f0e2cf7b KVA	324	if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
	325	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	326	"pcie_pcs");
	327	control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
	328	if (IS_ERR(control_phy->pcie_pcs))
	329	return PTR_ERR(control_phy->pcie_pcs);
	330	}
	331
14da699b	332	dev_set_drvdata(control_phy->dev, control_phy);
01658f0f KVA	333
	334	return 0;
	335	}
	336
14da699b KVA	337	static struct platform_driver omap_control_phy_driver = {
14da699b KVA	338	.probe = omap_control_phy_probe,
01658f0f	339	.driver = {
14da699b	340	.name = "omap-control-phy",
1f9ba767	341	.of_match_table = omap_control_phy_id_table,
01658f0f KVA	342	},
	343	};
	344
14da699b	345	static int __init omap_control_phy_init(void)
01658f0f	346	{
14da699b	347	return platform_driver_register(&omap_control_phy_driver);
01658f0f	348	}
14da699b	349	subsys_initcall(omap_control_phy_init);
01658f0f	350
14da699b	351	static void __exit omap_control_phy_exit(void)
01658f0f	352	{
14da699b	353	platform_driver_unregister(&omap_control_phy_driver);
01658f0f	354	}
14da699b	355	module_exit(omap_control_phy_exit);
01658f0f	356
dd64ad38	357	MODULE_ALIAS("platform:omap_control_phy");
01658f0f	358	MODULE_AUTHOR("Texas Instruments Inc.");
14da699b	359	MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
01658f0f	360	MODULE_LICENSE("GPL v2");