[linux.git] / drivers / mfd / jz4740-adc.c

/*
 * Copyright (C) 2009-2010, Lars-Peter Clausen <[email protected]>
 * JZ4740 SoC ADC driver
 *
 * This program is free software; you can redistribute it and/or modify it
 * under  the terms of the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the License, or (at your
 * option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * This driver synchronizes access to the JZ4740 ADC core between the
 * JZ4740 battery and hwmon drivers.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/clk.h>
#include <linux/mfd/core.h>

#include <linux/jz4740-adc.h>


#define JZ_REG_ADC_ENABLE	0x00
#define JZ_REG_ADC_CFG		0x04
#define JZ_REG_ADC_CTRL		0x08
#define JZ_REG_ADC_STATUS	0x0c

#define JZ_REG_ADC_TOUCHSCREEN_BASE	0x10
#define JZ_REG_ADC_BATTERY_BASE	0x1c
#define JZ_REG_ADC_HWMON_BASE	0x20

#define JZ_ADC_ENABLE_TOUCH	BIT(2)
#define JZ_ADC_ENABLE_BATTERY	BIT(1)
#define JZ_ADC_ENABLE_ADCIN	BIT(0)

enum {
	JZ_ADC_IRQ_ADCIN = 0,
	JZ_ADC_IRQ_BATTERY,
	JZ_ADC_IRQ_TOUCH,
	JZ_ADC_IRQ_PENUP,
	JZ_ADC_IRQ_PENDOWN,
};

struct jz4740_adc {
	struct resource *mem;
	void __iomem *base;

	int irq;
	struct irq_chip_generic *gc;

	struct clk *clk;
	atomic_t clk_ref;

	spinlock_t lock;
};

static void jz4740_adc_irq_demux(struct irq_desc *desc)
{
	struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
	uint8_t status;
	unsigned int i;

	status = readb(gc->reg_base + JZ_REG_ADC_STATUS);

	for (i = 0; i < 5; ++i) {
		if (status & BIT(i))
			generic_handle_irq(gc->irq_base + i);
	}
}


/* Refcounting for the ADC clock is done in here instead of in the clock
 * framework, because it is the only clock which is shared between multiple
 * devices and thus is the only clock which needs refcounting */
static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
{
	if (atomic_inc_return(&adc->clk_ref) == 1)
		clk_prepare_enable(adc->clk);
}

static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
{
	if (atomic_dec_return(&adc->clk_ref) == 0)
		clk_disable_unprepare(adc->clk);
}

static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
	bool enabled)
{
	unsigned long flags;
	uint8_t val;

	spin_lock_irqsave(&adc->lock, flags);

	val = readb(adc->base + JZ_REG_ADC_ENABLE);
	if (enabled)
		val |= BIT(engine);
	else
		val &= ~BIT(engine);
	writeb(val, adc->base + JZ_REG_ADC_ENABLE);

	spin_unlock_irqrestore(&adc->lock, flags);
}

static int jz4740_adc_cell_enable(struct platform_device *pdev)
{
	struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);

	jz4740_adc_clk_enable(adc);
	jz4740_adc_set_enabled(adc, pdev->id, true);

	return 0;
}

static int jz4740_adc_cell_disable(struct platform_device *pdev)
{
	struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);

	jz4740_adc_set_enabled(adc, pdev->id, false);
	jz4740_adc_clk_disable(adc);

	return 0;
}

int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
{
	struct jz4740_adc *adc = dev_get_drvdata(dev);
	unsigned long flags;
	uint32_t cfg;

	if (!adc)
		return -ENODEV;

	spin_lock_irqsave(&adc->lock, flags);

	cfg = readl(adc->base + JZ_REG_ADC_CFG);

	cfg &= ~mask;
	cfg |= val;

	writel(cfg, adc->base + JZ_REG_ADC_CFG);

	spin_unlock_irqrestore(&adc->lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(jz4740_adc_set_config);

static struct resource jz4740_hwmon_resources[] = {
	{
		.start = JZ_ADC_IRQ_ADCIN,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start	= JZ_REG_ADC_HWMON_BASE,
		.end	= JZ_REG_ADC_HWMON_BASE + 3,
		.flags	= IORESOURCE_MEM,
	},
};

static struct resource jz4740_battery_resources[] = {
	{
		.start = JZ_ADC_IRQ_BATTERY,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start	= JZ_REG_ADC_BATTERY_BASE,
		.end	= JZ_REG_ADC_BATTERY_BASE + 3,
		.flags	= IORESOURCE_MEM,
	},
};

static const struct mfd_cell jz4740_adc_cells[] = {
	{
		.id = 0,
		.name = "jz4740-hwmon",
		.num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
		.resources = jz4740_hwmon_resources,

		.enable = jz4740_adc_cell_enable,
		.disable = jz4740_adc_cell_disable,
	},
	{
		.id = 1,
		.name = "jz4740-battery",
		.num_resources = ARRAY_SIZE(jz4740_battery_resources),
		.resources = jz4740_battery_resources,

		.enable = jz4740_adc_cell_enable,
		.disable = jz4740_adc_cell_disable,
	},
};

static int jz4740_adc_probe(struct platform_device *pdev)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	struct jz4740_adc *adc;
	struct resource *mem_base;
	int ret;
	int irq_base;

	adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL);
	if (!adc)
		return -ENOMEM;

	adc->irq = platform_get_irq(pdev, 0);
	if (adc->irq < 0) {
		ret = adc->irq;
		dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
		return ret;
	}

	irq_base = platform_get_irq(pdev, 1);
	if (irq_base < 0) {
		dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base);
		return irq_base;
	}

	mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem_base) {
		dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
		return -ENOENT;
	}

	/* Only request the shared registers for the MFD driver */
	adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
					pdev->name);
	if (!adc->mem) {
		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
		return -EBUSY;
	}

	adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
	if (!adc->base) {
		ret = -EBUSY;
		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
		goto err_release_mem_region;
	}

	adc->clk = clk_get(&pdev->dev, "adc");
	if (IS_ERR(adc->clk)) {
		ret = PTR_ERR(adc->clk);
		dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
		goto err_iounmap;
	}

	spin_lock_init(&adc->lock);
	atomic_set(&adc->clk_ref, 0);

	platform_set_drvdata(pdev, adc);

	gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base,
		handle_level_irq);

	ct = gc->chip_types;
	ct->regs.mask = JZ_REG_ADC_CTRL;
	ct->regs.ack = JZ_REG_ADC_STATUS;
	ct->chip.irq_mask = irq_gc_mask_set_bit;
	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	ct->chip.irq_ack = irq_gc_ack_set_bit;

	irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0,
				IRQ_NOPROBE | IRQ_LEVEL);

	adc->gc = gc;

	irq_set_chained_handler_and_data(adc->irq, jz4740_adc_irq_demux, gc);

	writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
	writeb(0xff, adc->base + JZ_REG_ADC_CTRL);

	ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
			      ARRAY_SIZE(jz4740_adc_cells), mem_base,
			      irq_base, NULL);
	if (ret < 0)
		goto err_clk_put;

	return 0;

err_clk_put:
	clk_put(adc->clk);
err_iounmap:
	iounmap(adc->base);
err_release_mem_region:
	release_mem_region(adc->mem->start, resource_size(adc->mem));
	return ret;
}

static int jz4740_adc_remove(struct platform_device *pdev)
{
	struct jz4740_adc *adc = platform_get_drvdata(pdev);

	mfd_remove_devices(&pdev->dev);

	irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE | IRQ_LEVEL, 0);
	kfree(adc->gc);
	irq_set_chained_handler_and_data(adc->irq, NULL, NULL);

	iounmap(adc->base);
	release_mem_region(adc->mem->start, resource_size(adc->mem));

	clk_put(adc->clk);

	return 0;
}

static struct platform_driver jz4740_adc_driver = {
	.probe	= jz4740_adc_probe,
	.remove = jz4740_adc_remove,
	.driver = {
		.name = "jz4740-adc",
	},
};

module_platform_driver(jz4740_adc_driver);

MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:jz4740-adc");
Commit	Line	Data
91f4debf LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <[email protected]>
	3	* JZ4740 SoC ADC driver
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* You should have received a copy of the GNU General Public License along
	11	* with this program; if not, write to the Free Software Foundation, Inc.,
	12	* 675 Mass Ave, Cambridge, MA 02139, USA.
	13	*
	14	* This driver synchronizes access to the JZ4740 ADC core between the
	15	* JZ4740 battery and hwmon drivers.
	16	*/
	17
	18	#include <linux/err.h>
fa860403	19	#include <linux/io.h>
91f4debf LPC	20	#include <linux/irq.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/slab.h>
	26	#include <linux/spinlock.h>
	27
	28	#include <linux/clk.h>
	29	#include <linux/mfd/core.h>
	30
	31	#include <linux/jz4740-adc.h>
	32
	33
	34	#define JZ_REG_ADC_ENABLE 0x00
	35	#define JZ_REG_ADC_CFG 0x04
	36	#define JZ_REG_ADC_CTRL 0x08
	37	#define JZ_REG_ADC_STATUS 0x0c
	38
	39	#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
	40	#define JZ_REG_ADC_BATTERY_BASE 0x1c
	41	#define JZ_REG_ADC_HWMON_BASE 0x20
	42
	43	#define JZ_ADC_ENABLE_TOUCH BIT(2)
	44	#define JZ_ADC_ENABLE_BATTERY BIT(1)
	45	#define JZ_ADC_ENABLE_ADCIN BIT(0)
	46
	47	enum {
	48	JZ_ADC_IRQ_ADCIN = 0,
	49	JZ_ADC_IRQ_BATTERY,
	50	JZ_ADC_IRQ_TOUCH,
	51	JZ_ADC_IRQ_PENUP,
	52	JZ_ADC_IRQ_PENDOWN,
	53	};
	54
	55	struct jz4740_adc {
	56	struct resource *mem;
	57	void __iomem *base;
	58
	59	int irq;
914e6d4e	60	struct irq_chip_generic *gc;
91f4debf LPC	61
	62	struct clk *clk;
	63	atomic_t clk_ref;
	64
	65	spinlock_t lock;
	66	};
	67
bd0b9ac4	68	static void jz4740_adc_irq_demux(struct irq_desc *desc)
91f4debf	69	{
914e6d4e	70	struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
91f4debf LPC	71	uint8_t status;
	72	unsigned int i;
	73
914e6d4e	74	status = readb(gc->reg_base + JZ_REG_ADC_STATUS);
91f4debf LPC	75
	76	for (i = 0; i < 5; ++i) {
	77	if (status & BIT(i))
914e6d4e	78	generic_handle_irq(gc->irq_base + i);
91f4debf LPC	79	}
	80	}
	81
	82
	83	/* Refcounting for the ADC clock is done in here instead of in the clock
	84	* framework, because it is the only clock which is shared between multiple
	85	* devices and thus is the only clock which needs refcounting */
	86	static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
	87	{
	88	if (atomic_inc_return(&adc->clk_ref) == 1)
404d5df4	89	clk_prepare_enable(adc->clk);
91f4debf LPC	90	}
	91
	92	static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
	93	{
	94	if (atomic_dec_return(&adc->clk_ref) == 0)
404d5df4	95	clk_disable_unprepare(adc->clk);
91f4debf LPC	96	}
	97
	98	static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
	99	bool enabled)
	100	{
	101	unsigned long flags;
	102	uint8_t val;
	103
	104	spin_lock_irqsave(&adc->lock, flags);
	105
	106	val = readb(adc->base + JZ_REG_ADC_ENABLE);
	107	if (enabled)
	108	val \|= BIT(engine);
	109	else
f9c28019	110	val &= ~BIT(engine);
91f4debf LPC	111	writeb(val, adc->base + JZ_REG_ADC_ENABLE);
	112
	113	spin_unlock_irqrestore(&adc->lock, flags);
	114	}
	115
	116	static int jz4740_adc_cell_enable(struct platform_device *pdev)
	117	{
	118	struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
	119
	120	jz4740_adc_clk_enable(adc);
	121	jz4740_adc_set_enabled(adc, pdev->id, true);
	122
	123	return 0;
	124	}
	125
	126	static int jz4740_adc_cell_disable(struct platform_device *pdev)
	127	{
	128	struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
	129
	130	jz4740_adc_set_enabled(adc, pdev->id, false);
	131	jz4740_adc_clk_disable(adc);
	132
	133	return 0;
	134	}
	135
	136	int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
	137	{
	138	struct jz4740_adc *adc = dev_get_drvdata(dev);
	139	unsigned long flags;
	140	uint32_t cfg;
	141
	142	if (!adc)
	143	return -ENODEV;
	144
	145	spin_lock_irqsave(&adc->lock, flags);
	146
	147	cfg = readl(adc->base + JZ_REG_ADC_CFG);
	148
	149	cfg &= ~mask;
	150	cfg \|= val;
	151
	152	writel(cfg, adc->base + JZ_REG_ADC_CFG);
	153
	154	spin_unlock_irqrestore(&adc->lock, flags);
	155
	156	return 0;
	157	}
	158	EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
	159
	160	static struct resource jz4740_hwmon_resources[] = {
	161	{
	162	.start = JZ_ADC_IRQ_ADCIN,
	163	.flags = IORESOURCE_IRQ,
	164	},
	165	{
	166	.start = JZ_REG_ADC_HWMON_BASE,
	167	.end = JZ_REG_ADC_HWMON_BASE + 3,
	168	.flags = IORESOURCE_MEM,
	169	},
	170	};
	171
	172	static struct resource jz4740_battery_resources[] = {
	173	{
	174	.start = JZ_ADC_IRQ_BATTERY,
175	.flags = IORESOURCE_IRQ,
176	},
177	{
178	.start = JZ_REG_ADC_BATTERY_BASE,
179	.end = JZ_REG_ADC_BATTERY_BASE + 3,
180	.flags = IORESOURCE_MEM,
181	},
182	};
183
5ac98553	184	static const struct mfd_cell jz4740_adc_cells[] = {
91f4debf LPC	185	{
	186	.id = 0,
	187	.name = "jz4740-hwmon",
	188	.num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
	189	.resources = jz4740_hwmon_resources,
91f4debf LPC	190
	191	.enable = jz4740_adc_cell_enable,
	192	.disable = jz4740_adc_cell_disable,
	193	},
	194	{
	195	.id = 1,
	196	.name = "jz4740-battery",
	197	.num_resources = ARRAY_SIZE(jz4740_battery_resources),
	198	.resources = jz4740_battery_resources,
91f4debf LPC	199
	200	.enable = jz4740_adc_cell_enable,
	201	.disable = jz4740_adc_cell_disable,
	202	},
	203	};
	204
f791be49	205	static int jz4740_adc_probe(struct platform_device *pdev)
91f4debf	206	{
914e6d4e LPC	207	struct irq_chip_generic *gc;
914e6d4e LPC	208	struct irq_chip_type *ct;
91f4debf LPC	209	struct jz4740_adc *adc;
91f4debf LPC	210	struct resource *mem_base;
914e6d4e LPC	211	int ret;
914e6d4e LPC	212	int irq_base;
91f4debf	213
931cbaf3	214	adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL);
17963b54	215	if (!adc)
789133b7	216	return -ENOMEM;
91f4debf LPC	217
	218	adc->irq = platform_get_irq(pdev, 0);
	219	if (adc->irq < 0) {
	220	ret = adc->irq;
	221	dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
931cbaf3	222	return ret;
91f4debf LPC	223	}
91f4debf LPC	224
914e6d4e LPC	225	irq_base = platform_get_irq(pdev, 1);
914e6d4e LPC	226	if (irq_base < 0) {
931cbaf3 DN	227	dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base);
931cbaf3 DN	228	return irq_base;
91f4debf LPC	229	}
	230
	231	mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	232	if (!mem_base) {
91f4debf	233	dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
931cbaf3	234	return -ENOENT;
91f4debf LPC	235	}
	236
	237	/* Only request the shared registers for the MFD driver */
	238	adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
	239	pdev->name);
	240	if (!adc->mem) {
91f4debf	241	dev_err(&pdev->dev, "Failed to request mmio memory region\n");
931cbaf3	242	return -EBUSY;
91f4debf LPC	243	}
	244
	245	adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
	246	if (!adc->base) {
	247	ret = -EBUSY;
	248	dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
	249	goto err_release_mem_region;
	250	}
	251
	252	adc->clk = clk_get(&pdev->dev, "adc");
	253	if (IS_ERR(adc->clk)) {
	254	ret = PTR_ERR(adc->clk);
	255	dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
	256	goto err_iounmap;
	257	}
	258
	259	spin_lock_init(&adc->lock);
	260	atomic_set(&adc->clk_ref, 0);
	261
	262	platform_set_drvdata(pdev, adc);
	263
914e6d4e LPC	264	gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base,
	265	handle_level_irq);
	266
	267	ct = gc->chip_types;
	268	ct->regs.mask = JZ_REG_ADC_CTRL;
	269	ct->regs.ack = JZ_REG_ADC_STATUS;
	270	ct->chip.irq_mask = irq_gc_mask_set_bit;
	271	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
6fcb8a3a	272	ct->chip.irq_ack = irq_gc_ack_set_bit;
914e6d4e	273
5a688c45 MR	274	irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0,
5a688c45 MR	275	IRQ_NOPROBE \| IRQ_LEVEL);
914e6d4e LPC	276
914e6d4e LPC	277	adc->gc = gc;
91f4debf	278
59fa909e	279	irq_set_chained_handler_and_data(adc->irq, jz4740_adc_irq_demux, gc);
91f4debf LPC	280
	281	writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
	282	writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
	283
48736c80	284	ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
0848c94f MB	285	ARRAY_SIZE(jz4740_adc_cells), mem_base,
0848c94f MB	286	irq_base, NULL);
48736c80 AL	287	if (ret < 0)
48736c80 AL	288	goto err_clk_put;
91f4debf	289
48736c80 AL	290	return 0;
	291
	292	err_clk_put:
	293	clk_put(adc->clk);
91f4debf	294	err_iounmap:
91f4debf LPC	295	iounmap(adc->base);
	296	err_release_mem_region:
	297	release_mem_region(adc->mem->start, resource_size(adc->mem));
91f4debf LPC	298	return ret;
	299	}
	300
4740f73f	301	static int jz4740_adc_remove(struct platform_device *pdev)
91f4debf LPC	302	{
	303	struct jz4740_adc *adc = platform_get_drvdata(pdev);
	304
	305	mfd_remove_devices(&pdev->dev);
	306
914e6d4e LPC	307	irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE \| IRQ_LEVEL, 0);
914e6d4e LPC	308	kfree(adc->gc);
59fa909e	309	irq_set_chained_handler_and_data(adc->irq, NULL, NULL);
91f4debf LPC	310
	311	iounmap(adc->base);
	312	release_mem_region(adc->mem->start, resource_size(adc->mem));
	313
	314	clk_put(adc->clk);
	315
91f4debf LPC	316	return 0;
	317	}
	318
429c9ecc	319	static struct platform_driver jz4740_adc_driver = {
91f4debf	320	.probe = jz4740_adc_probe,
84449216	321	.remove = jz4740_adc_remove,
91f4debf LPC	322	.driver = {
91f4debf LPC	323	.name = "jz4740-adc",
91f4debf LPC	324	},
	325	};
	326
65349d60	327	module_platform_driver(jz4740_adc_driver);
91f4debf LPC	328
	329	MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
	330	MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
	331	MODULE_LICENSE("GPL");
	332	MODULE_ALIAS("platform:jz4740-adc");