[linux.git] / drivers / phy / phy-berlin-sata.c

/*
 * Marvell Berlin SATA PHY driver
 *
 * Copyright (C) 2014 Marvell Technology Group Ltd.
 *
 * Antoine Ténart <[email protected]>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/io.h>
#include <linux/platform_device.h>

#define HOST_VSA_ADDR		0x0
#define HOST_VSA_DATA		0x4
#define PORT_SCR_CTL		0x2c
#define PORT_VSR_ADDR		0x78
#define PORT_VSR_DATA		0x7c

#define CONTROL_REGISTER	0x0
#define MBUS_SIZE_CONTROL	0x4

#define POWER_DOWN_PHY0			BIT(6)
#define POWER_DOWN_PHY1			BIT(14)
#define MBUS_WRITE_REQUEST_SIZE_128	(BIT(2) << 16)
#define MBUS_READ_REQUEST_SIZE_128	(BIT(2) << 19)

#define BG2_PHY_BASE		0x080
#define BG2Q_PHY_BASE		0x200

/* register 0x01 */
#define REF_FREF_SEL_25		BIT(0)
#define PHY_MODE_SATA		(0x0 << 5)

/* register 0x02 */
#define USE_MAX_PLL_RATE	BIT(12)

/* register 0x23 */
#define DATA_BIT_WIDTH_10	(0x0 << 10)
#define DATA_BIT_WIDTH_20	(0x1 << 10)
#define DATA_BIT_WIDTH_40	(0x2 << 10)

/* register 0x25 */
#define PHY_GEN_MAX_1_5		(0x0 << 10)
#define PHY_GEN_MAX_3_0		(0x1 << 10)
#define PHY_GEN_MAX_6_0		(0x2 << 10)

struct phy_berlin_desc {
	struct phy	*phy;
	u32		power_bit;
	unsigned	index;
};

struct phy_berlin_priv {
	void __iomem		*base;
	spinlock_t		lock;
	struct clk		*clk;
	struct phy_berlin_desc	**phys;
	unsigned		nphys;
	u32			phy_base;
};

static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
			       u32 phy_base, u32 reg, u32 mask, u32 val)
{
	u32 regval;

	/* select register */
	writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);

	/* set bits */
	regval = readl(ctrl_reg + PORT_VSR_DATA);
	regval &= ~mask;
	regval |= val;
	writel(regval, ctrl_reg + PORT_VSR_DATA);
}

static int phy_berlin_sata_power_on(struct phy *phy)
{
	struct phy_berlin_desc *desc = phy_get_drvdata(phy);
	struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
	void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
	int ret = 0;
	u32 regval;

	clk_prepare_enable(priv->clk);

	spin_lock(&priv->lock);

	/* Power on PHY */
	writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
	regval = readl(priv->base + HOST_VSA_DATA);
	regval &= ~desc->power_bit;
	writel(regval, priv->base + HOST_VSA_DATA);

	/* Configure MBus */
	writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
	regval = readl(priv->base + HOST_VSA_DATA);
	regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
	writel(regval, priv->base + HOST_VSA_DATA);

	/* set PHY mode and ref freq to 25 MHz */
	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
				    0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);

	/* set PHY up to 6 Gbps */
	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
				    0x0c00, PHY_GEN_MAX_6_0);

	/* set 40 bits width */
	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
				    0x0c00, DATA_BIT_WIDTH_40);

	/* use max pll rate */
	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
				    0x0000, USE_MAX_PLL_RATE);

	/* set Gen3 controller speed */
	regval = readl(ctrl_reg + PORT_SCR_CTL);
	regval &= ~GENMASK(7, 4);
	regval |= 0x30;
	writel(regval, ctrl_reg + PORT_SCR_CTL);

	spin_unlock(&priv->lock);

	clk_disable_unprepare(priv->clk);

	return ret;
}

static int phy_berlin_sata_power_off(struct phy *phy)
{
	struct phy_berlin_desc *desc = phy_get_drvdata(phy);
	struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
	u32 regval;

	clk_prepare_enable(priv->clk);

	spin_lock(&priv->lock);

	/* Power down PHY */
	writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
	regval = readl(priv->base + HOST_VSA_DATA);
	regval |= desc->power_bit;
	writel(regval, priv->base + HOST_VSA_DATA);

	spin_unlock(&priv->lock);

	clk_disable_unprepare(priv->clk);

	return 0;
}

static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
					     struct of_phandle_args *args)
{
	struct phy_berlin_priv *priv = dev_get_drvdata(dev);
	int i;

	if (WARN_ON(args->args[0] >= priv->nphys))
		return ERR_PTR(-ENODEV);

	for (i = 0; i < priv->nphys; i++) {
		if (priv->phys[i]->index == args->args[0])
			break;
	}

	if (i == priv->nphys)
		return ERR_PTR(-ENODEV);

	return priv->phys[i]->phy;
}

static struct phy_ops phy_berlin_sata_ops = {
	.power_on	= phy_berlin_sata_power_on,
	.power_off	= phy_berlin_sata_power_off,
	.owner		= THIS_MODULE,
};

static u32 phy_berlin_power_down_bits[] = {
	POWER_DOWN_PHY0,
	POWER_DOWN_PHY1,
};

static int phy_berlin_sata_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *child;
	struct phy *phy;
	struct phy_provider *phy_provider;
	struct phy_berlin_priv *priv;
	struct resource *res;
	int i = 0;
	u32 phy_id;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;

	priv->base = devm_ioremap(dev, res->start, resource_size(res));
	if (!priv->base)
		return -ENOMEM;

	priv->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(priv->clk))
		return PTR_ERR(priv->clk);

	priv->nphys = of_get_child_count(dev->of_node);
	if (priv->nphys == 0)
		return -ENODEV;

	priv->phys = devm_kzalloc(dev, priv->nphys * sizeof(*priv->phys),
				  GFP_KERNEL);
	if (!priv->phys)
		return -ENOMEM;

	if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
		priv->phy_base = BG2_PHY_BASE;
	else
		priv->phy_base = BG2Q_PHY_BASE;

	dev_set_drvdata(dev, priv);
	spin_lock_init(&priv->lock);

	for_each_available_child_of_node(dev->of_node, child) {
		struct phy_berlin_desc *phy_desc;

		if (of_property_read_u32(child, "reg", &phy_id)) {
			dev_err(dev, "missing reg property in node %s\n",
				child->name);
			return -EINVAL;
		}

		if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
			dev_err(dev, "invalid reg in node %s\n", child->name);
			return -EINVAL;
		}

		phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
		if (!phy_desc)
			return -ENOMEM;

		phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
		if (IS_ERR(phy)) {
			dev_err(dev, "failed to create PHY %d\n", phy_id);
			return PTR_ERR(phy);
		}

		phy_desc->phy = phy;
		phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
		phy_desc->index = phy_id;
		phy_set_drvdata(phy, phy_desc);

		priv->phys[i++] = phy_desc;

		/* Make sure the PHY is off */
		phy_berlin_sata_power_off(phy);
	}

	phy_provider =
		devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id phy_berlin_sata_of_match[] = {
	{ .compatible = "marvell,berlin2-sata-phy" },
	{ .compatible = "marvell,berlin2q-sata-phy" },
	{ },
};

static struct platform_driver phy_berlin_sata_driver = {
	.probe	= phy_berlin_sata_probe,
	.driver	= {
		.name		= "phy-berlin-sata",
		.of_match_table	= phy_berlin_sata_of_match,
	},
};
module_platform_driver(phy_berlin_sata_driver);

MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
MODULE_AUTHOR("Antoine Ténart <[email protected]>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
942a31b5 AT	1	/*
	2	* Marvell Berlin SATA PHY driver
	3	*
	4	* Copyright (C) 2014 Marvell Technology Group Ltd.
	5	*
	6	* Antoine Ténart <[email protected]>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/module.h>
	15	#include <linux/phy/phy.h>
	16	#include <linux/io.h>
	17	#include <linux/platform_device.h>
	18
	19	#define HOST_VSA_ADDR 0x0
	20	#define HOST_VSA_DATA 0x4
	21	#define PORT_SCR_CTL 0x2c
	22	#define PORT_VSR_ADDR 0x78
	23	#define PORT_VSR_DATA 0x7c
	24
	25	#define CONTROL_REGISTER 0x0
	26	#define MBUS_SIZE_CONTROL 0x4
	27
	28	#define POWER_DOWN_PHY0 BIT(6)
	29	#define POWER_DOWN_PHY1 BIT(14)
	30	#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
	31	#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
	32
8203f8b4	33	#define BG2_PHY_BASE 0x080
a98d41d6	34	#define BG2Q_PHY_BASE 0x200
942a31b5 AT	35
	36	/* register 0x01 */
	37	#define REF_FREF_SEL_25 BIT(0)
	38	#define PHY_MODE_SATA (0x0 << 5)
	39
	40	/* register 0x02 */
	41	#define USE_MAX_PLL_RATE BIT(12)
	42
	43	/* register 0x23 */
	44	#define DATA_BIT_WIDTH_10 (0x0 << 10)
	45	#define DATA_BIT_WIDTH_20 (0x1 << 10)
	46	#define DATA_BIT_WIDTH_40 (0x2 << 10)
	47
	48	/* register 0x25 */
	49	#define PHY_GEN_MAX_1_5 (0x0 << 10)
	50	#define PHY_GEN_MAX_3_0 (0x1 << 10)
	51	#define PHY_GEN_MAX_6_0 (0x2 << 10)
	52
	53	struct phy_berlin_desc {
	54	struct phy *phy;
	55	u32 power_bit;
	56	unsigned index;
	57	};
	58
	59	struct phy_berlin_priv {
	60	void __iomem *base;
	61	spinlock_t lock;
	62	struct clk *clk;
	63	struct phy_berlin_desc **phys;
	64	unsigned nphys;
a98d41d6	65	u32 phy_base;
942a31b5 AT	66	};
942a31b5 AT	67
a98d41d6 SH	68	static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
a98d41d6 SH	69	u32 phy_base, u32 reg, u32 mask, u32 val)
942a31b5 AT	70	{
	71	u32 regval;
	72
	73	/* select register */
a98d41d6	74	writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
942a31b5 AT	75
	76	/* set bits */
	77	regval = readl(ctrl_reg + PORT_VSR_DATA);
	78	regval &= ~mask;
	79	regval \|= val;
	80	writel(regval, ctrl_reg + PORT_VSR_DATA);
	81	}
	82
	83	static int phy_berlin_sata_power_on(struct phy *phy)
	84	{
	85	struct phy_berlin_desc *desc = phy_get_drvdata(phy);
	86	struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
	87	void __iomem ctrl_reg = priv->base + 0x60 + (desc->index 0x80);
	88	int ret = 0;
	89	u32 regval;
	90
	91	clk_prepare_enable(priv->clk);
	92
	93	spin_lock(&priv->lock);
	94
	95	/* Power on PHY */
	96	writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
	97	regval = readl(priv->base + HOST_VSA_DATA);
	98	regval &= ~desc->power_bit;
	99	writel(regval, priv->base + HOST_VSA_DATA);
	100
	101	/* Configure MBus */
	102	writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
	103	regval = readl(priv->base + HOST_VSA_DATA);
	104	regval \|= MBUS_WRITE_REQUEST_SIZE_128 \| MBUS_READ_REQUEST_SIZE_128;
	105	writel(regval, priv->base + HOST_VSA_DATA);
	106
	107	/* set PHY mode and ref freq to 25 MHz */
a98d41d6 SH	108	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
a98d41d6 SH	109	0x00ff, REF_FREF_SEL_25 \| PHY_MODE_SATA);
942a31b5 AT	110
942a31b5 AT	111	/* set PHY up to 6 Gbps */
a98d41d6 SH	112	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
a98d41d6 SH	113	0x0c00, PHY_GEN_MAX_6_0);
942a31b5 AT	114
942a31b5 AT	115	/* set 40 bits width */
a98d41d6 SH	116	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
a98d41d6 SH	117	0x0c00, DATA_BIT_WIDTH_40);
942a31b5 AT	118
942a31b5 AT	119	/* use max pll rate */
a98d41d6 SH	120	phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
a98d41d6 SH	121	0x0000, USE_MAX_PLL_RATE);
942a31b5 AT	122
	123	/* set Gen3 controller speed */
	124	regval = readl(ctrl_reg + PORT_SCR_CTL);
	125	regval &= ~GENMASK(7, 4);
	126	regval \|= 0x30;
	127	writel(regval, ctrl_reg + PORT_SCR_CTL);
	128
	129	spin_unlock(&priv->lock);
	130
	131	clk_disable_unprepare(priv->clk);
	132
	133	return ret;
	134	}
	135
	136	static int phy_berlin_sata_power_off(struct phy *phy)
	137	{
	138	struct phy_berlin_desc *desc = phy_get_drvdata(phy);
	139	struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
	140	u32 regval;
	141
	142	clk_prepare_enable(priv->clk);
	143
	144	spin_lock(&priv->lock);
	145
	146	/* Power down PHY */
	147	writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
	148	regval = readl(priv->base + HOST_VSA_DATA);
	149	regval \|= desc->power_bit;
	150	writel(regval, priv->base + HOST_VSA_DATA);
	151
	152	spin_unlock(&priv->lock);
	153
	154	clk_disable_unprepare(priv->clk);
	155
	156	return 0;
	157	}
	158
	159	static struct phy phy_berlin_sata_phy_xlate(struct device dev,
	160	struct of_phandle_args *args)
	161	{
	162	struct phy_berlin_priv *priv = dev_get_drvdata(dev);
	163	int i;
	164
	165	if (WARN_ON(args->args[0] >= priv->nphys))
	166	return ERR_PTR(-ENODEV);
	167
	168	for (i = 0; i < priv->nphys; i++) {
	169	if (priv->phys[i]->index == args->args[0])
	170	break;
	171	}
	172
	173	if (i == priv->nphys)
	174	return ERR_PTR(-ENODEV);
	175
	176	return priv->phys[i]->phy;
	177	}
	178
	179	static struct phy_ops phy_berlin_sata_ops = {
	180	.power_on = phy_berlin_sata_power_on,
	181	.power_off = phy_berlin_sata_power_off,
	182	.owner = THIS_MODULE,
	183	};
	184
	185	static u32 phy_berlin_power_down_bits[] = {
186	POWER_DOWN_PHY0,
187	POWER_DOWN_PHY1,
188	};
189
190	static int phy_berlin_sata_probe(struct platform_device *pdev)
191	{
192	struct device *dev = &pdev->dev;
193	struct device_node *child;
194	struct phy *phy;
195	struct phy_provider *phy_provider;
196	struct phy_berlin_priv *priv;
197	struct resource *res;
198	int i = 0;
199	u32 phy_id;
200
201	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
202	if (!priv)
203	return -ENOMEM;
204
205	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
206	if (!res)
207	return -EINVAL;
208
209	priv->base = devm_ioremap(dev, res->start, resource_size(res));
210	if (!priv->base)
211	return -ENOMEM;
212
213	priv->clk = devm_clk_get(dev, NULL);
214	if (IS_ERR(priv->clk))
215	return PTR_ERR(priv->clk);
216
217	priv->nphys = of_get_child_count(dev->of_node);
218	if (priv->nphys == 0)
219	return -ENODEV;
220
221	priv->phys = devm_kzalloc(dev, priv->nphys * sizeof(*priv->phys),
222	GFP_KERNEL);
223	if (!priv->phys)
224	return -ENOMEM;
225
8203f8b4 SH	226	if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
	227	priv->phy_base = BG2_PHY_BASE;
	228	else
	229	priv->phy_base = BG2Q_PHY_BASE;
a98d41d6	230
942a31b5 AT	231	dev_set_drvdata(dev, priv);
	232	spin_lock_init(&priv->lock);
	233
	234	for_each_available_child_of_node(dev->of_node, child) {
	235	struct phy_berlin_desc *phy_desc;
	236
	237	if (of_property_read_u32(child, "reg", &phy_id)) {
	238	dev_err(dev, "missing reg property in node %s\n",
	239	child->name);
	240	return -EINVAL;
	241	}
	242
	243	if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
	244	dev_err(dev, "invalid reg in node %s\n", child->name);
	245	return -EINVAL;
	246	}
	247
	248	phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
	249	if (!phy_desc)
	250	return -ENOMEM;
	251
dbc98635	252	phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
942a31b5 AT	253	if (IS_ERR(phy)) {
	254	dev_err(dev, "failed to create PHY %d\n", phy_id);
	255	return PTR_ERR(phy);
	256	}
	257
	258	phy_desc->phy = phy;
	259	phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
	260	phy_desc->index = phy_id;
	261	phy_set_drvdata(phy, phy_desc);
	262
	263	priv->phys[i++] = phy_desc;
	264
	265	/* Make sure the PHY is off */
	266	phy_berlin_sata_power_off(phy);
	267	}
	268
	269	phy_provider =
	270	devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
c1fc0050	271	return PTR_ERR_OR_ZERO(phy_provider);
942a31b5 AT	272	}
	273
	274	static const struct of_device_id phy_berlin_sata_of_match[] = {
8203f8b4	275	{ .compatible = "marvell,berlin2-sata-phy" },
942a31b5 AT	276	{ .compatible = "marvell,berlin2q-sata-phy" },
	277	{ },
	278	};
	279
	280	static struct platform_driver phy_berlin_sata_driver = {
	281	.probe = phy_berlin_sata_probe,
	282	.driver = {
	283	.name = "phy-berlin-sata",
942a31b5 AT	284	.of_match_table = phy_berlin_sata_of_match,
	285	},
	286	};
	287	module_platform_driver(phy_berlin_sata_driver);
	288
	289	MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
	290	MODULE_AUTHOR("Antoine Ténart <[email protected]>");
	291	MODULE_LICENSE("GPL v2");