[linux.git] / include / asm-xtensa / elf.h

/*
 * include/asm-xtensa/elf.h
 *
 * ELF register definitions
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2001 - 2005 Tensilica Inc.
 */

#ifndef _XTENSA_ELF_H
#define _XTENSA_ELF_H

#include <asm/ptrace.h>
#include <asm/coprocessor.h>
#include <xtensa/config/core.h>

/* Xtensa processor ELF architecture-magic number */

#define EM_XTENSA	94
#define EM_XTENSA_OLD	0xABC7

/* ELF register definitions. This is needed for core dump support.  */

/*
 * elf_gregset_t contains the application-level state in the following order:
 * Processor info: 	config_version, cpuxy
 * Processor state:	pc, ps, exccause, excvaddr, wb, ws,
 *			lbeg, lend, lcount, sar
 * GP regs:		ar0 - arXX
 */

typedef unsigned long elf_greg_t;

typedef struct {
	elf_greg_t xchal_config_id0;
	elf_greg_t xchal_config_id1;
	elf_greg_t cpux;
	elf_greg_t cpuy;
	elf_greg_t pc;
	elf_greg_t ps;
	elf_greg_t exccause;
	elf_greg_t excvaddr;
	elf_greg_t windowbase;
	elf_greg_t windowstart;
	elf_greg_t lbeg;
	elf_greg_t lend;
	elf_greg_t lcount;
	elf_greg_t sar;
	elf_greg_t syscall;
	elf_greg_t ar[XCHAL_NUM_AREGS];
} xtensa_gregset_t;

#define ELF_NGREG	(sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))

typedef elf_greg_t elf_gregset_t[ELF_NGREG];

/*
 *  Compute the size of the coprocessor and extra state layout (register info)
 *  table (in bytes).
 *  This is actually the maximum size of the table, as opposed to the size,
 *  which is available from the _xtensa_reginfo_table_size global variable.
 *
 *  (See also arch/xtensa/kernel/coprocessor.S)
 *
 */

#ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
# define XTENSA_CPE_LTABLE_SIZE		0
#else
# define XTENSA_CPE_SEGMENT(num)	(num ? (1+num) : 0)
# define XTENSA_CPE_LTABLE_ENTRIES	\
		( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM)	\
		+ XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM)	\
		+ 1		/* final entry */			\
		)
# define XTENSA_CPE_LTABLE_SIZE		(XTENSA_CPE_LTABLE_ENTRIES * 8)
#endif


/*
 * Instantiations of the elf_fpregset_t type contain, in most
 * architectures, the floating point (FPU) register set.
 * For Xtensa, this type is extended to contain all custom state,
 * ie. coprocessor and "extra" (non-coprocessor) state (including,
 * for example, TIE-defined states and register files; as well
 * as other optional processor state).
 * This includes FPU state if a floating-point coprocessor happens
 * to have been configured within the Xtensa processor.
 *
 * TOTAL_FPREGS_SIZE is the required size (without rounding)
 * of elf_fpregset_t.  It provides space for the following:
 *
 *  a)	32-bit mask of active coprocessors for this task (similar
 *	to CPENABLE in single-threaded Xtensa processor systems)
 *
 *  b)	table describing the layout of custom states (ie. of
 *      individual registers, etc) within the save areas
 *
 *  c)  save areas for each coprocessor and for non-coprocessor
 *      ("extra") state
 *
 * Note that save areas may require up to 16-byte alignment when
 * accessed by save/restore sequences.  We do not need to ensure
 * such alignment in an elf_fpregset_t structure because custom
 * state is not directly loaded/stored into it; rather, save area
 * contents are copied to elf_fpregset_t from the active save areas
 * (see 'struct task_struct' definition in processor.h for that)
 * using memcpy().  But we do allow space for such alignment,
 * to allow optimizations of layout and copying.
 */

#define TOTAL_FPREGS_SIZE						\
  	(4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
#define ELF_NFPREG							\
	((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))

typedef unsigned int elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];

#define ELF_CORE_COPY_REGS(_eregs, _pregs) 				\
	xtensa_elf_core_copy_regs (&_eregs, _pregs);

extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);

/*
 * This is used to ensure we don't load something for the wrong architecture.
 */

#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA )  || \
			    ( (x)->e_machine == EM_XTENSA_OLD ) )

/*
 * These are used to set parameters in the core dumps.
 */

#ifdef __XTENSA_EL__
# define ELF_DATA	ELFDATA2LSB
#elif defined(__XTENSA_EB__)
# define ELF_DATA	ELFDATA2MSB
#else
# error processor byte order undefined!
#endif

#define ELF_CLASS	ELFCLASS32
#define ELF_ARCH	EM_XTENSA

#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE	PAGE_SIZE

/*
 * This is the location that an ET_DYN program is loaded if exec'ed.  Typical
 * use of this is to invoke "./ld.so someprog" to test out a new version of
 * the loader.  We need to make sure that it is out of the way of the program
 * that it will "exec", and that there is sufficient room for the brk.
 */

#define ELF_ET_DYN_BASE         (2 * TASK_SIZE / 3)

/*
 * This yields a mask that user programs can use to figure out what
 * instruction set this CPU supports.  This could be done in user space,
 * but it's not easy, and we've already done it here.
 */

#define ELF_HWCAP	(0)

/*
 * This yields a string that ld.so will use to load implementation
 * specific libraries for optimization.  This is more specific in
 * intent than poking at uname or /proc/cpuinfo.
 * For the moment, we have only optimizations for the Intel generations,
 * but that could change...
 */

#define ELF_PLATFORM  (NULL)

/*
 * The Xtensa processor ABI says that when the program starts, a2
 * contains a pointer to a function which might be registered using
 * `atexit'.  This provides a mean for the dynamic linker to call
 * DT_FINI functions for shared libraries that have been loaded before
 * the code runs.
 *
 * A value of 0 tells we have no such handler.
 *
 * We might as well make sure everything else is cleared too (except
 * for the stack pointer in a1), just to make things more
 * deterministic.  Also, clearing a0 terminates debugger backtraces.
 */

#define ELF_PLAT_INIT(_r, load_addr) \
  do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0;  _r->areg[3]=0;  \
       _r->areg[4]=0;  _r->areg[5]=0;    _r->areg[6]=0;  _r->areg[7]=0;  \
       _r->areg[8]=0;  _r->areg[9]=0;    _r->areg[10]=0; _r->areg[11]=0; \
       _r->areg[12]=0; _r->areg[13]=0;   _r->areg[14]=0; _r->areg[15]=0; \
  } while (0)

#ifdef __KERNEL__

#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)

struct task_struct;

extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*,
			  struct task_struct*);
extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*,
			     struct task_struct*);
extern void do_save_fpregs (elf_fpregset_t*, struct pt_regs*,
			    struct task_struct*);
extern int do_restore_fpregs (elf_fpregset_t*, struct pt_regs*,
			      struct task_struct*);

#endif	/* __KERNEL__ */
#endif	/* _XTENSA_ELF_H */
Commit	Line	Data
9a8fd558 CZ	1	/*
	2	* include/asm-xtensa/elf.h
	3	*
	4	* ELF register definitions
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*
	10	* Copyright (C) 2001 - 2005 Tensilica Inc.
	11	*/
	12
	13	#ifndef _XTENSA_ELF_H
	14	#define _XTENSA_ELF_H
	15
	16	#include <asm/ptrace.h>
	17	#include <asm/coprocessor.h>
	18	#include <xtensa/config/core.h>
	19
	20	/* Xtensa processor ELF architecture-magic number */
	21
	22	#define EM_XTENSA 94
	23	#define EM_XTENSA_OLD 0xABC7
	24
	25	/* ELF register definitions. This is needed for core dump support. */
	26
	27	/*
	28	* elf_gregset_t contains the application-level state in the following order:
	29	* Processor info: config_version, cpuxy
	30	* Processor state: pc, ps, exccause, excvaddr, wb, ws,
	31	* lbeg, lend, lcount, sar
	32	* GP regs: ar0 - arXX
	33	*/
	34
	35	typedef unsigned long elf_greg_t;
	36
	37	typedef struct {
	38	elf_greg_t xchal_config_id0;
	39	elf_greg_t xchal_config_id1;
	40	elf_greg_t cpux;
	41	elf_greg_t cpuy;
	42	elf_greg_t pc;
	43	elf_greg_t ps;
	44	elf_greg_t exccause;
	45	elf_greg_t excvaddr;
	46	elf_greg_t windowbase;
	47	elf_greg_t windowstart;
	48	elf_greg_t lbeg;
	49	elf_greg_t lend;
	50	elf_greg_t lcount;
	51	elf_greg_t sar;
	52	elf_greg_t syscall;
	53	elf_greg_t ar[XCHAL_NUM_AREGS];
	54	} xtensa_gregset_t;
	55
	56	#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
	57
	58	typedef elf_greg_t elf_gregset_t[ELF_NGREG];
	59
	60	/*
	61	* Compute the size of the coprocessor and extra state layout (register info)
	62	* table (in bytes).
	63	* This is actually the maximum size of the table, as opposed to the size,
	64	* which is available from the _xtensa_reginfo_table_size global variable.
65	*
66	* (See also arch/xtensa/kernel/coprocessor.S)
67	*
68	*/
69
70	#ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
71	# define XTENSA_CPE_LTABLE_SIZE 0
72	#else
73	# define XTENSA_CPE_SEGMENT(num) (num ? (1+num) : 0)
74	# define XTENSA_CPE_LTABLE_ENTRIES \
75	( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \
76	+ XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM) \
77	+ XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM) \
78	+ XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM) \
79	+ XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM) \
80	+ XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM) \
81	+ XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM) \
82	+ XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM) \
83	+ XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM) \
84	+ 1 /* final entry */ \
85	)
86	# define XTENSA_CPE_LTABLE_SIZE (XTENSA_CPE_LTABLE_ENTRIES * 8)
87	#endif
88
89
90	/*
91	* Instantiations of the elf_fpregset_t type contain, in most
92	* architectures, the floating point (FPU) register set.
93	* For Xtensa, this type is extended to contain all custom state,
94	* ie. coprocessor and "extra" (non-coprocessor) state (including,
95	* for example, TIE-defined states and register files; as well
96	* as other optional processor state).
97	* This includes FPU state if a floating-point coprocessor happens
98	* to have been configured within the Xtensa processor.
99	*
100	* TOTAL_FPREGS_SIZE is the required size (without rounding)
101	* of elf_fpregset_t. It provides space for the following:
102	*
103	* a) 32-bit mask of active coprocessors for this task (similar
104	* to CPENABLE in single-threaded Xtensa processor systems)
105	*
106	* b) table describing the layout of custom states (ie. of
107	* individual registers, etc) within the save areas
108	*
109	* c) save areas for each coprocessor and for non-coprocessor
110	* ("extra") state
111	*
112	* Note that save areas may require up to 16-byte alignment when
113	* accessed by save/restore sequences. We do not need to ensure
114	* such alignment in an elf_fpregset_t structure because custom
115	* state is not directly loaded/stored into it; rather, save area
116	* contents are copied to elf_fpregset_t from the active save areas
117	* (see 'struct task_struct' definition in processor.h for that)
118	* using memcpy(). But we do allow space for such alignment,
119	* to allow optimizations of layout and copying.
120	*/
121
122	#define TOTAL_FPREGS_SIZE \
123	(4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
124	#define ELF_NFPREG \
125	((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
126
127	typedef unsigned int elf_fpreg_t;
128	typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
129
130	#define ELF_CORE_COPY_REGS(_eregs, _pregs) \
131	xtensa_elf_core_copy_regs (&_eregs, _pregs);
132
133	extern void xtensa_elf_core_copy_regs (xtensa_gregset_t , struct pt_regs );
134
135	/*
136	* This is used to ensure we don't load something for the wrong architecture.
137	*/
138
139	#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA ) \|\| \
140	( (x)->e_machine == EM_XTENSA_OLD ) )
141
142	/*
143	* These are used to set parameters in the core dumps.
144	*/
145
146	#ifdef __XTENSA_EL__
147	# define ELF_DATA ELFDATA2LSB
148	#elif defined(__XTENSA_EB__)
149	# define ELF_DATA ELFDATA2MSB
150	#else
151	# error processor byte order undefined!
152	#endif
153
154	#define ELF_CLASS ELFCLASS32
155	#define ELF_ARCH EM_XTENSA
156
157	#define USE_ELF_CORE_DUMP
158	#define ELF_EXEC_PAGESIZE PAGE_SIZE
159
160	/*
161	* This is the location that an ET_DYN program is loaded if exec'ed. Typical
162	* use of this is to invoke "./ld.so someprog" to test out a new version of
163	* the loader. We need to make sure that it is out of the way of the program
164	* that it will "exec", and that there is sufficient room for the brk.
165	*/
166
167	#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
168
169	/*
170	* This yields a mask that user programs can use to figure out what
171	* instruction set this CPU supports. This could be done in user space,
172	* but it's not easy, and we've already done it here.
173	*/
174
175	#define ELF_HWCAP (0)
176
177	/*
178	* This yields a string that ld.so will use to load implementation
179	* specific libraries for optimization. This is more specific in
180	* intent than poking at uname or /proc/cpuinfo.
181	* For the moment, we have only optimizations for the Intel generations,
182	* but that could change...
183	*/
184
185	#define ELF_PLATFORM (NULL)
186
187	/*
188	* The Xtensa processor ABI says that when the program starts, a2
189	* contains a pointer to a function which might be registered using
190	* `atexit'. This provides a mean for the dynamic linker to call
191	* DT_FINI functions for shared libraries that have been loaded before
192	* the code runs.
193	*
194	* A value of 0 tells we have no such handler.
195	*
196	* We might as well make sure everything else is cleared too (except
197	* for the stack pointer in a1), just to make things more
198	* deterministic. Also, clearing a0 terminates debugger backtraces.
199	*/
200
201	#define ELF_PLAT_INIT(_r, load_addr) \
202	do { _r->areg[0]=0; /_r->areg[1]=0;/ _r->areg[2]=0; _r->areg[3]=0; \
203	_r->areg[4]=0; _r->areg[5]=0; _r->areg[6]=0; _r->areg[7]=0; \
204	_r->areg[8]=0; _r->areg[9]=0; _r->areg[10]=0; _r->areg[11]=0; \
205	_r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
206	} while (0)
207
208	#ifdef __KERNEL__
209
210	#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
211
8c65b4a6 TS	212	struct task_struct;
8c65b4a6 TS	213
9a8fd558 CZ	214	extern void do_copy_regs (xtensa_gregset_t, struct pt_regs,
	215	struct task_struct*);
	216	extern void do_restore_regs (xtensa_gregset_t, struct pt_regs,
	217	struct task_struct*);
	218	extern void do_save_fpregs (elf_fpregset_t, struct pt_regs,
	219	struct task_struct*);
	220	extern int do_restore_fpregs (elf_fpregset_t, struct pt_regs,
	221	struct task_struct*);
	222
	223	#endif /* __KERNEL__ */
	224	#endif /* _XTENSA_ELF_H */