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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[linux.git] / arch / mips / dec / setup.c
CommitLineData
1da177e4 1/*
902d21d5 2 * System-specific setup, especially interrupts.
1da177e4
LT		 3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Harald Koerfgen
902d21d5 9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
1da177e4 10 */
1da177e4
LT		 11#include <linux/console.h>
12#include <linux/init.h>
902d21d5
MR		 13#include <linux/interrupt.h>
14#include <linux/ioport.h>
1da177e4 15#include <linux/module.h>
902d21d5
MR		 16#include <linux/param.h>
17#include <linux/sched.h>
1da177e4
LT		 18#include <linux/spinlock.h>
19#include <linux/types.h>
fcdb27ad 20#include <linux/pm.h>
ca4d3e67 21#include <linux/irq.h>
1da177e4
LT		 22
23#include <asm/bootinfo.h>
24#include <asm/cpu.h>
25#include <asm/cpu-features.h>
26#include <asm/irq.h>
27#include <asm/irq_cpu.h>
28#include <asm/mipsregs.h>
29#include <asm/reboot.h>
30#include <asm/time.h>
31#include <asm/traps.h>
32#include <asm/wbflush.h>
33
34#include <asm/dec/interrupts.h>
35#include <asm/dec/ioasic.h>
36#include <asm/dec/ioasic_addrs.h>
37#include <asm/dec/ioasic_ints.h>
38#include <asm/dec/kn01.h>
39#include <asm/dec/kn02.h>
40#include <asm/dec/kn02ba.h>
41#include <asm/dec/kn02ca.h>
42#include <asm/dec/kn03.h>
43#include <asm/dec/kn230.h>
a5fc9c0b 44#include <asm/dec/system.h>
1da177e4
LT		 45
46
47extern void dec_machine_restart(char *command);
48extern void dec_machine_halt(void);
49extern void dec_machine_power_off(void);
d62801e9 50extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
1da177e4 51
a5fc9c0b
MR		 52unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54EXPORT_SYMBOL(dec_kn_slot_base);
55EXPORT_SYMBOL(dec_kn_slot_size);
56
33cf45b9
MR		 57int dec_tc_bus;
58
68835999 59DEFINE_SPINLOCK(ioasic_ssr_lock);
1da177e4
LT		 60
61volatile u32 *ioasic_base;
a5fc9c0b
MR		 62
63EXPORT_SYMBOL(ioasic_base);
1da177e4
LT		 64
65/*
66 * IRQ routing and priority tables. Priorites are set as follows:
67 *
68 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
69 *
70 * MEMORY CPU CPU CPU ASIC CPU CPU
71 * RTC CPU CPU CPU ASIC CPU CPU
72 * DMA - - - ASIC ASIC ASIC
73 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
74 * SERIAL1 - - - ASIC - ASIC
75 * SCSI CPU CPU CSR ASIC ASIC ASIC
76 * ETHERNET CPU * CSR ASIC ASIC ASIC
77 * other - - - ASIC - -
78 * TC2 - - CSR CPU ASIC ASIC
79 * TC1 - - CSR CPU ASIC ASIC
80 * TC0 - - CSR CPU ASIC ASIC
81 * other - CPU - CPU ASIC ASIC
82 * other - - - - CPU CPU
83 *
84 * * -- shared with SCSI
85 */
86
87int dec_interrupt[DEC_NR_INTS] = {
88 [0 ... DEC_NR_INTS - 1] = -1
89};
a5fc9c0b
MR		 90
91EXPORT_SYMBOL(dec_interrupt);
92
1da177e4
LT		 93int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
94 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
95};
96int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
97 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
98};
99int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
100
101static struct irqaction ioirq = {
102 .handler = no_action,
103 .name = "cascade",
104};
105static struct irqaction fpuirq = {
106 .handler = no_action,
107 .name = "fpu",
108};
109
110static struct irqaction busirq = {
f40298fd 111 .flags = IRQF_DISABLED,
1da177e4
LT		 112 .name = "bus error",
113};
114
115static struct irqaction haltirq = {
116 .handler = dec_intr_halt,
117 .name = "halt",
118};
119
120
121/*
122 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
123 */
23bbbaf8 124static void __init dec_be_init(void)
1da177e4
LT		 125{
126 switch (mips_machtype) {
127 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
64dac503
MR		 128 board_be_handler = dec_kn01_be_handler;
129 busirq.handler = dec_kn01_be_interrupt;
f40298fd 130 busirq.flags |= IRQF_SHARED;
64dac503
MR		 131 dec_kn01_be_init();
132 break;
133 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
134 case MACH_DS5000_XX: /* DS5000/xx Maxine */
135 board_be_handler = dec_kn02xa_be_handler;
136 busirq.handler = dec_kn02xa_be_interrupt;
137 dec_kn02xa_be_init();
1da177e4
LT		 138 break;
139 case MACH_DS5000_200: /* DS5000/200 3max */
140 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
141 case MACH_DS5900: /* DS5900 bigmax */
142 board_be_handler = dec_ecc_be_handler;
143 busirq.handler = dec_ecc_be_interrupt;
144 dec_ecc_be_init();
145 break;
146 }
147}
148
2925aba4 149void __init plat_mem_setup(void)
1da177e4
LT		 150{
151 board_be_init = dec_be_init;
1da177e4
LT		 152
153 wbflush_setup();
154
155 _machine_restart = dec_machine_restart;
156 _machine_halt = dec_machine_halt;
fcdb27ad 157 pm_power_off = dec_machine_power_off;
902d21d5
MR		 158
159 ioport_resource.start = ~0UL;
160 ioport_resource.end = 0UL;
1da177e4
LT		 161}
162
1da177e4
LT		 163/*
164 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
165 * or DS3100 (aka Pmax).
166 */
167static int kn01_interrupt[DEC_NR_INTS] __initdata = {
168 [DEC_IRQ_CASCADE] = -1,
169 [DEC_IRQ_AB_RECV] = -1,
170 [DEC_IRQ_AB_XMIT] = -1,
171 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
172 [DEC_IRQ_ASC] = -1,
173 [DEC_IRQ_FLOPPY] = -1,
174 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
175 [DEC_IRQ_HALT] = -1,
176 [DEC_IRQ_ISDN] = -1,
177 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
178 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
179 [DEC_IRQ_PSU] = -1,
180 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
181 [DEC_IRQ_SCC0] = -1,
182 [DEC_IRQ_SCC1] = -1,
183 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
184 [DEC_IRQ_TC0] = -1,
185 [DEC_IRQ_TC1] = -1,
186 [DEC_IRQ_TC2] = -1,
187 [DEC_IRQ_TIMER] = -1,
188 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
189 [DEC_IRQ_ASC_MERR] = -1,
190 [DEC_IRQ_ASC_ERR] = -1,
191 [DEC_IRQ_ASC_DMA] = -1,
192 [DEC_IRQ_FLOPPY_ERR] = -1,
193 [DEC_IRQ_ISDN_ERR] = -1,
194 [DEC_IRQ_ISDN_RXDMA] = -1,
195 [DEC_IRQ_ISDN_TXDMA] = -1,
196 [DEC_IRQ_LANCE_MERR] = -1,
197 [DEC_IRQ_SCC0A_RXERR] = -1,
198 [DEC_IRQ_SCC0A_RXDMA] = -1,
199 [DEC_IRQ_SCC0A_TXERR] = -1,
200 [DEC_IRQ_SCC0A_TXDMA] = -1,
201 [DEC_IRQ_AB_RXERR] = -1,
202 [DEC_IRQ_AB_RXDMA] = -1,
203 [DEC_IRQ_AB_TXERR] = -1,
204 [DEC_IRQ_AB_TXDMA] = -1,
205 [DEC_IRQ_SCC1A_RXERR] = -1,
206 [DEC_IRQ_SCC1A_RXDMA] = -1,
207 [DEC_IRQ_SCC1A_TXERR] = -1,
208 [DEC_IRQ_SCC1A_TXDMA] = -1,
209};
210
211static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
212 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
213 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
214 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
215 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
216 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
217 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
218 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
219 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
220 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
221 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
222 { { .i = DEC_CPU_IRQ_ALL },
223 { .p = cpu_all_int } },
224};
225
23bbbaf8 226static void __init dec_init_kn01(void)
1da177e4
LT		 227{
228 /* IRQ routing. */
229 memcpy(&dec_interrupt, &kn01_interrupt,
230 sizeof(kn01_interrupt));
231
232 /* CPU IRQ priorities. */
233 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
234 sizeof(kn01_cpu_mask_nr_tbl));
235
97dcb82d 236 mips_cpu_irq_init();
1da177e4
LT		 237
238} /* dec_init_kn01 */
239
240
241/*
242 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
243 */
244static int kn230_interrupt[DEC_NR_INTS] __initdata = {
245 [DEC_IRQ_CASCADE] = -1,
246 [DEC_IRQ_AB_RECV] = -1,
247 [DEC_IRQ_AB_XMIT] = -1,
248 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
249 [DEC_IRQ_ASC] = -1,
250 [DEC_IRQ_FLOPPY] = -1,
251 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
252 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
253 [DEC_IRQ_ISDN] = -1,
254 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
255 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
256 [DEC_IRQ_PSU] = -1,
257 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
258 [DEC_IRQ_SCC0] = -1,
259 [DEC_IRQ_SCC1] = -1,
260 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
261 [DEC_IRQ_TC0] = -1,
262 [DEC_IRQ_TC1] = -1,
263 [DEC_IRQ_TC2] = -1,
264 [DEC_IRQ_TIMER] = -1,
265 [DEC_IRQ_VIDEO] = -1,
266 [DEC_IRQ_ASC_MERR] = -1,
267 [DEC_IRQ_ASC_ERR] = -1,
268 [DEC_IRQ_ASC_DMA] = -1,
269 [DEC_IRQ_FLOPPY_ERR] = -1,
270 [DEC_IRQ_ISDN_ERR] = -1,
271 [DEC_IRQ_ISDN_RXDMA] = -1,
272 [DEC_IRQ_ISDN_TXDMA] = -1,
273 [DEC_IRQ_LANCE_MERR] = -1,
274 [DEC_IRQ_SCC0A_RXERR] = -1,
275 [DEC_IRQ_SCC0A_RXDMA] = -1,
276 [DEC_IRQ_SCC0A_TXERR] = -1,
277 [DEC_IRQ_SCC0A_TXDMA] = -1,
278 [DEC_IRQ_AB_RXERR] = -1,
279 [DEC_IRQ_AB_RXDMA] = -1,
280 [DEC_IRQ_AB_TXERR] = -1,
281 [DEC_IRQ_AB_TXDMA] = -1,
282 [DEC_IRQ_SCC1A_RXERR] = -1,
283 [DEC_IRQ_SCC1A_RXDMA] = -1,
284 [DEC_IRQ_SCC1A_TXERR] = -1,
285 [DEC_IRQ_SCC1A_TXDMA] = -1,
286};
287
288static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
289 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
290 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
291 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
292 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
293 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
294 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
295 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
296 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
297 { { .i = DEC_CPU_IRQ_ALL },
298 { .p = cpu_all_int } },
299};
300
23bbbaf8 301static void __init dec_init_kn230(void)
1da177e4
LT		 302{
303 /* IRQ routing. */
304 memcpy(&dec_interrupt, &kn230_interrupt,
305 sizeof(kn230_interrupt));
306
307 /* CPU IRQ priorities. */
308 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
309 sizeof(kn230_cpu_mask_nr_tbl));
310
97dcb82d 311 mips_cpu_irq_init();
1da177e4
LT		 312
313} /* dec_init_kn230 */
314
315
316/*
317 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
318 */
319static int kn02_interrupt[DEC_NR_INTS] __initdata = {
320 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
321 [DEC_IRQ_AB_RECV] = -1,
322 [DEC_IRQ_AB_XMIT] = -1,
323 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
324 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
325 [DEC_IRQ_FLOPPY] = -1,
326 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
327 [DEC_IRQ_HALT] = -1,
328 [DEC_IRQ_ISDN] = -1,
329 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
330 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
331 [DEC_IRQ_PSU] = -1,
332 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
333 [DEC_IRQ_SCC0] = -1,
334 [DEC_IRQ_SCC1] = -1,
335 [DEC_IRQ_SII] = -1,
336 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
337 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
338 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
339 [DEC_IRQ_TIMER] = -1,
340 [DEC_IRQ_VIDEO] = -1,
341 [DEC_IRQ_ASC_MERR] = -1,
342 [DEC_IRQ_ASC_ERR] = -1,
343 [DEC_IRQ_ASC_DMA] = -1,
344 [DEC_IRQ_FLOPPY_ERR] = -1,
345 [DEC_IRQ_ISDN_ERR] = -1,
346 [DEC_IRQ_ISDN_RXDMA] = -1,
347 [DEC_IRQ_ISDN_TXDMA] = -1,
348 [DEC_IRQ_LANCE_MERR] = -1,
349 [DEC_IRQ_SCC0A_RXERR] = -1,
350 [DEC_IRQ_SCC0A_RXDMA] = -1,
351 [DEC_IRQ_SCC0A_TXERR] = -1,
352 [DEC_IRQ_SCC0A_TXDMA] = -1,
353 [DEC_IRQ_AB_RXERR] = -1,
354 [DEC_IRQ_AB_RXDMA] = -1,
355 [DEC_IRQ_AB_TXERR] = -1,
356 [DEC_IRQ_AB_TXDMA] = -1,
357 [DEC_IRQ_SCC1A_RXERR] = -1,
358 [DEC_IRQ_SCC1A_RXDMA] = -1,
359 [DEC_IRQ_SCC1A_TXERR] = -1,
360 [DEC_IRQ_SCC1A_TXDMA] = -1,
361};
362
363static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
364 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
365 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
366 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
367 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
368 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
369 { .p = kn02_io_int } },
370 { { .i = DEC_CPU_IRQ_ALL },
371 { .p = cpu_all_int } },
372};
373
374static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
375 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
376 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
377 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
378 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
379 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
380 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
381 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
382 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
383 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
384 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
385 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
386 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
387 { { .i = KN02_IRQ_ALL },
388 { .p = kn02_all_int } },
389};
390
23bbbaf8 391static void __init dec_init_kn02(void)
1da177e4
LT		 392{
393 /* IRQ routing. */
394 memcpy(&dec_interrupt, &kn02_interrupt,
395 sizeof(kn02_interrupt));
396
397 /* CPU IRQ priorities. */
398 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
399 sizeof(kn02_cpu_mask_nr_tbl));
400
401 /* KN02 CSR IRQ priorities. */
402 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
403 sizeof(kn02_asic_mask_nr_tbl));
404
97dcb82d 405 mips_cpu_irq_init();
1da177e4
LT		 406 init_kn02_irqs(KN02_IRQ_BASE);
407
408} /* dec_init_kn02 */
409
410
411/*
412 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
413 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
414 * DS5000/150, aka 4min.
415 */
416static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
417 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
418 [DEC_IRQ_AB_RECV] = -1,
419 [DEC_IRQ_AB_XMIT] = -1,
420 [DEC_IRQ_DZ11] = -1,
421 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
422 [DEC_IRQ_FLOPPY] = -1,
423 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
424 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
425 [DEC_IRQ_ISDN] = -1,
426 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
427 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
428 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
429 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
430 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
431 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
432 [DEC_IRQ_SII] = -1,
433 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
434 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
435 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
436 [DEC_IRQ_TIMER] = -1,
437 [DEC_IRQ_VIDEO] = -1,
438 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
439 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
440 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
441 [DEC_IRQ_FLOPPY_ERR] = -1,
442 [DEC_IRQ_ISDN_ERR] = -1,
443 [DEC_IRQ_ISDN_RXDMA] = -1,
444 [DEC_IRQ_ISDN_TXDMA] = -1,
445 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
446 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
447 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
448 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
449 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
450 [DEC_IRQ_AB_RXERR] = -1,
451 [DEC_IRQ_AB_RXDMA] = -1,
452 [DEC_IRQ_AB_TXERR] = -1,
453 [DEC_IRQ_AB_TXDMA] = -1,
454 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
455 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
456 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
457 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
458};
459
460static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
461 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
462 { .p = kn02xa_io_int } },
463 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
464 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
465 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
466 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
467 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
468 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
469 { { .i = DEC_CPU_IRQ_ALL },
470 { .p = cpu_all_int } },
471};
472
473static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
474 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
475 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
476 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
477 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
478 { { .i = IO_IRQ_DMA },
479 { .p = asic_dma_int } },
480 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
481 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
482 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
483 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
484 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
485 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
486 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
487 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
488 { { .i = IO_IRQ_ALL },
489 { .p = asic_all_int } },
490};
491
23bbbaf8 492static void __init dec_init_kn02ba(void)
1da177e4
LT		 493{
494 /* IRQ routing. */
495 memcpy(&dec_interrupt, &kn02ba_interrupt,
496 sizeof(kn02ba_interrupt));
497
498 /* CPU IRQ priorities. */
499 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
500 sizeof(kn02ba_cpu_mask_nr_tbl));
501
502 /* I/O ASIC IRQ priorities. */
503 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
504 sizeof(kn02ba_asic_mask_nr_tbl));
505
97dcb82d 506 mips_cpu_irq_init();
1da177e4
LT		 507 init_ioasic_irqs(IO_IRQ_BASE);
508
509} /* dec_init_kn02ba */
510
511
512/*
513 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
514 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
515 * DS5000/50, aka 4MAXine.
516 */
517static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
518 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
519 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
520 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
521 [DEC_IRQ_DZ11] = -1,
522 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
523 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
524 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
525 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
526 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
527 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
528 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
529 [DEC_IRQ_PSU] = -1,
530 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
531 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
532 [DEC_IRQ_SCC1] = -1,
533 [DEC_IRQ_SII] = -1,
534 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
535 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
536 [DEC_IRQ_TC2] = -1,
537 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
538 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
539 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
540 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
541 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
542 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
543 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
544 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
545 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
546 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
547 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
548 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
549 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
550 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
551 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
552 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
553 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
554 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
555 [DEC_IRQ_SCC1A_RXERR] = -1,
556 [DEC_IRQ_SCC1A_RXDMA] = -1,
557 [DEC_IRQ_SCC1A_TXERR] = -1,
558 [DEC_IRQ_SCC1A_TXDMA] = -1,
559};
560
561static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
562 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
563 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
564 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
565 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
566 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
567 { .p = kn02xa_io_int } },
568 { { .i = DEC_CPU_IRQ_ALL },
569 { .p = cpu_all_int } },
570};
571
572static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
573 { { .i = IO_IRQ_DMA },
574 { .p = asic_dma_int } },
575 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
576 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
577 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
578 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
579 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
580 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
581 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
582 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
583 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
584 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
585 { { .i = IO_IRQ_ALL },
586 { .p = asic_all_int } },
587};
588
23bbbaf8 589static void __init dec_init_kn02ca(void)
1da177e4
LT		 590{
591 /* IRQ routing. */
592 memcpy(&dec_interrupt, &kn02ca_interrupt,
593 sizeof(kn02ca_interrupt));
594
595 /* CPU IRQ priorities. */
596 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
597 sizeof(kn02ca_cpu_mask_nr_tbl));
598
599 /* I/O ASIC IRQ priorities. */
600 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
601 sizeof(kn02ca_asic_mask_nr_tbl));
602
97dcb82d 603 mips_cpu_irq_init();
1da177e4
LT		 604 init_ioasic_irqs(IO_IRQ_BASE);
605
606} /* dec_init_kn02ca */
607
608
609/*
610 * Machine-specific initialisation for KN03, aka DS5000/240,
611 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
612 * DS5000/260, aka 4max+ and DS5900/260.
613 */
614static int kn03_interrupt[DEC_NR_INTS] __initdata = {
615 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
616 [DEC_IRQ_AB_RECV] = -1,
617 [DEC_IRQ_AB_XMIT] = -1,
618 [DEC_IRQ_DZ11] = -1,
619 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
620 [DEC_IRQ_FLOPPY] = -1,
621 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
622 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
623 [DEC_IRQ_ISDN] = -1,
624 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
625 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
626 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
627 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
628 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
629 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
630 [DEC_IRQ_SII] = -1,
631 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
632 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
633 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
634 [DEC_IRQ_TIMER] = -1,
635 [DEC_IRQ_VIDEO] = -1,
636 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
637 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
638 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
639 [DEC_IRQ_FLOPPY_ERR] = -1,
640 [DEC_IRQ_ISDN_ERR] = -1,
641 [DEC_IRQ_ISDN_RXDMA] = -1,
642 [DEC_IRQ_ISDN_TXDMA] = -1,
643 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
644 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
645 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
646 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
647 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
648 [DEC_IRQ_AB_RXERR] = -1,
649 [DEC_IRQ_AB_RXDMA] = -1,
650 [DEC_IRQ_AB_TXERR] = -1,
651 [DEC_IRQ_AB_TXDMA] = -1,
652 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
653 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
654 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
655 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
656};
657
658static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
659 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
660 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
661 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
662 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
663 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
664 { .p = kn03_io_int } },
665 { { .i = DEC_CPU_IRQ_ALL },
666 { .p = cpu_all_int } },
667};
668
669static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
670 { { .i = IO_IRQ_DMA },
671 { .p = asic_dma_int } },
672 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
673 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
674 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
675 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
676 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
677 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
678 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
679 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
680 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
681 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
682 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
683 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
684 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
685 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
686 { { .i = IO_IRQ_ALL },
687 { .p = asic_all_int } },
688};
689
23bbbaf8 690static void __init dec_init_kn03(void)
1da177e4
LT		 691{
692 /* IRQ routing. */
693 memcpy(&dec_interrupt, &kn03_interrupt,
694 sizeof(kn03_interrupt));
695
696 /* CPU IRQ priorities. */
697 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
698 sizeof(kn03_cpu_mask_nr_tbl));
699
700 /* I/O ASIC IRQ priorities. */
701 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
702 sizeof(kn03_asic_mask_nr_tbl));
703
97dcb82d 704 mips_cpu_irq_init();
1da177e4
LT		 705 init_ioasic_irqs(IO_IRQ_BASE);
706
707} /* dec_init_kn03 */
708
709
710void __init arch_init_irq(void)
711{
712 switch (mips_machtype) {
713 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
714 dec_init_kn01();
715 break;
716 case MACH_DS5100: /* DS5100 MIPSmate */
717 dec_init_kn230();
718 break;
719 case MACH_DS5000_200: /* DS5000/200 3max */
720 dec_init_kn02();
721 break;
722 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
723 dec_init_kn02ba();
724 break;
725 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
726 case MACH_DS5900: /* DS5900 bigmax */
727 dec_init_kn03();
728 break;
729 case MACH_DS5000_XX: /* Personal DS5000/xx */
730 dec_init_kn02ca();
731 break;
732 case MACH_DS5800: /* DS5800 Isis */
733 panic("Don't know how to set this up!");
734 break;
735 case MACH_DS5400: /* DS5400 MIPSfair */
736 panic("Don't know how to set this up!");
737 break;
738 case MACH_DS5500: /* DS5500 MIPSfair-2 */
739 panic("Don't know how to set this up!");
740 break;
741 }
1da177e4
LT		 742
743 /* Free the FPU interrupt if the exception is present. */
744 if (!cpu_has_nofpuex) {
745 cpu_fpu_mask = 0;
746 dec_interrupt[DEC_IRQ_FPU] = -1;
747 }
748
749 /* Register board interrupts: FPU and cascade. */
750 if (dec_interrupt[DEC_IRQ_FPU] >= 0)
751 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
752 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
753 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
754
755 /* Register the bus error interrupt. */
756 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
757 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
758
759 /* Register the HALT interrupt. */
760 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
761 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
762}
187933f2
AN		 763
764asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
765{
766 do_IRQ(irq);
767 return 0;
768}
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