projects / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | /* |
| 1da177e4 LT |
2 | * DEC I/O ASIC interrupts. |
| 3 | * | |
| 4 | * Copyright (c) 2002, 2003 Maciej W. Rozycki | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * as published by the Free Software Foundation; either version | |
| 9 | * 2 of the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/init.h> | |
| 13 | #include <linux/irq.h> | |
| 1da177e4 LT |
14 | #include <linux/types.h> |
| 15 | ||
| 16 | #include <asm/dec/ioasic.h> | |
| 17 | #include <asm/dec/ioasic_addrs.h> | |
| 18 | #include <asm/dec/ioasic_ints.h> | |
| 19 | ||
| 20 | ||
| 1da177e4 LT |
21 | static int ioasic_irq_base; |
| 22 | ||
| 23 | ||
| 24 | static inline void unmask_ioasic_irq(unsigned int irq) | |
| 25 | { | |
| 26 | u32 simr; | |
| 27 | ||
| 28 | simr = ioasic_read(IO_REG_SIMR); | |
| 29 | simr |= (1 << (irq - ioasic_irq_base)); | |
| 30 | ioasic_write(IO_REG_SIMR, simr); | |
| 31 | } | |
| 32 | ||
| 33 | static inline void mask_ioasic_irq(unsigned int irq) | |
| 34 | { | |
| 35 | u32 simr; | |
| 36 | ||
| 37 | simr = ioasic_read(IO_REG_SIMR); | |
| 38 | simr &= ~(1 << (irq - ioasic_irq_base)); | |
| 39 | ioasic_write(IO_REG_SIMR, simr); | |
| 40 | } | |
| 41 | ||
| 42 | static inline void clear_ioasic_irq(unsigned int irq) | |
| 43 | { | |
| 44 | u32 sir; | |
| 45 | ||
| 46 | sir = ~(1 << (irq - ioasic_irq_base)); | |
| 47 | ioasic_write(IO_REG_SIR, sir); | |
| 48 | } | |
| 49 | ||
| 1da177e4 LT |
50 | static inline void ack_ioasic_irq(unsigned int irq) |
| 51 | { | |
| 1da177e4 | 52 | mask_ioasic_irq(irq); |
| 1da177e4 LT |
53 | fast_iob(); |
| 54 | } | |
| 55 | ||
| 56 | static inline void end_ioasic_irq(unsigned int irq) | |
| 57 | { | |
| 58 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | |
| 1603b5ac | 59 | unmask_ioasic_irq(irq); |
| 1da177e4 LT |
60 | } |
| 61 | ||
| 94dee171 | 62 | static struct irq_chip ioasic_irq_type = { |
| 70d21cde | 63 | .name = "IO-ASIC", |
| 1da177e4 | 64 | .ack = ack_ioasic_irq, |
| 1603b5ac AN |
65 | .mask = mask_ioasic_irq, |
| 66 | .mask_ack = ack_ioasic_irq, | |
| 67 | .unmask = unmask_ioasic_irq, | |
| 1da177e4 LT |
68 | }; |
| 69 | ||
| 70 | ||
| 1603b5ac | 71 | #define unmask_ioasic_dma_irq unmask_ioasic_irq |
| 1da177e4 | 72 | |
| 1603b5ac | 73 | #define mask_ioasic_dma_irq mask_ioasic_irq |
| 1da177e4 LT |
74 | |
| 75 | #define ack_ioasic_dma_irq ack_ioasic_irq | |
| 76 | ||
| 77 | static inline void end_ioasic_dma_irq(unsigned int irq) | |
| 78 | { | |
| 79 | clear_ioasic_irq(irq); | |
| 80 | fast_iob(); | |
| 81 | end_ioasic_irq(irq); | |
| 82 | } | |
| 83 | ||
| 94dee171 | 84 | static struct irq_chip ioasic_dma_irq_type = { |
| 70d21cde | 85 | .name = "IO-ASIC-DMA", |
| 1da177e4 | 86 | .ack = ack_ioasic_dma_irq, |
| 1603b5ac AN |
87 | .mask = mask_ioasic_dma_irq, |
| 88 | .mask_ack = ack_ioasic_dma_irq, | |
| 89 | .unmask = unmask_ioasic_dma_irq, | |
| 1da177e4 LT |
90 | .end = end_ioasic_dma_irq, |
| 91 | }; | |
| 92 | ||
| 93 | ||
| 94 | void __init init_ioasic_irqs(int base) | |
| 95 | { | |
| 96 | int i; | |
| 97 | ||
| 98 | /* Mask interrupts. */ | |
| 99 | ioasic_write(IO_REG_SIMR, 0); | |
| 100 | fast_iob(); | |
| 101 | ||
| 1603b5ac | 102 | for (i = base; i < base + IO_INR_DMA; i++) |
| 1417836e AN |
103 | set_irq_chip_and_handler(i, &ioasic_irq_type, |
| 104 | handle_level_irq); | |
| 1603b5ac | 105 | for (; i < base + IO_IRQ_LINES; i++) |
| 25ba2f50 | 106 | set_irq_chip(i, &ioasic_dma_irq_type); |
| 1da177e4 LT |
107 | |
| 108 | ioasic_irq_base = base; | |
| 109 | } |