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[PATCH] swsusp: switch pm_message_t to struct
[linux.git] / drivers / video / aty / aty128fb.c
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1da177e4
LT		 1/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <[email protected]>
5 * Copyright (C) 1999, Anthony Tong <[email protected]>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <[email protected]>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <[email protected]>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <[email protected]>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <[email protected]>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to [email protected].
41 */
42
43/*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49#include <linux/config.h>
50#include <linux/module.h>
51#include <linux/moduleparam.h>
52#include <linux/kernel.h>
53#include <linux/errno.h>
54#include <linux/string.h>
55#include <linux/mm.h>
56#include <linux/tty.h>
57#include <linux/slab.h>
58#include <linux/vmalloc.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h>
61#include <asm/uaccess.h>
62#include <linux/fb.h>
63#include <linux/init.h>
64#include <linux/pci.h>
65#include <linux/ioport.h>
66#include <linux/console.h>
67#include <asm/io.h>
68
69#ifdef CONFIG_PPC_PMAC
70#include <asm/pmac_feature.h>
71#include <asm/prom.h>
72#include <asm/pci-bridge.h>
73#include "../macmodes.h"
74#endif
75
76#ifdef CONFIG_PMAC_BACKLIGHT
77#include <asm/backlight.h>
78#endif
79
80#ifdef CONFIG_BOOTX_TEXT
81#include <asm/btext.h>
82#endif /* CONFIG_BOOTX_TEXT */
83
84#ifdef CONFIG_MTRR
85#include <asm/mtrr.h>
86#endif
87
88#include <video/aty128.h>
89
90/* Debug flag */
91#undef DEBUG
92
93#ifdef DEBUG
94#define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
95#else
96#define DBG(fmt, args...)
97#endif
98
99#ifndef CONFIG_PPC_PMAC
100/* default mode */
101static struct fb_var_screeninfo default_var __initdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107};
108
109#else /* CONFIG_PPC_PMAC */
110/* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119};
120#endif /* CONFIG_PPC_PMAC */
121
122/* default modedb mode */
123/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124static struct fb_videomode defaultmode __initdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137};
138
139/* Chip generations */
140enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149};
150
151/* Must match above enum */
152static const char *r128_family[] __devinitdata = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161};
162
163/*
164 * PCI driver prototypes
165 */
166static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168static void aty128_remove(struct pci_dev *pdev);
169static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170static int aty128_pci_resume(struct pci_dev *pdev);
171static int aty128_do_resume(struct pci_dev *pdev);
172
173/* supported Rage128 chipsets */
174static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270};
271
272MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281};
282
283/* packed BIOS settings */
284#ifndef CONFIG_PPC
285typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308} __attribute__ ((packed)) PLL_BLOCK;
309#endif /* !CONFIG_PPC */
310
311/* onboard memory information */
312struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324};
325
326/* various memory configurations */
327static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336static struct fb_fix_screeninfo aty128fb_fix __initdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344};
345
346static char *mode_option __initdata = NULL;
347
348#ifdef CONFIG_PPC_PMAC
349static int default_vmode __initdata = VMODE_1024_768_60;
350static int default_cmode __initdata = CMODE_8;
351#endif
352
1da177e4
LT		 353static int default_crt_on __initdata = 0;
354static int default_lcd_on __initdata = 1;
1da177e4
LT		 355
356#ifdef CONFIG_MTRR
357static int mtrr = 1;
358#endif
359
360/* PLL constants */
361struct aty128_constants {
362 u32 ref_clk;
363 u32 ppll_min;
364 u32 ppll_max;
365 u32 ref_divider;
366 u32 xclk;
367 u32 fifo_width;
368 u32 fifo_depth;
369};
370
371struct aty128_crtc {
372 u32 gen_cntl;
373 u32 h_total, h_sync_strt_wid;
374 u32 v_total, v_sync_strt_wid;
375 u32 pitch;
376 u32 offset, offset_cntl;
377 u32 xoffset, yoffset;
378 u32 vxres, vyres;
379 u32 depth, bpp;
380};
381
382struct aty128_pll {
383 u32 post_divider;
384 u32 feedback_divider;
385 u32 vclk;
386};
387
388struct aty128_ddafifo {
389 u32 dda_config;
390 u32 dda_on_off;
391};
392
393/* register values for a specific mode */
394struct aty128fb_par {
395 struct aty128_crtc crtc;
396 struct aty128_pll pll;
397 struct aty128_ddafifo fifo_reg;
398 u32 accel_flags;
399 struct aty128_constants constants; /* PLL and others */
400 void __iomem *regbase; /* remapped mmio */
401 u32 vram_size; /* onboard video ram */
402 int chip_gen;
403 const struct aty128_meminfo *mem; /* onboard mem info */
404#ifdef CONFIG_MTRR
405 struct { int vram; int vram_valid; } mtrr;
406#endif
407 int blitter_may_be_busy;
408 int fifo_slots; /* free slots in FIFO (64 max) */
409
410 int pm_reg;
411 int crt_on, lcd_on;
412 struct pci_dev *pdev;
413 struct fb_info *next;
414 int asleep;
415 int lock_blank;
416
417 u8 red[32]; /* see aty128fb_setcolreg */
418 u8 green[64];
419 u8 blue[32];
420 u32 pseudo_palette[16]; /* used for TRUECOLOR */
421};
422
423
424#define round_div(n, d) ((n+(d/2))/d)
425
426static int aty128fb_check_var(struct fb_var_screeninfo *var,
427 struct fb_info *info);
428static int aty128fb_set_par(struct fb_info *info);
429static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
430 u_int transp, struct fb_info *info);
431static int aty128fb_pan_display(struct fb_var_screeninfo *var,
432 struct fb_info *fb);
433static int aty128fb_blank(int blank, struct fb_info *fb);
434static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
435 u_long arg, struct fb_info *info);
436static int aty128fb_sync(struct fb_info *info);
437
438 /*
439 * Internal routines
440 */
441
442static int aty128_encode_var(struct fb_var_screeninfo *var,
443 const struct aty128fb_par *par);
444static int aty128_decode_var(struct fb_var_screeninfo *var,
445 struct aty128fb_par *par);
446#if 0
447static void __init aty128_get_pllinfo(struct aty128fb_par *par,
448 void __iomem *bios);
449static void __init __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
450#endif
451static void aty128_timings(struct aty128fb_par *par);
452static void aty128_init_engine(struct aty128fb_par *par);
453static void aty128_reset_engine(const struct aty128fb_par *par);
454static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
455static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
456static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
457static void wait_for_idle(struct aty128fb_par *par);
458static u32 depth_to_dst(u32 depth);
459
460#define BIOS_IN8(v) (readb(bios + (v)))
461#define BIOS_IN16(v) (readb(bios + (v)) | \
462 (readb(bios + (v) + 1) << 8))
463#define BIOS_IN32(v) (readb(bios + (v)) | \
464 (readb(bios + (v) + 1) << 8) | \
465 (readb(bios + (v) + 2) << 16) | \
466 (readb(bios + (v) + 3) << 24))
467
468
469static struct fb_ops aty128fb_ops = {
470 .owner = THIS_MODULE,
471 .fb_check_var = aty128fb_check_var,
472 .fb_set_par = aty128fb_set_par,
473 .fb_setcolreg = aty128fb_setcolreg,
474 .fb_pan_display = aty128fb_pan_display,
475 .fb_blank = aty128fb_blank,
476 .fb_ioctl = aty128fb_ioctl,
477 .fb_sync = aty128fb_sync,
478 .fb_fillrect = cfb_fillrect,
479 .fb_copyarea = cfb_copyarea,
480 .fb_imageblit = cfb_imageblit,
481 .fb_cursor = soft_cursor,
482};
483
484#ifdef CONFIG_PMAC_BACKLIGHT
485static int aty128_set_backlight_enable(int on, int level, void* data);
486static int aty128_set_backlight_level(int level, void* data);
487
488static struct backlight_controller aty128_backlight_controller = {
489 aty128_set_backlight_enable,
490 aty128_set_backlight_level
491};
492#endif /* CONFIG_PMAC_BACKLIGHT */
493
494 /*
495 * Functions to read from/write to the mmio registers
496 * - endian conversions may possibly be avoided by
497 * using the other register aperture. TODO.
498 */
499static inline u32 _aty_ld_le32(volatile unsigned int regindex,
500 const struct aty128fb_par *par)
501{
502 return readl (par->regbase + regindex);
503}
504
505static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
506 const struct aty128fb_par *par)
507{
508 writel (val, par->regbase + regindex);
509}
510
511static inline u8 _aty_ld_8(unsigned int regindex,
512 const struct aty128fb_par *par)
513{
514 return readb (par->regbase + regindex);
515}
516
517static inline void _aty_st_8(unsigned int regindex, u8 val,
518 const struct aty128fb_par *par)
519{
520 writeb (val, par->regbase + regindex);
521}
522
523#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
524#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
525#define aty_ld_8(regindex) _aty_ld_8(regindex, par)
526#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
527
528 /*
529 * Functions to read from/write to the pll registers
530 */
531
532#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
533#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
534
535
536static u32 _aty_ld_pll(unsigned int pll_index,
537 const struct aty128fb_par *par)
538{
539 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
540 return aty_ld_le32(CLOCK_CNTL_DATA);
541}
542
543
544static void _aty_st_pll(unsigned int pll_index, u32 val,
545 const struct aty128fb_par *par)
546{
547 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
548 aty_st_le32(CLOCK_CNTL_DATA, val);
549}
550
551
552/* return true when the PLL has completed an atomic update */
553static int aty_pll_readupdate(const struct aty128fb_par *par)
554{
555 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
556}
557
558
559static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
560{
561 unsigned long timeout = jiffies + HZ/100; // should be more than enough
562 int reset = 1;
563
564 while (time_before(jiffies, timeout))
565 if (aty_pll_readupdate(par)) {
566 reset = 0;
567 break;
568 }
569
570 if (reset) /* reset engine?? */
571 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
572}
573
574
575/* tell PLL to update */
576static void aty_pll_writeupdate(const struct aty128fb_par *par)
577{
578 aty_pll_wait_readupdate(par);
579
580 aty_st_pll(PPLL_REF_DIV,
581 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
582}
583
584
585/* write to the scratch register to test r/w functionality */
586static int __init register_test(const struct aty128fb_par *par)
587{
588 u32 val;
589 int flag = 0;
590
591 val = aty_ld_le32(BIOS_0_SCRATCH);
592
593 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
595 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
596
597 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
598 flag = 1;
599 }
600
601 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
602 return flag;
603}
604
605
606/*
607 * Accelerator engine functions
608 */
609static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
610{
611 int i;
612
613 for (;;) {
614 for (i = 0; i < 2000000; i++) {
615 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
616 if (par->fifo_slots >= entries)
617 return;
618 }
619 aty128_reset_engine(par);
620 }
621}
622
623
624static void wait_for_idle(struct aty128fb_par *par)
625{
626 int i;
627
628 do_wait_for_fifo(64, par);
629
630 for (;;) {
631 for (i = 0; i < 2000000; i++) {
632 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
633 aty128_flush_pixel_cache(par);
634 par->blitter_may_be_busy = 0;
635 return;
636 }
637 }
638 aty128_reset_engine(par);
639 }
640}
641
642
643static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
644{
645 if (par->fifo_slots < entries)
646 do_wait_for_fifo(64, par);
647 par->fifo_slots -= entries;
648}
649
650
651static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
652{
653 int i;
654 u32 tmp;
655
656 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
657 tmp &= ~(0x00ff);
658 tmp |= 0x00ff;
659 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
660
661 for (i = 0; i < 2000000; i++)
662 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
663 break;
664}
665
666
667static void aty128_reset_engine(const struct aty128fb_par *par)
668{
669 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
670
671 aty128_flush_pixel_cache(par);
672
673 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
674 mclk_cntl = aty_ld_pll(MCLK_CNTL);
675
676 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
677
678 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
679 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
680 aty_ld_le32(GEN_RESET_CNTL);
681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
682 aty_ld_le32(GEN_RESET_CNTL);
683
684 aty_st_pll(MCLK_CNTL, mclk_cntl);
685 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
686 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
687
688 /* use old pio mode */
689 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
690
691 DBG("engine reset");
692}
693
694
695static void aty128_init_engine(struct aty128fb_par *par)
696{
697 u32 pitch_value;
698
699 wait_for_idle(par);
700
701 /* 3D scaler not spoken here */
702 wait_for_fifo(1, par);
703 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
704
705 aty128_reset_engine(par);
706
707 pitch_value = par->crtc.pitch;
708 if (par->crtc.bpp == 24) {
709 pitch_value = pitch_value * 3;
710 }
711
712 wait_for_fifo(4, par);
713 /* setup engine offset registers */
714 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
715
716 /* setup engine pitch registers */
717 aty_st_le32(DEFAULT_PITCH, pitch_value);
718
719 /* set the default scissor register to max dimensions */
720 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
721
722 /* set the drawing controls registers */
723 aty_st_le32(DP_GUI_MASTER_CNTL,
724 GMC_SRC_PITCH_OFFSET_DEFAULT |
725 GMC_DST_PITCH_OFFSET_DEFAULT |
726 GMC_SRC_CLIP_DEFAULT |
727 GMC_DST_CLIP_DEFAULT |
728 GMC_BRUSH_SOLIDCOLOR |
729 (depth_to_dst(par->crtc.depth) << 8) |
730 GMC_SRC_DSTCOLOR |
731 GMC_BYTE_ORDER_MSB_TO_LSB |
732 GMC_DP_CONVERSION_TEMP_6500 |
733 ROP3_PATCOPY |
734 GMC_DP_SRC_RECT |
735 GMC_3D_FCN_EN_CLR |
736 GMC_DST_CLR_CMP_FCN_CLEAR |
737 GMC_AUX_CLIP_CLEAR |
738 GMC_WRITE_MASK_SET);
739
740 wait_for_fifo(8, par);
741 /* clear the line drawing registers */
742 aty_st_le32(DST_BRES_ERR, 0);
743 aty_st_le32(DST_BRES_INC, 0);
744 aty_st_le32(DST_BRES_DEC, 0);
745
746 /* set brush color registers */
747 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
748 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
749
750 /* set source color registers */
751 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
752 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
753
754 /* default write mask */
755 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
756
757 /* Wait for all the writes to be completed before returning */
758 wait_for_idle(par);
759}
760
761
762/* convert depth values to their register representation */
763static u32 depth_to_dst(u32 depth)
764{
765 if (depth <= 8)
766 return DST_8BPP;
767 else if (depth <= 15)
768 return DST_15BPP;
769 else if (depth == 16)
770 return DST_16BPP;
771 else if (depth <= 24)
772 return DST_24BPP;
773 else if (depth <= 32)
774 return DST_32BPP;
775
776 return -EINVAL;
777}
778
779/*
780 * PLL informations retreival
781 */
782
783
784#ifndef __sparc__
785static void __iomem * __init aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
786{
787 u16 dptr;
788 u8 rom_type;
789 void __iomem *bios;
790 size_t rom_size;
791
792 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
793 unsigned int temp;
794 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
795 temp &= 0x00ffffffu;
796 temp |= 0x04 << 24;
797 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
798 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
799
800 bios = pci_map_rom(dev, &rom_size);
801
802 if (!bios) {
803 printk(KERN_ERR "aty128fb: ROM failed to map\n");
804 return NULL;
805 }
806
807 /* Very simple test to make sure it appeared */
808 if (BIOS_IN16(0) != 0xaa55) {
809 printk(KERN_ERR "aty128fb: Invalid ROM signature %x should be 0xaa55\n",
810 BIOS_IN16(0));
811 goto failed;
812 }
813
814 /* Look for the PCI data to check the ROM type */
815 dptr = BIOS_IN16(0x18);
816
817 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
818 * for now, until I've verified this works everywhere. The goal here is more
819 * to phase out Open Firmware images.
820 *
821 * Currently, we only look at the first PCI data, we could iteratre and deal with
822 * them all, and we should use fb_bios_start relative to start of image and not
823 * relative start of ROM, but so far, I never found a dual-image ATI card
824 *
825 * typedef struct {
826 * u32 signature; + 0x00
827 * u16 vendor; + 0x04
828 * u16 device; + 0x06
829 * u16 reserved_1; + 0x08
830 * u16 dlen; + 0x0a
831 * u8 drevision; + 0x0c
832 * u8 class_hi; + 0x0d
833 * u16 class_lo; + 0x0e
834 * u16 ilen; + 0x10
835 * u16 irevision; + 0x12
836 * u8 type; + 0x14
837 * u8 indicator; + 0x15
838 * u16 reserved_2; + 0x16
839 * } pci_data_t;
840 */
841 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
842 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
843 BIOS_IN32(dptr));
844 goto anyway;
845 }
846 rom_type = BIOS_IN8(dptr + 0x14);
847 switch(rom_type) {
848 case 0:
849 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
850 break;
851 case 1:
852 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
853 goto failed;
854 case 2:
855 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
856 goto failed;
857 default:
858 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
859 goto failed;
860 }
861 anyway:
862 return bios;
863
864 failed:
865 pci_unmap_rom(dev, bios);
866 return NULL;
867}
868
869static void __init aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
870{
871 unsigned int bios_hdr;
872 unsigned int bios_pll;
873
874 bios_hdr = BIOS_IN16(0x48);
875 bios_pll = BIOS_IN16(bios_hdr + 0x30);
876
877 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
878 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
879 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
880 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
881 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
882
883 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
884 par->constants.ppll_max, par->constants.ppll_min,
885 par->constants.xclk, par->constants.ref_divider,
886 par->constants.ref_clk);
887
888}
889
890#ifdef CONFIG_X86
891static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
892{
893 /* I simplified this code as we used to miss the signatures in
894 * a lot of case. It's now closer to XFree, we just don't check
895 * for signatures at all... Something better will have to be done
896 * if we end up having conflicts
897 */
898 u32 segstart;
899 unsigned char __iomem *rom_base = NULL;
900
901 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
902 rom_base = ioremap(segstart, 0x10000);
903 if (rom_base == NULL)
904 return NULL;
905 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
906 break;
907 iounmap(rom_base);
908 rom_base = NULL;
909 }
910 return rom_base;
911}
912#endif
913#endif /* ndef(__sparc__) */
914
915/* fill in known card constants if pll_block is not available */
916static void __init aty128_timings(struct aty128fb_par *par)
917{
918#ifdef CONFIG_PPC_OF
919 /* instead of a table lookup, assume OF has properly
920 * setup the PLL registers and use their values
921 * to set the XCLK values and reference divider values */
922
923 u32 x_mpll_ref_fb_div;
924 u32 xclk_cntl;
925 u32 Nx, M;
926 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
927#endif
928
929 if (!par->constants.ref_clk)
930 par->constants.ref_clk = 2950;
931
932#ifdef CONFIG_PPC_OF
933 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
934 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
935 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
936 M = x_mpll_ref_fb_div & 0x0000ff;
937
938 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
939 (M * PostDivSet[xclk_cntl]));
940
941 par->constants.ref_divider =
942 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
943#endif
944
945 if (!par->constants.ref_divider) {
946 par->constants.ref_divider = 0x3b;
947
948 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
949 aty_pll_writeupdate(par);
950 }
951 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
952 aty_pll_writeupdate(par);
953
954 /* from documentation */
955 if (!par->constants.ppll_min)
956 par->constants.ppll_min = 12500;
957 if (!par->constants.ppll_max)
958 par->constants.ppll_max = 25000; /* 23000 on some cards? */
959 if (!par->constants.xclk)
960 par->constants.xclk = 0x1d4d; /* same as mclk */
961
962 par->constants.fifo_width = 128;
963 par->constants.fifo_depth = 32;
964
965 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
966 case 0:
967 par->mem = &sdr_128;
968 break;
969 case 1:
970 par->mem = &sdr_sgram;
971 break;
972 case 2:
973 par->mem = &ddr_sgram;
974 break;
975 default:
976 par->mem = &sdr_sgram;
977 }
978}
979
980
981
982/*
983 * CRTC programming
984 */
985
986/* Program the CRTC registers */
987static void aty128_set_crtc(const struct aty128_crtc *crtc,
988 const struct aty128fb_par *par)
989{
990 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
991 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
992 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
993 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
994 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
995 aty_st_le32(CRTC_PITCH, crtc->pitch);
996 aty_st_le32(CRTC_OFFSET, crtc->offset);
997 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
998 /* Disable ATOMIC updating. Is this the right place? */
999 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1000}
1001
1002
1003static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1004 struct aty128_crtc *crtc,
1005 const struct aty128fb_par *par)
1006{
1007 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1008 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1009 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1010 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1011 u32 depth, bytpp;
1012 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1013
1014 /* input */
1015 xres = var->xres;
1016 yres = var->yres;
1017 vxres = var->xres_virtual;
1018 vyres = var->yres_virtual;
1019 xoffset = var->xoffset;
1020 yoffset = var->yoffset;
1021 bpp = var->bits_per_pixel;
1022 left = var->left_margin;
1023 right = var->right_margin;
1024 upper = var->upper_margin;
1025 lower = var->lower_margin;
1026 hslen = var->hsync_len;
1027 vslen = var->vsync_len;
1028 sync = var->sync;
1029 vmode = var->vmode;
1030
1031 if (bpp != 16)
1032 depth = bpp;
1033 else
1034 depth = (var->green.length == 6) ? 16 : 15;
1035
1036 /* check for mode eligibility
1037 * accept only non interlaced modes */
1038 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1039 return -EINVAL;
1040
1041 /* convert (and round up) and validate */
1042 xres = (xres + 7) & ~7;
1043 xoffset = (xoffset + 7) & ~7;
1044
1045 if (vxres < xres + xoffset)
1046 vxres = xres + xoffset;
1047
1048 if (vyres < yres + yoffset)
1049 vyres = yres + yoffset;
1050
1051 /* convert depth into ATI register depth */
1052 dst = depth_to_dst(depth);
1053
1054 if (dst == -EINVAL) {
1055 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1056 return -EINVAL;
1057 }
1058
1059 /* convert register depth to bytes per pixel */
1060 bytpp = mode_bytpp[dst];
1061
1062 /* make sure there is enough video ram for the mode */
1063 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1064 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1065 return -EINVAL;
1066 }
1067
1068 h_disp = (xres >> 3) - 1;
1069 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1070
1071 v_disp = yres - 1;
1072 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1073
1074 /* check to make sure h_total and v_total are in range */
1075 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1076 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1077 return -EINVAL;
1078 }
1079
1080 h_sync_wid = (hslen + 7) >> 3;
1081 if (h_sync_wid == 0)
1082 h_sync_wid = 1;
1083 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1084 h_sync_wid = 0x3f;
1085
1086 h_sync_strt = (h_disp << 3) + right;
1087
1088 v_sync_wid = vslen;
1089 if (v_sync_wid == 0)
1090 v_sync_wid = 1;
1091 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1092 v_sync_wid = 0x1f;
1093
1094 v_sync_strt = v_disp + lower;
1095
1096 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1097 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1098
1099 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1100
1101 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1102
1103 crtc->h_total = h_total | (h_disp << 16);
1104 crtc->v_total = v_total | (v_disp << 16);
1105
1106 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1107 (h_sync_pol << 23);
1108 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1109 (v_sync_pol << 23);
1110
1111 crtc->pitch = vxres >> 3;
1112
1113 crtc->offset = 0;
1114
1115 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1116 crtc->offset_cntl = 0x00010000;
1117 else
1118 crtc->offset_cntl = 0;
1119
1120 crtc->vxres = vxres;
1121 crtc->vyres = vyres;
1122 crtc->xoffset = xoffset;
1123 crtc->yoffset = yoffset;
1124 crtc->depth = depth;
1125 crtc->bpp = bpp;
1126
1127 return 0;
1128}
1129
1130
1131static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1132{
1133
1134 /* fill in pixel info */
1135 var->red.msb_right = 0;
1136 var->green.msb_right = 0;
1137 var->blue.offset = 0;
1138 var->blue.msb_right = 0;
1139 var->transp.offset = 0;
1140 var->transp.length = 0;
1141 var->transp.msb_right = 0;
1142 switch (pix_width) {
1143 case CRTC_PIX_WIDTH_8BPP:
1144 var->bits_per_pixel = 8;
1145 var->red.offset = 0;
1146 var->red.length = 8;
1147 var->green.offset = 0;
1148 var->green.length = 8;
1149 var->blue.length = 8;
1150 break;
1151 case CRTC_PIX_WIDTH_15BPP:
1152 var->bits_per_pixel = 16;
1153 var->red.offset = 10;
1154 var->red.length = 5;
1155 var->green.offset = 5;
1156 var->green.length = 5;
1157 var->blue.length = 5;
1158 break;
1159 case CRTC_PIX_WIDTH_16BPP:
1160 var->bits_per_pixel = 16;
1161 var->red.offset = 11;
1162 var->red.length = 5;
1163 var->green.offset = 5;
1164 var->green.length = 6;
1165 var->blue.length = 5;
1166 break;
1167 case CRTC_PIX_WIDTH_24BPP:
1168 var->bits_per_pixel = 24;
1169 var->red.offset = 16;
1170 var->red.length = 8;
1171 var->green.offset = 8;
1172 var->green.length = 8;
1173 var->blue.length = 8;
1174 break;
1175 case CRTC_PIX_WIDTH_32BPP:
1176 var->bits_per_pixel = 32;
1177 var->red.offset = 16;
1178 var->red.length = 8;
1179 var->green.offset = 8;
1180 var->green.length = 8;
1181 var->blue.length = 8;
1182 var->transp.offset = 24;
1183 var->transp.length = 8;
1184 break;
1185 default:
1186 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1187 return -EINVAL;
1188 }
1189
1190 return 0;
1191}
1192
1193
1194static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1195 struct fb_var_screeninfo *var)
1196{
1197 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1198 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1199 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1200 u32 pix_width;
1201
1202 /* fun with masking */
1203 h_total = crtc->h_total & 0x1ff;
1204 h_disp = (crtc->h_total >> 16) & 0xff;
1205 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1206 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1207 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1208 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1209 v_total = crtc->v_total & 0x7ff;
1210 v_disp = (crtc->v_total >> 16) & 0x7ff;
1211 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1212 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1213 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1214 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1215 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1216
1217 /* do conversions */
1218 xres = (h_disp + 1) << 3;
1219 yres = v_disp + 1;
1220 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1221 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1222 hslen = h_sync_wid << 3;
1223 upper = v_total - v_sync_strt - v_sync_wid;
1224 lower = v_sync_strt - v_disp;
1225 vslen = v_sync_wid;
1226 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1227 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1228 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1229
1230 aty128_pix_width_to_var(pix_width, var);
1231
1232 var->xres = xres;
1233 var->yres = yres;
1234 var->xres_virtual = crtc->vxres;
1235 var->yres_virtual = crtc->vyres;
1236 var->xoffset = crtc->xoffset;
1237 var->yoffset = crtc->yoffset;
1238 var->left_margin = left;
1239 var->right_margin = right;
1240 var->upper_margin = upper;
1241 var->lower_margin = lower;
1242 var->hsync_len = hslen;
1243 var->vsync_len = vslen;
1244 var->sync = sync;
1245 var->vmode = FB_VMODE_NONINTERLACED;
1246
1247 return 0;
1248}
1249
1da177e4
LT		 1250static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1251{
1252 if (on) {
1253 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1254 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1255 } else
1256 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1257}
1258
1259static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1260{
1261 u32 reg;
1262
1263 if (on) {
1264 reg = aty_ld_le32(LVDS_GEN_CNTL);
1265 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1266 reg &= ~LVDS_DISPLAY_DIS;
1267 aty_st_le32(LVDS_GEN_CNTL, reg);
1268#ifdef CONFIG_PMAC_BACKLIGHT
1269 aty128_set_backlight_enable(get_backlight_enable(),
1270 get_backlight_level(), par);
1271#endif
1272 } else {
1273#ifdef CONFIG_PMAC_BACKLIGHT
1274 aty128_set_backlight_enable(0, 0, par);
1275#endif
1276 reg = aty_ld_le32(LVDS_GEN_CNTL);
1277 reg |= LVDS_DISPLAY_DIS;
1278 aty_st_le32(LVDS_GEN_CNTL, reg);
1279 mdelay(100);
1280 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1281 aty_st_le32(LVDS_GEN_CNTL, reg);
1282 }
1283}
1da177e4
LT		 1284
1285static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1286{
1287 u32 div3;
1288
1289 unsigned char post_conv[] = /* register values for post dividers */
1290 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1291
1292 /* select PPLL_DIV_3 */
1293 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1294
1295 /* reset PLL */
1296 aty_st_pll(PPLL_CNTL,
1297 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1298
1299 /* write the reference divider */
1300 aty_pll_wait_readupdate(par);
1301 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1302 aty_pll_writeupdate(par);
1303
1304 div3 = aty_ld_pll(PPLL_DIV_3);
1305 div3 &= ~PPLL_FB3_DIV_MASK;
1306 div3 |= pll->feedback_divider;
1307 div3 &= ~PPLL_POST3_DIV_MASK;
1308 div3 |= post_conv[pll->post_divider] << 16;
1309
1310 /* write feedback and post dividers */
1311 aty_pll_wait_readupdate(par);
1312 aty_st_pll(PPLL_DIV_3, div3);
1313 aty_pll_writeupdate(par);
1314
1315 aty_pll_wait_readupdate(par);
1316 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1317 aty_pll_writeupdate(par);
1318
1319 /* clear the reset, just in case */
1320 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1321}
1322
1323
1324static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1325 const struct aty128fb_par *par)
1326{
1327 const struct aty128_constants c = par->constants;
1328 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1329 u32 output_freq;
1330 u32 vclk; /* in .01 MHz */
1331 int i;
1332 u32 n, d;
1333
1334 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1335
1336 /* adjust pixel clock if necessary */
1337 if (vclk > c.ppll_max)
1338 vclk = c.ppll_max;
1339 if (vclk * 12 < c.ppll_min)
1340 vclk = c.ppll_min/12;
1341
1342 /* now, find an acceptable divider */
1343 for (i = 0; i < sizeof(post_dividers); i++) {
1344 output_freq = post_dividers[i] * vclk;
1345 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1346 break;
1347 }
1348
1349 /* calculate feedback divider */
1350 n = c.ref_divider * output_freq;
1351 d = c.ref_clk;
1352
1353 pll->post_divider = post_dividers[i];
1354 pll->feedback_divider = round_div(n, d);
1355 pll->vclk = vclk;
1356
1357 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1358 "vclk_per: %d\n", pll->post_divider,
1359 pll->feedback_divider, vclk, output_freq,
1360 c.ref_divider, period_in_ps);
1361
1362 return 0;
1363}
1364
1365
1366static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1367{
1368 var->pixclock = 100000000 / pll->vclk;
1369
1370 return 0;
1371}
1372
1373
1374static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1375 const struct aty128fb_par *par)
1376{
1377 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1378 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1379}
1380
1381
1382static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1383 const struct aty128_pll *pll,
1384 u32 depth,
1385 const struct aty128fb_par *par)
1386{
1387 const struct aty128_meminfo *m = par->mem;
1388 u32 xclk = par->constants.xclk;
1389 u32 fifo_width = par->constants.fifo_width;
1390 u32 fifo_depth = par->constants.fifo_depth;
1391 s32 x, b, p, ron, roff;
1392 u32 n, d, bpp;
1393
1394 /* round up to multiple of 8 */
1395 bpp = (depth+7) & ~7;
1396
1397 n = xclk * fifo_width;
1398 d = pll->vclk * bpp;
1399 x = round_div(n, d);
1400
1401 ron = 4 * m->MB +
1402 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1403 2 * m->Trp +
1404 m->Twr +
1405 m->CL +
1406 m->Tr2w +
1407 x;
1408
1409 DBG("x %x\n", x);
1410
1411 b = 0;
1412 while (x) {
1413 x >>= 1;
1414 b++;
1415 }
1416 p = b + 1;
1417
1418 ron <<= (11 - p);
1419
1420 n <<= (11 - p);
1421 x = round_div(n, d);
1422 roff = x * (fifo_depth - 4);
1423
1424 if ((ron + m->Rloop) >= roff) {
1425 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1426 return -EINVAL;
1427 }
1428
1429 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1430 p, m->Rloop, x, ron, roff);
1431
1432 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1433 dsp->dda_on_off = ron << 16 | roff;
1434
1435 return 0;
1436}
1437
1438
1439/*
1440 * This actually sets the video mode.
1441 */
1442static int aty128fb_set_par(struct fb_info *info)
1443{
1444 struct aty128fb_par *par = info->par;
1445 u32 config;
1446 int err;
1447
1448 if ((err = aty128_decode_var(&info->var, par)) != 0)
1449 return err;
1450
1451 if (par->blitter_may_be_busy)
1452 wait_for_idle(par);
1453
1454 /* clear all registers that may interfere with mode setting */
1455 aty_st_le32(OVR_CLR, 0);
1456 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1457 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1458 aty_st_le32(OV0_SCALE_CNTL, 0);
1459 aty_st_le32(MPP_TB_CONFIG, 0);
1460 aty_st_le32(MPP_GP_CONFIG, 0);
1461 aty_st_le32(SUBPIC_CNTL, 0);
1462 aty_st_le32(VIPH_CONTROL, 0);
1463 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1464 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1465 aty_st_le32(CAP0_TRIG_CNTL, 0);
1466 aty_st_le32(CAP1_TRIG_CNTL, 0);
1467
1468 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1469
1470 aty128_set_crtc(&par->crtc, par);
1471 aty128_set_pll(&par->pll, par);
1472 aty128_set_fifo(&par->fifo_reg, par);
1473
1474 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1475
1476#if defined(__BIG_ENDIAN)
1477 if (par->crtc.bpp == 32)
1478 config |= 2; /* make aperture do 32 bit swapping */
1479 else if (par->crtc.bpp == 16)
1480 config |= 1; /* make aperture do 16 bit swapping */
1481#endif
1482
1483 aty_st_le32(CONFIG_CNTL, config);
1484 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1485
1486 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1487 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1488 : FB_VISUAL_DIRECTCOLOR;
1489
1da177e4
LT		 1490 if (par->chip_gen == rage_M3) {
1491 aty128_set_crt_enable(par, par->crt_on);
1492 aty128_set_lcd_enable(par, par->lcd_on);
1493 }
1da177e4
LT		 1494 if (par->accel_flags & FB_ACCELF_TEXT)
1495 aty128_init_engine(par);
1496
1497#ifdef CONFIG_BOOTX_TEXT
1498 btext_update_display(info->fix.smem_start,
1499 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1500 ((par->crtc.v_total>>16) & 0x7ff)+1,
1501 par->crtc.bpp,
1502 par->crtc.vxres*par->crtc.bpp/8);
1503#endif /* CONFIG_BOOTX_TEXT */
1504
1505 return 0;
1506}
1507
1508/*
1509 * encode/decode the User Defined Part of the Display
1510 */
1511
1512static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1513{
1514 int err;
1515 struct aty128_crtc crtc;
1516 struct aty128_pll pll;
1517 struct aty128_ddafifo fifo_reg;
1518
1519 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1520 return err;
1521
1522 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1523 return err;
1524
1525 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1526 return err;
1527
1528 par->crtc = crtc;
1529 par->pll = pll;
1530 par->fifo_reg = fifo_reg;
1531 par->accel_flags = var->accel_flags;
1532
1533 return 0;
1534}
1535
1536
1537static int aty128_encode_var(struct fb_var_screeninfo *var,
1538 const struct aty128fb_par *par)
1539{
1540 int err;
1541
1542 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1543 return err;
1544
1545 if ((err = aty128_pll_to_var(&par->pll, var)))
1546 return err;
1547
1548 var->nonstd = 0;
1549 var->activate = 0;
1550
1551 var->height = -1;
1552 var->width = -1;
1553 var->accel_flags = par->accel_flags;
1554
1555 return 0;
1556}
1557
1558
1559static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1560{
1561 struct aty128fb_par par;
1562 int err;
1563
1564 par = *(struct aty128fb_par *)info->par;
1565 if ((err = aty128_decode_var(var, &par)) != 0)
1566 return err;
1567 aty128_encode_var(var, &par);
1568 return 0;
1569}
1570
1571
1572/*
1573 * Pan or Wrap the Display
1574 */
1575static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1576{
1577 struct aty128fb_par *par = fb->par;
1578 u32 xoffset, yoffset;
1579 u32 offset;
1580 u32 xres, yres;
1581
1582 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1583 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1584
1585 xoffset = (var->xoffset +7) & ~7;
1586 yoffset = var->yoffset;
1587
1588 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1589 return -EINVAL;
1590
1591 par->crtc.xoffset = xoffset;
1592 par->crtc.yoffset = yoffset;
1593
1594 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1595
1596 if (par->crtc.bpp == 24)
1597 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1598
1599 aty_st_le32(CRTC_OFFSET, offset);
1600
1601 return 0;
1602}
1603
1604
1605/*
1606 * Helper function to store a single palette register
1607 */
1608static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1609 struct aty128fb_par *par)
1610{
1611 if (par->chip_gen == rage_M3) {
1612#if 0
1613 /* Note: For now, on M3, we set palette on both heads, which may
1614 * be useless. Can someone with a M3 check this ?
1615 *
1616 * This code would still be useful if using the second CRTC to
1617 * do mirroring
1618 */
1619
1620 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1621 aty_st_8(PALETTE_INDEX, regno);
1622 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1623#endif
1624 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1625 }
1626
1627 aty_st_8(PALETTE_INDEX, regno);
1628 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1629}
1630
1631static int aty128fb_sync(struct fb_info *info)
1632{
1633 struct aty128fb_par *par = info->par;
1634
1635 if (par->blitter_may_be_busy)
1636 wait_for_idle(par);
1637 return 0;
1638}
1639
1640#ifndef MODULE
1641static int __init aty128fb_setup(char *options)
1642{
1643 char *this_opt;
1644
1645 if (!options || !*options)
1646 return 0;
1647
1648 while ((this_opt = strsep(&options, ",")) != NULL) {
1da177e4
LT		 1649 if (!strncmp(this_opt, "lcd:", 4)) {
1650 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1651 continue;
1652 } else if (!strncmp(this_opt, "crt:", 4)) {
1653 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1654 continue;
1655 }
1da177e4
LT		 1656#ifdef CONFIG_MTRR
1657 if(!strncmp(this_opt, "nomtrr", 6)) {
1658 mtrr = 0;
1659 continue;
1660 }
1661#endif
1662#ifdef CONFIG_PPC_PMAC
1663 /* vmode and cmode deprecated */
1664 if (!strncmp(this_opt, "vmode:", 6)) {
1665 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1666 if (vmode > 0 && vmode <= VMODE_MAX)
1667 default_vmode = vmode;
1668 continue;
1669 } else if (!strncmp(this_opt, "cmode:", 6)) {
1670 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1671 switch (cmode) {
1672 case 0:
1673 case 8:
1674 default_cmode = CMODE_8;
1675 break;
1676 case 15:
1677 case 16:
1678 default_cmode = CMODE_16;
1679 break;
1680 case 24:
1681 case 32:
1682 default_cmode = CMODE_32;
1683 break;
1684 }
1685 continue;
1686 }
1687#endif /* CONFIG_PPC_PMAC */
1688 mode_option = this_opt;
1689 }
1690 return 0;
1691}
1692#endif /* MODULE */
1693
1694
1695/*
1696 * Initialisation
1697 */
1698
1699#ifdef CONFIG_PPC_PMAC
1700static void aty128_early_resume(void *data)
1701{
1702 struct aty128fb_par *par = data;
1703
1704 if (try_acquire_console_sem())
1705 return;
1706 aty128_do_resume(par->pdev);
1707 release_console_sem();
1708}
1709#endif /* CONFIG_PPC_PMAC */
1710
1711static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1712{
1713 struct fb_info *info = pci_get_drvdata(pdev);
1714 struct aty128fb_par *par = info->par;
1715 struct fb_var_screeninfo var;
1716 char video_card[DEVICE_NAME_SIZE];
1717 u8 chip_rev;
1718 u32 dac;
1719
1720 if (!par->vram_size) /* may have already been probed */
1721 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1722
1723 /* Get the chip revision */
1724 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1725
1726 strcpy(video_card, "Rage128 XX ");
1727 video_card[8] = ent->device >> 8;
1728 video_card[9] = ent->device & 0xFF;
1729
1730 /* range check to make sure */
1731 if (ent->driver_data < (sizeof(r128_family)/sizeof(char *)))
1732 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1733
1734 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1735
1736 if (par->vram_size % (1024 * 1024) == 0)
1737 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1738 else
1739 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1740
1741 par->chip_gen = ent->driver_data;
1742
1743 /* fill in info */
1744 info->fbops = &aty128fb_ops;
1745 info->flags = FBINFO_FLAG_DEFAULT;
1746
1da177e4
LT		 1747 par->lcd_on = default_lcd_on;
1748 par->crt_on = default_crt_on;
1da177e4
LT		 1749
1750 var = default_var;
1751#ifdef CONFIG_PPC_PMAC
1752 if (_machine == _MACH_Pmac) {
1753 /* Indicate sleep capability */
1754 if (par->chip_gen == rage_M3) {
1755 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1756 pmac_set_early_video_resume(aty128_early_resume, par);
1757 }
1758
1759 /* Find default mode */
1760 if (mode_option) {
1761 if (!mac_find_mode(&var, info, mode_option, 8))
1762 var = default_var;
1763 } else {
1764 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1765 default_vmode = VMODE_1024_768_60;
1766
1767 /* iMacs need that resolution
1768 * PowerMac2,1 first r128 iMacs
1769 * PowerMac2,2 summer 2000 iMacs
1770 * PowerMac4,1 january 2001 iMacs "flower power"
1771 */
1772 if (machine_is_compatible("PowerMac2,1") ||
1773 machine_is_compatible("PowerMac2,2") ||
1774 machine_is_compatible("PowerMac4,1"))
1775 default_vmode = VMODE_1024_768_75;
1776
1777 /* iBook SE */
1778 if (machine_is_compatible("PowerBook2,2"))
1779 default_vmode = VMODE_800_600_60;
1780
1781 /* PowerBook Firewire (Pismo), iBook Dual USB */
1782 if (machine_is_compatible("PowerBook3,1") ||
1783 machine_is_compatible("PowerBook4,1"))
1784 default_vmode = VMODE_1024_768_60;
1785
1786 /* PowerBook Titanium */
1787 if (machine_is_compatible("PowerBook3,2"))
1788 default_vmode = VMODE_1152_768_60;
1789
1790 if (default_cmode > 16)
1791 default_cmode = CMODE_32;
1792 else if (default_cmode > 8)
1793 default_cmode = CMODE_16;
1794 else
1795 default_cmode = CMODE_8;
1796
1797 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1798 var = default_var;
1799 }
1800 } else
1801#endif /* CONFIG_PPC_PMAC */
1802 {
1803 if (mode_option)
1804 if (fb_find_mode(&var, info, mode_option, NULL,
1805 0, &defaultmode, 8) == 0)
1806 var = default_var;
1807 }
1808
1809 var.accel_flags &= ~FB_ACCELF_TEXT;
1810// var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1811
1812 if (aty128fb_check_var(&var, info)) {
1813 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1814 return 0;
1815 }
1816
1817 /* setup the DAC the way we like it */
1818 dac = aty_ld_le32(DAC_CNTL);
1819 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1820 dac |= DAC_MASK;
1821 if (par->chip_gen == rage_M3)
1822 dac |= DAC_PALETTE2_SNOOP_EN;
1823 aty_st_le32(DAC_CNTL, dac);
1824
1825 /* turn off bus mastering, just in case */
1826 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1827
1828 info->var = var;
1829 fb_alloc_cmap(&info->cmap, 256, 0);
1830
1831 var.activate = FB_ACTIVATE_NOW;
1832
1833 aty128_init_engine(par);
1834
1835 if (register_framebuffer(info) < 0)
1836 return 0;
1837
1838#ifdef CONFIG_PMAC_BACKLIGHT
1839 /* Could be extended to Rage128Pro LVDS output too */
1840 if (par->chip_gen == rage_M3)
1841 register_backlight_controller(&aty128_backlight_controller, par, "ati");
1842#endif /* CONFIG_PMAC_BACKLIGHT */
1843
1844 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1845 par->pdev = pdev;
1846 par->asleep = 0;
1847 par->lock_blank = 0;
1848
1849 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1850 info->node, info->fix.id, video_card);
1851
1852 return 1; /* success! */
1853}
1854
1855#ifdef CONFIG_PCI
1856/* register a card ++ajoshi */
1857static int __init aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1858{
1859 unsigned long fb_addr, reg_addr;
1860 struct aty128fb_par *par;
1861 struct fb_info *info;
1862 int err;
1863#ifndef __sparc__
1864 void __iomem *bios = NULL;
1865#endif
1866
1867 /* Enable device in PCI config */
1868 if ((err = pci_enable_device(pdev))) {
1869 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1870 err);
1871 return -ENODEV;
1872 }
1873
1874 fb_addr = pci_resource_start(pdev, 0);
1875 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1876 "aty128fb FB")) {
1877 printk(KERN_ERR "aty128fb: cannot reserve frame "
1878 "buffer memory\n");
1879 return -ENODEV;
1880 }
1881
1882 reg_addr = pci_resource_start(pdev, 2);
1883 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1884 "aty128fb MMIO")) {
1885 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1886 goto err_free_fb;
1887 }
1888
1889 /* We have the resources. Now virtualize them */
1890 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
1891 if (info == NULL) {
1892 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1893 goto err_free_mmio;
1894 }
1895 par = info->par;
1896
1897 info->pseudo_palette = par->pseudo_palette;
1898 info->fix = aty128fb_fix;
1899
1900 /* Virtualize mmio region */
1901 info->fix.mmio_start = reg_addr;
1902 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
1903 if (!par->regbase)
1904 goto err_free_info;
1905
1906 /* Grab memory size from the card */
1907 // How does this relate to the resource length from the PCI hardware?
1908 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1909
1910 /* Virtualize the framebuffer */
1911 info->screen_base = ioremap(fb_addr, par->vram_size);
1912 if (!info->screen_base)
1913 goto err_unmap_out;
1914
1915 /* Set up info->fix */
1916 info->fix = aty128fb_fix;
1917 info->fix.smem_start = fb_addr;
1918 info->fix.smem_len = par->vram_size;
1919 info->fix.mmio_start = reg_addr;
1920
1921 /* If we can't test scratch registers, something is seriously wrong */
1922 if (!register_test(par)) {
1923 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1924 goto err_out;
1925 }
1926
1927#ifndef __sparc__
1928 bios = aty128_map_ROM(par, pdev);
1929#ifdef CONFIG_X86
1930 if (bios == NULL)
1931 bios = aty128_find_mem_vbios(par);
1932#endif
1933 if (bios == NULL)
1934 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
1935 else {
1936 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
1937 aty128_get_pllinfo(par, bios);
1938 pci_unmap_rom(pdev, bios);
1939 }
1940#endif /* __sparc__ */
1941
1942 aty128_timings(par);
1943 pci_set_drvdata(pdev, info);
1944
1945 if (!aty128_init(pdev, ent))
1946 goto err_out;
1947
1948#ifdef CONFIG_MTRR
1949 if (mtrr) {
1950 par->mtrr.vram = mtrr_add(info->fix.smem_start,
1951 par->vram_size, MTRR_TYPE_WRCOMB, 1);
1952 par->mtrr.vram_valid = 1;
1953 /* let there be speed */
1954 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1955 }
1956#endif /* CONFIG_MTRR */
1957 return 0;
1958
1959err_out:
1960 iounmap(info->screen_base);
1961err_unmap_out:
1962 iounmap(par->regbase);
1963err_free_info:
1964 framebuffer_release(info);
1965err_free_mmio:
1966 release_mem_region(pci_resource_start(pdev, 2),
1967 pci_resource_len(pdev, 2));
1968err_free_fb:
1969 release_mem_region(pci_resource_start(pdev, 0),
1970 pci_resource_len(pdev, 0));
1971 return -ENODEV;
1972}
1973
1974static void __devexit aty128_remove(struct pci_dev *pdev)
1975{
1976 struct fb_info *info = pci_get_drvdata(pdev);
1977 struct aty128fb_par *par;
1978
1979 if (!info)
1980 return;
1981
1982 par = info->par;
1983
1984 unregister_framebuffer(info);
1985#ifdef CONFIG_MTRR
1986 if (par->mtrr.vram_valid)
1987 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1988 par->vram_size);
1989#endif /* CONFIG_MTRR */
1990 iounmap(par->regbase);
1991 iounmap(info->screen_base);
1992
1993 release_mem_region(pci_resource_start(pdev, 0),
1994 pci_resource_len(pdev, 0));
1995 release_mem_region(pci_resource_start(pdev, 2),
1996 pci_resource_len(pdev, 2));
1997 framebuffer_release(info);
1998}
1999#endif /* CONFIG_PCI */
2000
2001
2002
2003 /*
2004 * Blank the display.
2005 */
2006static int aty128fb_blank(int blank, struct fb_info *fb)
2007{
2008 struct aty128fb_par *par = fb->par;
2009 u8 state = 0;
2010
2011 if (par->lock_blank || par->asleep)
2012 return 0;
2013
2014#ifdef CONFIG_PMAC_BACKLIGHT
2015 if ((_machine == _MACH_Pmac) && blank)
2016 set_backlight_enable(0);
2017#endif /* CONFIG_PMAC_BACKLIGHT */
2018
2019 if (blank & FB_BLANK_VSYNC_SUSPEND)
2020 state |= 2;
2021 if (blank & FB_BLANK_HSYNC_SUSPEND)
2022 state |= 1;
2023 if (blank & FB_BLANK_POWERDOWN)
2024 state |= 4;
2025
2026 aty_st_8(CRTC_EXT_CNTL+1, state);
2027
1da177e4
LT		 2028 if (par->chip_gen == rage_M3) {
2029 aty128_set_crt_enable(par, par->crt_on && !blank);
2030 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2031 }
1da177e4
LT		 2032#ifdef CONFIG_PMAC_BACKLIGHT
2033 if ((_machine == _MACH_Pmac) && !blank)
2034 set_backlight_enable(1);
2035#endif /* CONFIG_PMAC_BACKLIGHT */
2036 return 0;
2037}
2038
2039/*
2040 * Set a single color register. The values supplied are already
2041 * rounded down to the hardware's capabilities (according to the
2042 * entries in the var structure). Return != 0 for invalid regno.
2043 */
2044static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2045 u_int transp, struct fb_info *info)
2046{
2047 struct aty128fb_par *par = info->par;
2048
2049 if (regno > 255
2050 || (par->crtc.depth == 16 && regno > 63)
2051 || (par->crtc.depth == 15 && regno > 31))
2052 return 1;
2053
2054 red >>= 8;
2055 green >>= 8;
2056 blue >>= 8;
2057
2058 if (regno < 16) {
2059 int i;
2060 u32 *pal = info->pseudo_palette;
2061
2062 switch (par->crtc.depth) {
2063 case 15:
2064 pal[regno] = (regno << 10) | (regno << 5) | regno;
2065 break;
2066 case 16:
2067 pal[regno] = (regno << 11) | (regno << 6) | regno;
2068 break;
2069 case 24:
2070 pal[regno] = (regno << 16) | (regno << 8) | regno;
2071 break;
2072 case 32:
2073 i = (regno << 8) | regno;
2074 pal[regno] = (i << 16) | i;
2075 break;
2076 }
2077 }
2078
2079 if (par->crtc.depth == 16 && regno > 0) {
2080 /*
2081 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2082 * have 32 slots for R and B values but 64 slots for G values.
2083 * Thus the R and B values go in one slot but the G value
2084 * goes in a different slot, and we have to avoid disturbing
2085 * the other fields in the slots we touch.
2086 */
2087 par->green[regno] = green;
2088 if (regno < 32) {
2089 par->red[regno] = red;
2090 par->blue[regno] = blue;
2091 aty128_st_pal(regno * 8, red, par->green[regno*2],
2092 blue, par);
2093 }
2094 red = par->red[regno/2];
2095 blue = par->blue[regno/2];
2096 regno <<= 2;
2097 } else if (par->crtc.bpp == 16)
2098 regno <<= 3;
2099 aty128_st_pal(regno, red, green, blue, par);
2100
2101 return 0;
2102}
2103
2104#define ATY_MIRROR_LCD_ON 0x00000001
2105#define ATY_MIRROR_CRT_ON 0x00000002
2106
2107/* out param: u32* backlight value: 0 to 15 */
2108#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2109/* in param: u32* backlight value: 0 to 15 */
2110#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2111
2112static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2113 u_long arg, struct fb_info *info)
2114{
1da177e4
LT		 2115 struct aty128fb_par *par = info->par;
2116 u32 value;
2117 int rc;
2118
2119 switch (cmd) {
2120 case FBIO_ATY128_SET_MIRROR:
2121 if (par->chip_gen != rage_M3)
2122 return -EINVAL;
2123 rc = get_user(value, (__u32 __user *)arg);
2124 if (rc)
2125 return rc;
2126 par->lcd_on = (value & 0x01) != 0;
2127 par->crt_on = (value & 0x02) != 0;
2128 if (!par->crt_on && !par->lcd_on)
2129 par->lcd_on = 1;
2130 aty128_set_crt_enable(par, par->crt_on);
2131 aty128_set_lcd_enable(par, par->lcd_on);
2132 return 0;
2133 case FBIO_ATY128_GET_MIRROR:
2134 if (par->chip_gen != rage_M3)
2135 return -EINVAL;
2136 value = (par->crt_on << 1) | par->lcd_on;
2137 return put_user(value, (__u32 __user *)arg);
2138 }
1da177e4
LT		 2139 return -EINVAL;
2140}
2141
2142#ifdef CONFIG_PMAC_BACKLIGHT
2143static int backlight_conv[] = {
2144 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2145 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2146};
2147
2148/* We turn off the LCD completely instead of just dimming the backlight.
2149 * This provides greater power saving and the display is useless without
2150 * backlight anyway
2151 */
2152#define BACKLIGHT_LVDS_OFF
2153/* That one prevents proper CRT output with LCD off */
2154#undef BACKLIGHT_DAC_OFF
2155
2156static int aty128_set_backlight_enable(int on, int level, void *data)
2157{
2158 struct aty128fb_par *par = data;
2159 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2160
2161 if (!par->lcd_on)
2162 on = 0;
2163 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2164 if (on && level > BACKLIGHT_OFF) {
2165 reg |= LVDS_DIGION;
2166 if (!(reg & LVDS_ON)) {
2167 reg &= ~LVDS_BLON;
2168 aty_st_le32(LVDS_GEN_CNTL, reg);
2169 (void)aty_ld_le32(LVDS_GEN_CNTL);
2170 mdelay(10);
2171 reg |= LVDS_BLON;
2172 aty_st_le32(LVDS_GEN_CNTL, reg);
2173 }
2174 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2175 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2176#ifdef BACKLIGHT_LVDS_OFF
2177 reg |= LVDS_ON | LVDS_EN;
2178 reg &= ~LVDS_DISPLAY_DIS;
2179#endif
2180 aty_st_le32(LVDS_GEN_CNTL, reg);
2181#ifdef BACKLIGHT_DAC_OFF
2182 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2183#endif
2184 } else {
2185 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2186 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2187#ifdef BACKLIGHT_LVDS_OFF
2188 reg |= LVDS_DISPLAY_DIS;
2189 aty_st_le32(LVDS_GEN_CNTL, reg);
2190 (void)aty_ld_le32(LVDS_GEN_CNTL);
2191 udelay(10);
2192 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2193#endif
2194 aty_st_le32(LVDS_GEN_CNTL, reg);
2195#ifdef BACKLIGHT_DAC_OFF
2196 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2197#endif
2198 }
2199
2200 return 0;
2201}
2202
2203static int aty128_set_backlight_level(int level, void* data)
2204{
2205 return aty128_set_backlight_enable(1, level, data);
2206}
2207#endif /* CONFIG_PMAC_BACKLIGHT */
2208
2209#if 0
2210 /*
2211 * Accelerated functions
2212 */
2213
2214static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2215 u_int width, u_int height,
2216 struct fb_info_aty128 *par)
2217{
2218 u32 save_dp_datatype, save_dp_cntl, dstval;
2219
2220 if (!width || !height)
2221 return;
2222
2223 dstval = depth_to_dst(par->current_par.crtc.depth);
2224 if (dstval == DST_24BPP) {
2225 srcx *= 3;
2226 dstx *= 3;
2227 width *= 3;
2228 } else if (dstval == -EINVAL) {
2229 printk("aty128fb: invalid depth or RGBA\n");
2230 return;
2231 }
2232
2233 wait_for_fifo(2, par);
2234 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2235 save_dp_cntl = aty_ld_le32(DP_CNTL);
2236
2237 wait_for_fifo(6, par);
2238 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2239 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2240 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2241 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2242
2243 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2244 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2245
2246 par->blitter_may_be_busy = 1;
2247
2248 wait_for_fifo(2, par);
2249 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2250 aty_st_le32(DP_CNTL, save_dp_cntl);
2251}
2252
2253
2254 /*
2255 * Text mode accelerated functions
2256 */
2257
2258static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2259 int height, int width)
2260{
2261 sx *= fontwidth(p);
2262 sy *= fontheight(p);
2263 dx *= fontwidth(p);
2264 dy *= fontheight(p);
2265 width *= fontwidth(p);
2266 height *= fontheight(p);
2267
2268 aty128_rectcopy(sx, sy, dx, dy, width, height,
2269 (struct fb_info_aty128 *)p->fb_info);
2270}
2271#endif /* 0 */
2272
2273static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2274{
2275 u32 pmgt;
2276 u16 pwr_command;
2277 struct pci_dev *pdev = par->pdev;
2278
2279 if (!par->pm_reg)
2280 return;
2281
2282 /* Set the chip into the appropriate suspend mode (we use D2,
2283 * D3 would require a complete re-initialisation of the chip,
2284 * including PCI config registers, clocks, AGP configuration, ...)
2285 */
2286 if (suspend) {
2287 /* Make sure CRTC2 is reset. Remove that the day we decide to
2288 * actually use CRTC2 and replace it with real code for disabling
2289 * the CRTC2 output during sleep
2290 */
2291 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2292 ~(CRTC2_EN));
2293
2294 /* Set the power management mode to be PCI based */
2295 /* Use this magic value for now */
2296 pmgt = 0x0c005407;
2297 aty_st_pll(POWER_MANAGEMENT, pmgt);
2298 (void)aty_ld_pll(POWER_MANAGEMENT);
2299 aty_st_le32(BUS_CNTL1, 0x00000010);
2300 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2301 mdelay(100);
2302 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2303 /* Switch PCI power management to D2 */
2304 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2305 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2306 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2307 } else {
2308 /* Switch back PCI power management to D0 */
2309 mdelay(100);
2310 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2311 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2312 mdelay(100);
2313 }
2314}
2315
2316static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2317{
2318 struct fb_info *info = pci_get_drvdata(pdev);
2319 struct aty128fb_par *par = info->par;
1da177e4
LT		 2320
2321 /* We don't do anything but D2, for now we return 0, but
2322 * we may want to change that. How do we know if the BIOS
2323 * can properly take care of D3 ? Also, with swsusp, we
2324 * know we'll be rebooted, ...
2325 */
ca078bae 2326#ifndef CONFIG_PPC_PMAC
1da177e4
LT		 2327 /* HACK ALERT ! Once I find a proper way to say to each driver
2328 * individually what will happen with it's PCI slot, I'll change
2329 * that. On laptops, the AGP slot is just unclocked, so D2 is
2330 * expected, while on desktops, the card is powered off
2331 */
ca078bae 2332 return 0;
1da177e4
LT		 2333#endif /* CONFIG_PPC_PMAC */
2334
ca078bae 2335 if (state.event == pdev->dev.power.power_state.event)
1da177e4
LT		 2336 return 0;
2337
2338 printk(KERN_DEBUG "aty128fb: suspending...\n");
2339
2340 acquire_console_sem();
2341
2342 fb_set_suspend(info, 1);
2343
2344 /* Make sure engine is reset */
2345 wait_for_idle(par);
2346 aty128_reset_engine(par);
2347 wait_for_idle(par);
2348
2349 /* Blank display and LCD */
2350 aty128fb_blank(VESA_POWERDOWN, info);
2351
2352 /* Sleep */
2353 par->asleep = 1;
2354 par->lock_blank = 1;
2355
0c541b44
BH		 2356#ifdef CONFIG_PPC_PMAC
2357 /* On powermac, we have hooks to properly suspend/resume AGP now,
2358 * use them here. We'll ultimately need some generic support here,
2359 * but the generic code isn't quite ready for that yet
1da177e4 2360 */
0c541b44
BH		 2361 pmac_suspend_agp_for_card(pdev);
2362#endif /* CONFIG_PPC_PMAC */
1da177e4
LT		 2363
2364 /* We need a way to make sure the fbdev layer will _not_ touch the
2365 * framebuffer before we put the chip to suspend state. On 2.4, I
2366 * used dummy fb ops, 2.5 need proper support for this at the
2367 * fbdev level
2368 */
ca078bae 2369 if (state.event != PM_EVENT_ON)
1da177e4
LT		 2370 aty128_set_suspend(par, 1);
2371
2372 release_console_sem();
2373
2374 pdev->dev.power.power_state = state;
2375
2376 return 0;
2377}
2378
2379static int aty128_do_resume(struct pci_dev *pdev)
2380{
2381 struct fb_info *info = pci_get_drvdata(pdev);
2382 struct aty128fb_par *par = info->par;
2383
ca078bae 2384 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
1da177e4
LT		 2385 return 0;
2386
2387 /* Wakeup chip */
ca078bae 2388 aty128_set_suspend(par, 0);
1da177e4
LT		 2389 par->asleep = 0;
2390
2391 /* Restore display & engine */
2392 aty128_reset_engine(par);
2393 wait_for_idle(par);
2394 aty128fb_set_par(info);
2395 fb_pan_display(info, &info->var);
2396 fb_set_cmap(&info->cmap, info);
2397
2398 /* Refresh */
2399 fb_set_suspend(info, 0);
2400
2401 /* Unblank */
2402 par->lock_blank = 0;
2403 aty128fb_blank(0, info);
2404
0c541b44
BH		 2405#ifdef CONFIG_PPC_PMAC
2406 /* On powermac, we have hooks to properly suspend/resume AGP now,
2407 * use them here. We'll ultimately need some generic support here,
2408 * but the generic code isn't quite ready for that yet
2409 */
2410 pmac_resume_agp_for_card(pdev);
2411#endif /* CONFIG_PPC_PMAC */
2412
1da177e4
LT		 2413 pdev->dev.power.power_state = PMSG_ON;
2414
2415 printk(KERN_DEBUG "aty128fb: resumed !\n");
2416
2417 return 0;
2418}
2419
2420static int aty128_pci_resume(struct pci_dev *pdev)
2421{
2422 int rc;
2423
2424 acquire_console_sem();
2425 rc = aty128_do_resume(pdev);
2426 release_console_sem();
2427
2428 return rc;
2429}
2430
2431
2432static int __init aty128fb_init(void)
2433{
2434#ifndef MODULE
2435 char *option = NULL;
2436
2437 if (fb_get_options("aty128fb", &option))
2438 return -ENODEV;
2439 aty128fb_setup(option);
2440#endif
2441
2442 return pci_register_driver(&aty128fb_driver);
2443}
2444
2445static void __exit aty128fb_exit(void)
2446{
2447 pci_unregister_driver(&aty128fb_driver);
2448}
2449
2450module_init(aty128fb_init);
2451
2452module_exit(aty128fb_exit);
2453
2454MODULE_AUTHOR("(c)1999-2003 Brad Douglas <[email protected]>");
2455MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2456MODULE_LICENSE("GPL");
2457module_param(mode_option, charp, 0);
2458MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2459#ifdef CONFIG_MTRR
2460module_param_named(nomtrr, mtrr, invbool, 0);
2461MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2462#endif
2463
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